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x86: Force irq complete move during cpu offline
[deliverable/linux.git] / arch / x86 / kernel / apic / io_apic.c
1 /*
2 * Intel IO-APIC support for multi-Pentium hosts.
3 *
4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
5 *
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
8 *
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
14 *
15 * Fixes
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
18 * and Rolf G. Tews
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
21 */
22
23 #include <linux/mm.h>
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/sysdev.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38 #include <linux/jiffies.h> /* time_after() */
39 #ifdef CONFIG_ACPI
40 #include <acpi/acpi_bus.h>
41 #endif
42 #include <linux/bootmem.h>
43 #include <linux/dmar.h>
44 #include <linux/hpet.h>
45
46 #include <asm/idle.h>
47 #include <asm/io.h>
48 #include <asm/smp.h>
49 #include <asm/cpu.h>
50 #include <asm/desc.h>
51 #include <asm/proto.h>
52 #include <asm/acpi.h>
53 #include <asm/dma.h>
54 #include <asm/timer.h>
55 #include <asm/i8259.h>
56 #include <asm/nmi.h>
57 #include <asm/msidef.h>
58 #include <asm/hypertransport.h>
59 #include <asm/setup.h>
60 #include <asm/irq_remapping.h>
61 #include <asm/hpet.h>
62 #include <asm/hw_irq.h>
63
64 #include <asm/apic.h>
65
66 #define __apicdebuginit(type) static type __init
67 #define for_each_irq_pin(entry, head) \
68 for (entry = head; entry; entry = entry->next)
69
70 /*
71 * Is the SiS APIC rmw bug present ?
72 * -1 = don't know, 0 = no, 1 = yes
73 */
74 int sis_apic_bug = -1;
75
76 static DEFINE_SPINLOCK(ioapic_lock);
77 static DEFINE_SPINLOCK(vector_lock);
78
79 /*
80 * # of IRQ routing registers
81 */
82 int nr_ioapic_registers[MAX_IO_APICS];
83
84 /* I/O APIC entries */
85 struct mpc_ioapic mp_ioapics[MAX_IO_APICS];
86 int nr_ioapics;
87
88 /* IO APIC gsi routing info */
89 struct mp_ioapic_gsi mp_gsi_routing[MAX_IO_APICS];
90
91 /* MP IRQ source entries */
92 struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
93
94 /* # of MP IRQ source entries */
95 int mp_irq_entries;
96
97 /* Number of legacy interrupts */
98 static int nr_legacy_irqs __read_mostly = NR_IRQS_LEGACY;
99 /* GSI interrupts */
100 static int nr_irqs_gsi = NR_IRQS_LEGACY;
101
102 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
103 int mp_bus_id_to_type[MAX_MP_BUSSES];
104 #endif
105
106 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
107
108 int skip_ioapic_setup;
109
110 void arch_disable_smp_support(void)
111 {
112 #ifdef CONFIG_PCI
113 noioapicquirk = 1;
114 noioapicreroute = -1;
115 #endif
116 skip_ioapic_setup = 1;
117 }
118
119 static int __init parse_noapic(char *str)
120 {
121 /* disable IO-APIC */
122 arch_disable_smp_support();
123 return 0;
124 }
125 early_param("noapic", parse_noapic);
126
127 struct irq_pin_list {
128 int apic, pin;
129 struct irq_pin_list *next;
130 };
131
132 static struct irq_pin_list *get_one_free_irq_2_pin(int node)
133 {
134 struct irq_pin_list *pin;
135
136 pin = kzalloc_node(sizeof(*pin), GFP_ATOMIC, node);
137
138 return pin;
139 }
140
141 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
142 #ifdef CONFIG_SPARSE_IRQ
143 static struct irq_cfg irq_cfgx[] = {
144 #else
145 static struct irq_cfg irq_cfgx[NR_IRQS] = {
146 #endif
147 [0] = { .vector = IRQ0_VECTOR, },
148 [1] = { .vector = IRQ1_VECTOR, },
149 [2] = { .vector = IRQ2_VECTOR, },
150 [3] = { .vector = IRQ3_VECTOR, },
151 [4] = { .vector = IRQ4_VECTOR, },
152 [5] = { .vector = IRQ5_VECTOR, },
153 [6] = { .vector = IRQ6_VECTOR, },
154 [7] = { .vector = IRQ7_VECTOR, },
155 [8] = { .vector = IRQ8_VECTOR, },
156 [9] = { .vector = IRQ9_VECTOR, },
157 [10] = { .vector = IRQ10_VECTOR, },
158 [11] = { .vector = IRQ11_VECTOR, },
159 [12] = { .vector = IRQ12_VECTOR, },
160 [13] = { .vector = IRQ13_VECTOR, },
161 [14] = { .vector = IRQ14_VECTOR, },
162 [15] = { .vector = IRQ15_VECTOR, },
163 };
164
165 void __init io_apic_disable_legacy(void)
166 {
167 nr_legacy_irqs = 0;
168 nr_irqs_gsi = 0;
169 }
170
171 int __init arch_early_irq_init(void)
172 {
173 struct irq_cfg *cfg;
174 struct irq_desc *desc;
175 int count;
176 int node;
177 int i;
178
179 cfg = irq_cfgx;
180 count = ARRAY_SIZE(irq_cfgx);
181 node= cpu_to_node(boot_cpu_id);
182
183 for (i = 0; i < count; i++) {
184 desc = irq_to_desc(i);
185 desc->chip_data = &cfg[i];
186 zalloc_cpumask_var_node(&cfg[i].domain, GFP_NOWAIT, node);
187 zalloc_cpumask_var_node(&cfg[i].old_domain, GFP_NOWAIT, node);
188 if (i < nr_legacy_irqs)
189 cpumask_setall(cfg[i].domain);
190 }
191
192 return 0;
193 }
194
195 #ifdef CONFIG_SPARSE_IRQ
196 struct irq_cfg *irq_cfg(unsigned int irq)
197 {
198 struct irq_cfg *cfg = NULL;
199 struct irq_desc *desc;
200
201 desc = irq_to_desc(irq);
202 if (desc)
203 cfg = desc->chip_data;
204
205 return cfg;
206 }
207
208 static struct irq_cfg *get_one_free_irq_cfg(int node)
209 {
210 struct irq_cfg *cfg;
211
212 cfg = kzalloc_node(sizeof(*cfg), GFP_ATOMIC, node);
213 if (cfg) {
214 if (!zalloc_cpumask_var_node(&cfg->domain, GFP_ATOMIC, node)) {
215 kfree(cfg);
216 cfg = NULL;
217 } else if (!zalloc_cpumask_var_node(&cfg->old_domain,
218 GFP_ATOMIC, node)) {
219 free_cpumask_var(cfg->domain);
220 kfree(cfg);
221 cfg = NULL;
222 }
223 }
224
225 return cfg;
226 }
227
228 int arch_init_chip_data(struct irq_desc *desc, int node)
229 {
230 struct irq_cfg *cfg;
231
232 cfg = desc->chip_data;
233 if (!cfg) {
234 desc->chip_data = get_one_free_irq_cfg(node);
235 if (!desc->chip_data) {
236 printk(KERN_ERR "can not alloc irq_cfg\n");
237 BUG_ON(1);
238 }
239 }
240
241 return 0;
242 }
243
244 /* for move_irq_desc */
245 static void
246 init_copy_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg, int node)
247 {
248 struct irq_pin_list *old_entry, *head, *tail, *entry;
249
250 cfg->irq_2_pin = NULL;
251 old_entry = old_cfg->irq_2_pin;
252 if (!old_entry)
253 return;
254
255 entry = get_one_free_irq_2_pin(node);
256 if (!entry)
257 return;
258
259 entry->apic = old_entry->apic;
260 entry->pin = old_entry->pin;
261 head = entry;
262 tail = entry;
263 old_entry = old_entry->next;
264 while (old_entry) {
265 entry = get_one_free_irq_2_pin(node);
266 if (!entry) {
267 entry = head;
268 while (entry) {
269 head = entry->next;
270 kfree(entry);
271 entry = head;
272 }
273 /* still use the old one */
274 return;
275 }
276 entry->apic = old_entry->apic;
277 entry->pin = old_entry->pin;
278 tail->next = entry;
279 tail = entry;
280 old_entry = old_entry->next;
281 }
282
283 tail->next = NULL;
284 cfg->irq_2_pin = head;
285 }
286
287 static void free_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg)
288 {
289 struct irq_pin_list *entry, *next;
290
291 if (old_cfg->irq_2_pin == cfg->irq_2_pin)
292 return;
293
294 entry = old_cfg->irq_2_pin;
295
296 while (entry) {
297 next = entry->next;
298 kfree(entry);
299 entry = next;
300 }
301 old_cfg->irq_2_pin = NULL;
302 }
303
304 void arch_init_copy_chip_data(struct irq_desc *old_desc,
305 struct irq_desc *desc, int node)
306 {
307 struct irq_cfg *cfg;
308 struct irq_cfg *old_cfg;
309
310 cfg = get_one_free_irq_cfg(node);
311
312 if (!cfg)
313 return;
314
315 desc->chip_data = cfg;
316
317 old_cfg = old_desc->chip_data;
318
319 memcpy(cfg, old_cfg, sizeof(struct irq_cfg));
320
321 init_copy_irq_2_pin(old_cfg, cfg, node);
322 }
323
324 static void free_irq_cfg(struct irq_cfg *old_cfg)
325 {
326 kfree(old_cfg);
327 }
328
329 void arch_free_chip_data(struct irq_desc *old_desc, struct irq_desc *desc)
330 {
331 struct irq_cfg *old_cfg, *cfg;
332
333 old_cfg = old_desc->chip_data;
334 cfg = desc->chip_data;
335
336 if (old_cfg == cfg)
337 return;
338
339 if (old_cfg) {
340 free_irq_2_pin(old_cfg, cfg);
341 free_irq_cfg(old_cfg);
342 old_desc->chip_data = NULL;
343 }
344 }
345 /* end for move_irq_desc */
346
347 #else
348 struct irq_cfg *irq_cfg(unsigned int irq)
349 {
350 return irq < nr_irqs ? irq_cfgx + irq : NULL;
351 }
352
353 #endif
354
355 struct io_apic {
356 unsigned int index;
357 unsigned int unused[3];
358 unsigned int data;
359 unsigned int unused2[11];
360 unsigned int eoi;
361 };
362
363 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
364 {
365 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
366 + (mp_ioapics[idx].apicaddr & ~PAGE_MASK);
367 }
368
369 static inline void io_apic_eoi(unsigned int apic, unsigned int vector)
370 {
371 struct io_apic __iomem *io_apic = io_apic_base(apic);
372 writel(vector, &io_apic->eoi);
373 }
374
375 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
376 {
377 struct io_apic __iomem *io_apic = io_apic_base(apic);
378 writel(reg, &io_apic->index);
379 return readl(&io_apic->data);
380 }
381
382 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
383 {
384 struct io_apic __iomem *io_apic = io_apic_base(apic);
385 writel(reg, &io_apic->index);
386 writel(value, &io_apic->data);
387 }
388
389 /*
390 * Re-write a value: to be used for read-modify-write
391 * cycles where the read already set up the index register.
392 *
393 * Older SiS APIC requires we rewrite the index register
394 */
395 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
396 {
397 struct io_apic __iomem *io_apic = io_apic_base(apic);
398
399 if (sis_apic_bug)
400 writel(reg, &io_apic->index);
401 writel(value, &io_apic->data);
402 }
403
404 static bool io_apic_level_ack_pending(struct irq_cfg *cfg)
405 {
406 struct irq_pin_list *entry;
407 unsigned long flags;
408
409 spin_lock_irqsave(&ioapic_lock, flags);
410 for_each_irq_pin(entry, cfg->irq_2_pin) {
411 unsigned int reg;
412 int pin;
413
414 pin = entry->pin;
415 reg = io_apic_read(entry->apic, 0x10 + pin*2);
416 /* Is the remote IRR bit set? */
417 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
418 spin_unlock_irqrestore(&ioapic_lock, flags);
419 return true;
420 }
421 }
422 spin_unlock_irqrestore(&ioapic_lock, flags);
423
424 return false;
425 }
426
427 union entry_union {
428 struct { u32 w1, w2; };
429 struct IO_APIC_route_entry entry;
430 };
431
432 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
433 {
434 union entry_union eu;
435 unsigned long flags;
436 spin_lock_irqsave(&ioapic_lock, flags);
437 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
438 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
439 spin_unlock_irqrestore(&ioapic_lock, flags);
440 return eu.entry;
441 }
442
443 /*
444 * When we write a new IO APIC routing entry, we need to write the high
445 * word first! If the mask bit in the low word is clear, we will enable
446 * the interrupt, and we need to make sure the entry is fully populated
447 * before that happens.
448 */
449 static void
450 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
451 {
452 union entry_union eu = {{0, 0}};
453
454 eu.entry = e;
455 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
456 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
457 }
458
459 void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
460 {
461 unsigned long flags;
462 spin_lock_irqsave(&ioapic_lock, flags);
463 __ioapic_write_entry(apic, pin, e);
464 spin_unlock_irqrestore(&ioapic_lock, flags);
465 }
466
467 /*
468 * When we mask an IO APIC routing entry, we need to write the low
469 * word first, in order to set the mask bit before we change the
470 * high bits!
471 */
472 static void ioapic_mask_entry(int apic, int pin)
473 {
474 unsigned long flags;
475 union entry_union eu = { .entry.mask = 1 };
476
477 spin_lock_irqsave(&ioapic_lock, flags);
478 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
479 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
480 spin_unlock_irqrestore(&ioapic_lock, flags);
481 }
482
483 /*
484 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
485 * shared ISA-space IRQs, so we have to support them. We are super
486 * fast in the common case, and fast for shared ISA-space IRQs.
487 */
488 static int
489 add_pin_to_irq_node_nopanic(struct irq_cfg *cfg, int node, int apic, int pin)
490 {
491 struct irq_pin_list **last, *entry;
492
493 /* don't allow duplicates */
494 last = &cfg->irq_2_pin;
495 for_each_irq_pin(entry, cfg->irq_2_pin) {
496 if (entry->apic == apic && entry->pin == pin)
497 return 0;
498 last = &entry->next;
499 }
500
501 entry = get_one_free_irq_2_pin(node);
502 if (!entry) {
503 printk(KERN_ERR "can not alloc irq_pin_list (%d,%d,%d)\n",
504 node, apic, pin);
505 return -ENOMEM;
506 }
507 entry->apic = apic;
508 entry->pin = pin;
509
510 *last = entry;
511 return 0;
512 }
513
514 static void add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin)
515 {
516 if (add_pin_to_irq_node_nopanic(cfg, node, apic, pin))
517 panic("IO-APIC: failed to add irq-pin. Can not proceed\n");
518 }
519
520 /*
521 * Reroute an IRQ to a different pin.
522 */
523 static void __init replace_pin_at_irq_node(struct irq_cfg *cfg, int node,
524 int oldapic, int oldpin,
525 int newapic, int newpin)
526 {
527 struct irq_pin_list *entry;
528
529 for_each_irq_pin(entry, cfg->irq_2_pin) {
530 if (entry->apic == oldapic && entry->pin == oldpin) {
531 entry->apic = newapic;
532 entry->pin = newpin;
533 /* every one is different, right? */
534 return;
535 }
536 }
537
538 /* old apic/pin didn't exist, so just add new ones */
539 add_pin_to_irq_node(cfg, node, newapic, newpin);
540 }
541
542 static void io_apic_modify_irq(struct irq_cfg *cfg,
543 int mask_and, int mask_or,
544 void (*final)(struct irq_pin_list *entry))
545 {
546 int pin;
547 struct irq_pin_list *entry;
548
549 for_each_irq_pin(entry, cfg->irq_2_pin) {
550 unsigned int reg;
551 pin = entry->pin;
552 reg = io_apic_read(entry->apic, 0x10 + pin * 2);
553 reg &= mask_and;
554 reg |= mask_or;
555 io_apic_modify(entry->apic, 0x10 + pin * 2, reg);
556 if (final)
557 final(entry);
558 }
559 }
560
561 static void __unmask_IO_APIC_irq(struct irq_cfg *cfg)
562 {
563 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL);
564 }
565
566 static void io_apic_sync(struct irq_pin_list *entry)
567 {
568 /*
569 * Synchronize the IO-APIC and the CPU by doing
570 * a dummy read from the IO-APIC
571 */
572 struct io_apic __iomem *io_apic;
573 io_apic = io_apic_base(entry->apic);
574 readl(&io_apic->data);
575 }
576
577 static void __mask_IO_APIC_irq(struct irq_cfg *cfg)
578 {
579 io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
580 }
581
582 static void __mask_and_edge_IO_APIC_irq(struct irq_cfg *cfg)
583 {
584 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_LEVEL_TRIGGER,
585 IO_APIC_REDIR_MASKED, NULL);
586 }
587
588 static void __unmask_and_level_IO_APIC_irq(struct irq_cfg *cfg)
589 {
590 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED,
591 IO_APIC_REDIR_LEVEL_TRIGGER, NULL);
592 }
593
594 static void mask_IO_APIC_irq_desc(struct irq_desc *desc)
595 {
596 struct irq_cfg *cfg = desc->chip_data;
597 unsigned long flags;
598
599 BUG_ON(!cfg);
600
601 spin_lock_irqsave(&ioapic_lock, flags);
602 __mask_IO_APIC_irq(cfg);
603 spin_unlock_irqrestore(&ioapic_lock, flags);
604 }
605
606 static void unmask_IO_APIC_irq_desc(struct irq_desc *desc)
607 {
608 struct irq_cfg *cfg = desc->chip_data;
609 unsigned long flags;
610
611 spin_lock_irqsave(&ioapic_lock, flags);
612 __unmask_IO_APIC_irq(cfg);
613 spin_unlock_irqrestore(&ioapic_lock, flags);
614 }
615
616 static void mask_IO_APIC_irq(unsigned int irq)
617 {
618 struct irq_desc *desc = irq_to_desc(irq);
619
620 mask_IO_APIC_irq_desc(desc);
621 }
622 static void unmask_IO_APIC_irq(unsigned int irq)
623 {
624 struct irq_desc *desc = irq_to_desc(irq);
625
626 unmask_IO_APIC_irq_desc(desc);
627 }
628
629 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
630 {
631 struct IO_APIC_route_entry entry;
632
633 /* Check delivery_mode to be sure we're not clearing an SMI pin */
634 entry = ioapic_read_entry(apic, pin);
635 if (entry.delivery_mode == dest_SMI)
636 return;
637 /*
638 * Disable it in the IO-APIC irq-routing table:
639 */
640 ioapic_mask_entry(apic, pin);
641 }
642
643 static void clear_IO_APIC (void)
644 {
645 int apic, pin;
646
647 for (apic = 0; apic < nr_ioapics; apic++)
648 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
649 clear_IO_APIC_pin(apic, pin);
650 }
651
652 #ifdef CONFIG_X86_32
653 /*
654 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
655 * specific CPU-side IRQs.
656 */
657
658 #define MAX_PIRQS 8
659 static int pirq_entries[MAX_PIRQS] = {
660 [0 ... MAX_PIRQS - 1] = -1
661 };
662
663 static int __init ioapic_pirq_setup(char *str)
664 {
665 int i, max;
666 int ints[MAX_PIRQS+1];
667
668 get_options(str, ARRAY_SIZE(ints), ints);
669
670 apic_printk(APIC_VERBOSE, KERN_INFO
671 "PIRQ redirection, working around broken MP-BIOS.\n");
672 max = MAX_PIRQS;
673 if (ints[0] < MAX_PIRQS)
674 max = ints[0];
675
676 for (i = 0; i < max; i++) {
677 apic_printk(APIC_VERBOSE, KERN_DEBUG
678 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
679 /*
680 * PIRQs are mapped upside down, usually.
681 */
682 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
683 }
684 return 1;
685 }
686
687 __setup("pirq=", ioapic_pirq_setup);
688 #endif /* CONFIG_X86_32 */
689
690 struct IO_APIC_route_entry **alloc_ioapic_entries(void)
691 {
692 int apic;
693 struct IO_APIC_route_entry **ioapic_entries;
694
695 ioapic_entries = kzalloc(sizeof(*ioapic_entries) * nr_ioapics,
696 GFP_ATOMIC);
697 if (!ioapic_entries)
698 return 0;
699
700 for (apic = 0; apic < nr_ioapics; apic++) {
701 ioapic_entries[apic] =
702 kzalloc(sizeof(struct IO_APIC_route_entry) *
703 nr_ioapic_registers[apic], GFP_ATOMIC);
704 if (!ioapic_entries[apic])
705 goto nomem;
706 }
707
708 return ioapic_entries;
709
710 nomem:
711 while (--apic >= 0)
712 kfree(ioapic_entries[apic]);
713 kfree(ioapic_entries);
714
715 return 0;
716 }
717
718 /*
719 * Saves all the IO-APIC RTE's
720 */
721 int save_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
722 {
723 int apic, pin;
724
725 if (!ioapic_entries)
726 return -ENOMEM;
727
728 for (apic = 0; apic < nr_ioapics; apic++) {
729 if (!ioapic_entries[apic])
730 return -ENOMEM;
731
732 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
733 ioapic_entries[apic][pin] =
734 ioapic_read_entry(apic, pin);
735 }
736
737 return 0;
738 }
739
740 /*
741 * Mask all IO APIC entries.
742 */
743 void mask_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
744 {
745 int apic, pin;
746
747 if (!ioapic_entries)
748 return;
749
750 for (apic = 0; apic < nr_ioapics; apic++) {
751 if (!ioapic_entries[apic])
752 break;
753
754 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
755 struct IO_APIC_route_entry entry;
756
757 entry = ioapic_entries[apic][pin];
758 if (!entry.mask) {
759 entry.mask = 1;
760 ioapic_write_entry(apic, pin, entry);
761 }
762 }
763 }
764 }
765
766 /*
767 * Restore IO APIC entries which was saved in ioapic_entries.
768 */
769 int restore_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
770 {
771 int apic, pin;
772
773 if (!ioapic_entries)
774 return -ENOMEM;
775
776 for (apic = 0; apic < nr_ioapics; apic++) {
777 if (!ioapic_entries[apic])
778 return -ENOMEM;
779
780 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
781 ioapic_write_entry(apic, pin,
782 ioapic_entries[apic][pin]);
783 }
784 return 0;
785 }
786
787 void free_ioapic_entries(struct IO_APIC_route_entry **ioapic_entries)
788 {
789 int apic;
790
791 for (apic = 0; apic < nr_ioapics; apic++)
792 kfree(ioapic_entries[apic]);
793
794 kfree(ioapic_entries);
795 }
796
797 /*
798 * Find the IRQ entry number of a certain pin.
799 */
800 static int find_irq_entry(int apic, int pin, int type)
801 {
802 int i;
803
804 for (i = 0; i < mp_irq_entries; i++)
805 if (mp_irqs[i].irqtype == type &&
806 (mp_irqs[i].dstapic == mp_ioapics[apic].apicid ||
807 mp_irqs[i].dstapic == MP_APIC_ALL) &&
808 mp_irqs[i].dstirq == pin)
809 return i;
810
811 return -1;
812 }
813
814 /*
815 * Find the pin to which IRQ[irq] (ISA) is connected
816 */
817 static int __init find_isa_irq_pin(int irq, int type)
818 {
819 int i;
820
821 for (i = 0; i < mp_irq_entries; i++) {
822 int lbus = mp_irqs[i].srcbus;
823
824 if (test_bit(lbus, mp_bus_not_pci) &&
825 (mp_irqs[i].irqtype == type) &&
826 (mp_irqs[i].srcbusirq == irq))
827
828 return mp_irqs[i].dstirq;
829 }
830 return -1;
831 }
832
833 static int __init find_isa_irq_apic(int irq, int type)
834 {
835 int i;
836
837 for (i = 0; i < mp_irq_entries; i++) {
838 int lbus = mp_irqs[i].srcbus;
839
840 if (test_bit(lbus, mp_bus_not_pci) &&
841 (mp_irqs[i].irqtype == type) &&
842 (mp_irqs[i].srcbusirq == irq))
843 break;
844 }
845 if (i < mp_irq_entries) {
846 int apic;
847 for(apic = 0; apic < nr_ioapics; apic++) {
848 if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic)
849 return apic;
850 }
851 }
852
853 return -1;
854 }
855
856 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
857 /*
858 * EISA Edge/Level control register, ELCR
859 */
860 static int EISA_ELCR(unsigned int irq)
861 {
862 if (irq < nr_legacy_irqs) {
863 unsigned int port = 0x4d0 + (irq >> 3);
864 return (inb(port) >> (irq & 7)) & 1;
865 }
866 apic_printk(APIC_VERBOSE, KERN_INFO
867 "Broken MPtable reports ISA irq %d\n", irq);
868 return 0;
869 }
870
871 #endif
872
873 /* ISA interrupts are always polarity zero edge triggered,
874 * when listed as conforming in the MP table. */
875
876 #define default_ISA_trigger(idx) (0)
877 #define default_ISA_polarity(idx) (0)
878
879 /* EISA interrupts are always polarity zero and can be edge or level
880 * trigger depending on the ELCR value. If an interrupt is listed as
881 * EISA conforming in the MP table, that means its trigger type must
882 * be read in from the ELCR */
883
884 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq))
885 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
886
887 /* PCI interrupts are always polarity one level triggered,
888 * when listed as conforming in the MP table. */
889
890 #define default_PCI_trigger(idx) (1)
891 #define default_PCI_polarity(idx) (1)
892
893 /* MCA interrupts are always polarity zero level triggered,
894 * when listed as conforming in the MP table. */
895
896 #define default_MCA_trigger(idx) (1)
897 #define default_MCA_polarity(idx) default_ISA_polarity(idx)
898
899 static int MPBIOS_polarity(int idx)
900 {
901 int bus = mp_irqs[idx].srcbus;
902 int polarity;
903
904 /*
905 * Determine IRQ line polarity (high active or low active):
906 */
907 switch (mp_irqs[idx].irqflag & 3)
908 {
909 case 0: /* conforms, ie. bus-type dependent polarity */
910 if (test_bit(bus, mp_bus_not_pci))
911 polarity = default_ISA_polarity(idx);
912 else
913 polarity = default_PCI_polarity(idx);
914 break;
915 case 1: /* high active */
916 {
917 polarity = 0;
918 break;
919 }
920 case 2: /* reserved */
921 {
922 printk(KERN_WARNING "broken BIOS!!\n");
923 polarity = 1;
924 break;
925 }
926 case 3: /* low active */
927 {
928 polarity = 1;
929 break;
930 }
931 default: /* invalid */
932 {
933 printk(KERN_WARNING "broken BIOS!!\n");
934 polarity = 1;
935 break;
936 }
937 }
938 return polarity;
939 }
940
941 static int MPBIOS_trigger(int idx)
942 {
943 int bus = mp_irqs[idx].srcbus;
944 int trigger;
945
946 /*
947 * Determine IRQ trigger mode (edge or level sensitive):
948 */
949 switch ((mp_irqs[idx].irqflag>>2) & 3)
950 {
951 case 0: /* conforms, ie. bus-type dependent */
952 if (test_bit(bus, mp_bus_not_pci))
953 trigger = default_ISA_trigger(idx);
954 else
955 trigger = default_PCI_trigger(idx);
956 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
957 switch (mp_bus_id_to_type[bus]) {
958 case MP_BUS_ISA: /* ISA pin */
959 {
960 /* set before the switch */
961 break;
962 }
963 case MP_BUS_EISA: /* EISA pin */
964 {
965 trigger = default_EISA_trigger(idx);
966 break;
967 }
968 case MP_BUS_PCI: /* PCI pin */
969 {
970 /* set before the switch */
971 break;
972 }
973 case MP_BUS_MCA: /* MCA pin */
974 {
975 trigger = default_MCA_trigger(idx);
976 break;
977 }
978 default:
979 {
980 printk(KERN_WARNING "broken BIOS!!\n");
981 trigger = 1;
982 break;
983 }
984 }
985 #endif
986 break;
987 case 1: /* edge */
988 {
989 trigger = 0;
990 break;
991 }
992 case 2: /* reserved */
993 {
994 printk(KERN_WARNING "broken BIOS!!\n");
995 trigger = 1;
996 break;
997 }
998 case 3: /* level */
999 {
1000 trigger = 1;
1001 break;
1002 }
1003 default: /* invalid */
1004 {
1005 printk(KERN_WARNING "broken BIOS!!\n");
1006 trigger = 0;
1007 break;
1008 }
1009 }
1010 return trigger;
1011 }
1012
1013 static inline int irq_polarity(int idx)
1014 {
1015 return MPBIOS_polarity(idx);
1016 }
1017
1018 static inline int irq_trigger(int idx)
1019 {
1020 return MPBIOS_trigger(idx);
1021 }
1022
1023 int (*ioapic_renumber_irq)(int ioapic, int irq);
1024 static int pin_2_irq(int idx, int apic, int pin)
1025 {
1026 int irq, i;
1027 int bus = mp_irqs[idx].srcbus;
1028
1029 /*
1030 * Debugging check, we are in big trouble if this message pops up!
1031 */
1032 if (mp_irqs[idx].dstirq != pin)
1033 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1034
1035 if (test_bit(bus, mp_bus_not_pci)) {
1036 irq = mp_irqs[idx].srcbusirq;
1037 } else {
1038 /*
1039 * PCI IRQs are mapped in order
1040 */
1041 i = irq = 0;
1042 while (i < apic)
1043 irq += nr_ioapic_registers[i++];
1044 irq += pin;
1045 /*
1046 * For MPS mode, so far only needed by ES7000 platform
1047 */
1048 if (ioapic_renumber_irq)
1049 irq = ioapic_renumber_irq(apic, irq);
1050 }
1051
1052 #ifdef CONFIG_X86_32
1053 /*
1054 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1055 */
1056 if ((pin >= 16) && (pin <= 23)) {
1057 if (pirq_entries[pin-16] != -1) {
1058 if (!pirq_entries[pin-16]) {
1059 apic_printk(APIC_VERBOSE, KERN_DEBUG
1060 "disabling PIRQ%d\n", pin-16);
1061 } else {
1062 irq = pirq_entries[pin-16];
1063 apic_printk(APIC_VERBOSE, KERN_DEBUG
1064 "using PIRQ%d -> IRQ %d\n",
1065 pin-16, irq);
1066 }
1067 }
1068 }
1069 #endif
1070
1071 return irq;
1072 }
1073
1074 /*
1075 * Find a specific PCI IRQ entry.
1076 * Not an __init, possibly needed by modules
1077 */
1078 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin,
1079 struct io_apic_irq_attr *irq_attr)
1080 {
1081 int apic, i, best_guess = -1;
1082
1083 apic_printk(APIC_DEBUG,
1084 "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1085 bus, slot, pin);
1086 if (test_bit(bus, mp_bus_not_pci)) {
1087 apic_printk(APIC_VERBOSE,
1088 "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
1089 return -1;
1090 }
1091 for (i = 0; i < mp_irq_entries; i++) {
1092 int lbus = mp_irqs[i].srcbus;
1093
1094 for (apic = 0; apic < nr_ioapics; apic++)
1095 if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic ||
1096 mp_irqs[i].dstapic == MP_APIC_ALL)
1097 break;
1098
1099 if (!test_bit(lbus, mp_bus_not_pci) &&
1100 !mp_irqs[i].irqtype &&
1101 (bus == lbus) &&
1102 (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) {
1103 int irq = pin_2_irq(i, apic, mp_irqs[i].dstirq);
1104
1105 if (!(apic || IO_APIC_IRQ(irq)))
1106 continue;
1107
1108 if (pin == (mp_irqs[i].srcbusirq & 3)) {
1109 set_io_apic_irq_attr(irq_attr, apic,
1110 mp_irqs[i].dstirq,
1111 irq_trigger(i),
1112 irq_polarity(i));
1113 return irq;
1114 }
1115 /*
1116 * Use the first all-but-pin matching entry as a
1117 * best-guess fuzzy result for broken mptables.
1118 */
1119 if (best_guess < 0) {
1120 set_io_apic_irq_attr(irq_attr, apic,
1121 mp_irqs[i].dstirq,
1122 irq_trigger(i),
1123 irq_polarity(i));
1124 best_guess = irq;
1125 }
1126 }
1127 }
1128 return best_guess;
1129 }
1130 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
1131
1132 void lock_vector_lock(void)
1133 {
1134 /* Used to the online set of cpus does not change
1135 * during assign_irq_vector.
1136 */
1137 spin_lock(&vector_lock);
1138 }
1139
1140 void unlock_vector_lock(void)
1141 {
1142 spin_unlock(&vector_lock);
1143 }
1144
1145 static int
1146 __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1147 {
1148 /*
1149 * NOTE! The local APIC isn't very good at handling
1150 * multiple interrupts at the same interrupt level.
1151 * As the interrupt level is determined by taking the
1152 * vector number and shifting that right by 4, we
1153 * want to spread these out a bit so that they don't
1154 * all fall in the same interrupt level.
1155 *
1156 * Also, we've got to be careful not to trash gate
1157 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1158 */
1159 static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
1160 unsigned int old_vector;
1161 int cpu, err;
1162 cpumask_var_t tmp_mask;
1163
1164 if (cfg->move_in_progress)
1165 return -EBUSY;
1166
1167 if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC))
1168 return -ENOMEM;
1169
1170 old_vector = cfg->vector;
1171 if (old_vector) {
1172 cpumask_and(tmp_mask, mask, cpu_online_mask);
1173 cpumask_and(tmp_mask, cfg->domain, tmp_mask);
1174 if (!cpumask_empty(tmp_mask)) {
1175 free_cpumask_var(tmp_mask);
1176 return 0;
1177 }
1178 }
1179
1180 /* Only try and allocate irqs on cpus that are present */
1181 err = -ENOSPC;
1182 for_each_cpu_and(cpu, mask, cpu_online_mask) {
1183 int new_cpu;
1184 int vector, offset;
1185
1186 apic->vector_allocation_domain(cpu, tmp_mask);
1187
1188 vector = current_vector;
1189 offset = current_offset;
1190 next:
1191 vector += 8;
1192 if (vector >= first_system_vector) {
1193 /* If out of vectors on large boxen, must share them. */
1194 offset = (offset + 1) % 8;
1195 vector = FIRST_DEVICE_VECTOR + offset;
1196 }
1197 if (unlikely(current_vector == vector))
1198 continue;
1199
1200 if (test_bit(vector, used_vectors))
1201 goto next;
1202
1203 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1204 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
1205 goto next;
1206 /* Found one! */
1207 current_vector = vector;
1208 current_offset = offset;
1209 if (old_vector) {
1210 cfg->move_in_progress = 1;
1211 cpumask_copy(cfg->old_domain, cfg->domain);
1212 }
1213 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1214 per_cpu(vector_irq, new_cpu)[vector] = irq;
1215 cfg->vector = vector;
1216 cpumask_copy(cfg->domain, tmp_mask);
1217 err = 0;
1218 break;
1219 }
1220 free_cpumask_var(tmp_mask);
1221 return err;
1222 }
1223
1224 int assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1225 {
1226 int err;
1227 unsigned long flags;
1228
1229 spin_lock_irqsave(&vector_lock, flags);
1230 err = __assign_irq_vector(irq, cfg, mask);
1231 spin_unlock_irqrestore(&vector_lock, flags);
1232 return err;
1233 }
1234
1235 static void __clear_irq_vector(int irq, struct irq_cfg *cfg)
1236 {
1237 int cpu, vector;
1238
1239 BUG_ON(!cfg->vector);
1240
1241 vector = cfg->vector;
1242 for_each_cpu_and(cpu, cfg->domain, cpu_online_mask)
1243 per_cpu(vector_irq, cpu)[vector] = -1;
1244
1245 cfg->vector = 0;
1246 cpumask_clear(cfg->domain);
1247
1248 if (likely(!cfg->move_in_progress))
1249 return;
1250 for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) {
1251 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS;
1252 vector++) {
1253 if (per_cpu(vector_irq, cpu)[vector] != irq)
1254 continue;
1255 per_cpu(vector_irq, cpu)[vector] = -1;
1256 break;
1257 }
1258 }
1259 cfg->move_in_progress = 0;
1260 }
1261
1262 void __setup_vector_irq(int cpu)
1263 {
1264 /* Initialize vector_irq on a new cpu */
1265 /* This function must be called with vector_lock held */
1266 int irq, vector;
1267 struct irq_cfg *cfg;
1268 struct irq_desc *desc;
1269
1270 /* Mark the inuse vectors */
1271 for_each_irq_desc(irq, desc) {
1272 cfg = desc->chip_data;
1273 if (!cpumask_test_cpu(cpu, cfg->domain))
1274 continue;
1275 vector = cfg->vector;
1276 per_cpu(vector_irq, cpu)[vector] = irq;
1277 }
1278 /* Mark the free vectors */
1279 for (vector = 0; vector < NR_VECTORS; ++vector) {
1280 irq = per_cpu(vector_irq, cpu)[vector];
1281 if (irq < 0)
1282 continue;
1283
1284 cfg = irq_cfg(irq);
1285 if (!cpumask_test_cpu(cpu, cfg->domain))
1286 per_cpu(vector_irq, cpu)[vector] = -1;
1287 }
1288 }
1289
1290 static struct irq_chip ioapic_chip;
1291 static struct irq_chip ir_ioapic_chip;
1292
1293 #define IOAPIC_AUTO -1
1294 #define IOAPIC_EDGE 0
1295 #define IOAPIC_LEVEL 1
1296
1297 #ifdef CONFIG_X86_32
1298 static inline int IO_APIC_irq_trigger(int irq)
1299 {
1300 int apic, idx, pin;
1301
1302 for (apic = 0; apic < nr_ioapics; apic++) {
1303 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1304 idx = find_irq_entry(apic, pin, mp_INT);
1305 if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
1306 return irq_trigger(idx);
1307 }
1308 }
1309 /*
1310 * nonexistent IRQs are edge default
1311 */
1312 return 0;
1313 }
1314 #else
1315 static inline int IO_APIC_irq_trigger(int irq)
1316 {
1317 return 1;
1318 }
1319 #endif
1320
1321 static void ioapic_register_intr(int irq, struct irq_desc *desc, unsigned long trigger)
1322 {
1323
1324 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1325 trigger == IOAPIC_LEVEL)
1326 desc->status |= IRQ_LEVEL;
1327 else
1328 desc->status &= ~IRQ_LEVEL;
1329
1330 if (irq_remapped(irq)) {
1331 desc->status |= IRQ_MOVE_PCNTXT;
1332 if (trigger)
1333 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1334 handle_fasteoi_irq,
1335 "fasteoi");
1336 else
1337 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1338 handle_edge_irq, "edge");
1339 return;
1340 }
1341
1342 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1343 trigger == IOAPIC_LEVEL)
1344 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1345 handle_fasteoi_irq,
1346 "fasteoi");
1347 else
1348 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1349 handle_edge_irq, "edge");
1350 }
1351
1352 int setup_ioapic_entry(int apic_id, int irq,
1353 struct IO_APIC_route_entry *entry,
1354 unsigned int destination, int trigger,
1355 int polarity, int vector, int pin)
1356 {
1357 /*
1358 * add it to the IO-APIC irq-routing table:
1359 */
1360 memset(entry,0,sizeof(*entry));
1361
1362 if (intr_remapping_enabled) {
1363 struct intel_iommu *iommu = map_ioapic_to_ir(apic_id);
1364 struct irte irte;
1365 struct IR_IO_APIC_route_entry *ir_entry =
1366 (struct IR_IO_APIC_route_entry *) entry;
1367 int index;
1368
1369 if (!iommu)
1370 panic("No mapping iommu for ioapic %d\n", apic_id);
1371
1372 index = alloc_irte(iommu, irq, 1);
1373 if (index < 0)
1374 panic("Failed to allocate IRTE for ioapic %d\n", apic_id);
1375
1376 memset(&irte, 0, sizeof(irte));
1377
1378 irte.present = 1;
1379 irte.dst_mode = apic->irq_dest_mode;
1380 /*
1381 * Trigger mode in the IRTE will always be edge, and the
1382 * actual level or edge trigger will be setup in the IO-APIC
1383 * RTE. This will help simplify level triggered irq migration.
1384 * For more details, see the comments above explainig IO-APIC
1385 * irq migration in the presence of interrupt-remapping.
1386 */
1387 irte.trigger_mode = 0;
1388 irte.dlvry_mode = apic->irq_delivery_mode;
1389 irte.vector = vector;
1390 irte.dest_id = IRTE_DEST(destination);
1391
1392 /* Set source-id of interrupt request */
1393 set_ioapic_sid(&irte, apic_id);
1394
1395 modify_irte(irq, &irte);
1396
1397 ir_entry->index2 = (index >> 15) & 0x1;
1398 ir_entry->zero = 0;
1399 ir_entry->format = 1;
1400 ir_entry->index = (index & 0x7fff);
1401 /*
1402 * IO-APIC RTE will be configured with virtual vector.
1403 * irq handler will do the explicit EOI to the io-apic.
1404 */
1405 ir_entry->vector = pin;
1406 } else {
1407 entry->delivery_mode = apic->irq_delivery_mode;
1408 entry->dest_mode = apic->irq_dest_mode;
1409 entry->dest = destination;
1410 entry->vector = vector;
1411 }
1412
1413 entry->mask = 0; /* enable IRQ */
1414 entry->trigger = trigger;
1415 entry->polarity = polarity;
1416
1417 /* Mask level triggered irqs.
1418 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1419 */
1420 if (trigger)
1421 entry->mask = 1;
1422 return 0;
1423 }
1424
1425 static void setup_IO_APIC_irq(int apic_id, int pin, unsigned int irq, struct irq_desc *desc,
1426 int trigger, int polarity)
1427 {
1428 struct irq_cfg *cfg;
1429 struct IO_APIC_route_entry entry;
1430 unsigned int dest;
1431
1432 if (!IO_APIC_IRQ(irq))
1433 return;
1434
1435 cfg = desc->chip_data;
1436
1437 if (assign_irq_vector(irq, cfg, apic->target_cpus()))
1438 return;
1439
1440 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
1441
1442 apic_printk(APIC_VERBOSE,KERN_DEBUG
1443 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1444 "IRQ %d Mode:%i Active:%i)\n",
1445 apic_id, mp_ioapics[apic_id].apicid, pin, cfg->vector,
1446 irq, trigger, polarity);
1447
1448
1449 if (setup_ioapic_entry(mp_ioapics[apic_id].apicid, irq, &entry,
1450 dest, trigger, polarity, cfg->vector, pin)) {
1451 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1452 mp_ioapics[apic_id].apicid, pin);
1453 __clear_irq_vector(irq, cfg);
1454 return;
1455 }
1456
1457 ioapic_register_intr(irq, desc, trigger);
1458 if (irq < nr_legacy_irqs)
1459 disable_8259A_irq(irq);
1460
1461 ioapic_write_entry(apic_id, pin, entry);
1462 }
1463
1464 static struct {
1465 DECLARE_BITMAP(pin_programmed, MP_MAX_IOAPIC_PIN + 1);
1466 } mp_ioapic_routing[MAX_IO_APICS];
1467
1468 static void __init setup_IO_APIC_irqs(void)
1469 {
1470 int apic_id = 0, pin, idx, irq;
1471 int notcon = 0;
1472 struct irq_desc *desc;
1473 struct irq_cfg *cfg;
1474 int node = cpu_to_node(boot_cpu_id);
1475
1476 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1477
1478 #ifdef CONFIG_ACPI
1479 if (!acpi_disabled && acpi_ioapic) {
1480 apic_id = mp_find_ioapic(0);
1481 if (apic_id < 0)
1482 apic_id = 0;
1483 }
1484 #endif
1485
1486 for (pin = 0; pin < nr_ioapic_registers[apic_id]; pin++) {
1487 idx = find_irq_entry(apic_id, pin, mp_INT);
1488 if (idx == -1) {
1489 if (!notcon) {
1490 notcon = 1;
1491 apic_printk(APIC_VERBOSE,
1492 KERN_DEBUG " %d-%d",
1493 mp_ioapics[apic_id].apicid, pin);
1494 } else
1495 apic_printk(APIC_VERBOSE, " %d-%d",
1496 mp_ioapics[apic_id].apicid, pin);
1497 continue;
1498 }
1499 if (notcon) {
1500 apic_printk(APIC_VERBOSE,
1501 " (apicid-pin) not connected\n");
1502 notcon = 0;
1503 }
1504
1505 irq = pin_2_irq(idx, apic_id, pin);
1506
1507 /*
1508 * Skip the timer IRQ if there's a quirk handler
1509 * installed and if it returns 1:
1510 */
1511 if (apic->multi_timer_check &&
1512 apic->multi_timer_check(apic_id, irq))
1513 continue;
1514
1515 desc = irq_to_desc_alloc_node(irq, node);
1516 if (!desc) {
1517 printk(KERN_INFO "can not get irq_desc for %d\n", irq);
1518 continue;
1519 }
1520 cfg = desc->chip_data;
1521 add_pin_to_irq_node(cfg, node, apic_id, pin);
1522 /*
1523 * don't mark it in pin_programmed, so later acpi could
1524 * set it correctly when irq < 16
1525 */
1526 setup_IO_APIC_irq(apic_id, pin, irq, desc,
1527 irq_trigger(idx), irq_polarity(idx));
1528 }
1529
1530 if (notcon)
1531 apic_printk(APIC_VERBOSE,
1532 " (apicid-pin) not connected\n");
1533 }
1534
1535 /*
1536 * Set up the timer pin, possibly with the 8259A-master behind.
1537 */
1538 static void __init setup_timer_IRQ0_pin(unsigned int apic_id, unsigned int pin,
1539 int vector)
1540 {
1541 struct IO_APIC_route_entry entry;
1542
1543 if (intr_remapping_enabled)
1544 return;
1545
1546 memset(&entry, 0, sizeof(entry));
1547
1548 /*
1549 * We use logical delivery to get the timer IRQ
1550 * to the first CPU.
1551 */
1552 entry.dest_mode = apic->irq_dest_mode;
1553 entry.mask = 0; /* don't mask IRQ for edge */
1554 entry.dest = apic->cpu_mask_to_apicid(apic->target_cpus());
1555 entry.delivery_mode = apic->irq_delivery_mode;
1556 entry.polarity = 0;
1557 entry.trigger = 0;
1558 entry.vector = vector;
1559
1560 /*
1561 * The timer IRQ doesn't have to know that behind the
1562 * scene we may have a 8259A-master in AEOI mode ...
1563 */
1564 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
1565
1566 /*
1567 * Add it to the IO-APIC irq-routing table:
1568 */
1569 ioapic_write_entry(apic_id, pin, entry);
1570 }
1571
1572
1573 __apicdebuginit(void) print_IO_APIC(void)
1574 {
1575 int apic, i;
1576 union IO_APIC_reg_00 reg_00;
1577 union IO_APIC_reg_01 reg_01;
1578 union IO_APIC_reg_02 reg_02;
1579 union IO_APIC_reg_03 reg_03;
1580 unsigned long flags;
1581 struct irq_cfg *cfg;
1582 struct irq_desc *desc;
1583 unsigned int irq;
1584
1585 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1586 for (i = 0; i < nr_ioapics; i++)
1587 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1588 mp_ioapics[i].apicid, nr_ioapic_registers[i]);
1589
1590 /*
1591 * We are a bit conservative about what we expect. We have to
1592 * know about every hardware change ASAP.
1593 */
1594 printk(KERN_INFO "testing the IO APIC.......................\n");
1595
1596 for (apic = 0; apic < nr_ioapics; apic++) {
1597
1598 spin_lock_irqsave(&ioapic_lock, flags);
1599 reg_00.raw = io_apic_read(apic, 0);
1600 reg_01.raw = io_apic_read(apic, 1);
1601 if (reg_01.bits.version >= 0x10)
1602 reg_02.raw = io_apic_read(apic, 2);
1603 if (reg_01.bits.version >= 0x20)
1604 reg_03.raw = io_apic_read(apic, 3);
1605 spin_unlock_irqrestore(&ioapic_lock, flags);
1606
1607 printk("\n");
1608 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].apicid);
1609 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1610 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1611 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1612 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1613
1614 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
1615 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1616
1617 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1618 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1619
1620 /*
1621 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1622 * but the value of reg_02 is read as the previous read register
1623 * value, so ignore it if reg_02 == reg_01.
1624 */
1625 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1626 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1627 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1628 }
1629
1630 /*
1631 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1632 * or reg_03, but the value of reg_0[23] is read as the previous read
1633 * register value, so ignore it if reg_03 == reg_0[12].
1634 */
1635 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1636 reg_03.raw != reg_01.raw) {
1637 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1638 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1639 }
1640
1641 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1642
1643 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1644 " Stat Dmod Deli Vect: \n");
1645
1646 for (i = 0; i <= reg_01.bits.entries; i++) {
1647 struct IO_APIC_route_entry entry;
1648
1649 entry = ioapic_read_entry(apic, i);
1650
1651 printk(KERN_DEBUG " %02x %03X ",
1652 i,
1653 entry.dest
1654 );
1655
1656 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1657 entry.mask,
1658 entry.trigger,
1659 entry.irr,
1660 entry.polarity,
1661 entry.delivery_status,
1662 entry.dest_mode,
1663 entry.delivery_mode,
1664 entry.vector
1665 );
1666 }
1667 }
1668 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1669 for_each_irq_desc(irq, desc) {
1670 struct irq_pin_list *entry;
1671
1672 cfg = desc->chip_data;
1673 entry = cfg->irq_2_pin;
1674 if (!entry)
1675 continue;
1676 printk(KERN_DEBUG "IRQ%d ", irq);
1677 for_each_irq_pin(entry, cfg->irq_2_pin)
1678 printk("-> %d:%d", entry->apic, entry->pin);
1679 printk("\n");
1680 }
1681
1682 printk(KERN_INFO ".................................... done.\n");
1683
1684 return;
1685 }
1686
1687 __apicdebuginit(void) print_APIC_field(int base)
1688 {
1689 int i;
1690
1691 printk(KERN_DEBUG);
1692
1693 for (i = 0; i < 8; i++)
1694 printk(KERN_CONT "%08x", apic_read(base + i*0x10));
1695
1696 printk(KERN_CONT "\n");
1697 }
1698
1699 __apicdebuginit(void) print_local_APIC(void *dummy)
1700 {
1701 unsigned int i, v, ver, maxlvt;
1702 u64 icr;
1703
1704 printk(KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1705 smp_processor_id(), hard_smp_processor_id());
1706 v = apic_read(APIC_ID);
1707 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id());
1708 v = apic_read(APIC_LVR);
1709 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1710 ver = GET_APIC_VERSION(v);
1711 maxlvt = lapic_get_maxlvt();
1712
1713 v = apic_read(APIC_TASKPRI);
1714 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1715
1716 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1717 if (!APIC_XAPIC(ver)) {
1718 v = apic_read(APIC_ARBPRI);
1719 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1720 v & APIC_ARBPRI_MASK);
1721 }
1722 v = apic_read(APIC_PROCPRI);
1723 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1724 }
1725
1726 /*
1727 * Remote read supported only in the 82489DX and local APIC for
1728 * Pentium processors.
1729 */
1730 if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
1731 v = apic_read(APIC_RRR);
1732 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1733 }
1734
1735 v = apic_read(APIC_LDR);
1736 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1737 if (!x2apic_enabled()) {
1738 v = apic_read(APIC_DFR);
1739 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1740 }
1741 v = apic_read(APIC_SPIV);
1742 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1743
1744 printk(KERN_DEBUG "... APIC ISR field:\n");
1745 print_APIC_field(APIC_ISR);
1746 printk(KERN_DEBUG "... APIC TMR field:\n");
1747 print_APIC_field(APIC_TMR);
1748 printk(KERN_DEBUG "... APIC IRR field:\n");
1749 print_APIC_field(APIC_IRR);
1750
1751 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1752 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1753 apic_write(APIC_ESR, 0);
1754
1755 v = apic_read(APIC_ESR);
1756 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1757 }
1758
1759 icr = apic_icr_read();
1760 printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr);
1761 printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32));
1762
1763 v = apic_read(APIC_LVTT);
1764 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1765
1766 if (maxlvt > 3) { /* PC is LVT#4. */
1767 v = apic_read(APIC_LVTPC);
1768 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1769 }
1770 v = apic_read(APIC_LVT0);
1771 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1772 v = apic_read(APIC_LVT1);
1773 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1774
1775 if (maxlvt > 2) { /* ERR is LVT#3. */
1776 v = apic_read(APIC_LVTERR);
1777 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1778 }
1779
1780 v = apic_read(APIC_TMICT);
1781 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1782 v = apic_read(APIC_TMCCT);
1783 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1784 v = apic_read(APIC_TDCR);
1785 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1786
1787 if (boot_cpu_has(X86_FEATURE_EXTAPIC)) {
1788 v = apic_read(APIC_EFEAT);
1789 maxlvt = (v >> 16) & 0xff;
1790 printk(KERN_DEBUG "... APIC EFEAT: %08x\n", v);
1791 v = apic_read(APIC_ECTRL);
1792 printk(KERN_DEBUG "... APIC ECTRL: %08x\n", v);
1793 for (i = 0; i < maxlvt; i++) {
1794 v = apic_read(APIC_EILVTn(i));
1795 printk(KERN_DEBUG "... APIC EILVT%d: %08x\n", i, v);
1796 }
1797 }
1798 printk("\n");
1799 }
1800
1801 __apicdebuginit(void) print_local_APICs(int maxcpu)
1802 {
1803 int cpu;
1804
1805 if (!maxcpu)
1806 return;
1807
1808 preempt_disable();
1809 for_each_online_cpu(cpu) {
1810 if (cpu >= maxcpu)
1811 break;
1812 smp_call_function_single(cpu, print_local_APIC, NULL, 1);
1813 }
1814 preempt_enable();
1815 }
1816
1817 __apicdebuginit(void) print_PIC(void)
1818 {
1819 unsigned int v;
1820 unsigned long flags;
1821
1822 if (!nr_legacy_irqs)
1823 return;
1824
1825 printk(KERN_DEBUG "\nprinting PIC contents\n");
1826
1827 spin_lock_irqsave(&i8259A_lock, flags);
1828
1829 v = inb(0xa1) << 8 | inb(0x21);
1830 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1831
1832 v = inb(0xa0) << 8 | inb(0x20);
1833 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1834
1835 outb(0x0b,0xa0);
1836 outb(0x0b,0x20);
1837 v = inb(0xa0) << 8 | inb(0x20);
1838 outb(0x0a,0xa0);
1839 outb(0x0a,0x20);
1840
1841 spin_unlock_irqrestore(&i8259A_lock, flags);
1842
1843 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1844
1845 v = inb(0x4d1) << 8 | inb(0x4d0);
1846 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1847 }
1848
1849 static int __initdata show_lapic = 1;
1850 static __init int setup_show_lapic(char *arg)
1851 {
1852 int num = -1;
1853
1854 if (strcmp(arg, "all") == 0) {
1855 show_lapic = CONFIG_NR_CPUS;
1856 } else {
1857 get_option(&arg, &num);
1858 if (num >= 0)
1859 show_lapic = num;
1860 }
1861
1862 return 1;
1863 }
1864 __setup("show_lapic=", setup_show_lapic);
1865
1866 __apicdebuginit(int) print_ICs(void)
1867 {
1868 if (apic_verbosity == APIC_QUIET)
1869 return 0;
1870
1871 print_PIC();
1872
1873 /* don't print out if apic is not there */
1874 if (!cpu_has_apic && !apic_from_smp_config())
1875 return 0;
1876
1877 print_local_APICs(show_lapic);
1878 print_IO_APIC();
1879
1880 return 0;
1881 }
1882
1883 fs_initcall(print_ICs);
1884
1885
1886 /* Where if anywhere is the i8259 connect in external int mode */
1887 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1888
1889 void __init enable_IO_APIC(void)
1890 {
1891 union IO_APIC_reg_01 reg_01;
1892 int i8259_apic, i8259_pin;
1893 int apic;
1894 unsigned long flags;
1895
1896 /*
1897 * The number of IO-APIC IRQ registers (== #pins):
1898 */
1899 for (apic = 0; apic < nr_ioapics; apic++) {
1900 spin_lock_irqsave(&ioapic_lock, flags);
1901 reg_01.raw = io_apic_read(apic, 1);
1902 spin_unlock_irqrestore(&ioapic_lock, flags);
1903 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1904 }
1905
1906 if (!nr_legacy_irqs)
1907 return;
1908
1909 for(apic = 0; apic < nr_ioapics; apic++) {
1910 int pin;
1911 /* See if any of the pins is in ExtINT mode */
1912 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1913 struct IO_APIC_route_entry entry;
1914 entry = ioapic_read_entry(apic, pin);
1915
1916 /* If the interrupt line is enabled and in ExtInt mode
1917 * I have found the pin where the i8259 is connected.
1918 */
1919 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1920 ioapic_i8259.apic = apic;
1921 ioapic_i8259.pin = pin;
1922 goto found_i8259;
1923 }
1924 }
1925 }
1926 found_i8259:
1927 /* Look to see what if the MP table has reported the ExtINT */
1928 /* If we could not find the appropriate pin by looking at the ioapic
1929 * the i8259 probably is not connected the ioapic but give the
1930 * mptable a chance anyway.
1931 */
1932 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1933 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1934 /* Trust the MP table if nothing is setup in the hardware */
1935 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1936 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1937 ioapic_i8259.pin = i8259_pin;
1938 ioapic_i8259.apic = i8259_apic;
1939 }
1940 /* Complain if the MP table and the hardware disagree */
1941 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1942 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1943 {
1944 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1945 }
1946
1947 /*
1948 * Do not trust the IO-APIC being empty at bootup
1949 */
1950 clear_IO_APIC();
1951 }
1952
1953 /*
1954 * Not an __init, needed by the reboot code
1955 */
1956 void disable_IO_APIC(void)
1957 {
1958 /*
1959 * Clear the IO-APIC before rebooting:
1960 */
1961 clear_IO_APIC();
1962
1963 if (!nr_legacy_irqs)
1964 return;
1965
1966 /*
1967 * If the i8259 is routed through an IOAPIC
1968 * Put that IOAPIC in virtual wire mode
1969 * so legacy interrupts can be delivered.
1970 *
1971 * With interrupt-remapping, for now we will use virtual wire A mode,
1972 * as virtual wire B is little complex (need to configure both
1973 * IOAPIC RTE aswell as interrupt-remapping table entry).
1974 * As this gets called during crash dump, keep this simple for now.
1975 */
1976 if (ioapic_i8259.pin != -1 && !intr_remapping_enabled) {
1977 struct IO_APIC_route_entry entry;
1978
1979 memset(&entry, 0, sizeof(entry));
1980 entry.mask = 0; /* Enabled */
1981 entry.trigger = 0; /* Edge */
1982 entry.irr = 0;
1983 entry.polarity = 0; /* High */
1984 entry.delivery_status = 0;
1985 entry.dest_mode = 0; /* Physical */
1986 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1987 entry.vector = 0;
1988 entry.dest = read_apic_id();
1989
1990 /*
1991 * Add it to the IO-APIC irq-routing table:
1992 */
1993 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1994 }
1995
1996 /*
1997 * Use virtual wire A mode when interrupt remapping is enabled.
1998 */
1999 if (cpu_has_apic || apic_from_smp_config())
2000 disconnect_bsp_APIC(!intr_remapping_enabled &&
2001 ioapic_i8259.pin != -1);
2002 }
2003
2004 #ifdef CONFIG_X86_32
2005 /*
2006 * function to set the IO-APIC physical IDs based on the
2007 * values stored in the MPC table.
2008 *
2009 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
2010 */
2011
2012 void __init setup_ioapic_ids_from_mpc(void)
2013 {
2014 union IO_APIC_reg_00 reg_00;
2015 physid_mask_t phys_id_present_map;
2016 int apic_id;
2017 int i;
2018 unsigned char old_id;
2019 unsigned long flags;
2020
2021 if (acpi_ioapic)
2022 return;
2023 /*
2024 * Don't check I/O APIC IDs for xAPIC systems. They have
2025 * no meaning without the serial APIC bus.
2026 */
2027 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
2028 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
2029 return;
2030 /*
2031 * This is broken; anything with a real cpu count has to
2032 * circumvent this idiocy regardless.
2033 */
2034 phys_id_present_map = apic->ioapic_phys_id_map(phys_cpu_present_map);
2035
2036 /*
2037 * Set the IOAPIC ID to the value stored in the MPC table.
2038 */
2039 for (apic_id = 0; apic_id < nr_ioapics; apic_id++) {
2040
2041 /* Read the register 0 value */
2042 spin_lock_irqsave(&ioapic_lock, flags);
2043 reg_00.raw = io_apic_read(apic_id, 0);
2044 spin_unlock_irqrestore(&ioapic_lock, flags);
2045
2046 old_id = mp_ioapics[apic_id].apicid;
2047
2048 if (mp_ioapics[apic_id].apicid >= get_physical_broadcast()) {
2049 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
2050 apic_id, mp_ioapics[apic_id].apicid);
2051 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2052 reg_00.bits.ID);
2053 mp_ioapics[apic_id].apicid = reg_00.bits.ID;
2054 }
2055
2056 /*
2057 * Sanity check, is the ID really free? Every APIC in a
2058 * system must have a unique ID or we get lots of nice
2059 * 'stuck on smp_invalidate_needed IPI wait' messages.
2060 */
2061 if (apic->check_apicid_used(phys_id_present_map,
2062 mp_ioapics[apic_id].apicid)) {
2063 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
2064 apic_id, mp_ioapics[apic_id].apicid);
2065 for (i = 0; i < get_physical_broadcast(); i++)
2066 if (!physid_isset(i, phys_id_present_map))
2067 break;
2068 if (i >= get_physical_broadcast())
2069 panic("Max APIC ID exceeded!\n");
2070 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2071 i);
2072 physid_set(i, phys_id_present_map);
2073 mp_ioapics[apic_id].apicid = i;
2074 } else {
2075 physid_mask_t tmp;
2076 tmp = apic->apicid_to_cpu_present(mp_ioapics[apic_id].apicid);
2077 apic_printk(APIC_VERBOSE, "Setting %d in the "
2078 "phys_id_present_map\n",
2079 mp_ioapics[apic_id].apicid);
2080 physids_or(phys_id_present_map, phys_id_present_map, tmp);
2081 }
2082
2083
2084 /*
2085 * We need to adjust the IRQ routing table
2086 * if the ID changed.
2087 */
2088 if (old_id != mp_ioapics[apic_id].apicid)
2089 for (i = 0; i < mp_irq_entries; i++)
2090 if (mp_irqs[i].dstapic == old_id)
2091 mp_irqs[i].dstapic
2092 = mp_ioapics[apic_id].apicid;
2093
2094 /*
2095 * Read the right value from the MPC table and
2096 * write it into the ID register.
2097 */
2098 apic_printk(APIC_VERBOSE, KERN_INFO
2099 "...changing IO-APIC physical APIC ID to %d ...",
2100 mp_ioapics[apic_id].apicid);
2101
2102 reg_00.bits.ID = mp_ioapics[apic_id].apicid;
2103 spin_lock_irqsave(&ioapic_lock, flags);
2104 io_apic_write(apic_id, 0, reg_00.raw);
2105 spin_unlock_irqrestore(&ioapic_lock, flags);
2106
2107 /*
2108 * Sanity check
2109 */
2110 spin_lock_irqsave(&ioapic_lock, flags);
2111 reg_00.raw = io_apic_read(apic_id, 0);
2112 spin_unlock_irqrestore(&ioapic_lock, flags);
2113 if (reg_00.bits.ID != mp_ioapics[apic_id].apicid)
2114 printk("could not set ID!\n");
2115 else
2116 apic_printk(APIC_VERBOSE, " ok.\n");
2117 }
2118 }
2119 #endif
2120
2121 int no_timer_check __initdata;
2122
2123 static int __init notimercheck(char *s)
2124 {
2125 no_timer_check = 1;
2126 return 1;
2127 }
2128 __setup("no_timer_check", notimercheck);
2129
2130 /*
2131 * There is a nasty bug in some older SMP boards, their mptable lies
2132 * about the timer IRQ. We do the following to work around the situation:
2133 *
2134 * - timer IRQ defaults to IO-APIC IRQ
2135 * - if this function detects that timer IRQs are defunct, then we fall
2136 * back to ISA timer IRQs
2137 */
2138 static int __init timer_irq_works(void)
2139 {
2140 unsigned long t1 = jiffies;
2141 unsigned long flags;
2142
2143 if (no_timer_check)
2144 return 1;
2145
2146 local_save_flags(flags);
2147 local_irq_enable();
2148 /* Let ten ticks pass... */
2149 mdelay((10 * 1000) / HZ);
2150 local_irq_restore(flags);
2151
2152 /*
2153 * Expect a few ticks at least, to be sure some possible
2154 * glue logic does not lock up after one or two first
2155 * ticks in a non-ExtINT mode. Also the local APIC
2156 * might have cached one ExtINT interrupt. Finally, at
2157 * least one tick may be lost due to delays.
2158 */
2159
2160 /* jiffies wrap? */
2161 if (time_after(jiffies, t1 + 4))
2162 return 1;
2163 return 0;
2164 }
2165
2166 /*
2167 * In the SMP+IOAPIC case it might happen that there are an unspecified
2168 * number of pending IRQ events unhandled. These cases are very rare,
2169 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2170 * better to do it this way as thus we do not have to be aware of
2171 * 'pending' interrupts in the IRQ path, except at this point.
2172 */
2173 /*
2174 * Edge triggered needs to resend any interrupt
2175 * that was delayed but this is now handled in the device
2176 * independent code.
2177 */
2178
2179 /*
2180 * Starting up a edge-triggered IO-APIC interrupt is
2181 * nasty - we need to make sure that we get the edge.
2182 * If it is already asserted for some reason, we need
2183 * return 1 to indicate that is was pending.
2184 *
2185 * This is not complete - we should be able to fake
2186 * an edge even if it isn't on the 8259A...
2187 */
2188
2189 static unsigned int startup_ioapic_irq(unsigned int irq)
2190 {
2191 int was_pending = 0;
2192 unsigned long flags;
2193 struct irq_cfg *cfg;
2194
2195 spin_lock_irqsave(&ioapic_lock, flags);
2196 if (irq < nr_legacy_irqs) {
2197 disable_8259A_irq(irq);
2198 if (i8259A_irq_pending(irq))
2199 was_pending = 1;
2200 }
2201 cfg = irq_cfg(irq);
2202 __unmask_IO_APIC_irq(cfg);
2203 spin_unlock_irqrestore(&ioapic_lock, flags);
2204
2205 return was_pending;
2206 }
2207
2208 static int ioapic_retrigger_irq(unsigned int irq)
2209 {
2210
2211 struct irq_cfg *cfg = irq_cfg(irq);
2212 unsigned long flags;
2213
2214 spin_lock_irqsave(&vector_lock, flags);
2215 apic->send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector);
2216 spin_unlock_irqrestore(&vector_lock, flags);
2217
2218 return 1;
2219 }
2220
2221 /*
2222 * Level and edge triggered IO-APIC interrupts need different handling,
2223 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2224 * handled with the level-triggered descriptor, but that one has slightly
2225 * more overhead. Level-triggered interrupts cannot be handled with the
2226 * edge-triggered handler, without risking IRQ storms and other ugly
2227 * races.
2228 */
2229
2230 #ifdef CONFIG_SMP
2231 void send_cleanup_vector(struct irq_cfg *cfg)
2232 {
2233 cpumask_var_t cleanup_mask;
2234
2235 if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) {
2236 unsigned int i;
2237 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
2238 apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR);
2239 } else {
2240 cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask);
2241 apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
2242 free_cpumask_var(cleanup_mask);
2243 }
2244 cfg->move_in_progress = 0;
2245 }
2246
2247 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg)
2248 {
2249 int apic, pin;
2250 struct irq_pin_list *entry;
2251 u8 vector = cfg->vector;
2252
2253 for_each_irq_pin(entry, cfg->irq_2_pin) {
2254 unsigned int reg;
2255
2256 apic = entry->apic;
2257 pin = entry->pin;
2258 /*
2259 * With interrupt-remapping, destination information comes
2260 * from interrupt-remapping table entry.
2261 */
2262 if (!irq_remapped(irq))
2263 io_apic_write(apic, 0x11 + pin*2, dest);
2264 reg = io_apic_read(apic, 0x10 + pin*2);
2265 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
2266 reg |= vector;
2267 io_apic_modify(apic, 0x10 + pin*2, reg);
2268 }
2269 }
2270
2271 /*
2272 * Either sets desc->affinity to a valid value, and returns
2273 * ->cpu_mask_to_apicid of that, or returns BAD_APICID and
2274 * leaves desc->affinity untouched.
2275 */
2276 unsigned int
2277 set_desc_affinity(struct irq_desc *desc, const struct cpumask *mask)
2278 {
2279 struct irq_cfg *cfg;
2280 unsigned int irq;
2281
2282 if (!cpumask_intersects(mask, cpu_online_mask))
2283 return BAD_APICID;
2284
2285 irq = desc->irq;
2286 cfg = desc->chip_data;
2287 if (assign_irq_vector(irq, cfg, mask))
2288 return BAD_APICID;
2289
2290 cpumask_copy(desc->affinity, mask);
2291
2292 return apic->cpu_mask_to_apicid_and(desc->affinity, cfg->domain);
2293 }
2294
2295 static int
2296 set_ioapic_affinity_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
2297 {
2298 struct irq_cfg *cfg;
2299 unsigned long flags;
2300 unsigned int dest;
2301 unsigned int irq;
2302 int ret = -1;
2303
2304 irq = desc->irq;
2305 cfg = desc->chip_data;
2306
2307 spin_lock_irqsave(&ioapic_lock, flags);
2308 dest = set_desc_affinity(desc, mask);
2309 if (dest != BAD_APICID) {
2310 /* Only the high 8 bits are valid. */
2311 dest = SET_APIC_LOGICAL_ID(dest);
2312 __target_IO_APIC_irq(irq, dest, cfg);
2313 ret = 0;
2314 }
2315 spin_unlock_irqrestore(&ioapic_lock, flags);
2316
2317 return ret;
2318 }
2319
2320 static int
2321 set_ioapic_affinity_irq(unsigned int irq, const struct cpumask *mask)
2322 {
2323 struct irq_desc *desc;
2324
2325 desc = irq_to_desc(irq);
2326
2327 return set_ioapic_affinity_irq_desc(desc, mask);
2328 }
2329
2330 #ifdef CONFIG_INTR_REMAP
2331
2332 /*
2333 * Migrate the IO-APIC irq in the presence of intr-remapping.
2334 *
2335 * For both level and edge triggered, irq migration is a simple atomic
2336 * update(of vector and cpu destination) of IRTE and flush the hardware cache.
2337 *
2338 * For level triggered, we eliminate the io-apic RTE modification (with the
2339 * updated vector information), by using a virtual vector (io-apic pin number).
2340 * Real vector that is used for interrupting cpu will be coming from
2341 * the interrupt-remapping table entry.
2342 */
2343 static int
2344 migrate_ioapic_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
2345 {
2346 struct irq_cfg *cfg;
2347 struct irte irte;
2348 unsigned int dest;
2349 unsigned int irq;
2350 int ret = -1;
2351
2352 if (!cpumask_intersects(mask, cpu_online_mask))
2353 return ret;
2354
2355 irq = desc->irq;
2356 if (get_irte(irq, &irte))
2357 return ret;
2358
2359 cfg = desc->chip_data;
2360 if (assign_irq_vector(irq, cfg, mask))
2361 return ret;
2362
2363 dest = apic->cpu_mask_to_apicid_and(cfg->domain, mask);
2364
2365 irte.vector = cfg->vector;
2366 irte.dest_id = IRTE_DEST(dest);
2367
2368 /*
2369 * Modified the IRTE and flushes the Interrupt entry cache.
2370 */
2371 modify_irte(irq, &irte);
2372
2373 if (cfg->move_in_progress)
2374 send_cleanup_vector(cfg);
2375
2376 cpumask_copy(desc->affinity, mask);
2377
2378 return 0;
2379 }
2380
2381 /*
2382 * Migrates the IRQ destination in the process context.
2383 */
2384 static int set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc,
2385 const struct cpumask *mask)
2386 {
2387 return migrate_ioapic_irq_desc(desc, mask);
2388 }
2389 static int set_ir_ioapic_affinity_irq(unsigned int irq,
2390 const struct cpumask *mask)
2391 {
2392 struct irq_desc *desc = irq_to_desc(irq);
2393
2394 return set_ir_ioapic_affinity_irq_desc(desc, mask);
2395 }
2396 #else
2397 static inline int set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc,
2398 const struct cpumask *mask)
2399 {
2400 return 0;
2401 }
2402 #endif
2403
2404 asmlinkage void smp_irq_move_cleanup_interrupt(void)
2405 {
2406 unsigned vector, me;
2407
2408 ack_APIC_irq();
2409 exit_idle();
2410 irq_enter();
2411
2412 me = smp_processor_id();
2413 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
2414 unsigned int irq;
2415 unsigned int irr;
2416 struct irq_desc *desc;
2417 struct irq_cfg *cfg;
2418 irq = __get_cpu_var(vector_irq)[vector];
2419
2420 if (irq == -1)
2421 continue;
2422
2423 desc = irq_to_desc(irq);
2424 if (!desc)
2425 continue;
2426
2427 cfg = irq_cfg(irq);
2428 spin_lock(&desc->lock);
2429
2430 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2431 goto unlock;
2432
2433 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
2434 /*
2435 * Check if the vector that needs to be cleanedup is
2436 * registered at the cpu's IRR. If so, then this is not
2437 * the best time to clean it up. Lets clean it up in the
2438 * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
2439 * to myself.
2440 */
2441 if (irr & (1 << (vector % 32))) {
2442 apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR);
2443 goto unlock;
2444 }
2445 __get_cpu_var(vector_irq)[vector] = -1;
2446 unlock:
2447 spin_unlock(&desc->lock);
2448 }
2449
2450 irq_exit();
2451 }
2452
2453 static void __irq_complete_move(struct irq_desc **descp, unsigned vector)
2454 {
2455 struct irq_desc *desc = *descp;
2456 struct irq_cfg *cfg = desc->chip_data;
2457 unsigned me;
2458
2459 if (likely(!cfg->move_in_progress))
2460 return;
2461
2462 me = smp_processor_id();
2463
2464 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2465 send_cleanup_vector(cfg);
2466 }
2467
2468 static void irq_complete_move(struct irq_desc **descp)
2469 {
2470 __irq_complete_move(descp, ~get_irq_regs()->orig_ax);
2471 }
2472
2473 void irq_force_complete_move(int irq)
2474 {
2475 struct irq_desc *desc = irq_to_desc(irq);
2476 struct irq_cfg *cfg = desc->chip_data;
2477
2478 __irq_complete_move(&desc, cfg->vector);
2479 }
2480 #else
2481 static inline void irq_complete_move(struct irq_desc **descp) {}
2482 #endif
2483
2484 static void ack_apic_edge(unsigned int irq)
2485 {
2486 struct irq_desc *desc = irq_to_desc(irq);
2487
2488 irq_complete_move(&desc);
2489 move_native_irq(irq);
2490 ack_APIC_irq();
2491 }
2492
2493 atomic_t irq_mis_count;
2494
2495 static void ack_apic_level(unsigned int irq)
2496 {
2497 struct irq_desc *desc = irq_to_desc(irq);
2498 unsigned long v;
2499 int i;
2500 struct irq_cfg *cfg;
2501 int do_unmask_irq = 0;
2502
2503 irq_complete_move(&desc);
2504 #ifdef CONFIG_GENERIC_PENDING_IRQ
2505 /* If we are moving the irq we need to mask it */
2506 if (unlikely(desc->status & IRQ_MOVE_PENDING)) {
2507 do_unmask_irq = 1;
2508 mask_IO_APIC_irq_desc(desc);
2509 }
2510 #endif
2511
2512 /*
2513 * It appears there is an erratum which affects at least version 0x11
2514 * of I/O APIC (that's the 82093AA and cores integrated into various
2515 * chipsets). Under certain conditions a level-triggered interrupt is
2516 * erroneously delivered as edge-triggered one but the respective IRR
2517 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2518 * message but it will never arrive and further interrupts are blocked
2519 * from the source. The exact reason is so far unknown, but the
2520 * phenomenon was observed when two consecutive interrupt requests
2521 * from a given source get delivered to the same CPU and the source is
2522 * temporarily disabled in between.
2523 *
2524 * A workaround is to simulate an EOI message manually. We achieve it
2525 * by setting the trigger mode to edge and then to level when the edge
2526 * trigger mode gets detected in the TMR of a local APIC for a
2527 * level-triggered interrupt. We mask the source for the time of the
2528 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2529 * The idea is from Manfred Spraul. --macro
2530 */
2531 cfg = desc->chip_data;
2532 i = cfg->vector;
2533 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2534
2535 /*
2536 * We must acknowledge the irq before we move it or the acknowledge will
2537 * not propagate properly.
2538 */
2539 ack_APIC_irq();
2540
2541 /* Now we can move and renable the irq */
2542 if (unlikely(do_unmask_irq)) {
2543 /* Only migrate the irq if the ack has been received.
2544 *
2545 * On rare occasions the broadcast level triggered ack gets
2546 * delayed going to ioapics, and if we reprogram the
2547 * vector while Remote IRR is still set the irq will never
2548 * fire again.
2549 *
2550 * To prevent this scenario we read the Remote IRR bit
2551 * of the ioapic. This has two effects.
2552 * - On any sane system the read of the ioapic will
2553 * flush writes (and acks) going to the ioapic from
2554 * this cpu.
2555 * - We get to see if the ACK has actually been delivered.
2556 *
2557 * Based on failed experiments of reprogramming the
2558 * ioapic entry from outside of irq context starting
2559 * with masking the ioapic entry and then polling until
2560 * Remote IRR was clear before reprogramming the
2561 * ioapic I don't trust the Remote IRR bit to be
2562 * completey accurate.
2563 *
2564 * However there appears to be no other way to plug
2565 * this race, so if the Remote IRR bit is not
2566 * accurate and is causing problems then it is a hardware bug
2567 * and you can go talk to the chipset vendor about it.
2568 */
2569 cfg = desc->chip_data;
2570 if (!io_apic_level_ack_pending(cfg))
2571 move_masked_irq(irq);
2572 unmask_IO_APIC_irq_desc(desc);
2573 }
2574
2575 /* Tail end of version 0x11 I/O APIC bug workaround */
2576 if (!(v & (1 << (i & 0x1f)))) {
2577 atomic_inc(&irq_mis_count);
2578 spin_lock(&ioapic_lock);
2579 __mask_and_edge_IO_APIC_irq(cfg);
2580 __unmask_and_level_IO_APIC_irq(cfg);
2581 spin_unlock(&ioapic_lock);
2582 }
2583 }
2584
2585 #ifdef CONFIG_INTR_REMAP
2586 static void __eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg)
2587 {
2588 struct irq_pin_list *entry;
2589
2590 for_each_irq_pin(entry, cfg->irq_2_pin)
2591 io_apic_eoi(entry->apic, entry->pin);
2592 }
2593
2594 static void
2595 eoi_ioapic_irq(struct irq_desc *desc)
2596 {
2597 struct irq_cfg *cfg;
2598 unsigned long flags;
2599 unsigned int irq;
2600
2601 irq = desc->irq;
2602 cfg = desc->chip_data;
2603
2604 spin_lock_irqsave(&ioapic_lock, flags);
2605 __eoi_ioapic_irq(irq, cfg);
2606 spin_unlock_irqrestore(&ioapic_lock, flags);
2607 }
2608
2609 static void ir_ack_apic_edge(unsigned int irq)
2610 {
2611 ack_APIC_irq();
2612 }
2613
2614 static void ir_ack_apic_level(unsigned int irq)
2615 {
2616 struct irq_desc *desc = irq_to_desc(irq);
2617
2618 ack_APIC_irq();
2619 eoi_ioapic_irq(desc);
2620 }
2621 #endif /* CONFIG_INTR_REMAP */
2622
2623 static struct irq_chip ioapic_chip __read_mostly = {
2624 .name = "IO-APIC",
2625 .startup = startup_ioapic_irq,
2626 .mask = mask_IO_APIC_irq,
2627 .unmask = unmask_IO_APIC_irq,
2628 .ack = ack_apic_edge,
2629 .eoi = ack_apic_level,
2630 #ifdef CONFIG_SMP
2631 .set_affinity = set_ioapic_affinity_irq,
2632 #endif
2633 .retrigger = ioapic_retrigger_irq,
2634 };
2635
2636 static struct irq_chip ir_ioapic_chip __read_mostly = {
2637 .name = "IR-IO-APIC",
2638 .startup = startup_ioapic_irq,
2639 .mask = mask_IO_APIC_irq,
2640 .unmask = unmask_IO_APIC_irq,
2641 #ifdef CONFIG_INTR_REMAP
2642 .ack = ir_ack_apic_edge,
2643 .eoi = ir_ack_apic_level,
2644 #ifdef CONFIG_SMP
2645 .set_affinity = set_ir_ioapic_affinity_irq,
2646 #endif
2647 #endif
2648 .retrigger = ioapic_retrigger_irq,
2649 };
2650
2651 static inline void init_IO_APIC_traps(void)
2652 {
2653 int irq;
2654 struct irq_desc *desc;
2655 struct irq_cfg *cfg;
2656
2657 /*
2658 * NOTE! The local APIC isn't very good at handling
2659 * multiple interrupts at the same interrupt level.
2660 * As the interrupt level is determined by taking the
2661 * vector number and shifting that right by 4, we
2662 * want to spread these out a bit so that they don't
2663 * all fall in the same interrupt level.
2664 *
2665 * Also, we've got to be careful not to trash gate
2666 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2667 */
2668 for_each_irq_desc(irq, desc) {
2669 cfg = desc->chip_data;
2670 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
2671 /*
2672 * Hmm.. We don't have an entry for this,
2673 * so default to an old-fashioned 8259
2674 * interrupt if we can..
2675 */
2676 if (irq < nr_legacy_irqs)
2677 make_8259A_irq(irq);
2678 else
2679 /* Strange. Oh, well.. */
2680 desc->chip = &no_irq_chip;
2681 }
2682 }
2683 }
2684
2685 /*
2686 * The local APIC irq-chip implementation:
2687 */
2688
2689 static void mask_lapic_irq(unsigned int irq)
2690 {
2691 unsigned long v;
2692
2693 v = apic_read(APIC_LVT0);
2694 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
2695 }
2696
2697 static void unmask_lapic_irq(unsigned int irq)
2698 {
2699 unsigned long v;
2700
2701 v = apic_read(APIC_LVT0);
2702 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
2703 }
2704
2705 static void ack_lapic_irq(unsigned int irq)
2706 {
2707 ack_APIC_irq();
2708 }
2709
2710 static struct irq_chip lapic_chip __read_mostly = {
2711 .name = "local-APIC",
2712 .mask = mask_lapic_irq,
2713 .unmask = unmask_lapic_irq,
2714 .ack = ack_lapic_irq,
2715 };
2716
2717 static void lapic_register_intr(int irq, struct irq_desc *desc)
2718 {
2719 desc->status &= ~IRQ_LEVEL;
2720 set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2721 "edge");
2722 }
2723
2724 static void __init setup_nmi(void)
2725 {
2726 /*
2727 * Dirty trick to enable the NMI watchdog ...
2728 * We put the 8259A master into AEOI mode and
2729 * unmask on all local APICs LVT0 as NMI.
2730 *
2731 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2732 * is from Maciej W. Rozycki - so we do not have to EOI from
2733 * the NMI handler or the timer interrupt.
2734 */
2735 apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2736
2737 enable_NMI_through_LVT0();
2738
2739 apic_printk(APIC_VERBOSE, " done.\n");
2740 }
2741
2742 /*
2743 * This looks a bit hackish but it's about the only one way of sending
2744 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2745 * not support the ExtINT mode, unfortunately. We need to send these
2746 * cycles as some i82489DX-based boards have glue logic that keeps the
2747 * 8259A interrupt line asserted until INTA. --macro
2748 */
2749 static inline void __init unlock_ExtINT_logic(void)
2750 {
2751 int apic, pin, i;
2752 struct IO_APIC_route_entry entry0, entry1;
2753 unsigned char save_control, save_freq_select;
2754
2755 pin = find_isa_irq_pin(8, mp_INT);
2756 if (pin == -1) {
2757 WARN_ON_ONCE(1);
2758 return;
2759 }
2760 apic = find_isa_irq_apic(8, mp_INT);
2761 if (apic == -1) {
2762 WARN_ON_ONCE(1);
2763 return;
2764 }
2765
2766 entry0 = ioapic_read_entry(apic, pin);
2767 clear_IO_APIC_pin(apic, pin);
2768
2769 memset(&entry1, 0, sizeof(entry1));
2770
2771 entry1.dest_mode = 0; /* physical delivery */
2772 entry1.mask = 0; /* unmask IRQ now */
2773 entry1.dest = hard_smp_processor_id();
2774 entry1.delivery_mode = dest_ExtINT;
2775 entry1.polarity = entry0.polarity;
2776 entry1.trigger = 0;
2777 entry1.vector = 0;
2778
2779 ioapic_write_entry(apic, pin, entry1);
2780
2781 save_control = CMOS_READ(RTC_CONTROL);
2782 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2783 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2784 RTC_FREQ_SELECT);
2785 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2786
2787 i = 100;
2788 while (i-- > 0) {
2789 mdelay(10);
2790 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2791 i -= 10;
2792 }
2793
2794 CMOS_WRITE(save_control, RTC_CONTROL);
2795 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2796 clear_IO_APIC_pin(apic, pin);
2797
2798 ioapic_write_entry(apic, pin, entry0);
2799 }
2800
2801 static int disable_timer_pin_1 __initdata;
2802 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2803 static int __init disable_timer_pin_setup(char *arg)
2804 {
2805 disable_timer_pin_1 = 1;
2806 return 0;
2807 }
2808 early_param("disable_timer_pin_1", disable_timer_pin_setup);
2809
2810 int timer_through_8259 __initdata;
2811
2812 /*
2813 * This code may look a bit paranoid, but it's supposed to cooperate with
2814 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2815 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2816 * fanatically on his truly buggy board.
2817 *
2818 * FIXME: really need to revamp this for all platforms.
2819 */
2820 static inline void __init check_timer(void)
2821 {
2822 struct irq_desc *desc = irq_to_desc(0);
2823 struct irq_cfg *cfg = desc->chip_data;
2824 int node = cpu_to_node(boot_cpu_id);
2825 int apic1, pin1, apic2, pin2;
2826 unsigned long flags;
2827 int no_pin1 = 0;
2828
2829 local_irq_save(flags);
2830
2831 /*
2832 * get/set the timer IRQ vector:
2833 */
2834 disable_8259A_irq(0);
2835 assign_irq_vector(0, cfg, apic->target_cpus());
2836
2837 /*
2838 * As IRQ0 is to be enabled in the 8259A, the virtual
2839 * wire has to be disabled in the local APIC. Also
2840 * timer interrupts need to be acknowledged manually in
2841 * the 8259A for the i82489DX when using the NMI
2842 * watchdog as that APIC treats NMIs as level-triggered.
2843 * The AEOI mode will finish them in the 8259A
2844 * automatically.
2845 */
2846 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2847 init_8259A(1);
2848 #ifdef CONFIG_X86_32
2849 {
2850 unsigned int ver;
2851
2852 ver = apic_read(APIC_LVR);
2853 ver = GET_APIC_VERSION(ver);
2854 timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver));
2855 }
2856 #endif
2857
2858 pin1 = find_isa_irq_pin(0, mp_INT);
2859 apic1 = find_isa_irq_apic(0, mp_INT);
2860 pin2 = ioapic_i8259.pin;
2861 apic2 = ioapic_i8259.apic;
2862
2863 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2864 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2865 cfg->vector, apic1, pin1, apic2, pin2);
2866
2867 /*
2868 * Some BIOS writers are clueless and report the ExtINTA
2869 * I/O APIC input from the cascaded 8259A as the timer
2870 * interrupt input. So just in case, if only one pin
2871 * was found above, try it both directly and through the
2872 * 8259A.
2873 */
2874 if (pin1 == -1) {
2875 if (intr_remapping_enabled)
2876 panic("BIOS bug: timer not connected to IO-APIC");
2877 pin1 = pin2;
2878 apic1 = apic2;
2879 no_pin1 = 1;
2880 } else if (pin2 == -1) {
2881 pin2 = pin1;
2882 apic2 = apic1;
2883 }
2884
2885 if (pin1 != -1) {
2886 /*
2887 * Ok, does IRQ0 through the IOAPIC work?
2888 */
2889 if (no_pin1) {
2890 add_pin_to_irq_node(cfg, node, apic1, pin1);
2891 setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
2892 } else {
2893 /* for edge trigger, setup_IO_APIC_irq already
2894 * leave it unmasked.
2895 * so only need to unmask if it is level-trigger
2896 * do we really have level trigger timer?
2897 */
2898 int idx;
2899 idx = find_irq_entry(apic1, pin1, mp_INT);
2900 if (idx != -1 && irq_trigger(idx))
2901 unmask_IO_APIC_irq_desc(desc);
2902 }
2903 if (timer_irq_works()) {
2904 if (nmi_watchdog == NMI_IO_APIC) {
2905 setup_nmi();
2906 enable_8259A_irq(0);
2907 }
2908 if (disable_timer_pin_1 > 0)
2909 clear_IO_APIC_pin(0, pin1);
2910 goto out;
2911 }
2912 if (intr_remapping_enabled)
2913 panic("timer doesn't work through Interrupt-remapped IO-APIC");
2914 local_irq_disable();
2915 clear_IO_APIC_pin(apic1, pin1);
2916 if (!no_pin1)
2917 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2918 "8254 timer not connected to IO-APIC\n");
2919
2920 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2921 "(IRQ0) through the 8259A ...\n");
2922 apic_printk(APIC_QUIET, KERN_INFO
2923 "..... (found apic %d pin %d) ...\n", apic2, pin2);
2924 /*
2925 * legacy devices should be connected to IO APIC #0
2926 */
2927 replace_pin_at_irq_node(cfg, node, apic1, pin1, apic2, pin2);
2928 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
2929 enable_8259A_irq(0);
2930 if (timer_irq_works()) {
2931 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2932 timer_through_8259 = 1;
2933 if (nmi_watchdog == NMI_IO_APIC) {
2934 disable_8259A_irq(0);
2935 setup_nmi();
2936 enable_8259A_irq(0);
2937 }
2938 goto out;
2939 }
2940 /*
2941 * Cleanup, just in case ...
2942 */
2943 local_irq_disable();
2944 disable_8259A_irq(0);
2945 clear_IO_APIC_pin(apic2, pin2);
2946 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
2947 }
2948
2949 if (nmi_watchdog == NMI_IO_APIC) {
2950 apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work "
2951 "through the IO-APIC - disabling NMI Watchdog!\n");
2952 nmi_watchdog = NMI_NONE;
2953 }
2954 #ifdef CONFIG_X86_32
2955 timer_ack = 0;
2956 #endif
2957
2958 apic_printk(APIC_QUIET, KERN_INFO
2959 "...trying to set up timer as Virtual Wire IRQ...\n");
2960
2961 lapic_register_intr(0, desc);
2962 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
2963 enable_8259A_irq(0);
2964
2965 if (timer_irq_works()) {
2966 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2967 goto out;
2968 }
2969 local_irq_disable();
2970 disable_8259A_irq(0);
2971 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
2972 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
2973
2974 apic_printk(APIC_QUIET, KERN_INFO
2975 "...trying to set up timer as ExtINT IRQ...\n");
2976
2977 init_8259A(0);
2978 make_8259A_irq(0);
2979 apic_write(APIC_LVT0, APIC_DM_EXTINT);
2980
2981 unlock_ExtINT_logic();
2982
2983 if (timer_irq_works()) {
2984 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2985 goto out;
2986 }
2987 local_irq_disable();
2988 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
2989 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2990 "report. Then try booting with the 'noapic' option.\n");
2991 out:
2992 local_irq_restore(flags);
2993 }
2994
2995 /*
2996 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2997 * to devices. However there may be an I/O APIC pin available for
2998 * this interrupt regardless. The pin may be left unconnected, but
2999 * typically it will be reused as an ExtINT cascade interrupt for
3000 * the master 8259A. In the MPS case such a pin will normally be
3001 * reported as an ExtINT interrupt in the MP table. With ACPI
3002 * there is no provision for ExtINT interrupts, and in the absence
3003 * of an override it would be treated as an ordinary ISA I/O APIC
3004 * interrupt, that is edge-triggered and unmasked by default. We
3005 * used to do this, but it caused problems on some systems because
3006 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
3007 * the same ExtINT cascade interrupt to drive the local APIC of the
3008 * bootstrap processor. Therefore we refrain from routing IRQ2 to
3009 * the I/O APIC in all cases now. No actual device should request
3010 * it anyway. --macro
3011 */
3012 #define PIC_IRQS (1UL << PIC_CASCADE_IR)
3013
3014 void __init setup_IO_APIC(void)
3015 {
3016
3017 /*
3018 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
3019 */
3020 io_apic_irqs = nr_legacy_irqs ? ~PIC_IRQS : ~0UL;
3021
3022 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
3023 /*
3024 * Set up IO-APIC IRQ routing.
3025 */
3026 x86_init.mpparse.setup_ioapic_ids();
3027
3028 sync_Arb_IDs();
3029 setup_IO_APIC_irqs();
3030 init_IO_APIC_traps();
3031 if (nr_legacy_irqs)
3032 check_timer();
3033 }
3034
3035 /*
3036 * Called after all the initialization is done. If we didnt find any
3037 * APIC bugs then we can allow the modify fast path
3038 */
3039
3040 static int __init io_apic_bug_finalize(void)
3041 {
3042 if (sis_apic_bug == -1)
3043 sis_apic_bug = 0;
3044 return 0;
3045 }
3046
3047 late_initcall(io_apic_bug_finalize);
3048
3049 struct sysfs_ioapic_data {
3050 struct sys_device dev;
3051 struct IO_APIC_route_entry entry[0];
3052 };
3053 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
3054
3055 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
3056 {
3057 struct IO_APIC_route_entry *entry;
3058 struct sysfs_ioapic_data *data;
3059 int i;
3060
3061 data = container_of(dev, struct sysfs_ioapic_data, dev);
3062 entry = data->entry;
3063 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
3064 *entry = ioapic_read_entry(dev->id, i);
3065
3066 return 0;
3067 }
3068
3069 static int ioapic_resume(struct sys_device *dev)
3070 {
3071 struct IO_APIC_route_entry *entry;
3072 struct sysfs_ioapic_data *data;
3073 unsigned long flags;
3074 union IO_APIC_reg_00 reg_00;
3075 int i;
3076
3077 data = container_of(dev, struct sysfs_ioapic_data, dev);
3078 entry = data->entry;
3079
3080 spin_lock_irqsave(&ioapic_lock, flags);
3081 reg_00.raw = io_apic_read(dev->id, 0);
3082 if (reg_00.bits.ID != mp_ioapics[dev->id].apicid) {
3083 reg_00.bits.ID = mp_ioapics[dev->id].apicid;
3084 io_apic_write(dev->id, 0, reg_00.raw);
3085 }
3086 spin_unlock_irqrestore(&ioapic_lock, flags);
3087 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
3088 ioapic_write_entry(dev->id, i, entry[i]);
3089
3090 return 0;
3091 }
3092
3093 static struct sysdev_class ioapic_sysdev_class = {
3094 .name = "ioapic",
3095 .suspend = ioapic_suspend,
3096 .resume = ioapic_resume,
3097 };
3098
3099 static int __init ioapic_init_sysfs(void)
3100 {
3101 struct sys_device * dev;
3102 int i, size, error;
3103
3104 error = sysdev_class_register(&ioapic_sysdev_class);
3105 if (error)
3106 return error;
3107
3108 for (i = 0; i < nr_ioapics; i++ ) {
3109 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
3110 * sizeof(struct IO_APIC_route_entry);
3111 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
3112 if (!mp_ioapic_data[i]) {
3113 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3114 continue;
3115 }
3116 dev = &mp_ioapic_data[i]->dev;
3117 dev->id = i;
3118 dev->cls = &ioapic_sysdev_class;
3119 error = sysdev_register(dev);
3120 if (error) {
3121 kfree(mp_ioapic_data[i]);
3122 mp_ioapic_data[i] = NULL;
3123 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3124 continue;
3125 }
3126 }
3127
3128 return 0;
3129 }
3130
3131 device_initcall(ioapic_init_sysfs);
3132
3133 /*
3134 * Dynamic irq allocate and deallocation
3135 */
3136 unsigned int create_irq_nr(unsigned int irq_want, int node)
3137 {
3138 /* Allocate an unused irq */
3139 unsigned int irq;
3140 unsigned int new;
3141 unsigned long flags;
3142 struct irq_cfg *cfg_new = NULL;
3143 struct irq_desc *desc_new = NULL;
3144
3145 irq = 0;
3146 if (irq_want < nr_irqs_gsi)
3147 irq_want = nr_irqs_gsi;
3148
3149 spin_lock_irqsave(&vector_lock, flags);
3150 for (new = irq_want; new < nr_irqs; new++) {
3151 desc_new = irq_to_desc_alloc_node(new, node);
3152 if (!desc_new) {
3153 printk(KERN_INFO "can not get irq_desc for %d\n", new);
3154 continue;
3155 }
3156 cfg_new = desc_new->chip_data;
3157
3158 if (cfg_new->vector != 0)
3159 continue;
3160
3161 desc_new = move_irq_desc(desc_new, node);
3162
3163 if (__assign_irq_vector(new, cfg_new, apic->target_cpus()) == 0)
3164 irq = new;
3165 break;
3166 }
3167 spin_unlock_irqrestore(&vector_lock, flags);
3168
3169 if (irq > 0) {
3170 dynamic_irq_init(irq);
3171 /* restore it, in case dynamic_irq_init clear it */
3172 if (desc_new)
3173 desc_new->chip_data = cfg_new;
3174 }
3175 return irq;
3176 }
3177
3178 int create_irq(void)
3179 {
3180 int node = cpu_to_node(boot_cpu_id);
3181 unsigned int irq_want;
3182 int irq;
3183
3184 irq_want = nr_irqs_gsi;
3185 irq = create_irq_nr(irq_want, node);
3186
3187 if (irq == 0)
3188 irq = -1;
3189
3190 return irq;
3191 }
3192
3193 void destroy_irq(unsigned int irq)
3194 {
3195 unsigned long flags;
3196 struct irq_cfg *cfg;
3197 struct irq_desc *desc;
3198
3199 /* store it, in case dynamic_irq_cleanup clear it */
3200 desc = irq_to_desc(irq);
3201 cfg = desc->chip_data;
3202 dynamic_irq_cleanup(irq);
3203 /* connect back irq_cfg */
3204 desc->chip_data = cfg;
3205
3206 free_irte(irq);
3207 spin_lock_irqsave(&vector_lock, flags);
3208 __clear_irq_vector(irq, cfg);
3209 spin_unlock_irqrestore(&vector_lock, flags);
3210 }
3211
3212 /*
3213 * MSI message composition
3214 */
3215 #ifdef CONFIG_PCI_MSI
3216 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
3217 {
3218 struct irq_cfg *cfg;
3219 int err;
3220 unsigned dest;
3221
3222 if (disable_apic)
3223 return -ENXIO;
3224
3225 cfg = irq_cfg(irq);
3226 err = assign_irq_vector(irq, cfg, apic->target_cpus());
3227 if (err)
3228 return err;
3229
3230 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
3231
3232 if (irq_remapped(irq)) {
3233 struct irte irte;
3234 int ir_index;
3235 u16 sub_handle;
3236
3237 ir_index = map_irq_to_irte_handle(irq, &sub_handle);
3238 BUG_ON(ir_index == -1);
3239
3240 memset (&irte, 0, sizeof(irte));
3241
3242 irte.present = 1;
3243 irte.dst_mode = apic->irq_dest_mode;
3244 irte.trigger_mode = 0; /* edge */
3245 irte.dlvry_mode = apic->irq_delivery_mode;
3246 irte.vector = cfg->vector;
3247 irte.dest_id = IRTE_DEST(dest);
3248
3249 /* Set source-id of interrupt request */
3250 set_msi_sid(&irte, pdev);
3251
3252 modify_irte(irq, &irte);
3253
3254 msg->address_hi = MSI_ADDR_BASE_HI;
3255 msg->data = sub_handle;
3256 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
3257 MSI_ADDR_IR_SHV |
3258 MSI_ADDR_IR_INDEX1(ir_index) |
3259 MSI_ADDR_IR_INDEX2(ir_index);
3260 } else {
3261 if (x2apic_enabled())
3262 msg->address_hi = MSI_ADDR_BASE_HI |
3263 MSI_ADDR_EXT_DEST_ID(dest);
3264 else
3265 msg->address_hi = MSI_ADDR_BASE_HI;
3266
3267 msg->address_lo =
3268 MSI_ADDR_BASE_LO |
3269 ((apic->irq_dest_mode == 0) ?
3270 MSI_ADDR_DEST_MODE_PHYSICAL:
3271 MSI_ADDR_DEST_MODE_LOGICAL) |
3272 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3273 MSI_ADDR_REDIRECTION_CPU:
3274 MSI_ADDR_REDIRECTION_LOWPRI) |
3275 MSI_ADDR_DEST_ID(dest);
3276
3277 msg->data =
3278 MSI_DATA_TRIGGER_EDGE |
3279 MSI_DATA_LEVEL_ASSERT |
3280 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3281 MSI_DATA_DELIVERY_FIXED:
3282 MSI_DATA_DELIVERY_LOWPRI) |
3283 MSI_DATA_VECTOR(cfg->vector);
3284 }
3285 return err;
3286 }
3287
3288 #ifdef CONFIG_SMP
3289 static int set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
3290 {
3291 struct irq_desc *desc = irq_to_desc(irq);
3292 struct irq_cfg *cfg;
3293 struct msi_msg msg;
3294 unsigned int dest;
3295
3296 dest = set_desc_affinity(desc, mask);
3297 if (dest == BAD_APICID)
3298 return -1;
3299
3300 cfg = desc->chip_data;
3301
3302 read_msi_msg_desc(desc, &msg);
3303
3304 msg.data &= ~MSI_DATA_VECTOR_MASK;
3305 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3306 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3307 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3308
3309 write_msi_msg_desc(desc, &msg);
3310
3311 return 0;
3312 }
3313 #ifdef CONFIG_INTR_REMAP
3314 /*
3315 * Migrate the MSI irq to another cpumask. This migration is
3316 * done in the process context using interrupt-remapping hardware.
3317 */
3318 static int
3319 ir_set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
3320 {
3321 struct irq_desc *desc = irq_to_desc(irq);
3322 struct irq_cfg *cfg = desc->chip_data;
3323 unsigned int dest;
3324 struct irte irte;
3325
3326 if (get_irte(irq, &irte))
3327 return -1;
3328
3329 dest = set_desc_affinity(desc, mask);
3330 if (dest == BAD_APICID)
3331 return -1;
3332
3333 irte.vector = cfg->vector;
3334 irte.dest_id = IRTE_DEST(dest);
3335
3336 /*
3337 * atomically update the IRTE with the new destination and vector.
3338 */
3339 modify_irte(irq, &irte);
3340
3341 /*
3342 * After this point, all the interrupts will start arriving
3343 * at the new destination. So, time to cleanup the previous
3344 * vector allocation.
3345 */
3346 if (cfg->move_in_progress)
3347 send_cleanup_vector(cfg);
3348
3349 return 0;
3350 }
3351
3352 #endif
3353 #endif /* CONFIG_SMP */
3354
3355 /*
3356 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3357 * which implement the MSI or MSI-X Capability Structure.
3358 */
3359 static struct irq_chip msi_chip = {
3360 .name = "PCI-MSI",
3361 .unmask = unmask_msi_irq,
3362 .mask = mask_msi_irq,
3363 .ack = ack_apic_edge,
3364 #ifdef CONFIG_SMP
3365 .set_affinity = set_msi_irq_affinity,
3366 #endif
3367 .retrigger = ioapic_retrigger_irq,
3368 };
3369
3370 static struct irq_chip msi_ir_chip = {
3371 .name = "IR-PCI-MSI",
3372 .unmask = unmask_msi_irq,
3373 .mask = mask_msi_irq,
3374 #ifdef CONFIG_INTR_REMAP
3375 .ack = ir_ack_apic_edge,
3376 #ifdef CONFIG_SMP
3377 .set_affinity = ir_set_msi_irq_affinity,
3378 #endif
3379 #endif
3380 .retrigger = ioapic_retrigger_irq,
3381 };
3382
3383 /*
3384 * Map the PCI dev to the corresponding remapping hardware unit
3385 * and allocate 'nvec' consecutive interrupt-remapping table entries
3386 * in it.
3387 */
3388 static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec)
3389 {
3390 struct intel_iommu *iommu;
3391 int index;
3392
3393 iommu = map_dev_to_ir(dev);
3394 if (!iommu) {
3395 printk(KERN_ERR
3396 "Unable to map PCI %s to iommu\n", pci_name(dev));
3397 return -ENOENT;
3398 }
3399
3400 index = alloc_irte(iommu, irq, nvec);
3401 if (index < 0) {
3402 printk(KERN_ERR
3403 "Unable to allocate %d IRTE for PCI %s\n", nvec,
3404 pci_name(dev));
3405 return -ENOSPC;
3406 }
3407 return index;
3408 }
3409
3410 static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq)
3411 {
3412 int ret;
3413 struct msi_msg msg;
3414
3415 ret = msi_compose_msg(dev, irq, &msg);
3416 if (ret < 0)
3417 return ret;
3418
3419 set_irq_msi(irq, msidesc);
3420 write_msi_msg(irq, &msg);
3421
3422 if (irq_remapped(irq)) {
3423 struct irq_desc *desc = irq_to_desc(irq);
3424 /*
3425 * irq migration in process context
3426 */
3427 desc->status |= IRQ_MOVE_PCNTXT;
3428 set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge");
3429 } else
3430 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
3431
3432 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq);
3433
3434 return 0;
3435 }
3436
3437 int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
3438 {
3439 unsigned int irq;
3440 int ret, sub_handle;
3441 struct msi_desc *msidesc;
3442 unsigned int irq_want;
3443 struct intel_iommu *iommu = NULL;
3444 int index = 0;
3445 int node;
3446
3447 /* x86 doesn't support multiple MSI yet */
3448 if (type == PCI_CAP_ID_MSI && nvec > 1)
3449 return 1;
3450
3451 node = dev_to_node(&dev->dev);
3452 irq_want = nr_irqs_gsi;
3453 sub_handle = 0;
3454 list_for_each_entry(msidesc, &dev->msi_list, list) {
3455 irq = create_irq_nr(irq_want, node);
3456 if (irq == 0)
3457 return -1;
3458 irq_want = irq + 1;
3459 if (!intr_remapping_enabled)
3460 goto no_ir;
3461
3462 if (!sub_handle) {
3463 /*
3464 * allocate the consecutive block of IRTE's
3465 * for 'nvec'
3466 */
3467 index = msi_alloc_irte(dev, irq, nvec);
3468 if (index < 0) {
3469 ret = index;
3470 goto error;
3471 }
3472 } else {
3473 iommu = map_dev_to_ir(dev);
3474 if (!iommu) {
3475 ret = -ENOENT;
3476 goto error;
3477 }
3478 /*
3479 * setup the mapping between the irq and the IRTE
3480 * base index, the sub_handle pointing to the
3481 * appropriate interrupt remap table entry.
3482 */
3483 set_irte_irq(irq, iommu, index, sub_handle);
3484 }
3485 no_ir:
3486 ret = setup_msi_irq(dev, msidesc, irq);
3487 if (ret < 0)
3488 goto error;
3489 sub_handle++;
3490 }
3491 return 0;
3492
3493 error:
3494 destroy_irq(irq);
3495 return ret;
3496 }
3497
3498 void arch_teardown_msi_irq(unsigned int irq)
3499 {
3500 destroy_irq(irq);
3501 }
3502
3503 #if defined (CONFIG_DMAR) || defined (CONFIG_INTR_REMAP)
3504 #ifdef CONFIG_SMP
3505 static int dmar_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
3506 {
3507 struct irq_desc *desc = irq_to_desc(irq);
3508 struct irq_cfg *cfg;
3509 struct msi_msg msg;
3510 unsigned int dest;
3511
3512 dest = set_desc_affinity(desc, mask);
3513 if (dest == BAD_APICID)
3514 return -1;
3515
3516 cfg = desc->chip_data;
3517
3518 dmar_msi_read(irq, &msg);
3519
3520 msg.data &= ~MSI_DATA_VECTOR_MASK;
3521 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3522 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3523 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3524
3525 dmar_msi_write(irq, &msg);
3526
3527 return 0;
3528 }
3529
3530 #endif /* CONFIG_SMP */
3531
3532 static struct irq_chip dmar_msi_type = {
3533 .name = "DMAR_MSI",
3534 .unmask = dmar_msi_unmask,
3535 .mask = dmar_msi_mask,
3536 .ack = ack_apic_edge,
3537 #ifdef CONFIG_SMP
3538 .set_affinity = dmar_msi_set_affinity,
3539 #endif
3540 .retrigger = ioapic_retrigger_irq,
3541 };
3542
3543 int arch_setup_dmar_msi(unsigned int irq)
3544 {
3545 int ret;
3546 struct msi_msg msg;
3547
3548 ret = msi_compose_msg(NULL, irq, &msg);
3549 if (ret < 0)
3550 return ret;
3551 dmar_msi_write(irq, &msg);
3552 set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
3553 "edge");
3554 return 0;
3555 }
3556 #endif
3557
3558 #ifdef CONFIG_HPET_TIMER
3559
3560 #ifdef CONFIG_SMP
3561 static int hpet_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
3562 {
3563 struct irq_desc *desc = irq_to_desc(irq);
3564 struct irq_cfg *cfg;
3565 struct msi_msg msg;
3566 unsigned int dest;
3567
3568 dest = set_desc_affinity(desc, mask);
3569 if (dest == BAD_APICID)
3570 return -1;
3571
3572 cfg = desc->chip_data;
3573
3574 hpet_msi_read(irq, &msg);
3575
3576 msg.data &= ~MSI_DATA_VECTOR_MASK;
3577 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3578 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3579 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3580
3581 hpet_msi_write(irq, &msg);
3582
3583 return 0;
3584 }
3585
3586 #endif /* CONFIG_SMP */
3587
3588 static struct irq_chip hpet_msi_type = {
3589 .name = "HPET_MSI",
3590 .unmask = hpet_msi_unmask,
3591 .mask = hpet_msi_mask,
3592 .ack = ack_apic_edge,
3593 #ifdef CONFIG_SMP
3594 .set_affinity = hpet_msi_set_affinity,
3595 #endif
3596 .retrigger = ioapic_retrigger_irq,
3597 };
3598
3599 int arch_setup_hpet_msi(unsigned int irq)
3600 {
3601 int ret;
3602 struct msi_msg msg;
3603 struct irq_desc *desc = irq_to_desc(irq);
3604
3605 ret = msi_compose_msg(NULL, irq, &msg);
3606 if (ret < 0)
3607 return ret;
3608
3609 hpet_msi_write(irq, &msg);
3610 desc->status |= IRQ_MOVE_PCNTXT;
3611 set_irq_chip_and_handler_name(irq, &hpet_msi_type, handle_edge_irq,
3612 "edge");
3613
3614 return 0;
3615 }
3616 #endif
3617
3618 #endif /* CONFIG_PCI_MSI */
3619 /*
3620 * Hypertransport interrupt support
3621 */
3622 #ifdef CONFIG_HT_IRQ
3623
3624 #ifdef CONFIG_SMP
3625
3626 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
3627 {
3628 struct ht_irq_msg msg;
3629 fetch_ht_irq_msg(irq, &msg);
3630
3631 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
3632 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
3633
3634 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
3635 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
3636
3637 write_ht_irq_msg(irq, &msg);
3638 }
3639
3640 static int set_ht_irq_affinity(unsigned int irq, const struct cpumask *mask)
3641 {
3642 struct irq_desc *desc = irq_to_desc(irq);
3643 struct irq_cfg *cfg;
3644 unsigned int dest;
3645
3646 dest = set_desc_affinity(desc, mask);
3647 if (dest == BAD_APICID)
3648 return -1;
3649
3650 cfg = desc->chip_data;
3651
3652 target_ht_irq(irq, dest, cfg->vector);
3653
3654 return 0;
3655 }
3656
3657 #endif
3658
3659 static struct irq_chip ht_irq_chip = {
3660 .name = "PCI-HT",
3661 .mask = mask_ht_irq,
3662 .unmask = unmask_ht_irq,
3663 .ack = ack_apic_edge,
3664 #ifdef CONFIG_SMP
3665 .set_affinity = set_ht_irq_affinity,
3666 #endif
3667 .retrigger = ioapic_retrigger_irq,
3668 };
3669
3670 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
3671 {
3672 struct irq_cfg *cfg;
3673 int err;
3674
3675 if (disable_apic)
3676 return -ENXIO;
3677
3678 cfg = irq_cfg(irq);
3679 err = assign_irq_vector(irq, cfg, apic->target_cpus());
3680 if (!err) {
3681 struct ht_irq_msg msg;
3682 unsigned dest;
3683
3684 dest = apic->cpu_mask_to_apicid_and(cfg->domain,
3685 apic->target_cpus());
3686
3687 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
3688
3689 msg.address_lo =
3690 HT_IRQ_LOW_BASE |
3691 HT_IRQ_LOW_DEST_ID(dest) |
3692 HT_IRQ_LOW_VECTOR(cfg->vector) |
3693 ((apic->irq_dest_mode == 0) ?
3694 HT_IRQ_LOW_DM_PHYSICAL :
3695 HT_IRQ_LOW_DM_LOGICAL) |
3696 HT_IRQ_LOW_RQEOI_EDGE |
3697 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3698 HT_IRQ_LOW_MT_FIXED :
3699 HT_IRQ_LOW_MT_ARBITRATED) |
3700 HT_IRQ_LOW_IRQ_MASKED;
3701
3702 write_ht_irq_msg(irq, &msg);
3703
3704 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
3705 handle_edge_irq, "edge");
3706
3707 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq);
3708 }
3709 return err;
3710 }
3711 #endif /* CONFIG_HT_IRQ */
3712
3713 int __init io_apic_get_redir_entries (int ioapic)
3714 {
3715 union IO_APIC_reg_01 reg_01;
3716 unsigned long flags;
3717
3718 spin_lock_irqsave(&ioapic_lock, flags);
3719 reg_01.raw = io_apic_read(ioapic, 1);
3720 spin_unlock_irqrestore(&ioapic_lock, flags);
3721
3722 return reg_01.bits.entries;
3723 }
3724
3725 void __init probe_nr_irqs_gsi(void)
3726 {
3727 int nr = 0;
3728
3729 nr = acpi_probe_gsi();
3730 if (nr > nr_irqs_gsi) {
3731 nr_irqs_gsi = nr;
3732 } else {
3733 /* for acpi=off or acpi is not compiled in */
3734 int idx;
3735
3736 nr = 0;
3737 for (idx = 0; idx < nr_ioapics; idx++)
3738 nr += io_apic_get_redir_entries(idx) + 1;
3739
3740 if (nr > nr_irqs_gsi)
3741 nr_irqs_gsi = nr;
3742 }
3743
3744 printk(KERN_DEBUG "nr_irqs_gsi: %d\n", nr_irqs_gsi);
3745 }
3746
3747 #ifdef CONFIG_SPARSE_IRQ
3748 int __init arch_probe_nr_irqs(void)
3749 {
3750 int nr;
3751
3752 if (nr_irqs > (NR_VECTORS * nr_cpu_ids))
3753 nr_irqs = NR_VECTORS * nr_cpu_ids;
3754
3755 nr = nr_irqs_gsi + 8 * nr_cpu_ids;
3756 #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ)
3757 /*
3758 * for MSI and HT dyn irq
3759 */
3760 nr += nr_irqs_gsi * 16;
3761 #endif
3762 if (nr < nr_irqs)
3763 nr_irqs = nr;
3764
3765 return 0;
3766 }
3767 #endif
3768
3769 static int __io_apic_set_pci_routing(struct device *dev, int irq,
3770 struct io_apic_irq_attr *irq_attr)
3771 {
3772 struct irq_desc *desc;
3773 struct irq_cfg *cfg;
3774 int node;
3775 int ioapic, pin;
3776 int trigger, polarity;
3777
3778 ioapic = irq_attr->ioapic;
3779 if (!IO_APIC_IRQ(irq)) {
3780 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
3781 ioapic);
3782 return -EINVAL;
3783 }
3784
3785 if (dev)
3786 node = dev_to_node(dev);
3787 else
3788 node = cpu_to_node(boot_cpu_id);
3789
3790 desc = irq_to_desc_alloc_node(irq, node);
3791 if (!desc) {
3792 printk(KERN_INFO "can not get irq_desc %d\n", irq);
3793 return 0;
3794 }
3795
3796 pin = irq_attr->ioapic_pin;
3797 trigger = irq_attr->trigger;
3798 polarity = irq_attr->polarity;
3799
3800 /*
3801 * IRQs < 16 are already in the irq_2_pin[] map
3802 */
3803 if (irq >= nr_legacy_irqs) {
3804 cfg = desc->chip_data;
3805 if (add_pin_to_irq_node_nopanic(cfg, node, ioapic, pin)) {
3806 printk(KERN_INFO "can not add pin %d for irq %d\n",
3807 pin, irq);
3808 return 0;
3809 }
3810 }
3811
3812 setup_IO_APIC_irq(ioapic, pin, irq, desc, trigger, polarity);
3813
3814 return 0;
3815 }
3816
3817 int io_apic_set_pci_routing(struct device *dev, int irq,
3818 struct io_apic_irq_attr *irq_attr)
3819 {
3820 int ioapic, pin;
3821 /*
3822 * Avoid pin reprogramming. PRTs typically include entries
3823 * with redundant pin->gsi mappings (but unique PCI devices);
3824 * we only program the IOAPIC on the first.
3825 */
3826 ioapic = irq_attr->ioapic;
3827 pin = irq_attr->ioapic_pin;
3828 if (test_bit(pin, mp_ioapic_routing[ioapic].pin_programmed)) {
3829 pr_debug("Pin %d-%d already programmed\n",
3830 mp_ioapics[ioapic].apicid, pin);
3831 return 0;
3832 }
3833 set_bit(pin, mp_ioapic_routing[ioapic].pin_programmed);
3834
3835 return __io_apic_set_pci_routing(dev, irq, irq_attr);
3836 }
3837
3838 u8 __init io_apic_unique_id(u8 id)
3839 {
3840 #ifdef CONFIG_X86_32
3841 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
3842 !APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
3843 return io_apic_get_unique_id(nr_ioapics, id);
3844 else
3845 return id;
3846 #else
3847 int i;
3848 DECLARE_BITMAP(used, 256);
3849
3850 bitmap_zero(used, 256);
3851 for (i = 0; i < nr_ioapics; i++) {
3852 struct mpc_ioapic *ia = &mp_ioapics[i];
3853 __set_bit(ia->apicid, used);
3854 }
3855 if (!test_bit(id, used))
3856 return id;
3857 return find_first_zero_bit(used, 256);
3858 #endif
3859 }
3860
3861 #ifdef CONFIG_X86_32
3862 int __init io_apic_get_unique_id(int ioapic, int apic_id)
3863 {
3864 union IO_APIC_reg_00 reg_00;
3865 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
3866 physid_mask_t tmp;
3867 unsigned long flags;
3868 int i = 0;
3869
3870 /*
3871 * The P4 platform supports up to 256 APIC IDs on two separate APIC
3872 * buses (one for LAPICs, one for IOAPICs), where predecessors only
3873 * supports up to 16 on one shared APIC bus.
3874 *
3875 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3876 * advantage of new APIC bus architecture.
3877 */
3878
3879 if (physids_empty(apic_id_map))
3880 apic_id_map = apic->ioapic_phys_id_map(phys_cpu_present_map);
3881
3882 spin_lock_irqsave(&ioapic_lock, flags);
3883 reg_00.raw = io_apic_read(ioapic, 0);
3884 spin_unlock_irqrestore(&ioapic_lock, flags);
3885
3886 if (apic_id >= get_physical_broadcast()) {
3887 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
3888 "%d\n", ioapic, apic_id, reg_00.bits.ID);
3889 apic_id = reg_00.bits.ID;
3890 }
3891
3892 /*
3893 * Every APIC in a system must have a unique ID or we get lots of nice
3894 * 'stuck on smp_invalidate_needed IPI wait' messages.
3895 */
3896 if (apic->check_apicid_used(apic_id_map, apic_id)) {
3897
3898 for (i = 0; i < get_physical_broadcast(); i++) {
3899 if (!apic->check_apicid_used(apic_id_map, i))
3900 break;
3901 }
3902
3903 if (i == get_physical_broadcast())
3904 panic("Max apic_id exceeded!\n");
3905
3906 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
3907 "trying %d\n", ioapic, apic_id, i);
3908
3909 apic_id = i;
3910 }
3911
3912 tmp = apic->apicid_to_cpu_present(apic_id);
3913 physids_or(apic_id_map, apic_id_map, tmp);
3914
3915 if (reg_00.bits.ID != apic_id) {
3916 reg_00.bits.ID = apic_id;
3917
3918 spin_lock_irqsave(&ioapic_lock, flags);
3919 io_apic_write(ioapic, 0, reg_00.raw);
3920 reg_00.raw = io_apic_read(ioapic, 0);
3921 spin_unlock_irqrestore(&ioapic_lock, flags);
3922
3923 /* Sanity check */
3924 if (reg_00.bits.ID != apic_id) {
3925 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
3926 return -1;
3927 }
3928 }
3929
3930 apic_printk(APIC_VERBOSE, KERN_INFO
3931 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
3932
3933 return apic_id;
3934 }
3935 #endif
3936
3937 int __init io_apic_get_version(int ioapic)
3938 {
3939 union IO_APIC_reg_01 reg_01;
3940 unsigned long flags;
3941
3942 spin_lock_irqsave(&ioapic_lock, flags);
3943 reg_01.raw = io_apic_read(ioapic, 1);
3944 spin_unlock_irqrestore(&ioapic_lock, flags);
3945
3946 return reg_01.bits.version;
3947 }
3948
3949 int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
3950 {
3951 int i;
3952
3953 if (skip_ioapic_setup)
3954 return -1;
3955
3956 for (i = 0; i < mp_irq_entries; i++)
3957 if (mp_irqs[i].irqtype == mp_INT &&
3958 mp_irqs[i].srcbusirq == bus_irq)
3959 break;
3960 if (i >= mp_irq_entries)
3961 return -1;
3962
3963 *trigger = irq_trigger(i);
3964 *polarity = irq_polarity(i);
3965 return 0;
3966 }
3967
3968 /*
3969 * This function currently is only a helper for the i386 smp boot process where
3970 * we need to reprogram the ioredtbls to cater for the cpus which have come online
3971 * so mask in all cases should simply be apic->target_cpus()
3972 */
3973 #ifdef CONFIG_SMP
3974 void __init setup_ioapic_dest(void)
3975 {
3976 int pin, ioapic = 0, irq, irq_entry;
3977 struct irq_desc *desc;
3978 const struct cpumask *mask;
3979
3980 if (skip_ioapic_setup == 1)
3981 return;
3982
3983 #ifdef CONFIG_ACPI
3984 if (!acpi_disabled && acpi_ioapic) {
3985 ioapic = mp_find_ioapic(0);
3986 if (ioapic < 0)
3987 ioapic = 0;
3988 }
3989 #endif
3990
3991 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
3992 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
3993 if (irq_entry == -1)
3994 continue;
3995 irq = pin_2_irq(irq_entry, ioapic, pin);
3996
3997 desc = irq_to_desc(irq);
3998
3999 /*
4000 * Honour affinities which have been set in early boot
4001 */
4002 if (desc->status &
4003 (IRQ_NO_BALANCING | IRQ_AFFINITY_SET))
4004 mask = desc->affinity;
4005 else
4006 mask = apic->target_cpus();
4007
4008 if (intr_remapping_enabled)
4009 set_ir_ioapic_affinity_irq_desc(desc, mask);
4010 else
4011 set_ioapic_affinity_irq_desc(desc, mask);
4012 }
4013
4014 }
4015 #endif
4016
4017 #define IOAPIC_RESOURCE_NAME_SIZE 11
4018
4019 static struct resource *ioapic_resources;
4020
4021 static struct resource * __init ioapic_setup_resources(int nr_ioapics)
4022 {
4023 unsigned long n;
4024 struct resource *res;
4025 char *mem;
4026 int i;
4027
4028 if (nr_ioapics <= 0)
4029 return NULL;
4030
4031 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
4032 n *= nr_ioapics;
4033
4034 mem = alloc_bootmem(n);
4035 res = (void *)mem;
4036
4037 mem += sizeof(struct resource) * nr_ioapics;
4038
4039 for (i = 0; i < nr_ioapics; i++) {
4040 res[i].name = mem;
4041 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
4042 sprintf(mem, "IOAPIC %u", i);
4043 mem += IOAPIC_RESOURCE_NAME_SIZE;
4044 }
4045
4046 ioapic_resources = res;
4047
4048 return res;
4049 }
4050
4051 void __init ioapic_init_mappings(void)
4052 {
4053 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
4054 struct resource *ioapic_res;
4055 int i;
4056
4057 ioapic_res = ioapic_setup_resources(nr_ioapics);
4058 for (i = 0; i < nr_ioapics; i++) {
4059 if (smp_found_config) {
4060 ioapic_phys = mp_ioapics[i].apicaddr;
4061 #ifdef CONFIG_X86_32
4062 if (!ioapic_phys) {
4063 printk(KERN_ERR
4064 "WARNING: bogus zero IO-APIC "
4065 "address found in MPTABLE, "
4066 "disabling IO/APIC support!\n");
4067 smp_found_config = 0;
4068 skip_ioapic_setup = 1;
4069 goto fake_ioapic_page;
4070 }
4071 #endif
4072 } else {
4073 #ifdef CONFIG_X86_32
4074 fake_ioapic_page:
4075 #endif
4076 ioapic_phys = (unsigned long)
4077 alloc_bootmem_pages(PAGE_SIZE);
4078 ioapic_phys = __pa(ioapic_phys);
4079 }
4080 set_fixmap_nocache(idx, ioapic_phys);
4081 apic_printk(APIC_VERBOSE,
4082 "mapped IOAPIC to %08lx (%08lx)\n",
4083 __fix_to_virt(idx), ioapic_phys);
4084 idx++;
4085
4086 ioapic_res->start = ioapic_phys;
4087 ioapic_res->end = ioapic_phys + (4 * 1024) - 1;
4088 ioapic_res++;
4089 }
4090 }
4091
4092 void __init ioapic_insert_resources(void)
4093 {
4094 int i;
4095 struct resource *r = ioapic_resources;
4096
4097 if (!r) {
4098 if (nr_ioapics > 0)
4099 printk(KERN_ERR
4100 "IO APIC resources couldn't be allocated.\n");
4101 return;
4102 }
4103
4104 for (i = 0; i < nr_ioapics; i++) {
4105 insert_resource(&iomem_resource, r);
4106 r++;
4107 }
4108 }
4109
4110 int mp_find_ioapic(int gsi)
4111 {
4112 int i = 0;
4113
4114 /* Find the IOAPIC that manages this GSI. */
4115 for (i = 0; i < nr_ioapics; i++) {
4116 if ((gsi >= mp_gsi_routing[i].gsi_base)
4117 && (gsi <= mp_gsi_routing[i].gsi_end))
4118 return i;
4119 }
4120
4121 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
4122 return -1;
4123 }
4124
4125 int mp_find_ioapic_pin(int ioapic, int gsi)
4126 {
4127 if (WARN_ON(ioapic == -1))
4128 return -1;
4129 if (WARN_ON(gsi > mp_gsi_routing[ioapic].gsi_end))
4130 return -1;
4131
4132 return gsi - mp_gsi_routing[ioapic].gsi_base;
4133 }
4134
4135 static int bad_ioapic(unsigned long address)
4136 {
4137 if (nr_ioapics >= MAX_IO_APICS) {
4138 printk(KERN_WARNING "WARING: Max # of I/O APICs (%d) exceeded "
4139 "(found %d), skipping\n", MAX_IO_APICS, nr_ioapics);
4140 return 1;
4141 }
4142 if (!address) {
4143 printk(KERN_WARNING "WARNING: Bogus (zero) I/O APIC address"
4144 " found in table, skipping!\n");
4145 return 1;
4146 }
4147 return 0;
4148 }
4149
4150 void __init mp_register_ioapic(int id, u32 address, u32 gsi_base)
4151 {
4152 int idx = 0;
4153
4154 if (bad_ioapic(address))
4155 return;
4156
4157 idx = nr_ioapics;
4158
4159 mp_ioapics[idx].type = MP_IOAPIC;
4160 mp_ioapics[idx].flags = MPC_APIC_USABLE;
4161 mp_ioapics[idx].apicaddr = address;
4162
4163 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
4164 mp_ioapics[idx].apicid = io_apic_unique_id(id);
4165 mp_ioapics[idx].apicver = io_apic_get_version(idx);
4166
4167 /*
4168 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
4169 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
4170 */
4171 mp_gsi_routing[idx].gsi_base = gsi_base;
4172 mp_gsi_routing[idx].gsi_end = gsi_base +
4173 io_apic_get_redir_entries(idx);
4174
4175 printk(KERN_INFO "IOAPIC[%d]: apic_id %d, version %d, address 0x%x, "
4176 "GSI %d-%d\n", idx, mp_ioapics[idx].apicid,
4177 mp_ioapics[idx].apicver, mp_ioapics[idx].apicaddr,
4178 mp_gsi_routing[idx].gsi_base, mp_gsi_routing[idx].gsi_end);
4179
4180 nr_ioapics++;
4181 }
Linux kernel - Deliverables
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