2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/syscore_ops.h>
34 #include <linux/irqdomain.h>
35 #include <linux/freezer.h>
36 #include <linux/kthread.h>
37 #include <linux/jiffies.h> /* time_after() */
38 #include <linux/slab.h>
39 #include <linux/bootmem.h>
46 #include <asm/proto.h>
49 #include <asm/timer.h>
50 #include <asm/i8259.h>
51 #include <asm/setup.h>
52 #include <asm/irq_remapping.h>
53 #include <asm/hw_irq.h>
57 #define for_each_ioapic(idx) \
58 for ((idx) = 0; (idx) < nr_ioapics; (idx)++)
59 #define for_each_ioapic_reverse(idx) \
60 for ((idx) = nr_ioapics - 1; (idx) >= 0; (idx)--)
61 #define for_each_pin(idx, pin) \
62 for ((pin) = 0; (pin) < ioapics[(idx)].nr_registers; (pin)++)
63 #define for_each_ioapic_pin(idx, pin) \
64 for_each_ioapic((idx)) \
65 for_each_pin((idx), (pin))
67 #define for_each_irq_pin(entry, head) \
68 list_for_each_entry(entry, &head, list)
71 * Is the SiS APIC rmw bug present ?
72 * -1 = don't know, 0 = no, 1 = yes
74 int sis_apic_bug
= -1;
76 static DEFINE_RAW_SPINLOCK(ioapic_lock
);
77 static DEFINE_MUTEX(ioapic_mutex
);
78 static unsigned int ioapic_dynirq_base
;
79 static int ioapic_initialized
;
82 struct IO_APIC_route_entry entry
;
96 static struct ioapic
{
98 * # of IRQ routing registers
102 * Saved state during suspend/resume, or while enabling intr-remap.
104 struct IO_APIC_route_entry
*saved_registers
;
105 /* I/O APIC config */
106 struct mpc_ioapic mp_config
;
107 /* IO APIC gsi routing info */
108 struct mp_ioapic_gsi gsi_config
;
109 struct ioapic_domain_cfg irqdomain_cfg
;
110 struct irq_domain
*irqdomain
;
111 struct mp_pin_info
*pin_info
;
112 struct resource
*iomem_res
;
113 } ioapics
[MAX_IO_APICS
];
115 #define mpc_ioapic_ver(ioapic_idx) ioapics[ioapic_idx].mp_config.apicver
117 int mpc_ioapic_id(int ioapic_idx
)
119 return ioapics
[ioapic_idx
].mp_config
.apicid
;
122 unsigned int mpc_ioapic_addr(int ioapic_idx
)
124 return ioapics
[ioapic_idx
].mp_config
.apicaddr
;
127 struct mp_ioapic_gsi
*mp_ioapic_gsi_routing(int ioapic_idx
)
129 return &ioapics
[ioapic_idx
].gsi_config
;
132 static inline int mp_ioapic_pin_count(int ioapic
)
134 struct mp_ioapic_gsi
*gsi_cfg
= mp_ioapic_gsi_routing(ioapic
);
136 return gsi_cfg
->gsi_end
- gsi_cfg
->gsi_base
+ 1;
139 u32
mp_pin_to_gsi(int ioapic
, int pin
)
141 return mp_ioapic_gsi_routing(ioapic
)->gsi_base
+ pin
;
145 * Initialize all legacy IRQs and all pins on the first IOAPIC
146 * if we have legacy interrupt controller. Kernel boot option "pirq="
147 * may rely on non-legacy pins on the first IOAPIC.
149 static inline int mp_init_irq_at_boot(int ioapic
, int irq
)
151 if (!nr_legacy_irqs())
154 return ioapic
== 0 || (irq
>= 0 && irq
< nr_legacy_irqs());
157 static inline struct mp_pin_info
*mp_pin_info(int ioapic_idx
, int pin
)
159 return ioapics
[ioapic_idx
].pin_info
+ pin
;
162 static inline struct irq_domain
*mp_ioapic_irqdomain(int ioapic
)
164 return ioapics
[ioapic
].irqdomain
;
169 /* The one past the highest gsi number used */
172 /* MP IRQ source entries */
173 struct mpc_intsrc mp_irqs
[MAX_IRQ_SOURCES
];
175 /* # of MP IRQ source entries */
179 int mp_bus_id_to_type
[MAX_MP_BUSSES
];
182 DECLARE_BITMAP(mp_bus_not_pci
, MAX_MP_BUSSES
);
184 int skip_ioapic_setup
;
187 * disable_ioapic_support() - disables ioapic support at runtime
189 void disable_ioapic_support(void)
193 noioapicreroute
= -1;
195 skip_ioapic_setup
= 1;
198 static int __init
parse_noapic(char *str
)
200 /* disable IO-APIC */
201 disable_ioapic_support();
204 early_param("noapic", parse_noapic
);
206 /* Will be called in mpparse/acpi/sfi codes for saving IRQ info */
207 void mp_save_irq(struct mpc_intsrc
*m
)
211 apic_printk(APIC_VERBOSE
, "Int: type %d, pol %d, trig %d, bus %02x,"
212 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
213 m
->irqtype
, m
->irqflag
& 3, (m
->irqflag
>> 2) & 3, m
->srcbus
,
214 m
->srcbusirq
, m
->dstapic
, m
->dstirq
);
216 for (i
= 0; i
< mp_irq_entries
; i
++) {
217 if (!memcmp(&mp_irqs
[i
], m
, sizeof(*m
)))
221 memcpy(&mp_irqs
[mp_irq_entries
], m
, sizeof(*m
));
222 if (++mp_irq_entries
== MAX_IRQ_SOURCES
)
223 panic("Max # of irq sources exceeded!!\n");
226 struct irq_pin_list
{
227 struct list_head list
;
231 static struct irq_pin_list
*alloc_irq_pin_list(int node
)
233 return kzalloc_node(sizeof(struct irq_pin_list
), GFP_KERNEL
, node
);
236 static void alloc_ioapic_saved_registers(int idx
)
240 if (ioapics
[idx
].saved_registers
)
243 size
= sizeof(struct IO_APIC_route_entry
) * ioapics
[idx
].nr_registers
;
244 ioapics
[idx
].saved_registers
= kzalloc(size
, GFP_KERNEL
);
245 if (!ioapics
[idx
].saved_registers
)
246 pr_err("IOAPIC %d: suspend/resume impossible!\n", idx
);
249 static void free_ioapic_saved_registers(int idx
)
251 kfree(ioapics
[idx
].saved_registers
);
252 ioapics
[idx
].saved_registers
= NULL
;
255 int __init
arch_early_ioapic_init(void)
258 int i
, node
= cpu_to_node(0);
260 if (!nr_legacy_irqs())
264 alloc_ioapic_saved_registers(i
);
267 * For legacy IRQ's, start with assigning irq0 to irq15 to
268 * IRQ0_VECTOR to IRQ15_VECTOR for all cpu's.
270 for (i
= 0; i
< nr_legacy_irqs(); i
++) {
271 cfg
= alloc_irq_and_cfg_at(i
, node
);
272 cfg
->vector
= IRQ0_VECTOR
+ i
;
273 cpumask_setall(cfg
->domain
);
281 unsigned int unused
[3];
283 unsigned int unused2
[11];
287 static __attribute_const__
struct io_apic __iomem
*io_apic_base(int idx
)
289 return (void __iomem
*) __fix_to_virt(FIX_IO_APIC_BASE_0
+ idx
)
290 + (mpc_ioapic_addr(idx
) & ~PAGE_MASK
);
293 void io_apic_eoi(unsigned int apic
, unsigned int vector
)
295 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
296 writel(vector
, &io_apic
->eoi
);
299 unsigned int native_io_apic_read(unsigned int apic
, unsigned int reg
)
301 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
302 writel(reg
, &io_apic
->index
);
303 return readl(&io_apic
->data
);
306 void native_io_apic_write(unsigned int apic
, unsigned int reg
, unsigned int value
)
308 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
310 writel(reg
, &io_apic
->index
);
311 writel(value
, &io_apic
->data
);
315 * Re-write a value: to be used for read-modify-write
316 * cycles where the read already set up the index register.
318 * Older SiS APIC requires we rewrite the index register
320 void native_io_apic_modify(unsigned int apic
, unsigned int reg
, unsigned int value
)
322 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
325 writel(reg
, &io_apic
->index
);
326 writel(value
, &io_apic
->data
);
330 struct { u32 w1
, w2
; };
331 struct IO_APIC_route_entry entry
;
334 static struct IO_APIC_route_entry
__ioapic_read_entry(int apic
, int pin
)
336 union entry_union eu
;
338 eu
.w1
= io_apic_read(apic
, 0x10 + 2 * pin
);
339 eu
.w2
= io_apic_read(apic
, 0x11 + 2 * pin
);
344 static struct IO_APIC_route_entry
ioapic_read_entry(int apic
, int pin
)
346 union entry_union eu
;
349 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
350 eu
.entry
= __ioapic_read_entry(apic
, pin
);
351 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
357 * When we write a new IO APIC routing entry, we need to write the high
358 * word first! If the mask bit in the low word is clear, we will enable
359 * the interrupt, and we need to make sure the entry is fully populated
360 * before that happens.
362 static void __ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
364 union entry_union eu
= {{0, 0}};
367 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
368 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
371 static void ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
375 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
376 __ioapic_write_entry(apic
, pin
, e
);
377 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
381 * When we mask an IO APIC routing entry, we need to write the low
382 * word first, in order to set the mask bit before we change the
385 static void ioapic_mask_entry(int apic
, int pin
)
388 union entry_union eu
= { .entry
.mask
= 1 };
390 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
391 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
392 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
393 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
397 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
398 * shared ISA-space IRQs, so we have to support them. We are super
399 * fast in the common case, and fast for shared ISA-space IRQs.
401 static int __add_pin_to_irq_node(struct irq_cfg
*cfg
, int node
, int apic
, int pin
)
403 struct irq_pin_list
*entry
;
405 /* don't allow duplicates */
406 for_each_irq_pin(entry
, cfg
->irq_2_pin
)
407 if (entry
->apic
== apic
&& entry
->pin
== pin
)
410 entry
= alloc_irq_pin_list(node
);
412 pr_err("can not alloc irq_pin_list (%d,%d,%d)\n",
419 list_add_tail(&entry
->list
, &cfg
->irq_2_pin
);
423 static void __remove_pin_from_irq(struct irq_cfg
*cfg
, int apic
, int pin
)
425 struct irq_pin_list
*tmp
, *entry
;
427 list_for_each_entry_safe(entry
, tmp
, &cfg
->irq_2_pin
, list
)
428 if (entry
->apic
== apic
&& entry
->pin
== pin
) {
429 list_del(&entry
->list
);
435 static void add_pin_to_irq_node(struct irq_cfg
*cfg
, int node
, int apic
, int pin
)
437 if (__add_pin_to_irq_node(cfg
, node
, apic
, pin
))
438 panic("IO-APIC: failed to add irq-pin. Can not proceed\n");
442 * Reroute an IRQ to a different pin.
444 static void __init
replace_pin_at_irq_node(struct irq_cfg
*cfg
, int node
,
445 int oldapic
, int oldpin
,
446 int newapic
, int newpin
)
448 struct irq_pin_list
*entry
;
450 for_each_irq_pin(entry
, cfg
->irq_2_pin
) {
451 if (entry
->apic
== oldapic
&& entry
->pin
== oldpin
) {
452 entry
->apic
= newapic
;
454 /* every one is different, right? */
459 /* old apic/pin didn't exist, so just add new ones */
460 add_pin_to_irq_node(cfg
, node
, newapic
, newpin
);
463 static void __io_apic_modify_irq(struct irq_pin_list
*entry
,
464 int mask_and
, int mask_or
,
465 void (*final
)(struct irq_pin_list
*entry
))
467 unsigned int reg
, pin
;
470 reg
= io_apic_read(entry
->apic
, 0x10 + pin
* 2);
473 io_apic_modify(entry
->apic
, 0x10 + pin
* 2, reg
);
478 static void io_apic_modify_irq(struct irq_cfg
*cfg
,
479 int mask_and
, int mask_or
,
480 void (*final
)(struct irq_pin_list
*entry
))
482 struct irq_pin_list
*entry
;
484 for_each_irq_pin(entry
, cfg
->irq_2_pin
)
485 __io_apic_modify_irq(entry
, mask_and
, mask_or
, final
);
488 static void io_apic_sync(struct irq_pin_list
*entry
)
491 * Synchronize the IO-APIC and the CPU by doing
492 * a dummy read from the IO-APIC
494 struct io_apic __iomem
*io_apic
;
496 io_apic
= io_apic_base(entry
->apic
);
497 readl(&io_apic
->data
);
500 static void mask_ioapic(struct irq_cfg
*cfg
)
504 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
505 io_apic_modify_irq(cfg
, ~0, IO_APIC_REDIR_MASKED
, &io_apic_sync
);
506 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
509 static void mask_ioapic_irq(struct irq_data
*data
)
511 mask_ioapic(irqd_cfg(data
));
514 static void __unmask_ioapic(struct irq_cfg
*cfg
)
516 io_apic_modify_irq(cfg
, ~IO_APIC_REDIR_MASKED
, 0, NULL
);
519 static void unmask_ioapic(struct irq_cfg
*cfg
)
523 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
524 __unmask_ioapic(cfg
);
525 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
528 static void unmask_ioapic_irq(struct irq_data
*data
)
530 unmask_ioapic(irqd_cfg(data
));
534 * IO-APIC versions below 0x20 don't support EOI register.
535 * For the record, here is the information about various versions:
537 * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant
538 * 2Xh I/O(x)APIC which is PCI 2.2 Compliant
541 * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic
542 * version as 0x2. This is an error with documentation and these ICH chips
543 * use io-apic's of version 0x20.
545 * For IO-APIC's with EOI register, we use that to do an explicit EOI.
546 * Otherwise, we simulate the EOI message manually by changing the trigger
547 * mode to edge and then back to level, with RTE being masked during this.
549 void native_eoi_ioapic_pin(int apic
, int pin
, int vector
)
551 if (mpc_ioapic_ver(apic
) >= 0x20) {
552 io_apic_eoi(apic
, vector
);
554 struct IO_APIC_route_entry entry
, entry1
;
556 entry
= entry1
= __ioapic_read_entry(apic
, pin
);
559 * Mask the entry and change the trigger mode to edge.
562 entry1
.trigger
= IOAPIC_EDGE
;
564 __ioapic_write_entry(apic
, pin
, entry1
);
567 * Restore the previous level triggered entry.
569 __ioapic_write_entry(apic
, pin
, entry
);
573 void eoi_ioapic_irq(unsigned int irq
, struct irq_cfg
*cfg
)
575 struct irq_pin_list
*entry
;
578 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
579 for_each_irq_pin(entry
, cfg
->irq_2_pin
)
580 x86_io_apic_ops
.eoi_ioapic_pin(entry
->apic
, entry
->pin
,
582 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
585 static void clear_IO_APIC_pin(unsigned int apic
, unsigned int pin
)
587 struct IO_APIC_route_entry entry
;
589 /* Check delivery_mode to be sure we're not clearing an SMI pin */
590 entry
= ioapic_read_entry(apic
, pin
);
591 if (entry
.delivery_mode
== dest_SMI
)
595 * Make sure the entry is masked and re-read the contents to check
596 * if it is a level triggered pin and if the remote-IRR is set.
600 ioapic_write_entry(apic
, pin
, entry
);
601 entry
= ioapic_read_entry(apic
, pin
);
608 * Make sure the trigger mode is set to level. Explicit EOI
609 * doesn't clear the remote-IRR if the trigger mode is not
612 if (!entry
.trigger
) {
613 entry
.trigger
= IOAPIC_LEVEL
;
614 ioapic_write_entry(apic
, pin
, entry
);
617 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
618 x86_io_apic_ops
.eoi_ioapic_pin(apic
, pin
, entry
.vector
);
619 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
623 * Clear the rest of the bits in the IO-APIC RTE except for the mask
626 ioapic_mask_entry(apic
, pin
);
627 entry
= ioapic_read_entry(apic
, pin
);
629 pr_err("Unable to reset IRR for apic: %d, pin :%d\n",
630 mpc_ioapic_id(apic
), pin
);
633 static void clear_IO_APIC (void)
637 for_each_ioapic_pin(apic
, pin
)
638 clear_IO_APIC_pin(apic
, pin
);
643 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
644 * specific CPU-side IRQs.
648 static int pirq_entries
[MAX_PIRQS
] = {
649 [0 ... MAX_PIRQS
- 1] = -1
652 static int __init
ioapic_pirq_setup(char *str
)
655 int ints
[MAX_PIRQS
+1];
657 get_options(str
, ARRAY_SIZE(ints
), ints
);
659 apic_printk(APIC_VERBOSE
, KERN_INFO
660 "PIRQ redirection, working around broken MP-BIOS.\n");
662 if (ints
[0] < MAX_PIRQS
)
665 for (i
= 0; i
< max
; i
++) {
666 apic_printk(APIC_VERBOSE
, KERN_DEBUG
667 "... PIRQ%d -> IRQ %d\n", i
, ints
[i
+1]);
669 * PIRQs are mapped upside down, usually.
671 pirq_entries
[MAX_PIRQS
-i
-1] = ints
[i
+1];
676 __setup("pirq=", ioapic_pirq_setup
);
677 #endif /* CONFIG_X86_32 */
680 * Saves all the IO-APIC RTE's
682 int save_ioapic_entries(void)
687 for_each_ioapic(apic
) {
688 if (!ioapics
[apic
].saved_registers
) {
693 for_each_pin(apic
, pin
)
694 ioapics
[apic
].saved_registers
[pin
] =
695 ioapic_read_entry(apic
, pin
);
702 * Mask all IO APIC entries.
704 void mask_ioapic_entries(void)
708 for_each_ioapic(apic
) {
709 if (!ioapics
[apic
].saved_registers
)
712 for_each_pin(apic
, pin
) {
713 struct IO_APIC_route_entry entry
;
715 entry
= ioapics
[apic
].saved_registers
[pin
];
718 ioapic_write_entry(apic
, pin
, entry
);
725 * Restore IO APIC entries which was saved in the ioapic structure.
727 int restore_ioapic_entries(void)
731 for_each_ioapic(apic
) {
732 if (!ioapics
[apic
].saved_registers
)
735 for_each_pin(apic
, pin
)
736 ioapic_write_entry(apic
, pin
,
737 ioapics
[apic
].saved_registers
[pin
]);
743 * Find the IRQ entry number of a certain pin.
745 static int find_irq_entry(int ioapic_idx
, int pin
, int type
)
749 for (i
= 0; i
< mp_irq_entries
; i
++)
750 if (mp_irqs
[i
].irqtype
== type
&&
751 (mp_irqs
[i
].dstapic
== mpc_ioapic_id(ioapic_idx
) ||
752 mp_irqs
[i
].dstapic
== MP_APIC_ALL
) &&
753 mp_irqs
[i
].dstirq
== pin
)
760 * Find the pin to which IRQ[irq] (ISA) is connected
762 static int __init
find_isa_irq_pin(int irq
, int type
)
766 for (i
= 0; i
< mp_irq_entries
; i
++) {
767 int lbus
= mp_irqs
[i
].srcbus
;
769 if (test_bit(lbus
, mp_bus_not_pci
) &&
770 (mp_irqs
[i
].irqtype
== type
) &&
771 (mp_irqs
[i
].srcbusirq
== irq
))
773 return mp_irqs
[i
].dstirq
;
778 static int __init
find_isa_irq_apic(int irq
, int type
)
782 for (i
= 0; i
< mp_irq_entries
; i
++) {
783 int lbus
= mp_irqs
[i
].srcbus
;
785 if (test_bit(lbus
, mp_bus_not_pci
) &&
786 (mp_irqs
[i
].irqtype
== type
) &&
787 (mp_irqs
[i
].srcbusirq
== irq
))
791 if (i
< mp_irq_entries
) {
794 for_each_ioapic(ioapic_idx
)
795 if (mpc_ioapic_id(ioapic_idx
) == mp_irqs
[i
].dstapic
)
804 * EISA Edge/Level control register, ELCR
806 static int EISA_ELCR(unsigned int irq
)
808 if (irq
< nr_legacy_irqs()) {
809 unsigned int port
= 0x4d0 + (irq
>> 3);
810 return (inb(port
) >> (irq
& 7)) & 1;
812 apic_printk(APIC_VERBOSE
, KERN_INFO
813 "Broken MPtable reports ISA irq %d\n", irq
);
819 /* ISA interrupts are always polarity zero edge triggered,
820 * when listed as conforming in the MP table. */
822 #define default_ISA_trigger(idx) (0)
823 #define default_ISA_polarity(idx) (0)
825 /* EISA interrupts are always polarity zero and can be edge or level
826 * trigger depending on the ELCR value. If an interrupt is listed as
827 * EISA conforming in the MP table, that means its trigger type must
828 * be read in from the ELCR */
830 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq))
831 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
833 /* PCI interrupts are always polarity one level triggered,
834 * when listed as conforming in the MP table. */
836 #define default_PCI_trigger(idx) (1)
837 #define default_PCI_polarity(idx) (1)
839 static int irq_polarity(int idx
)
841 int bus
= mp_irqs
[idx
].srcbus
;
845 * Determine IRQ line polarity (high active or low active):
847 switch (mp_irqs
[idx
].irqflag
& 3)
849 case 0: /* conforms, ie. bus-type dependent polarity */
850 if (test_bit(bus
, mp_bus_not_pci
))
851 polarity
= default_ISA_polarity(idx
);
853 polarity
= default_PCI_polarity(idx
);
855 case 1: /* high active */
860 case 2: /* reserved */
862 pr_warn("broken BIOS!!\n");
866 case 3: /* low active */
871 default: /* invalid */
873 pr_warn("broken BIOS!!\n");
881 static int irq_trigger(int idx
)
883 int bus
= mp_irqs
[idx
].srcbus
;
887 * Determine IRQ trigger mode (edge or level sensitive):
889 switch ((mp_irqs
[idx
].irqflag
>>2) & 3)
891 case 0: /* conforms, ie. bus-type dependent */
892 if (test_bit(bus
, mp_bus_not_pci
))
893 trigger
= default_ISA_trigger(idx
);
895 trigger
= default_PCI_trigger(idx
);
897 switch (mp_bus_id_to_type
[bus
]) {
898 case MP_BUS_ISA
: /* ISA pin */
900 /* set before the switch */
903 case MP_BUS_EISA
: /* EISA pin */
905 trigger
= default_EISA_trigger(idx
);
908 case MP_BUS_PCI
: /* PCI pin */
910 /* set before the switch */
915 pr_warn("broken BIOS!!\n");
927 case 2: /* reserved */
929 pr_warn("broken BIOS!!\n");
938 default: /* invalid */
940 pr_warn("broken BIOS!!\n");
948 void ioapic_set_alloc_attr(struct irq_alloc_info
*info
, int node
,
949 int trigger
, int polarity
)
951 init_irq_alloc_info(info
, NULL
);
952 info
->type
= X86_IRQ_ALLOC_TYPE_IOAPIC
;
953 info
->ioapic_node
= node
;
954 info
->ioapic_trigger
= trigger
;
955 info
->ioapic_polarity
= polarity
;
956 info
->ioapic_valid
= 1;
959 static void mp_register_handler(unsigned int irq
, unsigned long trigger
)
961 irq_flow_handler_t hdl
;
965 irq_set_status_flags(irq
, IRQ_LEVEL
);
968 irq_clear_status_flags(irq
, IRQ_LEVEL
);
972 hdl
= fasteoi
? handle_fasteoi_irq
: handle_edge_irq
;
973 __irq_set_handler(irq
, hdl
, 0, fasteoi
? "fasteoi" : "edge");
976 static int alloc_irq_from_domain(struct irq_domain
*domain
, u32 gsi
, int pin
,
977 struct irq_alloc_info
*info
)
980 int ioapic
= mp_irqdomain_ioapic_idx(domain
);
981 int type
= ioapics
[ioapic
].irqdomain_cfg
.type
;
984 case IOAPIC_DOMAIN_LEGACY
:
986 * Dynamically allocate IRQ number for non-ISA IRQs in the first 16
987 * GSIs on some weird platforms.
989 if (gsi
< nr_legacy_irqs())
990 irq
= irq_create_mapping(domain
, pin
);
991 else if (irq_create_strict_mappings(domain
, gsi
, pin
, 1) == 0)
994 case IOAPIC_DOMAIN_STRICT
:
995 if (irq_create_strict_mappings(domain
, gsi
, pin
, 1) == 0)
998 case IOAPIC_DOMAIN_DYNAMIC
:
999 irq
= irq_create_mapping(domain
, pin
);
1002 WARN(1, "ioapic: unknown irqdomain type %d\n", type
);
1006 return irq
> 0 ? irq
: -1;
1009 static int mp_map_pin_to_irq(u32 gsi
, int idx
, int ioapic
, int pin
,
1010 unsigned int flags
, struct irq_alloc_info
*info
)
1013 struct irq_domain
*domain
= mp_ioapic_irqdomain(ioapic
);
1014 struct mp_pin_info
*pinfo
= mp_pin_info(ioapic
, pin
);
1019 mutex_lock(&ioapic_mutex
);
1022 * Don't use irqdomain to manage ISA IRQs because there may be
1023 * multiple IOAPIC pins sharing the same ISA IRQ number and
1024 * irqdomain only supports 1:1 mapping between IOAPIC pin and
1025 * IRQ number. A typical IOAPIC has 24 pins, pin 0-15 are used
1026 * for legacy IRQs and pin 16-23 are used for PCI IRQs (PIRQ A-H).
1027 * When ACPI is disabled, only legacy IRQ numbers (IRQ0-15) are
1028 * available, and some BIOSes may use MP Interrupt Source records
1029 * to override IRQ numbers for PIRQs instead of reprogramming
1030 * the interrupt routing logic. Thus there may be multiple pins
1031 * sharing the same legacy IRQ number when ACPI is disabled.
1033 if (idx
>= 0 && test_bit(mp_irqs
[idx
].srcbus
, mp_bus_not_pci
)) {
1034 irq
= mp_irqs
[idx
].srcbusirq
;
1035 if (flags
& IOAPIC_MAP_ALLOC
) {
1036 if (pinfo
->count
== 0 &&
1037 mp_irqdomain_map(domain
, irq
, pin
) != 0)
1040 /* special handling for timer IRQ0 */
1045 irq
= irq_find_mapping(domain
, pin
);
1046 if (irq
<= 0 && (flags
& IOAPIC_MAP_ALLOC
))
1047 irq
= alloc_irq_from_domain(domain
, gsi
, pin
, info
);
1050 if (flags
& IOAPIC_MAP_ALLOC
) {
1051 /* special handling for legacy IRQs */
1052 if (irq
< nr_legacy_irqs() && pinfo
->count
== 1 &&
1053 mp_irqdomain_map(domain
, irq
, pin
) != 0)
1058 else if (pinfo
->count
== 0)
1062 mutex_unlock(&ioapic_mutex
);
1064 return irq
> 0 ? irq
: -1;
1067 static int pin_2_irq(int idx
, int ioapic
, int pin
, unsigned int flags
)
1069 u32 gsi
= mp_pin_to_gsi(ioapic
, pin
);
1072 * Debugging check, we are in big trouble if this message pops up!
1074 if (mp_irqs
[idx
].dstirq
!= pin
)
1075 pr_err("broken BIOS or MPTABLE parser, ayiee!!\n");
1077 #ifdef CONFIG_X86_32
1079 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1081 if ((pin
>= 16) && (pin
<= 23)) {
1082 if (pirq_entries
[pin
-16] != -1) {
1083 if (!pirq_entries
[pin
-16]) {
1084 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1085 "disabling PIRQ%d\n", pin
-16);
1087 int irq
= pirq_entries
[pin
-16];
1088 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1089 "using PIRQ%d -> IRQ %d\n",
1097 return mp_map_pin_to_irq(gsi
, idx
, ioapic
, pin
, flags
, NULL
);
1100 int mp_map_gsi_to_irq(u32 gsi
, unsigned int flags
,
1101 struct irq_alloc_info
*info
)
1103 int ioapic
, pin
, idx
;
1105 ioapic
= mp_find_ioapic(gsi
);
1109 pin
= mp_find_ioapic_pin(ioapic
, gsi
);
1110 idx
= find_irq_entry(ioapic
, pin
, mp_INT
);
1111 if ((flags
& IOAPIC_MAP_CHECK
) && idx
< 0)
1114 return mp_map_pin_to_irq(gsi
, idx
, ioapic
, pin
, flags
, info
);
1117 void mp_unmap_irq(int irq
)
1119 struct irq_data
*data
= irq_get_irq_data(irq
);
1120 struct mp_pin_info
*info
;
1123 if (!data
|| !data
->domain
)
1126 ioapic
= (int)(long)data
->domain
->host_data
;
1127 pin
= (int)data
->hwirq
;
1128 info
= mp_pin_info(ioapic
, pin
);
1130 mutex_lock(&ioapic_mutex
);
1131 if (--info
->count
== 0) {
1133 if (irq
< nr_legacy_irqs() &&
1134 ioapics
[ioapic
].irqdomain_cfg
.type
== IOAPIC_DOMAIN_LEGACY
)
1135 mp_irqdomain_unmap(data
->domain
, irq
);
1137 irq_dispose_mapping(irq
);
1139 mutex_unlock(&ioapic_mutex
);
1143 * Find a specific PCI IRQ entry.
1144 * Not an __init, possibly needed by modules
1146 int IO_APIC_get_PCI_irq_vector(int bus
, int slot
, int pin
)
1148 int irq
, i
, best_ioapic
= -1, best_idx
= -1;
1150 apic_printk(APIC_DEBUG
,
1151 "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1153 if (test_bit(bus
, mp_bus_not_pci
)) {
1154 apic_printk(APIC_VERBOSE
,
1155 "PCI BIOS passed nonexistent PCI bus %d!\n", bus
);
1159 for (i
= 0; i
< mp_irq_entries
; i
++) {
1160 int lbus
= mp_irqs
[i
].srcbus
;
1161 int ioapic_idx
, found
= 0;
1163 if (bus
!= lbus
|| mp_irqs
[i
].irqtype
!= mp_INT
||
1164 slot
!= ((mp_irqs
[i
].srcbusirq
>> 2) & 0x1f))
1167 for_each_ioapic(ioapic_idx
)
1168 if (mpc_ioapic_id(ioapic_idx
) == mp_irqs
[i
].dstapic
||
1169 mp_irqs
[i
].dstapic
== MP_APIC_ALL
) {
1177 irq
= pin_2_irq(i
, ioapic_idx
, mp_irqs
[i
].dstirq
, 0);
1178 if (irq
> 0 && !IO_APIC_IRQ(irq
))
1181 if (pin
== (mp_irqs
[i
].srcbusirq
& 3)) {
1183 best_ioapic
= ioapic_idx
;
1188 * Use the first all-but-pin matching entry as a
1189 * best-guess fuzzy result for broken mptables.
1193 best_ioapic
= ioapic_idx
;
1200 return pin_2_irq(best_idx
, best_ioapic
, mp_irqs
[best_idx
].dstirq
,
1203 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector
);
1205 static struct irq_chip ioapic_chip
;
1207 #ifdef CONFIG_X86_32
1208 static inline int IO_APIC_irq_trigger(int irq
)
1212 for_each_ioapic_pin(apic
, pin
) {
1213 idx
= find_irq_entry(apic
, pin
, mp_INT
);
1214 if ((idx
!= -1) && (irq
== pin_2_irq(idx
, apic
, pin
, 0)))
1215 return irq_trigger(idx
);
1218 * nonexistent IRQs are edge default
1223 static inline int IO_APIC_irq_trigger(int irq
)
1229 static void ioapic_register_intr(unsigned int irq
, struct irq_cfg
*cfg
,
1230 unsigned long trigger
)
1232 struct irq_chip
*chip
= &ioapic_chip
;
1233 irq_flow_handler_t hdl
;
1236 if ((trigger
== IOAPIC_AUTO
&& IO_APIC_irq_trigger(irq
)) ||
1237 trigger
== IOAPIC_LEVEL
) {
1238 irq_set_status_flags(irq
, IRQ_LEVEL
);
1241 irq_clear_status_flags(irq
, IRQ_LEVEL
);
1245 if (setup_remapped_irq(irq
, cfg
, chip
))
1246 fasteoi
= trigger
!= 0;
1248 hdl
= fasteoi
? handle_fasteoi_irq
: handle_edge_irq
;
1249 irq_set_chip_and_handler_name(irq
, chip
, hdl
,
1250 fasteoi
? "fasteoi" : "edge");
1253 int native_setup_ioapic_entry(int irq
, struct IO_APIC_route_entry
*entry
,
1254 unsigned int destination
, int vector
,
1255 struct io_apic_irq_attr
*attr
)
1257 memset(entry
, 0, sizeof(*entry
));
1259 entry
->delivery_mode
= apic
->irq_delivery_mode
;
1260 entry
->dest_mode
= apic
->irq_dest_mode
;
1261 entry
->dest
= destination
;
1262 entry
->vector
= vector
;
1263 entry
->mask
= 0; /* enable IRQ */
1264 entry
->trigger
= attr
->trigger
;
1265 entry
->polarity
= attr
->polarity
;
1268 * Mask level triggered irqs.
1269 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1277 static void setup_ioapic_irq(unsigned int irq
, struct irq_cfg
*cfg
,
1278 struct io_apic_irq_attr
*attr
)
1280 struct IO_APIC_route_entry entry
;
1283 if (!IO_APIC_IRQ(irq
))
1286 if (assign_irq_vector(irq
, cfg
, apic
->target_cpus()))
1289 if (apic
->cpu_mask_to_apicid_and(cfg
->domain
, apic
->target_cpus(),
1291 pr_warn("Failed to obtain apicid for ioapic %d, pin %d\n",
1292 mpc_ioapic_id(attr
->ioapic
), attr
->ioapic_pin
);
1293 clear_irq_vector(irq
, cfg
);
1298 apic_printk(APIC_VERBOSE
,KERN_DEBUG
1299 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1300 "IRQ %d Mode:%i Active:%i Dest:%d)\n",
1301 attr
->ioapic
, mpc_ioapic_id(attr
->ioapic
), attr
->ioapic_pin
,
1302 cfg
->vector
, irq
, attr
->trigger
, attr
->polarity
, dest
);
1304 if (x86_io_apic_ops
.setup_entry(irq
, &entry
, dest
, cfg
->vector
, attr
)) {
1305 pr_warn("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1306 mpc_ioapic_id(attr
->ioapic
), attr
->ioapic_pin
);
1307 clear_irq_vector(irq
, cfg
);
1312 ioapic_register_intr(irq
, cfg
, attr
->trigger
);
1313 if (irq
< nr_legacy_irqs())
1314 legacy_pic
->mask(irq
);
1316 ioapic_write_entry(attr
->ioapic
, attr
->ioapic_pin
, entry
);
1319 static void __init
setup_IO_APIC_irqs(void)
1321 unsigned int ioapic
, pin
;
1324 apic_printk(APIC_VERBOSE
, KERN_DEBUG
"init IO_APIC IRQs\n");
1326 for_each_ioapic_pin(ioapic
, pin
) {
1327 idx
= find_irq_entry(ioapic
, pin
, mp_INT
);
1329 apic_printk(APIC_VERBOSE
,
1330 KERN_DEBUG
" apic %d pin %d not connected\n",
1331 mpc_ioapic_id(ioapic
), pin
);
1333 pin_2_irq(idx
, ioapic
, pin
,
1334 ioapic
? 0 : IOAPIC_MAP_ALLOC
);
1339 * Set up the timer pin, possibly with the 8259A-master behind.
1341 static void __init
setup_timer_IRQ0_pin(unsigned int ioapic_idx
,
1342 unsigned int pin
, int vector
)
1344 struct IO_APIC_route_entry entry
;
1347 memset(&entry
, 0, sizeof(entry
));
1350 * We use logical delivery to get the timer IRQ
1353 if (unlikely(apic
->cpu_mask_to_apicid_and(apic
->target_cpus(),
1354 apic
->target_cpus(), &dest
)))
1357 entry
.dest_mode
= apic
->irq_dest_mode
;
1358 entry
.mask
= 0; /* don't mask IRQ for edge */
1360 entry
.delivery_mode
= apic
->irq_delivery_mode
;
1363 entry
.vector
= vector
;
1366 * The timer IRQ doesn't have to know that behind the
1367 * scene we may have a 8259A-master in AEOI mode ...
1369 irq_set_chip_and_handler_name(0, &ioapic_chip
, handle_edge_irq
,
1373 * Add it to the IO-APIC irq-routing table:
1375 ioapic_write_entry(ioapic_idx
, pin
, entry
);
1378 void native_io_apic_print_entries(unsigned int apic
, unsigned int nr_entries
)
1382 pr_debug(" NR Dst Mask Trig IRR Pol Stat Dmod Deli Vect:\n");
1384 for (i
= 0; i
<= nr_entries
; i
++) {
1385 struct IO_APIC_route_entry entry
;
1387 entry
= ioapic_read_entry(apic
, i
);
1389 pr_debug(" %02x %02X ", i
, entry
.dest
);
1390 pr_cont("%1d %1d %1d %1d %1d "
1396 entry
.delivery_status
,
1398 entry
.delivery_mode
,
1403 void intel_ir_io_apic_print_entries(unsigned int apic
,
1404 unsigned int nr_entries
)
1408 pr_debug(" NR Indx Fmt Mask Trig IRR Pol Stat Indx2 Zero Vect:\n");
1410 for (i
= 0; i
<= nr_entries
; i
++) {
1411 struct IR_IO_APIC_route_entry
*ir_entry
;
1412 struct IO_APIC_route_entry entry
;
1414 entry
= ioapic_read_entry(apic
, i
);
1416 ir_entry
= (struct IR_IO_APIC_route_entry
*)&entry
;
1418 pr_debug(" %02x %04X ", i
, ir_entry
->index
);
1419 pr_cont("%1d %1d %1d %1d %1d "
1420 "%1d %1d %X %02X\n",
1426 ir_entry
->delivery_status
,
1433 void ioapic_zap_locks(void)
1435 raw_spin_lock_init(&ioapic_lock
);
1438 static void __init
print_IO_APIC(int ioapic_idx
)
1440 union IO_APIC_reg_00 reg_00
;
1441 union IO_APIC_reg_01 reg_01
;
1442 union IO_APIC_reg_02 reg_02
;
1443 union IO_APIC_reg_03 reg_03
;
1444 unsigned long flags
;
1446 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
1447 reg_00
.raw
= io_apic_read(ioapic_idx
, 0);
1448 reg_01
.raw
= io_apic_read(ioapic_idx
, 1);
1449 if (reg_01
.bits
.version
>= 0x10)
1450 reg_02
.raw
= io_apic_read(ioapic_idx
, 2);
1451 if (reg_01
.bits
.version
>= 0x20)
1452 reg_03
.raw
= io_apic_read(ioapic_idx
, 3);
1453 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
1455 printk(KERN_DEBUG
"IO APIC #%d......\n", mpc_ioapic_id(ioapic_idx
));
1456 printk(KERN_DEBUG
".... register #00: %08X\n", reg_00
.raw
);
1457 printk(KERN_DEBUG
"....... : physical APIC id: %02X\n", reg_00
.bits
.ID
);
1458 printk(KERN_DEBUG
"....... : Delivery Type: %X\n", reg_00
.bits
.delivery_type
);
1459 printk(KERN_DEBUG
"....... : LTS : %X\n", reg_00
.bits
.LTS
);
1461 printk(KERN_DEBUG
".... register #01: %08X\n", *(int *)®_01
);
1462 printk(KERN_DEBUG
"....... : max redirection entries: %02X\n",
1463 reg_01
.bits
.entries
);
1465 printk(KERN_DEBUG
"....... : PRQ implemented: %X\n", reg_01
.bits
.PRQ
);
1466 printk(KERN_DEBUG
"....... : IO APIC version: %02X\n",
1467 reg_01
.bits
.version
);
1470 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1471 * but the value of reg_02 is read as the previous read register
1472 * value, so ignore it if reg_02 == reg_01.
1474 if (reg_01
.bits
.version
>= 0x10 && reg_02
.raw
!= reg_01
.raw
) {
1475 printk(KERN_DEBUG
".... register #02: %08X\n", reg_02
.raw
);
1476 printk(KERN_DEBUG
"....... : arbitration: %02X\n", reg_02
.bits
.arbitration
);
1480 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1481 * or reg_03, but the value of reg_0[23] is read as the previous read
1482 * register value, so ignore it if reg_03 == reg_0[12].
1484 if (reg_01
.bits
.version
>= 0x20 && reg_03
.raw
!= reg_02
.raw
&&
1485 reg_03
.raw
!= reg_01
.raw
) {
1486 printk(KERN_DEBUG
".... register #03: %08X\n", reg_03
.raw
);
1487 printk(KERN_DEBUG
"....... : Boot DT : %X\n", reg_03
.bits
.boot_DT
);
1490 printk(KERN_DEBUG
".... IRQ redirection table:\n");
1492 x86_io_apic_ops
.print_entries(ioapic_idx
, reg_01
.bits
.entries
);
1495 void __init
print_IO_APICs(void)
1498 struct irq_cfg
*cfg
;
1500 struct irq_chip
*chip
;
1502 printk(KERN_DEBUG
"number of MP IRQ sources: %d.\n", mp_irq_entries
);
1503 for_each_ioapic(ioapic_idx
)
1504 printk(KERN_DEBUG
"number of IO-APIC #%d registers: %d.\n",
1505 mpc_ioapic_id(ioapic_idx
),
1506 ioapics
[ioapic_idx
].nr_registers
);
1509 * We are a bit conservative about what we expect. We have to
1510 * know about every hardware change ASAP.
1512 printk(KERN_INFO
"testing the IO APIC.......................\n");
1514 for_each_ioapic(ioapic_idx
)
1515 print_IO_APIC(ioapic_idx
);
1517 printk(KERN_DEBUG
"IRQ to pin mappings:\n");
1518 for_each_active_irq(irq
) {
1519 struct irq_pin_list
*entry
;
1521 chip
= irq_get_chip(irq
);
1522 if (chip
!= &ioapic_chip
)
1528 if (list_empty(&cfg
->irq_2_pin
))
1530 printk(KERN_DEBUG
"IRQ%d ", irq
);
1531 for_each_irq_pin(entry
, cfg
->irq_2_pin
)
1532 pr_cont("-> %d:%d", entry
->apic
, entry
->pin
);
1536 printk(KERN_INFO
".................................... done.\n");
1539 /* Where if anywhere is the i8259 connect in external int mode */
1540 static struct { int pin
, apic
; } ioapic_i8259
= { -1, -1 };
1542 void __init
enable_IO_APIC(void)
1544 int i8259_apic
, i8259_pin
;
1547 if (skip_ioapic_setup
)
1550 if (!nr_legacy_irqs() || !nr_ioapics
)
1553 for_each_ioapic_pin(apic
, pin
) {
1554 /* See if any of the pins is in ExtINT mode */
1555 struct IO_APIC_route_entry entry
= ioapic_read_entry(apic
, pin
);
1557 /* If the interrupt line is enabled and in ExtInt mode
1558 * I have found the pin where the i8259 is connected.
1560 if ((entry
.mask
== 0) && (entry
.delivery_mode
== dest_ExtINT
)) {
1561 ioapic_i8259
.apic
= apic
;
1562 ioapic_i8259
.pin
= pin
;
1567 /* Look to see what if the MP table has reported the ExtINT */
1568 /* If we could not find the appropriate pin by looking at the ioapic
1569 * the i8259 probably is not connected the ioapic but give the
1570 * mptable a chance anyway.
1572 i8259_pin
= find_isa_irq_pin(0, mp_ExtINT
);
1573 i8259_apic
= find_isa_irq_apic(0, mp_ExtINT
);
1574 /* Trust the MP table if nothing is setup in the hardware */
1575 if ((ioapic_i8259
.pin
== -1) && (i8259_pin
>= 0)) {
1576 printk(KERN_WARNING
"ExtINT not setup in hardware but reported by MP table\n");
1577 ioapic_i8259
.pin
= i8259_pin
;
1578 ioapic_i8259
.apic
= i8259_apic
;
1580 /* Complain if the MP table and the hardware disagree */
1581 if (((ioapic_i8259
.apic
!= i8259_apic
) || (ioapic_i8259
.pin
!= i8259_pin
)) &&
1582 (i8259_pin
>= 0) && (ioapic_i8259
.pin
>= 0))
1584 printk(KERN_WARNING
"ExtINT in hardware and MP table differ\n");
1588 * Do not trust the IO-APIC being empty at bootup
1593 void native_disable_io_apic(void)
1596 * If the i8259 is routed through an IOAPIC
1597 * Put that IOAPIC in virtual wire mode
1598 * so legacy interrupts can be delivered.
1600 if (ioapic_i8259
.pin
!= -1) {
1601 struct IO_APIC_route_entry entry
;
1603 memset(&entry
, 0, sizeof(entry
));
1604 entry
.mask
= 0; /* Enabled */
1605 entry
.trigger
= 0; /* Edge */
1607 entry
.polarity
= 0; /* High */
1608 entry
.delivery_status
= 0;
1609 entry
.dest_mode
= 0; /* Physical */
1610 entry
.delivery_mode
= dest_ExtINT
; /* ExtInt */
1612 entry
.dest
= read_apic_id();
1615 * Add it to the IO-APIC irq-routing table:
1617 ioapic_write_entry(ioapic_i8259
.apic
, ioapic_i8259
.pin
, entry
);
1620 if (cpu_has_apic
|| apic_from_smp_config())
1621 disconnect_bsp_APIC(ioapic_i8259
.pin
!= -1);
1626 * Not an __init, needed by the reboot code
1628 void disable_IO_APIC(void)
1631 * Clear the IO-APIC before rebooting:
1635 if (!nr_legacy_irqs())
1638 x86_io_apic_ops
.disable();
1641 #ifdef CONFIG_X86_32
1643 * function to set the IO-APIC physical IDs based on the
1644 * values stored in the MPC table.
1646 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1648 void __init
setup_ioapic_ids_from_mpc_nocheck(void)
1650 union IO_APIC_reg_00 reg_00
;
1651 physid_mask_t phys_id_present_map
;
1654 unsigned char old_id
;
1655 unsigned long flags
;
1658 * This is broken; anything with a real cpu count has to
1659 * circumvent this idiocy regardless.
1661 apic
->ioapic_phys_id_map(&phys_cpu_present_map
, &phys_id_present_map
);
1664 * Set the IOAPIC ID to the value stored in the MPC table.
1666 for_each_ioapic(ioapic_idx
) {
1667 /* Read the register 0 value */
1668 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
1669 reg_00
.raw
= io_apic_read(ioapic_idx
, 0);
1670 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
1672 old_id
= mpc_ioapic_id(ioapic_idx
);
1674 if (mpc_ioapic_id(ioapic_idx
) >= get_physical_broadcast()) {
1675 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1676 ioapic_idx
, mpc_ioapic_id(ioapic_idx
));
1677 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
1679 ioapics
[ioapic_idx
].mp_config
.apicid
= reg_00
.bits
.ID
;
1683 * Sanity check, is the ID really free? Every APIC in a
1684 * system must have a unique ID or we get lots of nice
1685 * 'stuck on smp_invalidate_needed IPI wait' messages.
1687 if (apic
->check_apicid_used(&phys_id_present_map
,
1688 mpc_ioapic_id(ioapic_idx
))) {
1689 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1690 ioapic_idx
, mpc_ioapic_id(ioapic_idx
));
1691 for (i
= 0; i
< get_physical_broadcast(); i
++)
1692 if (!physid_isset(i
, phys_id_present_map
))
1694 if (i
>= get_physical_broadcast())
1695 panic("Max APIC ID exceeded!\n");
1696 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
1698 physid_set(i
, phys_id_present_map
);
1699 ioapics
[ioapic_idx
].mp_config
.apicid
= i
;
1702 apic
->apicid_to_cpu_present(mpc_ioapic_id(ioapic_idx
),
1704 apic_printk(APIC_VERBOSE
, "Setting %d in the "
1705 "phys_id_present_map\n",
1706 mpc_ioapic_id(ioapic_idx
));
1707 physids_or(phys_id_present_map
, phys_id_present_map
, tmp
);
1711 * We need to adjust the IRQ routing table
1712 * if the ID changed.
1714 if (old_id
!= mpc_ioapic_id(ioapic_idx
))
1715 for (i
= 0; i
< mp_irq_entries
; i
++)
1716 if (mp_irqs
[i
].dstapic
== old_id
)
1718 = mpc_ioapic_id(ioapic_idx
);
1721 * Update the ID register according to the right value
1722 * from the MPC table if they are different.
1724 if (mpc_ioapic_id(ioapic_idx
) == reg_00
.bits
.ID
)
1727 apic_printk(APIC_VERBOSE
, KERN_INFO
1728 "...changing IO-APIC physical APIC ID to %d ...",
1729 mpc_ioapic_id(ioapic_idx
));
1731 reg_00
.bits
.ID
= mpc_ioapic_id(ioapic_idx
);
1732 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
1733 io_apic_write(ioapic_idx
, 0, reg_00
.raw
);
1734 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
1739 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
1740 reg_00
.raw
= io_apic_read(ioapic_idx
, 0);
1741 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
1742 if (reg_00
.bits
.ID
!= mpc_ioapic_id(ioapic_idx
))
1743 pr_cont("could not set ID!\n");
1745 apic_printk(APIC_VERBOSE
, " ok.\n");
1749 void __init
setup_ioapic_ids_from_mpc(void)
1755 * Don't check I/O APIC IDs for xAPIC systems. They have
1756 * no meaning without the serial APIC bus.
1758 if (!(boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
)
1759 || APIC_XAPIC(apic_version
[boot_cpu_physical_apicid
]))
1761 setup_ioapic_ids_from_mpc_nocheck();
1765 int no_timer_check __initdata
;
1767 static int __init
notimercheck(char *s
)
1772 __setup("no_timer_check", notimercheck
);
1775 * There is a nasty bug in some older SMP boards, their mptable lies
1776 * about the timer IRQ. We do the following to work around the situation:
1778 * - timer IRQ defaults to IO-APIC IRQ
1779 * - if this function detects that timer IRQs are defunct, then we fall
1780 * back to ISA timer IRQs
1782 static int __init
timer_irq_works(void)
1784 unsigned long t1
= jiffies
;
1785 unsigned long flags
;
1790 local_save_flags(flags
);
1792 /* Let ten ticks pass... */
1793 mdelay((10 * 1000) / HZ
);
1794 local_irq_restore(flags
);
1797 * Expect a few ticks at least, to be sure some possible
1798 * glue logic does not lock up after one or two first
1799 * ticks in a non-ExtINT mode. Also the local APIC
1800 * might have cached one ExtINT interrupt. Finally, at
1801 * least one tick may be lost due to delays.
1805 if (time_after(jiffies
, t1
+ 4))
1811 * In the SMP+IOAPIC case it might happen that there are an unspecified
1812 * number of pending IRQ events unhandled. These cases are very rare,
1813 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1814 * better to do it this way as thus we do not have to be aware of
1815 * 'pending' interrupts in the IRQ path, except at this point.
1818 * Edge triggered needs to resend any interrupt
1819 * that was delayed but this is now handled in the device
1824 * Starting up a edge-triggered IO-APIC interrupt is
1825 * nasty - we need to make sure that we get the edge.
1826 * If it is already asserted for some reason, we need
1827 * return 1 to indicate that is was pending.
1829 * This is not complete - we should be able to fake
1830 * an edge even if it isn't on the 8259A...
1833 static unsigned int startup_ioapic_irq(struct irq_data
*data
)
1835 int was_pending
= 0, irq
= data
->irq
;
1836 unsigned long flags
;
1838 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
1839 if (irq
< nr_legacy_irqs()) {
1840 legacy_pic
->mask(irq
);
1841 if (legacy_pic
->irq_pending(irq
))
1844 __unmask_ioapic(irqd_cfg(data
));
1845 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
1851 * Level and edge triggered IO-APIC interrupts need different handling,
1852 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1853 * handled with the level-triggered descriptor, but that one has slightly
1854 * more overhead. Level-triggered interrupts cannot be handled with the
1855 * edge-triggered handler, without risking IRQ storms and other ugly
1859 static void __target_IO_APIC_irq(unsigned int irq
, unsigned int dest
, struct irq_cfg
*cfg
)
1862 struct irq_pin_list
*entry
;
1863 u8 vector
= cfg
->vector
;
1865 for_each_irq_pin(entry
, cfg
->irq_2_pin
) {
1871 io_apic_write(apic
, 0x11 + pin
*2, dest
);
1872 reg
= io_apic_read(apic
, 0x10 + pin
*2);
1873 reg
&= ~IO_APIC_REDIR_VECTOR_MASK
;
1875 io_apic_modify(apic
, 0x10 + pin
*2, reg
);
1879 int native_ioapic_set_affinity(struct irq_data
*data
,
1880 const struct cpumask
*mask
,
1883 unsigned int dest
, irq
= data
->irq
;
1884 unsigned long flags
;
1887 if (!config_enabled(CONFIG_SMP
))
1890 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
1891 ret
= apic_set_affinity(data
, mask
, &dest
);
1893 /* Only the high 8 bits are valid. */
1894 dest
= SET_APIC_LOGICAL_ID(dest
);
1895 __target_IO_APIC_irq(irq
, dest
, irqd_cfg(data
));
1896 ret
= IRQ_SET_MASK_OK_NOCOPY
;
1898 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
1902 atomic_t irq_mis_count
;
1904 #ifdef CONFIG_GENERIC_PENDING_IRQ
1905 static bool io_apic_level_ack_pending(struct irq_cfg
*cfg
)
1907 struct irq_pin_list
*entry
;
1908 unsigned long flags
;
1910 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
1911 for_each_irq_pin(entry
, cfg
->irq_2_pin
) {
1916 reg
= io_apic_read(entry
->apic
, 0x10 + pin
*2);
1917 /* Is the remote IRR bit set? */
1918 if (reg
& IO_APIC_REDIR_REMOTE_IRR
) {
1919 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
1923 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
1928 static inline bool ioapic_irqd_mask(struct irq_data
*data
, struct irq_cfg
*cfg
)
1930 /* If we are moving the irq we need to mask it */
1931 if (unlikely(irqd_is_setaffinity_pending(data
))) {
1938 static inline void ioapic_irqd_unmask(struct irq_data
*data
,
1939 struct irq_cfg
*cfg
, bool masked
)
1941 if (unlikely(masked
)) {
1942 /* Only migrate the irq if the ack has been received.
1944 * On rare occasions the broadcast level triggered ack gets
1945 * delayed going to ioapics, and if we reprogram the
1946 * vector while Remote IRR is still set the irq will never
1949 * To prevent this scenario we read the Remote IRR bit
1950 * of the ioapic. This has two effects.
1951 * - On any sane system the read of the ioapic will
1952 * flush writes (and acks) going to the ioapic from
1954 * - We get to see if the ACK has actually been delivered.
1956 * Based on failed experiments of reprogramming the
1957 * ioapic entry from outside of irq context starting
1958 * with masking the ioapic entry and then polling until
1959 * Remote IRR was clear before reprogramming the
1960 * ioapic I don't trust the Remote IRR bit to be
1961 * completey accurate.
1963 * However there appears to be no other way to plug
1964 * this race, so if the Remote IRR bit is not
1965 * accurate and is causing problems then it is a hardware bug
1966 * and you can go talk to the chipset vendor about it.
1968 if (!io_apic_level_ack_pending(cfg
))
1969 irq_move_masked_irq(data
);
1974 static inline bool ioapic_irqd_mask(struct irq_data
*data
, struct irq_cfg
*cfg
)
1978 static inline void ioapic_irqd_unmask(struct irq_data
*data
,
1979 struct irq_cfg
*cfg
, bool masked
)
1984 static void ack_ioapic_level(struct irq_data
*data
)
1986 struct irq_cfg
*cfg
= irqd_cfg(data
);
1987 int i
, irq
= data
->irq
;
1991 irq_complete_move(cfg
);
1992 masked
= ioapic_irqd_mask(data
, cfg
);
1995 * It appears there is an erratum which affects at least version 0x11
1996 * of I/O APIC (that's the 82093AA and cores integrated into various
1997 * chipsets). Under certain conditions a level-triggered interrupt is
1998 * erroneously delivered as edge-triggered one but the respective IRR
1999 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2000 * message but it will never arrive and further interrupts are blocked
2001 * from the source. The exact reason is so far unknown, but the
2002 * phenomenon was observed when two consecutive interrupt requests
2003 * from a given source get delivered to the same CPU and the source is
2004 * temporarily disabled in between.
2006 * A workaround is to simulate an EOI message manually. We achieve it
2007 * by setting the trigger mode to edge and then to level when the edge
2008 * trigger mode gets detected in the TMR of a local APIC for a
2009 * level-triggered interrupt. We mask the source for the time of the
2010 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2011 * The idea is from Manfred Spraul. --macro
2013 * Also in the case when cpu goes offline, fixup_irqs() will forward
2014 * any unhandled interrupt on the offlined cpu to the new cpu
2015 * destination that is handling the corresponding interrupt. This
2016 * interrupt forwarding is done via IPI's. Hence, in this case also
2017 * level-triggered io-apic interrupt will be seen as an edge
2018 * interrupt in the IRR. And we can't rely on the cpu's EOI
2019 * to be broadcasted to the IO-APIC's which will clear the remoteIRR
2020 * corresponding to the level-triggered interrupt. Hence on IO-APIC's
2021 * supporting EOI register, we do an explicit EOI to clear the
2022 * remote IRR and on IO-APIC's which don't have an EOI register,
2023 * we use the above logic (mask+edge followed by unmask+level) from
2024 * Manfred Spraul to clear the remote IRR.
2027 v
= apic_read(APIC_TMR
+ ((i
& ~0x1f) >> 1));
2030 * We must acknowledge the irq before we move it or the acknowledge will
2031 * not propagate properly.
2036 * Tail end of clearing remote IRR bit (either by delivering the EOI
2037 * message via io-apic EOI register write or simulating it using
2038 * mask+edge followed by unnask+level logic) manually when the
2039 * level triggered interrupt is seen as the edge triggered interrupt
2042 if (!(v
& (1 << (i
& 0x1f)))) {
2043 atomic_inc(&irq_mis_count
);
2045 eoi_ioapic_irq(irq
, cfg
);
2048 ioapic_irqd_unmask(data
, cfg
, masked
);
2051 static struct irq_chip ioapic_chip __read_mostly
= {
2053 .irq_startup
= startup_ioapic_irq
,
2054 .irq_mask
= mask_ioapic_irq
,
2055 .irq_unmask
= unmask_ioapic_irq
,
2056 .irq_ack
= apic_ack_edge
,
2057 .irq_eoi
= ack_ioapic_level
,
2058 .irq_set_affinity
= native_ioapic_set_affinity
,
2059 .irq_retrigger
= apic_retrigger_irq
,
2060 .flags
= IRQCHIP_SKIP_SET_WAKE
,
2063 static inline void init_IO_APIC_traps(void)
2065 struct irq_cfg
*cfg
;
2068 for_each_active_irq(irq
) {
2070 if (IO_APIC_IRQ(irq
) && cfg
&& !cfg
->vector
) {
2072 * Hmm.. We don't have an entry for this,
2073 * so default to an old-fashioned 8259
2074 * interrupt if we can..
2076 if (irq
< nr_legacy_irqs())
2077 legacy_pic
->make_irq(irq
);
2079 /* Strange. Oh, well.. */
2080 irq_set_chip(irq
, &no_irq_chip
);
2086 * The local APIC irq-chip implementation:
2089 static void mask_lapic_irq(struct irq_data
*data
)
2093 v
= apic_read(APIC_LVT0
);
2094 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
2097 static void unmask_lapic_irq(struct irq_data
*data
)
2101 v
= apic_read(APIC_LVT0
);
2102 apic_write(APIC_LVT0
, v
& ~APIC_LVT_MASKED
);
2105 static void ack_lapic_irq(struct irq_data
*data
)
2110 static struct irq_chip lapic_chip __read_mostly
= {
2111 .name
= "local-APIC",
2112 .irq_mask
= mask_lapic_irq
,
2113 .irq_unmask
= unmask_lapic_irq
,
2114 .irq_ack
= ack_lapic_irq
,
2117 static void lapic_register_intr(int irq
)
2119 irq_clear_status_flags(irq
, IRQ_LEVEL
);
2120 irq_set_chip_and_handler_name(irq
, &lapic_chip
, handle_edge_irq
,
2125 * This looks a bit hackish but it's about the only one way of sending
2126 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2127 * not support the ExtINT mode, unfortunately. We need to send these
2128 * cycles as some i82489DX-based boards have glue logic that keeps the
2129 * 8259A interrupt line asserted until INTA. --macro
2131 static inline void __init
unlock_ExtINT_logic(void)
2134 struct IO_APIC_route_entry entry0
, entry1
;
2135 unsigned char save_control
, save_freq_select
;
2137 pin
= find_isa_irq_pin(8, mp_INT
);
2142 apic
= find_isa_irq_apic(8, mp_INT
);
2148 entry0
= ioapic_read_entry(apic
, pin
);
2149 clear_IO_APIC_pin(apic
, pin
);
2151 memset(&entry1
, 0, sizeof(entry1
));
2153 entry1
.dest_mode
= 0; /* physical delivery */
2154 entry1
.mask
= 0; /* unmask IRQ now */
2155 entry1
.dest
= hard_smp_processor_id();
2156 entry1
.delivery_mode
= dest_ExtINT
;
2157 entry1
.polarity
= entry0
.polarity
;
2161 ioapic_write_entry(apic
, pin
, entry1
);
2163 save_control
= CMOS_READ(RTC_CONTROL
);
2164 save_freq_select
= CMOS_READ(RTC_FREQ_SELECT
);
2165 CMOS_WRITE((save_freq_select
& ~RTC_RATE_SELECT
) | 0x6,
2167 CMOS_WRITE(save_control
| RTC_PIE
, RTC_CONTROL
);
2172 if ((CMOS_READ(RTC_INTR_FLAGS
) & RTC_PF
) == RTC_PF
)
2176 CMOS_WRITE(save_control
, RTC_CONTROL
);
2177 CMOS_WRITE(save_freq_select
, RTC_FREQ_SELECT
);
2178 clear_IO_APIC_pin(apic
, pin
);
2180 ioapic_write_entry(apic
, pin
, entry0
);
2183 static int disable_timer_pin_1 __initdata
;
2184 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2185 static int __init
disable_timer_pin_setup(char *arg
)
2187 disable_timer_pin_1
= 1;
2190 early_param("disable_timer_pin_1", disable_timer_pin_setup
);
2193 * This code may look a bit paranoid, but it's supposed to cooperate with
2194 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2195 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2196 * fanatically on his truly buggy board.
2198 * FIXME: really need to revamp this for all platforms.
2200 static inline void __init
check_timer(void)
2202 struct irq_cfg
*cfg
= irq_cfg(0);
2203 int node
= cpu_to_node(0);
2204 int apic1
, pin1
, apic2
, pin2
;
2205 unsigned long flags
;
2208 local_irq_save(flags
);
2211 * get/set the timer IRQ vector:
2213 legacy_pic
->mask(0);
2214 assign_irq_vector(0, cfg
, apic
->target_cpus());
2217 * As IRQ0 is to be enabled in the 8259A, the virtual
2218 * wire has to be disabled in the local APIC. Also
2219 * timer interrupts need to be acknowledged manually in
2220 * the 8259A for the i82489DX when using the NMI
2221 * watchdog as that APIC treats NMIs as level-triggered.
2222 * The AEOI mode will finish them in the 8259A
2225 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_EXTINT
);
2226 legacy_pic
->init(1);
2228 pin1
= find_isa_irq_pin(0, mp_INT
);
2229 apic1
= find_isa_irq_apic(0, mp_INT
);
2230 pin2
= ioapic_i8259
.pin
;
2231 apic2
= ioapic_i8259
.apic
;
2233 apic_printk(APIC_QUIET
, KERN_INFO
"..TIMER: vector=0x%02X "
2234 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2235 cfg
->vector
, apic1
, pin1
, apic2
, pin2
);
2238 * Some BIOS writers are clueless and report the ExtINTA
2239 * I/O APIC input from the cascaded 8259A as the timer
2240 * interrupt input. So just in case, if only one pin
2241 * was found above, try it both directly and through the
2245 panic_if_irq_remap("BIOS bug: timer not connected to IO-APIC");
2249 } else if (pin2
== -1) {
2256 * Ok, does IRQ0 through the IOAPIC work?
2259 add_pin_to_irq_node(cfg
, node
, apic1
, pin1
);
2260 setup_timer_IRQ0_pin(apic1
, pin1
, cfg
->vector
);
2262 /* for edge trigger, setup_ioapic_irq already
2263 * leave it unmasked.
2264 * so only need to unmask if it is level-trigger
2265 * do we really have level trigger timer?
2268 idx
= find_irq_entry(apic1
, pin1
, mp_INT
);
2269 if (idx
!= -1 && irq_trigger(idx
))
2272 if (timer_irq_works()) {
2273 if (disable_timer_pin_1
> 0)
2274 clear_IO_APIC_pin(0, pin1
);
2277 panic_if_irq_remap("timer doesn't work through Interrupt-remapped IO-APIC");
2278 local_irq_disable();
2279 clear_IO_APIC_pin(apic1
, pin1
);
2281 apic_printk(APIC_QUIET
, KERN_ERR
"..MP-BIOS bug: "
2282 "8254 timer not connected to IO-APIC\n");
2284 apic_printk(APIC_QUIET
, KERN_INFO
"...trying to set up timer "
2285 "(IRQ0) through the 8259A ...\n");
2286 apic_printk(APIC_QUIET
, KERN_INFO
2287 "..... (found apic %d pin %d) ...\n", apic2
, pin2
);
2289 * legacy devices should be connected to IO APIC #0
2291 replace_pin_at_irq_node(cfg
, node
, apic1
, pin1
, apic2
, pin2
);
2292 setup_timer_IRQ0_pin(apic2
, pin2
, cfg
->vector
);
2293 legacy_pic
->unmask(0);
2294 if (timer_irq_works()) {
2295 apic_printk(APIC_QUIET
, KERN_INFO
"....... works.\n");
2299 * Cleanup, just in case ...
2301 local_irq_disable();
2302 legacy_pic
->mask(0);
2303 clear_IO_APIC_pin(apic2
, pin2
);
2304 apic_printk(APIC_QUIET
, KERN_INFO
"....... failed.\n");
2307 apic_printk(APIC_QUIET
, KERN_INFO
2308 "...trying to set up timer as Virtual Wire IRQ...\n");
2310 lapic_register_intr(0);
2311 apic_write(APIC_LVT0
, APIC_DM_FIXED
| cfg
->vector
); /* Fixed mode */
2312 legacy_pic
->unmask(0);
2314 if (timer_irq_works()) {
2315 apic_printk(APIC_QUIET
, KERN_INFO
"..... works.\n");
2318 local_irq_disable();
2319 legacy_pic
->mask(0);
2320 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_FIXED
| cfg
->vector
);
2321 apic_printk(APIC_QUIET
, KERN_INFO
"..... failed.\n");
2323 apic_printk(APIC_QUIET
, KERN_INFO
2324 "...trying to set up timer as ExtINT IRQ...\n");
2326 legacy_pic
->init(0);
2327 legacy_pic
->make_irq(0);
2328 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
2330 unlock_ExtINT_logic();
2332 if (timer_irq_works()) {
2333 apic_printk(APIC_QUIET
, KERN_INFO
"..... works.\n");
2336 local_irq_disable();
2337 apic_printk(APIC_QUIET
, KERN_INFO
"..... failed :(.\n");
2338 if (apic_is_x2apic_enabled())
2339 apic_printk(APIC_QUIET
, KERN_INFO
2340 "Perhaps problem with the pre-enabled x2apic mode\n"
2341 "Try booting with x2apic and interrupt-remapping disabled in the bios.\n");
2342 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2343 "report. Then try booting with the 'noapic' option.\n");
2345 local_irq_restore(flags
);
2349 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2350 * to devices. However there may be an I/O APIC pin available for
2351 * this interrupt regardless. The pin may be left unconnected, but
2352 * typically it will be reused as an ExtINT cascade interrupt for
2353 * the master 8259A. In the MPS case such a pin will normally be
2354 * reported as an ExtINT interrupt in the MP table. With ACPI
2355 * there is no provision for ExtINT interrupts, and in the absence
2356 * of an override it would be treated as an ordinary ISA I/O APIC
2357 * interrupt, that is edge-triggered and unmasked by default. We
2358 * used to do this, but it caused problems on some systems because
2359 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2360 * the same ExtINT cascade interrupt to drive the local APIC of the
2361 * bootstrap processor. Therefore we refrain from routing IRQ2 to
2362 * the I/O APIC in all cases now. No actual device should request
2363 * it anyway. --macro
2365 #define PIC_IRQS (1UL << PIC_CASCADE_IR)
2367 static int mp_irqdomain_create(int ioapic
)
2370 int hwirqs
= mp_ioapic_pin_count(ioapic
);
2371 struct ioapic
*ip
= &ioapics
[ioapic
];
2372 struct ioapic_domain_cfg
*cfg
= &ip
->irqdomain_cfg
;
2373 struct mp_ioapic_gsi
*gsi_cfg
= mp_ioapic_gsi_routing(ioapic
);
2375 size
= sizeof(struct mp_pin_info
) * mp_ioapic_pin_count(ioapic
);
2376 ip
->pin_info
= kzalloc(size
, GFP_KERNEL
);
2380 if (cfg
->type
== IOAPIC_DOMAIN_INVALID
)
2383 ip
->irqdomain
= irq_domain_add_linear(cfg
->dev
, hwirqs
, cfg
->ops
,
2384 (void *)(long)ioapic
);
2385 if(!ip
->irqdomain
) {
2386 kfree(ip
->pin_info
);
2387 ip
->pin_info
= NULL
;
2391 if (cfg
->type
== IOAPIC_DOMAIN_LEGACY
||
2392 cfg
->type
== IOAPIC_DOMAIN_STRICT
)
2393 ioapic_dynirq_base
= max(ioapic_dynirq_base
,
2394 gsi_cfg
->gsi_end
+ 1);
2399 static void ioapic_destroy_irqdomain(int idx
)
2401 if (ioapics
[idx
].irqdomain
) {
2402 irq_domain_remove(ioapics
[idx
].irqdomain
);
2403 ioapics
[idx
].irqdomain
= NULL
;
2405 kfree(ioapics
[idx
].pin_info
);
2406 ioapics
[idx
].pin_info
= NULL
;
2409 void __init
setup_IO_APIC(void)
2413 if (skip_ioapic_setup
|| !nr_ioapics
)
2416 io_apic_irqs
= nr_legacy_irqs() ? ~PIC_IRQS
: ~0UL;
2418 apic_printk(APIC_VERBOSE
, "ENABLING IO-APIC IRQs\n");
2419 for_each_ioapic(ioapic
)
2420 BUG_ON(mp_irqdomain_create(ioapic
));
2423 * Set up IO-APIC IRQ routing.
2425 x86_init
.mpparse
.setup_ioapic_ids();
2428 setup_IO_APIC_irqs();
2429 init_IO_APIC_traps();
2430 if (nr_legacy_irqs())
2433 ioapic_initialized
= 1;
2437 * Called after all the initialization is done. If we didn't find any
2438 * APIC bugs then we can allow the modify fast path
2441 static int __init
io_apic_bug_finalize(void)
2443 if (sis_apic_bug
== -1)
2448 late_initcall(io_apic_bug_finalize
);
2450 static void resume_ioapic_id(int ioapic_idx
)
2452 unsigned long flags
;
2453 union IO_APIC_reg_00 reg_00
;
2455 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
2456 reg_00
.raw
= io_apic_read(ioapic_idx
, 0);
2457 if (reg_00
.bits
.ID
!= mpc_ioapic_id(ioapic_idx
)) {
2458 reg_00
.bits
.ID
= mpc_ioapic_id(ioapic_idx
);
2459 io_apic_write(ioapic_idx
, 0, reg_00
.raw
);
2461 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
2464 static void ioapic_resume(void)
2468 for_each_ioapic_reverse(ioapic_idx
)
2469 resume_ioapic_id(ioapic_idx
);
2471 restore_ioapic_entries();
2474 static struct syscore_ops ioapic_syscore_ops
= {
2475 .suspend
= save_ioapic_entries
,
2476 .resume
= ioapic_resume
,
2479 static int __init
ioapic_init_ops(void)
2481 register_syscore_ops(&ioapic_syscore_ops
);
2486 device_initcall(ioapic_init_ops
);
2489 io_apic_setup_irq_pin(unsigned int irq
, int node
, struct io_apic_irq_attr
*attr
)
2491 struct irq_cfg
*cfg
= alloc_irq_and_cfg_at(irq
, node
);
2496 ret
= __add_pin_to_irq_node(cfg
, node
, attr
->ioapic
, attr
->ioapic_pin
);
2498 setup_ioapic_irq(irq
, cfg
, attr
);
2502 static int io_apic_get_redir_entries(int ioapic
)
2504 union IO_APIC_reg_01 reg_01
;
2505 unsigned long flags
;
2507 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
2508 reg_01
.raw
= io_apic_read(ioapic
, 1);
2509 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
2511 /* The register returns the maximum index redir index
2512 * supported, which is one less than the total number of redir
2515 return reg_01
.bits
.entries
+ 1;
2518 unsigned int arch_dynirq_lower_bound(unsigned int from
)
2521 * dmar_alloc_hwirq() may be called before setup_IO_APIC(), so use
2522 * gsi_top if ioapic_dynirq_base hasn't been initialized yet.
2524 return ioapic_initialized
? ioapic_dynirq_base
: gsi_top
;
2527 #ifdef CONFIG_X86_32
2528 static int io_apic_get_unique_id(int ioapic
, int apic_id
)
2530 union IO_APIC_reg_00 reg_00
;
2531 static physid_mask_t apic_id_map
= PHYSID_MASK_NONE
;
2533 unsigned long flags
;
2537 * The P4 platform supports up to 256 APIC IDs on two separate APIC
2538 * buses (one for LAPICs, one for IOAPICs), where predecessors only
2539 * supports up to 16 on one shared APIC bus.
2541 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2542 * advantage of new APIC bus architecture.
2545 if (physids_empty(apic_id_map
))
2546 apic
->ioapic_phys_id_map(&phys_cpu_present_map
, &apic_id_map
);
2548 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
2549 reg_00
.raw
= io_apic_read(ioapic
, 0);
2550 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
2552 if (apic_id
>= get_physical_broadcast()) {
2553 printk(KERN_WARNING
"IOAPIC[%d]: Invalid apic_id %d, trying "
2554 "%d\n", ioapic
, apic_id
, reg_00
.bits
.ID
);
2555 apic_id
= reg_00
.bits
.ID
;
2559 * Every APIC in a system must have a unique ID or we get lots of nice
2560 * 'stuck on smp_invalidate_needed IPI wait' messages.
2562 if (apic
->check_apicid_used(&apic_id_map
, apic_id
)) {
2564 for (i
= 0; i
< get_physical_broadcast(); i
++) {
2565 if (!apic
->check_apicid_used(&apic_id_map
, i
))
2569 if (i
== get_physical_broadcast())
2570 panic("Max apic_id exceeded!\n");
2572 printk(KERN_WARNING
"IOAPIC[%d]: apic_id %d already used, "
2573 "trying %d\n", ioapic
, apic_id
, i
);
2578 apic
->apicid_to_cpu_present(apic_id
, &tmp
);
2579 physids_or(apic_id_map
, apic_id_map
, tmp
);
2581 if (reg_00
.bits
.ID
!= apic_id
) {
2582 reg_00
.bits
.ID
= apic_id
;
2584 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
2585 io_apic_write(ioapic
, 0, reg_00
.raw
);
2586 reg_00
.raw
= io_apic_read(ioapic
, 0);
2587 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
2590 if (reg_00
.bits
.ID
!= apic_id
) {
2591 pr_err("IOAPIC[%d]: Unable to change apic_id!\n",
2597 apic_printk(APIC_VERBOSE
, KERN_INFO
2598 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic
, apic_id
);
2603 static u8
io_apic_unique_id(int idx
, u8 id
)
2605 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
) &&
2606 !APIC_XAPIC(apic_version
[boot_cpu_physical_apicid
]))
2607 return io_apic_get_unique_id(idx
, id
);
2612 static u8
io_apic_unique_id(int idx
, u8 id
)
2614 union IO_APIC_reg_00 reg_00
;
2615 DECLARE_BITMAP(used
, 256);
2616 unsigned long flags
;
2620 bitmap_zero(used
, 256);
2622 __set_bit(mpc_ioapic_id(i
), used
);
2624 /* Hand out the requested id if available */
2625 if (!test_bit(id
, used
))
2629 * Read the current id from the ioapic and keep it if
2632 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
2633 reg_00
.raw
= io_apic_read(idx
, 0);
2634 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
2635 new_id
= reg_00
.bits
.ID
;
2636 if (!test_bit(new_id
, used
)) {
2637 apic_printk(APIC_VERBOSE
, KERN_INFO
2638 "IOAPIC[%d]: Using reg apic_id %d instead of %d\n",
2644 * Get the next free id and write it to the ioapic.
2646 new_id
= find_first_zero_bit(used
, 256);
2647 reg_00
.bits
.ID
= new_id
;
2648 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
2649 io_apic_write(idx
, 0, reg_00
.raw
);
2650 reg_00
.raw
= io_apic_read(idx
, 0);
2651 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
2653 BUG_ON(reg_00
.bits
.ID
!= new_id
);
2659 static int io_apic_get_version(int ioapic
)
2661 union IO_APIC_reg_01 reg_01
;
2662 unsigned long flags
;
2664 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
2665 reg_01
.raw
= io_apic_read(ioapic
, 1);
2666 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
2668 return reg_01
.bits
.version
;
2671 int acpi_get_override_irq(u32 gsi
, int *trigger
, int *polarity
)
2673 int ioapic
, pin
, idx
;
2675 if (skip_ioapic_setup
)
2678 ioapic
= mp_find_ioapic(gsi
);
2682 pin
= mp_find_ioapic_pin(ioapic
, gsi
);
2686 idx
= find_irq_entry(ioapic
, pin
, mp_INT
);
2690 *trigger
= irq_trigger(idx
);
2691 *polarity
= irq_polarity(idx
);
2696 * This function currently is only a helper for the i386 smp boot process where
2697 * we need to reprogram the ioredtbls to cater for the cpus which have come online
2698 * so mask in all cases should simply be apic->target_cpus()
2701 void __init
setup_ioapic_dest(void)
2703 int pin
, ioapic
, irq
, irq_entry
;
2704 const struct cpumask
*mask
;
2705 struct irq_data
*idata
;
2707 if (skip_ioapic_setup
== 1)
2710 for_each_ioapic_pin(ioapic
, pin
) {
2711 irq_entry
= find_irq_entry(ioapic
, pin
, mp_INT
);
2712 if (irq_entry
== -1)
2715 irq
= pin_2_irq(irq_entry
, ioapic
, pin
, 0);
2716 if (irq
< 0 || !mp_init_irq_at_boot(ioapic
, irq
))
2719 idata
= irq_get_irq_data(irq
);
2722 * Honour affinities which have been set in early boot
2724 if (!irqd_can_balance(idata
) || irqd_affinity_was_set(idata
))
2725 mask
= idata
->affinity
;
2727 mask
= apic
->target_cpus();
2729 x86_io_apic_ops
.set_affinity(idata
, mask
, false);
2735 #define IOAPIC_RESOURCE_NAME_SIZE 11
2737 static struct resource
*ioapic_resources
;
2739 static struct resource
* __init
ioapic_setup_resources(void)
2742 struct resource
*res
;
2751 n
= IOAPIC_RESOURCE_NAME_SIZE
+ sizeof(struct resource
);
2754 mem
= alloc_bootmem(n
);
2757 mem
+= sizeof(struct resource
) * num
;
2760 for_each_ioapic(i
) {
2761 res
[num
].name
= mem
;
2762 res
[num
].flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
;
2763 snprintf(mem
, IOAPIC_RESOURCE_NAME_SIZE
, "IOAPIC %u", i
);
2764 mem
+= IOAPIC_RESOURCE_NAME_SIZE
;
2766 ioapics
[i
].iomem_res
= res
;
2769 ioapic_resources
= res
;
2774 void __init
native_io_apic_init_mappings(void)
2776 unsigned long ioapic_phys
, idx
= FIX_IO_APIC_BASE_0
;
2777 struct resource
*ioapic_res
;
2780 ioapic_res
= ioapic_setup_resources();
2781 for_each_ioapic(i
) {
2782 if (smp_found_config
) {
2783 ioapic_phys
= mpc_ioapic_addr(i
);
2784 #ifdef CONFIG_X86_32
2787 "WARNING: bogus zero IO-APIC "
2788 "address found in MPTABLE, "
2789 "disabling IO/APIC support!\n");
2790 smp_found_config
= 0;
2791 skip_ioapic_setup
= 1;
2792 goto fake_ioapic_page
;
2796 #ifdef CONFIG_X86_32
2799 ioapic_phys
= (unsigned long)alloc_bootmem_pages(PAGE_SIZE
);
2800 ioapic_phys
= __pa(ioapic_phys
);
2802 set_fixmap_nocache(idx
, ioapic_phys
);
2803 apic_printk(APIC_VERBOSE
, "mapped IOAPIC to %08lx (%08lx)\n",
2804 __fix_to_virt(idx
) + (ioapic_phys
& ~PAGE_MASK
),
2808 ioapic_res
->start
= ioapic_phys
;
2809 ioapic_res
->end
= ioapic_phys
+ IO_APIC_SLOT_SIZE
- 1;
2814 void __init
ioapic_insert_resources(void)
2817 struct resource
*r
= ioapic_resources
;
2822 "IO APIC resources couldn't be allocated.\n");
2826 for_each_ioapic(i
) {
2827 insert_resource(&iomem_resource
, r
);
2832 int mp_find_ioapic(u32 gsi
)
2836 if (nr_ioapics
== 0)
2839 /* Find the IOAPIC that manages this GSI. */
2840 for_each_ioapic(i
) {
2841 struct mp_ioapic_gsi
*gsi_cfg
= mp_ioapic_gsi_routing(i
);
2842 if (gsi
>= gsi_cfg
->gsi_base
&& gsi
<= gsi_cfg
->gsi_end
)
2846 printk(KERN_ERR
"ERROR: Unable to locate IOAPIC for GSI %d\n", gsi
);
2850 int mp_find_ioapic_pin(int ioapic
, u32 gsi
)
2852 struct mp_ioapic_gsi
*gsi_cfg
;
2854 if (WARN_ON(ioapic
< 0))
2857 gsi_cfg
= mp_ioapic_gsi_routing(ioapic
);
2858 if (WARN_ON(gsi
> gsi_cfg
->gsi_end
))
2861 return gsi
- gsi_cfg
->gsi_base
;
2864 static int bad_ioapic_register(int idx
)
2866 union IO_APIC_reg_00 reg_00
;
2867 union IO_APIC_reg_01 reg_01
;
2868 union IO_APIC_reg_02 reg_02
;
2870 reg_00
.raw
= io_apic_read(idx
, 0);
2871 reg_01
.raw
= io_apic_read(idx
, 1);
2872 reg_02
.raw
= io_apic_read(idx
, 2);
2874 if (reg_00
.raw
== -1 && reg_01
.raw
== -1 && reg_02
.raw
== -1) {
2875 pr_warn("I/O APIC 0x%x registers return all ones, skipping!\n",
2876 mpc_ioapic_addr(idx
));
2883 static int find_free_ioapic_entry(void)
2887 for (idx
= 0; idx
< MAX_IO_APICS
; idx
++)
2888 if (ioapics
[idx
].nr_registers
== 0)
2891 return MAX_IO_APICS
;
2895 * mp_register_ioapic - Register an IOAPIC device
2896 * @id: hardware IOAPIC ID
2897 * @address: physical address of IOAPIC register area
2898 * @gsi_base: base of GSI associated with the IOAPIC
2899 * @cfg: configuration information for the IOAPIC
2901 int mp_register_ioapic(int id
, u32 address
, u32 gsi_base
,
2902 struct ioapic_domain_cfg
*cfg
)
2904 bool hotplug
= !!ioapic_initialized
;
2905 struct mp_ioapic_gsi
*gsi_cfg
;
2906 int idx
, ioapic
, entries
;
2910 pr_warn("Bogus (zero) I/O APIC address found, skipping!\n");
2913 for_each_ioapic(ioapic
)
2914 if (ioapics
[ioapic
].mp_config
.apicaddr
== address
) {
2915 pr_warn("address 0x%x conflicts with IOAPIC%d\n",
2920 idx
= find_free_ioapic_entry();
2921 if (idx
>= MAX_IO_APICS
) {
2922 pr_warn("Max # of I/O APICs (%d) exceeded (found %d), skipping\n",
2927 ioapics
[idx
].mp_config
.type
= MP_IOAPIC
;
2928 ioapics
[idx
].mp_config
.flags
= MPC_APIC_USABLE
;
2929 ioapics
[idx
].mp_config
.apicaddr
= address
;
2931 set_fixmap_nocache(FIX_IO_APIC_BASE_0
+ idx
, address
);
2932 if (bad_ioapic_register(idx
)) {
2933 clear_fixmap(FIX_IO_APIC_BASE_0
+ idx
);
2937 ioapics
[idx
].mp_config
.apicid
= io_apic_unique_id(idx
, id
);
2938 ioapics
[idx
].mp_config
.apicver
= io_apic_get_version(idx
);
2941 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
2942 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
2944 entries
= io_apic_get_redir_entries(idx
);
2945 gsi_end
= gsi_base
+ entries
- 1;
2946 for_each_ioapic(ioapic
) {
2947 gsi_cfg
= mp_ioapic_gsi_routing(ioapic
);
2948 if ((gsi_base
>= gsi_cfg
->gsi_base
&&
2949 gsi_base
<= gsi_cfg
->gsi_end
) ||
2950 (gsi_end
>= gsi_cfg
->gsi_base
&&
2951 gsi_end
<= gsi_cfg
->gsi_end
)) {
2952 pr_warn("GSI range [%u-%u] for new IOAPIC conflicts with GSI[%u-%u]\n",
2954 gsi_cfg
->gsi_base
, gsi_cfg
->gsi_end
);
2955 clear_fixmap(FIX_IO_APIC_BASE_0
+ idx
);
2959 gsi_cfg
= mp_ioapic_gsi_routing(idx
);
2960 gsi_cfg
->gsi_base
= gsi_base
;
2961 gsi_cfg
->gsi_end
= gsi_end
;
2963 ioapics
[idx
].irqdomain
= NULL
;
2964 ioapics
[idx
].irqdomain_cfg
= *cfg
;
2967 * If mp_register_ioapic() is called during early boot stage when
2968 * walking ACPI/SFI/DT tables, it's too early to create irqdomain,
2969 * we are still using bootmem allocator. So delay it to setup_IO_APIC().
2972 if (mp_irqdomain_create(idx
)) {
2973 clear_fixmap(FIX_IO_APIC_BASE_0
+ idx
);
2976 alloc_ioapic_saved_registers(idx
);
2979 if (gsi_cfg
->gsi_end
>= gsi_top
)
2980 gsi_top
= gsi_cfg
->gsi_end
+ 1;
2981 if (nr_ioapics
<= idx
)
2982 nr_ioapics
= idx
+ 1;
2984 /* Set nr_registers to mark entry present */
2985 ioapics
[idx
].nr_registers
= entries
;
2987 pr_info("IOAPIC[%d]: apic_id %d, version %d, address 0x%x, GSI %d-%d\n",
2988 idx
, mpc_ioapic_id(idx
),
2989 mpc_ioapic_ver(idx
), mpc_ioapic_addr(idx
),
2990 gsi_cfg
->gsi_base
, gsi_cfg
->gsi_end
);
2995 int mp_unregister_ioapic(u32 gsi_base
)
2999 struct mp_pin_info
*pin_info
;
3001 for_each_ioapic(ioapic
)
3002 if (ioapics
[ioapic
].gsi_config
.gsi_base
== gsi_base
) {
3007 pr_warn("can't find IOAPIC for GSI %d\n", gsi_base
);
3011 for_each_pin(ioapic
, pin
) {
3012 pin_info
= mp_pin_info(ioapic
, pin
);
3013 if (pin_info
->count
) {
3014 pr_warn("pin%d on IOAPIC%d is still in use.\n",
3020 /* Mark entry not present */
3021 ioapics
[ioapic
].nr_registers
= 0;
3022 ioapic_destroy_irqdomain(ioapic
);
3023 free_ioapic_saved_registers(ioapic
);
3024 if (ioapics
[ioapic
].iomem_res
)
3025 release_resource(ioapics
[ioapic
].iomem_res
);
3026 clear_fixmap(FIX_IO_APIC_BASE_0
+ ioapic
);
3027 memset(&ioapics
[ioapic
], 0, sizeof(ioapics
[ioapic
]));
3032 int mp_ioapic_registered(u32 gsi_base
)
3036 for_each_ioapic(ioapic
)
3037 if (ioapics
[ioapic
].gsi_config
.gsi_base
== gsi_base
)
3043 static inline void set_io_apic_irq_attr(struct io_apic_irq_attr
*irq_attr
,
3044 int ioapic
, int ioapic_pin
,
3045 int trigger
, int polarity
)
3047 irq_attr
->ioapic
= ioapic
;
3048 irq_attr
->ioapic_pin
= ioapic_pin
;
3049 irq_attr
->trigger
= trigger
;
3050 irq_attr
->polarity
= polarity
;
3053 int mp_irqdomain_map(struct irq_domain
*domain
, unsigned int virq
,
3054 irq_hw_number_t hwirq
)
3056 int ioapic
= mp_irqdomain_ioapic_idx(domain
);
3057 struct mp_pin_info
*info
= mp_pin_info(ioapic
, hwirq
);
3058 struct io_apic_irq_attr attr
;
3060 /* Get default attribute if not set by caller yet */
3062 u32 gsi
= mp_pin_to_gsi(ioapic
, hwirq
);
3064 if (acpi_get_override_irq(gsi
, &info
->trigger
,
3065 &info
->polarity
) < 0) {
3067 * PCI interrupts are always polarity one level
3073 info
->node
= NUMA_NO_NODE
;
3076 * setup_IO_APIC_irqs() programs all legacy IRQs with default
3077 * trigger and polarity attributes. Don't set the flag for that
3078 * case so the first legacy IRQ user could reprogram the pin
3079 * with real trigger and polarity attributes.
3081 if (virq
>= nr_legacy_irqs() || info
->count
)
3084 set_io_apic_irq_attr(&attr
, ioapic
, hwirq
, info
->trigger
,
3087 return io_apic_setup_irq_pin(virq
, info
->node
, &attr
);
3090 void mp_irqdomain_unmap(struct irq_domain
*domain
, unsigned int virq
)
3092 struct irq_data
*data
= irq_get_irq_data(virq
);
3093 struct irq_cfg
*cfg
= irq_cfg(virq
);
3094 int ioapic
= mp_irqdomain_ioapic_idx(domain
);
3095 int pin
= (int)data
->hwirq
;
3097 ioapic_mask_entry(ioapic
, pin
);
3098 __remove_pin_from_irq(cfg
, ioapic
, pin
);
3099 WARN_ON(!list_empty(&cfg
->irq_2_pin
));
3100 arch_teardown_hwirq(virq
);
3103 static void mp_irqdomain_get_attr(u32 gsi
, struct mp_chip_data
*data
,
3104 struct irq_alloc_info
*info
)
3106 if (info
&& info
->ioapic_valid
) {
3107 data
->trigger
= info
->ioapic_trigger
;
3108 data
->polarity
= info
->ioapic_polarity
;
3109 } else if (acpi_get_override_irq(gsi
, &data
->trigger
,
3110 &data
->polarity
) < 0) {
3111 /* PCI interrupts are always polarity one level triggered. */
3117 static void mp_setup_entry(struct irq_cfg
*cfg
, struct mp_chip_data
*data
,
3118 struct IO_APIC_route_entry
*entry
)
3120 memset(entry
, 0, sizeof(*entry
));
3121 entry
->delivery_mode
= apic
->irq_delivery_mode
;
3122 entry
->dest_mode
= apic
->irq_dest_mode
;
3123 entry
->dest
= cfg
->dest_apicid
;
3124 entry
->vector
= cfg
->vector
;
3125 entry
->mask
= 0; /* enable IRQ */
3126 entry
->trigger
= data
->trigger
;
3127 entry
->polarity
= data
->polarity
;
3129 * Mask level triggered irqs.
3130 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
3136 int mp_irqdomain_alloc(struct irq_domain
*domain
, unsigned int virq
,
3137 unsigned int nr_irqs
, void *arg
)
3139 int ret
, ioapic
, pin
;
3140 struct irq_cfg
*cfg
;
3141 struct irq_data
*irq_data
;
3142 struct mp_chip_data
*data
;
3143 struct irq_alloc_info
*info
= arg
;
3145 if (!info
|| nr_irqs
> 1)
3147 irq_data
= irq_domain_get_irq_data(domain
, virq
);
3151 ioapic
= mp_irqdomain_ioapic_idx(domain
);
3152 pin
= info
->ioapic_pin
;
3153 if (irq_find_mapping(domain
, (irq_hw_number_t
)pin
) > 0)
3156 data
= kzalloc(sizeof(*data
), GFP_KERNEL
);
3160 info
->ioapic_entry
= &data
->entry
;
3161 ret
= irq_domain_alloc_irqs_parent(domain
, virq
, nr_irqs
, info
);
3167 irq_data
->hwirq
= info
->ioapic_pin
;
3168 irq_data
->chip
= &ioapic_chip
;
3169 irq_data
->chip_data
= data
;
3170 mp_irqdomain_get_attr(mp_pin_to_gsi(ioapic
, pin
), data
, info
);
3172 cfg
= irqd_cfg(irq_data
);
3173 add_pin_to_irq_node(cfg
, info
->ioapic_node
, ioapic
, pin
);
3174 if (info
->ioapic_entry
)
3175 mp_setup_entry(cfg
, data
, info
->ioapic_entry
);
3176 mp_register_handler(virq
, data
->trigger
);
3177 if (virq
< nr_legacy_irqs())
3178 legacy_pic
->mask(virq
);
3180 apic_printk(APIC_VERBOSE
, KERN_DEBUG
3181 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i Dest:%d)\n",
3182 ioapic
, mpc_ioapic_id(ioapic
), pin
, cfg
->vector
,
3183 virq
, data
->trigger
, data
->polarity
, cfg
->dest_apicid
);
3188 void mp_irqdomain_free(struct irq_domain
*domain
, unsigned int virq
,
3189 unsigned int nr_irqs
)
3191 struct irq_cfg
*cfg
= irq_cfg(virq
);
3192 struct irq_data
*irq_data
;
3194 BUG_ON(nr_irqs
!= 1);
3195 irq_data
= irq_domain_get_irq_data(domain
, virq
);
3196 if (irq_data
&& irq_data
->chip_data
) {
3197 __remove_pin_from_irq(cfg
, mp_irqdomain_ioapic_idx(domain
),
3198 (int)irq_data
->hwirq
);
3199 WARN_ON(!list_empty(&cfg
->irq_2_pin
));
3200 kfree(irq_data
->chip_data
);
3202 irq_domain_free_irqs_top(domain
, virq
, nr_irqs
);
3205 void mp_irqdomain_activate(struct irq_domain
*domain
,
3206 struct irq_data
*irq_data
)
3208 unsigned long flags
;
3209 struct irq_pin_list
*entry
;
3210 struct mp_chip_data
*data
= irq_data
->chip_data
;
3211 struct irq_cfg
*cfg
= irqd_cfg(irq_data
);
3213 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
3214 for_each_irq_pin(entry
, cfg
->irq_2_pin
)
3215 __ioapic_write_entry(entry
->apic
, entry
->pin
, data
->entry
);
3216 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
3219 void mp_irqdomain_deactivate(struct irq_domain
*domain
,
3220 struct irq_data
*irq_data
)
3222 /* It won't be called for IRQ with multiple IOAPIC pins associated */
3223 ioapic_mask_entry(mp_irqdomain_ioapic_idx(domain
),
3224 (int)irq_data
->hwirq
);
3227 int mp_set_gsi_attr(u32 gsi
, int trigger
, int polarity
, int node
)
3231 struct mp_pin_info
*info
;
3233 ioapic
= mp_find_ioapic(gsi
);
3237 pin
= mp_find_ioapic_pin(ioapic
, gsi
);
3238 info
= mp_pin_info(ioapic
, pin
);
3239 trigger
= trigger
? 1 : 0;
3240 polarity
= polarity
? 1 : 0;
3242 mutex_lock(&ioapic_mutex
);
3244 info
->trigger
= trigger
;
3245 info
->polarity
= polarity
;
3248 } else if (info
->trigger
!= trigger
|| info
->polarity
!= polarity
) {
3251 mutex_unlock(&ioapic_mutex
);
3256 int mp_irqdomain_ioapic_idx(struct irq_domain
*domain
)
3258 return (int)(long)domain
->host_data
;