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x86/irq: Do not use apic_chip_data.old_domain as temporary buffer
[deliverable/linux.git] / arch / x86 / kernel / apic / vector.c
1 /*
2 * Local APIC related interfaces to support IOAPIC, MSI, HT_IRQ etc.
3 *
4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
5 * Moved from arch/x86/kernel/apic/io_apic.c.
6 * Jiang Liu <jiang.liu@linux.intel.com>
7 * Enable support of hierarchical irqdomains
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13 #include <linux/interrupt.h>
14 #include <linux/init.h>
15 #include <linux/compiler.h>
16 #include <linux/slab.h>
17 #include <asm/irqdomain.h>
18 #include <asm/hw_irq.h>
19 #include <asm/apic.h>
20 #include <asm/i8259.h>
21 #include <asm/desc.h>
22 #include <asm/irq_remapping.h>
23
24 struct apic_chip_data {
25 struct irq_cfg cfg;
26 cpumask_var_t domain;
27 cpumask_var_t old_domain;
28 u8 move_in_progress : 1;
29 };
30
31 struct irq_domain *x86_vector_domain;
32 EXPORT_SYMBOL_GPL(x86_vector_domain);
33 static DEFINE_RAW_SPINLOCK(vector_lock);
34 static cpumask_var_t vector_cpumask, searched_cpumask;
35 static struct irq_chip lapic_controller;
36 #ifdef CONFIG_X86_IO_APIC
37 static struct apic_chip_data *legacy_irq_data[NR_IRQS_LEGACY];
38 #endif
39
40 void lock_vector_lock(void)
41 {
42 /* Used to the online set of cpus does not change
43 * during assign_irq_vector.
44 */
45 raw_spin_lock(&vector_lock);
46 }
47
48 void unlock_vector_lock(void)
49 {
50 raw_spin_unlock(&vector_lock);
51 }
52
53 static struct apic_chip_data *apic_chip_data(struct irq_data *irq_data)
54 {
55 if (!irq_data)
56 return NULL;
57
58 while (irq_data->parent_data)
59 irq_data = irq_data->parent_data;
60
61 return irq_data->chip_data;
62 }
63
64 struct irq_cfg *irqd_cfg(struct irq_data *irq_data)
65 {
66 struct apic_chip_data *data = apic_chip_data(irq_data);
67
68 return data ? &data->cfg : NULL;
69 }
70 EXPORT_SYMBOL_GPL(irqd_cfg);
71
72 struct irq_cfg *irq_cfg(unsigned int irq)
73 {
74 return irqd_cfg(irq_get_irq_data(irq));
75 }
76
77 static struct apic_chip_data *alloc_apic_chip_data(int node)
78 {
79 struct apic_chip_data *data;
80
81 data = kzalloc_node(sizeof(*data), GFP_KERNEL, node);
82 if (!data)
83 return NULL;
84 if (!zalloc_cpumask_var_node(&data->domain, GFP_KERNEL, node))
85 goto out_data;
86 if (!zalloc_cpumask_var_node(&data->old_domain, GFP_KERNEL, node))
87 goto out_domain;
88 return data;
89 out_domain:
90 free_cpumask_var(data->domain);
91 out_data:
92 kfree(data);
93 return NULL;
94 }
95
96 static void free_apic_chip_data(struct apic_chip_data *data)
97 {
98 if (data) {
99 free_cpumask_var(data->domain);
100 free_cpumask_var(data->old_domain);
101 kfree(data);
102 }
103 }
104
105 static int __assign_irq_vector(int irq, struct apic_chip_data *d,
106 const struct cpumask *mask)
107 {
108 /*
109 * NOTE! The local APIC isn't very good at handling
110 * multiple interrupts at the same interrupt level.
111 * As the interrupt level is determined by taking the
112 * vector number and shifting that right by 4, we
113 * want to spread these out a bit so that they don't
114 * all fall in the same interrupt level.
115 *
116 * Also, we've got to be careful not to trash gate
117 * 0x80, because int 0x80 is hm, kind of importantish. ;)
118 */
119 static int current_vector = FIRST_EXTERNAL_VECTOR + VECTOR_OFFSET_START;
120 static int current_offset = VECTOR_OFFSET_START % 16;
121 int cpu, err;
122
123 if (d->move_in_progress)
124 return -EBUSY;
125
126 /* Only try and allocate irqs on cpus that are present */
127 err = -ENOSPC;
128 cpumask_clear(d->old_domain);
129 cpumask_clear(searched_cpumask);
130 cpu = cpumask_first_and(mask, cpu_online_mask);
131 while (cpu < nr_cpu_ids) {
132 int new_cpu, vector, offset;
133
134 apic->vector_allocation_domain(cpu, vector_cpumask, mask);
135
136 if (cpumask_subset(vector_cpumask, d->domain)) {
137 err = 0;
138 if (cpumask_equal(vector_cpumask, d->domain))
139 break;
140 /*
141 * New cpumask using the vector is a proper subset of
142 * the current in use mask. So cleanup the vector
143 * allocation for the members that are not used anymore.
144 */
145 cpumask_andnot(d->old_domain, d->domain,
146 vector_cpumask);
147 d->move_in_progress =
148 cpumask_intersects(d->old_domain, cpu_online_mask);
149 cpumask_and(d->domain, d->domain, vector_cpumask);
150 break;
151 }
152
153 vector = current_vector;
154 offset = current_offset;
155 next:
156 vector += 16;
157 if (vector >= first_system_vector) {
158 offset = (offset + 1) % 16;
159 vector = FIRST_EXTERNAL_VECTOR + offset;
160 }
161
162 if (unlikely(current_vector == vector)) {
163 cpumask_or(searched_cpumask, searched_cpumask,
164 vector_cpumask);
165 cpumask_andnot(vector_cpumask, mask, searched_cpumask);
166 cpu = cpumask_first_and(vector_cpumask,
167 cpu_online_mask);
168 continue;
169 }
170
171 if (test_bit(vector, used_vectors))
172 goto next;
173
174 for_each_cpu_and(new_cpu, vector_cpumask, cpu_online_mask) {
175 if (!IS_ERR_OR_NULL(per_cpu(vector_irq, new_cpu)[vector]))
176 goto next;
177 }
178 /* Found one! */
179 current_vector = vector;
180 current_offset = offset;
181 if (d->cfg.vector) {
182 cpumask_copy(d->old_domain, d->domain);
183 d->move_in_progress =
184 cpumask_intersects(d->old_domain, cpu_online_mask);
185 }
186 for_each_cpu_and(new_cpu, vector_cpumask, cpu_online_mask)
187 per_cpu(vector_irq, new_cpu)[vector] = irq_to_desc(irq);
188 d->cfg.vector = vector;
189 cpumask_copy(d->domain, vector_cpumask);
190 err = 0;
191 break;
192 }
193
194 if (!err) {
195 /* cache destination APIC IDs into cfg->dest_apicid */
196 err = apic->cpu_mask_to_apicid_and(mask, d->domain,
197 &d->cfg.dest_apicid);
198 }
199
200 return err;
201 }
202
203 static int assign_irq_vector(int irq, struct apic_chip_data *data,
204 const struct cpumask *mask)
205 {
206 int err;
207 unsigned long flags;
208
209 raw_spin_lock_irqsave(&vector_lock, flags);
210 err = __assign_irq_vector(irq, data, mask);
211 raw_spin_unlock_irqrestore(&vector_lock, flags);
212 return err;
213 }
214
215 static int assign_irq_vector_policy(int irq, int node,
216 struct apic_chip_data *data,
217 struct irq_alloc_info *info)
218 {
219 if (info && info->mask)
220 return assign_irq_vector(irq, data, info->mask);
221 if (node != NUMA_NO_NODE &&
222 assign_irq_vector(irq, data, cpumask_of_node(node)) == 0)
223 return 0;
224 return assign_irq_vector(irq, data, apic->target_cpus());
225 }
226
227 static void clear_irq_vector(int irq, struct apic_chip_data *data)
228 {
229 struct irq_desc *desc;
230 int cpu, vector;
231
232 BUG_ON(!data->cfg.vector);
233
234 vector = data->cfg.vector;
235 for_each_cpu_and(cpu, data->domain, cpu_online_mask)
236 per_cpu(vector_irq, cpu)[vector] = VECTOR_UNUSED;
237
238 data->cfg.vector = 0;
239 cpumask_clear(data->domain);
240
241 if (likely(!data->move_in_progress))
242 return;
243
244 desc = irq_to_desc(irq);
245 for_each_cpu_and(cpu, data->old_domain, cpu_online_mask) {
246 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS;
247 vector++) {
248 if (per_cpu(vector_irq, cpu)[vector] != desc)
249 continue;
250 per_cpu(vector_irq, cpu)[vector] = VECTOR_UNUSED;
251 break;
252 }
253 }
254 data->move_in_progress = 0;
255 }
256
257 void init_irq_alloc_info(struct irq_alloc_info *info,
258 const struct cpumask *mask)
259 {
260 memset(info, 0, sizeof(*info));
261 info->mask = mask;
262 }
263
264 void copy_irq_alloc_info(struct irq_alloc_info *dst, struct irq_alloc_info *src)
265 {
266 if (src)
267 *dst = *src;
268 else
269 memset(dst, 0, sizeof(*dst));
270 }
271
272 static void x86_vector_free_irqs(struct irq_domain *domain,
273 unsigned int virq, unsigned int nr_irqs)
274 {
275 struct apic_chip_data *apic_data;
276 struct irq_data *irq_data;
277 unsigned long flags;
278 int i;
279
280 for (i = 0; i < nr_irqs; i++) {
281 irq_data = irq_domain_get_irq_data(x86_vector_domain, virq + i);
282 if (irq_data && irq_data->chip_data) {
283 raw_spin_lock_irqsave(&vector_lock, flags);
284 clear_irq_vector(virq + i, irq_data->chip_data);
285 apic_data = irq_data->chip_data;
286 irq_domain_reset_irq_data(irq_data);
287 raw_spin_unlock_irqrestore(&vector_lock, flags);
288 free_apic_chip_data(apic_data);
289 #ifdef CONFIG_X86_IO_APIC
290 if (virq + i < nr_legacy_irqs())
291 legacy_irq_data[virq + i] = NULL;
292 #endif
293 }
294 }
295 }
296
297 static int x86_vector_alloc_irqs(struct irq_domain *domain, unsigned int virq,
298 unsigned int nr_irqs, void *arg)
299 {
300 struct irq_alloc_info *info = arg;
301 struct apic_chip_data *data;
302 struct irq_data *irq_data;
303 int i, err, node;
304
305 if (disable_apic)
306 return -ENXIO;
307
308 /* Currently vector allocator can't guarantee contiguous allocations */
309 if ((info->flags & X86_IRQ_ALLOC_CONTIGUOUS_VECTORS) && nr_irqs > 1)
310 return -ENOSYS;
311
312 for (i = 0; i < nr_irqs; i++) {
313 irq_data = irq_domain_get_irq_data(domain, virq + i);
314 BUG_ON(!irq_data);
315 node = irq_data_get_node(irq_data);
316 #ifdef CONFIG_X86_IO_APIC
317 if (virq + i < nr_legacy_irqs() && legacy_irq_data[virq + i])
318 data = legacy_irq_data[virq + i];
319 else
320 #endif
321 data = alloc_apic_chip_data(node);
322 if (!data) {
323 err = -ENOMEM;
324 goto error;
325 }
326
327 irq_data->chip = &lapic_controller;
328 irq_data->chip_data = data;
329 irq_data->hwirq = virq + i;
330 err = assign_irq_vector_policy(virq + i, node, data, info);
331 if (err)
332 goto error;
333 }
334
335 return 0;
336
337 error:
338 x86_vector_free_irqs(domain, virq, i + 1);
339 return err;
340 }
341
342 static const struct irq_domain_ops x86_vector_domain_ops = {
343 .alloc = x86_vector_alloc_irqs,
344 .free = x86_vector_free_irqs,
345 };
346
347 int __init arch_probe_nr_irqs(void)
348 {
349 int nr;
350
351 if (nr_irqs > (NR_VECTORS * nr_cpu_ids))
352 nr_irqs = NR_VECTORS * nr_cpu_ids;
353
354 nr = (gsi_top + nr_legacy_irqs()) + 8 * nr_cpu_ids;
355 #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ)
356 /*
357 * for MSI and HT dyn irq
358 */
359 if (gsi_top <= NR_IRQS_LEGACY)
360 nr += 8 * nr_cpu_ids;
361 else
362 nr += gsi_top * 16;
363 #endif
364 if (nr < nr_irqs)
365 nr_irqs = nr;
366
367 /*
368 * We don't know if PIC is present at this point so we need to do
369 * probe() to get the right number of legacy IRQs.
370 */
371 return legacy_pic->probe();
372 }
373
374 #ifdef CONFIG_X86_IO_APIC
375 static void init_legacy_irqs(void)
376 {
377 int i, node = cpu_to_node(0);
378 struct apic_chip_data *data;
379
380 /*
381 * For legacy IRQ's, start with assigning irq0 to irq15 to
382 * ISA_IRQ_VECTOR(i) for all cpu's.
383 */
384 for (i = 0; i < nr_legacy_irqs(); i++) {
385 data = legacy_irq_data[i] = alloc_apic_chip_data(node);
386 BUG_ON(!data);
387
388 data->cfg.vector = ISA_IRQ_VECTOR(i);
389 cpumask_setall(data->domain);
390 irq_set_chip_data(i, data);
391 }
392 }
393 #else
394 static void init_legacy_irqs(void) { }
395 #endif
396
397 int __init arch_early_irq_init(void)
398 {
399 init_legacy_irqs();
400
401 x86_vector_domain = irq_domain_add_tree(NULL, &x86_vector_domain_ops,
402 NULL);
403 BUG_ON(x86_vector_domain == NULL);
404 irq_set_default_host(x86_vector_domain);
405
406 arch_init_msi_domain(x86_vector_domain);
407 arch_init_htirq_domain(x86_vector_domain);
408
409 BUG_ON(!alloc_cpumask_var(&vector_cpumask, GFP_KERNEL));
410 BUG_ON(!alloc_cpumask_var(&searched_cpumask, GFP_KERNEL));
411
412 return arch_early_ioapic_init();
413 }
414
415 /* Initialize vector_irq on a new cpu */
416 static void __setup_vector_irq(int cpu)
417 {
418 struct apic_chip_data *data;
419 struct irq_desc *desc;
420 int irq, vector;
421
422 /* Mark the inuse vectors */
423 for_each_irq_desc(irq, desc) {
424 struct irq_data *idata = irq_desc_get_irq_data(desc);
425
426 data = apic_chip_data(idata);
427 if (!data || !cpumask_test_cpu(cpu, data->domain))
428 continue;
429 vector = data->cfg.vector;
430 per_cpu(vector_irq, cpu)[vector] = desc;
431 }
432 /* Mark the free vectors */
433 for (vector = 0; vector < NR_VECTORS; ++vector) {
434 desc = per_cpu(vector_irq, cpu)[vector];
435 if (IS_ERR_OR_NULL(desc))
436 continue;
437
438 data = apic_chip_data(irq_desc_get_irq_data(desc));
439 if (!cpumask_test_cpu(cpu, data->domain))
440 per_cpu(vector_irq, cpu)[vector] = VECTOR_UNUSED;
441 }
442 }
443
444 /*
445 * Setup the vector to irq mappings. Must be called with vector_lock held.
446 */
447 void setup_vector_irq(int cpu)
448 {
449 int irq;
450
451 lockdep_assert_held(&vector_lock);
452 /*
453 * On most of the platforms, legacy PIC delivers the interrupts on the
454 * boot cpu. But there are certain platforms where PIC interrupts are
455 * delivered to multiple cpu's. If the legacy IRQ is handled by the
456 * legacy PIC, for the new cpu that is coming online, setup the static
457 * legacy vector to irq mapping:
458 */
459 for (irq = 0; irq < nr_legacy_irqs(); irq++)
460 per_cpu(vector_irq, cpu)[ISA_IRQ_VECTOR(irq)] = irq_to_desc(irq);
461
462 __setup_vector_irq(cpu);
463 }
464
465 static int apic_retrigger_irq(struct irq_data *irq_data)
466 {
467 struct apic_chip_data *data = apic_chip_data(irq_data);
468 unsigned long flags;
469 int cpu;
470
471 raw_spin_lock_irqsave(&vector_lock, flags);
472 cpu = cpumask_first_and(data->domain, cpu_online_mask);
473 apic->send_IPI_mask(cpumask_of(cpu), data->cfg.vector);
474 raw_spin_unlock_irqrestore(&vector_lock, flags);
475
476 return 1;
477 }
478
479 void apic_ack_edge(struct irq_data *data)
480 {
481 irq_complete_move(irqd_cfg(data));
482 irq_move_irq(data);
483 ack_APIC_irq();
484 }
485
486 static int apic_set_affinity(struct irq_data *irq_data,
487 const struct cpumask *dest, bool force)
488 {
489 struct apic_chip_data *data = irq_data->chip_data;
490 int err, irq = irq_data->irq;
491
492 if (!config_enabled(CONFIG_SMP))
493 return -EPERM;
494
495 if (!cpumask_intersects(dest, cpu_online_mask))
496 return -EINVAL;
497
498 err = assign_irq_vector(irq, data, dest);
499 if (err) {
500 if (assign_irq_vector(irq, data,
501 irq_data_get_affinity_mask(irq_data)))
502 pr_err("Failed to recover vector for irq %d\n", irq);
503 return err;
504 }
505
506 return IRQ_SET_MASK_OK;
507 }
508
509 static struct irq_chip lapic_controller = {
510 .irq_ack = apic_ack_edge,
511 .irq_set_affinity = apic_set_affinity,
512 .irq_retrigger = apic_retrigger_irq,
513 };
514
515 #ifdef CONFIG_SMP
516 static void __send_cleanup_vector(struct apic_chip_data *data)
517 {
518 cpumask_var_t cleanup_mask;
519
520 if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) {
521 unsigned int i;
522
523 for_each_cpu_and(i, data->old_domain, cpu_online_mask)
524 apic->send_IPI_mask(cpumask_of(i),
525 IRQ_MOVE_CLEANUP_VECTOR);
526 } else {
527 cpumask_and(cleanup_mask, data->old_domain, cpu_online_mask);
528 apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
529 free_cpumask_var(cleanup_mask);
530 }
531 data->move_in_progress = 0;
532 }
533
534 void send_cleanup_vector(struct irq_cfg *cfg)
535 {
536 struct apic_chip_data *data;
537
538 data = container_of(cfg, struct apic_chip_data, cfg);
539 if (data->move_in_progress)
540 __send_cleanup_vector(data);
541 }
542
543 asmlinkage __visible void smp_irq_move_cleanup_interrupt(void)
544 {
545 unsigned vector, me;
546
547 entering_ack_irq();
548
549 /* Prevent vectors vanishing under us */
550 raw_spin_lock(&vector_lock);
551
552 me = smp_processor_id();
553 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
554 struct apic_chip_data *data;
555 struct irq_desc *desc;
556 unsigned int irr;
557
558 retry:
559 desc = __this_cpu_read(vector_irq[vector]);
560 if (IS_ERR_OR_NULL(desc))
561 continue;
562
563 if (!raw_spin_trylock(&desc->lock)) {
564 raw_spin_unlock(&vector_lock);
565 cpu_relax();
566 raw_spin_lock(&vector_lock);
567 goto retry;
568 }
569
570 data = apic_chip_data(irq_desc_get_irq_data(desc));
571 if (!data)
572 goto unlock;
573
574 /*
575 * Check if the irq migration is in progress. If so, we
576 * haven't received the cleanup request yet for this irq.
577 */
578 if (data->move_in_progress)
579 goto unlock;
580
581 if (vector == data->cfg.vector &&
582 cpumask_test_cpu(me, data->domain))
583 goto unlock;
584
585 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
586 /*
587 * Check if the vector that needs to be cleanedup is
588 * registered at the cpu's IRR. If so, then this is not
589 * the best time to clean it up. Lets clean it up in the
590 * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
591 * to myself.
592 */
593 if (irr & (1 << (vector % 32))) {
594 apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR);
595 goto unlock;
596 }
597 __this_cpu_write(vector_irq[vector], VECTOR_UNUSED);
598 unlock:
599 raw_spin_unlock(&desc->lock);
600 }
601
602 raw_spin_unlock(&vector_lock);
603
604 exiting_irq();
605 }
606
607 static void __irq_complete_move(struct irq_cfg *cfg, unsigned vector)
608 {
609 unsigned me;
610 struct apic_chip_data *data;
611
612 data = container_of(cfg, struct apic_chip_data, cfg);
613 if (likely(!data->move_in_progress))
614 return;
615
616 me = smp_processor_id();
617 if (vector == data->cfg.vector && cpumask_test_cpu(me, data->domain))
618 __send_cleanup_vector(data);
619 }
620
621 void irq_complete_move(struct irq_cfg *cfg)
622 {
623 __irq_complete_move(cfg, ~get_irq_regs()->orig_ax);
624 }
625
626 void irq_force_complete_move(int irq)
627 {
628 struct irq_cfg *cfg = irq_cfg(irq);
629
630 if (cfg)
631 __irq_complete_move(cfg, cfg->vector);
632 }
633 #endif
634
635 static void __init print_APIC_field(int base)
636 {
637 int i;
638
639 printk(KERN_DEBUG);
640
641 for (i = 0; i < 8; i++)
642 pr_cont("%08x", apic_read(base + i*0x10));
643
644 pr_cont("\n");
645 }
646
647 static void __init print_local_APIC(void *dummy)
648 {
649 unsigned int i, v, ver, maxlvt;
650 u64 icr;
651
652 pr_debug("printing local APIC contents on CPU#%d/%d:\n",
653 smp_processor_id(), hard_smp_processor_id());
654 v = apic_read(APIC_ID);
655 pr_info("... APIC ID: %08x (%01x)\n", v, read_apic_id());
656 v = apic_read(APIC_LVR);
657 pr_info("... APIC VERSION: %08x\n", v);
658 ver = GET_APIC_VERSION(v);
659 maxlvt = lapic_get_maxlvt();
660
661 v = apic_read(APIC_TASKPRI);
662 pr_debug("... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
663
664 /* !82489DX */
665 if (APIC_INTEGRATED(ver)) {
666 if (!APIC_XAPIC(ver)) {
667 v = apic_read(APIC_ARBPRI);
668 pr_debug("... APIC ARBPRI: %08x (%02x)\n",
669 v, v & APIC_ARBPRI_MASK);
670 }
671 v = apic_read(APIC_PROCPRI);
672 pr_debug("... APIC PROCPRI: %08x\n", v);
673 }
674
675 /*
676 * Remote read supported only in the 82489DX and local APIC for
677 * Pentium processors.
678 */
679 if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
680 v = apic_read(APIC_RRR);
681 pr_debug("... APIC RRR: %08x\n", v);
682 }
683
684 v = apic_read(APIC_LDR);
685 pr_debug("... APIC LDR: %08x\n", v);
686 if (!x2apic_enabled()) {
687 v = apic_read(APIC_DFR);
688 pr_debug("... APIC DFR: %08x\n", v);
689 }
690 v = apic_read(APIC_SPIV);
691 pr_debug("... APIC SPIV: %08x\n", v);
692
693 pr_debug("... APIC ISR field:\n");
694 print_APIC_field(APIC_ISR);
695 pr_debug("... APIC TMR field:\n");
696 print_APIC_field(APIC_TMR);
697 pr_debug("... APIC IRR field:\n");
698 print_APIC_field(APIC_IRR);
699
700 /* !82489DX */
701 if (APIC_INTEGRATED(ver)) {
702 /* Due to the Pentium erratum 3AP. */
703 if (maxlvt > 3)
704 apic_write(APIC_ESR, 0);
705
706 v = apic_read(APIC_ESR);
707 pr_debug("... APIC ESR: %08x\n", v);
708 }
709
710 icr = apic_icr_read();
711 pr_debug("... APIC ICR: %08x\n", (u32)icr);
712 pr_debug("... APIC ICR2: %08x\n", (u32)(icr >> 32));
713
714 v = apic_read(APIC_LVTT);
715 pr_debug("... APIC LVTT: %08x\n", v);
716
717 if (maxlvt > 3) {
718 /* PC is LVT#4. */
719 v = apic_read(APIC_LVTPC);
720 pr_debug("... APIC LVTPC: %08x\n", v);
721 }
722 v = apic_read(APIC_LVT0);
723 pr_debug("... APIC LVT0: %08x\n", v);
724 v = apic_read(APIC_LVT1);
725 pr_debug("... APIC LVT1: %08x\n", v);
726
727 if (maxlvt > 2) {
728 /* ERR is LVT#3. */
729 v = apic_read(APIC_LVTERR);
730 pr_debug("... APIC LVTERR: %08x\n", v);
731 }
732
733 v = apic_read(APIC_TMICT);
734 pr_debug("... APIC TMICT: %08x\n", v);
735 v = apic_read(APIC_TMCCT);
736 pr_debug("... APIC TMCCT: %08x\n", v);
737 v = apic_read(APIC_TDCR);
738 pr_debug("... APIC TDCR: %08x\n", v);
739
740 if (boot_cpu_has(X86_FEATURE_EXTAPIC)) {
741 v = apic_read(APIC_EFEAT);
742 maxlvt = (v >> 16) & 0xff;
743 pr_debug("... APIC EFEAT: %08x\n", v);
744 v = apic_read(APIC_ECTRL);
745 pr_debug("... APIC ECTRL: %08x\n", v);
746 for (i = 0; i < maxlvt; i++) {
747 v = apic_read(APIC_EILVTn(i));
748 pr_debug("... APIC EILVT%d: %08x\n", i, v);
749 }
750 }
751 pr_cont("\n");
752 }
753
754 static void __init print_local_APICs(int maxcpu)
755 {
756 int cpu;
757
758 if (!maxcpu)
759 return;
760
761 preempt_disable();
762 for_each_online_cpu(cpu) {
763 if (cpu >= maxcpu)
764 break;
765 smp_call_function_single(cpu, print_local_APIC, NULL, 1);
766 }
767 preempt_enable();
768 }
769
770 static void __init print_PIC(void)
771 {
772 unsigned int v;
773 unsigned long flags;
774
775 if (!nr_legacy_irqs())
776 return;
777
778 pr_debug("\nprinting PIC contents\n");
779
780 raw_spin_lock_irqsave(&i8259A_lock, flags);
781
782 v = inb(0xa1) << 8 | inb(0x21);
783 pr_debug("... PIC IMR: %04x\n", v);
784
785 v = inb(0xa0) << 8 | inb(0x20);
786 pr_debug("... PIC IRR: %04x\n", v);
787
788 outb(0x0b, 0xa0);
789 outb(0x0b, 0x20);
790 v = inb(0xa0) << 8 | inb(0x20);
791 outb(0x0a, 0xa0);
792 outb(0x0a, 0x20);
793
794 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
795
796 pr_debug("... PIC ISR: %04x\n", v);
797
798 v = inb(0x4d1) << 8 | inb(0x4d0);
799 pr_debug("... PIC ELCR: %04x\n", v);
800 }
801
802 static int show_lapic __initdata = 1;
803 static __init int setup_show_lapic(char *arg)
804 {
805 int num = -1;
806
807 if (strcmp(arg, "all") == 0) {
808 show_lapic = CONFIG_NR_CPUS;
809 } else {
810 get_option(&arg, &num);
811 if (num >= 0)
812 show_lapic = num;
813 }
814
815 return 1;
816 }
817 __setup("show_lapic=", setup_show_lapic);
818
819 static int __init print_ICs(void)
820 {
821 if (apic_verbosity == APIC_QUIET)
822 return 0;
823
824 print_PIC();
825
826 /* don't print out if apic is not there */
827 if (!cpu_has_apic && !apic_from_smp_config())
828 return 0;
829
830 print_local_APICs(show_lapic);
831 print_IO_APICs();
832
833 return 0;
834 }
835
836 late_initcall(print_ICs);
Linux kernel - Deliverables
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