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x86/platform/UV: Add UV MMR Illegal Access Function
[deliverable/linux.git] / arch / x86 / kernel / apic / x2apic_uv_x.c
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * SGI UV APIC functions (note: not an Intel compatible APIC)
7 *
8 * Copyright (C) 2007-2014 Silicon Graphics, Inc. All rights reserved.
9 */
10 #include <linux/cpumask.h>
11 #include <linux/hardirq.h>
12 #include <linux/proc_fs.h>
13 #include <linux/threads.h>
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/string.h>
17 #include <linux/ctype.h>
18 #include <linux/sched.h>
19 #include <linux/timer.h>
20 #include <linux/slab.h>
21 #include <linux/cpu.h>
22 #include <linux/init.h>
23 #include <linux/io.h>
24 #include <linux/pci.h>
25 #include <linux/kdebug.h>
26 #include <linux/delay.h>
27 #include <linux/crash_dump.h>
28 #include <linux/reboot.h>
29
30 #include <asm/uv/uv_mmrs.h>
31 #include <asm/uv/uv_hub.h>
32 #include <asm/current.h>
33 #include <asm/pgtable.h>
34 #include <asm/uv/bios.h>
35 #include <asm/uv/uv.h>
36 #include <asm/apic.h>
37 #include <asm/ipi.h>
38 #include <asm/smp.h>
39 #include <asm/x86_init.h>
40 #include <asm/nmi.h>
41
42 DEFINE_PER_CPU(int, x2apic_extra_bits);
43
44 #define PR_DEVEL(fmt, args...) pr_devel("%s: " fmt, __func__, args)
45
46 static enum uv_system_type uv_system_type;
47 static u64 gru_start_paddr, gru_end_paddr;
48 static u64 gru_dist_base, gru_first_node_paddr = -1LL, gru_last_node_paddr;
49 static u64 gru_dist_lmask, gru_dist_umask;
50 static union uvh_apicid uvh_apicid;
51 int uv_min_hub_revision_id;
52 EXPORT_SYMBOL_GPL(uv_min_hub_revision_id);
53 unsigned int uv_apicid_hibits;
54 EXPORT_SYMBOL_GPL(uv_apicid_hibits);
55
56 static struct apic apic_x2apic_uv_x;
57
58 /* Set this to use hardware error handler instead of kernel panic */
59 static int disable_uv_undefined_panic = 1;
60 unsigned long uv_undefined(char *str)
61 {
62 if (likely(!disable_uv_undefined_panic))
63 panic("UV: error: undefined MMR: %s\n", str);
64 else
65 pr_crit("UV: error: undefined MMR: %s\n", str);
66 return ~0ul; /* cause a machine fault */
67 }
68 EXPORT_SYMBOL(uv_undefined);
69
70 static unsigned long __init uv_early_read_mmr(unsigned long addr)
71 {
72 unsigned long val, *mmr;
73
74 mmr = early_ioremap(UV_LOCAL_MMR_BASE | addr, sizeof(*mmr));
75 val = *mmr;
76 early_iounmap(mmr, sizeof(*mmr));
77 return val;
78 }
79
80 static inline bool is_GRU_range(u64 start, u64 end)
81 {
82 if (gru_dist_base) {
83 u64 su = start & gru_dist_umask; /* upper (incl pnode) bits */
84 u64 sl = start & gru_dist_lmask; /* base offset bits */
85 u64 eu = end & gru_dist_umask;
86 u64 el = end & gru_dist_lmask;
87
88 /* Must reside completely within a single GRU range */
89 return (sl == gru_dist_base && el == gru_dist_base &&
90 su >= gru_first_node_paddr &&
91 su <= gru_last_node_paddr &&
92 eu == su);
93 } else {
94 return start >= gru_start_paddr && end <= gru_end_paddr;
95 }
96 }
97
98 static bool uv_is_untracked_pat_range(u64 start, u64 end)
99 {
100 return is_ISA_range(start, end) || is_GRU_range(start, end);
101 }
102
103 static int __init early_get_pnodeid(void)
104 {
105 union uvh_node_id_u node_id;
106 union uvh_rh_gam_config_mmr_u m_n_config;
107 int pnode;
108
109 /* Currently, all blades have same revision number */
110 node_id.v = uv_early_read_mmr(UVH_NODE_ID);
111 m_n_config.v = uv_early_read_mmr(UVH_RH_GAM_CONFIG_MMR);
112 uv_min_hub_revision_id = node_id.s.revision;
113
114 switch (node_id.s.part_number) {
115 case UV2_HUB_PART_NUMBER:
116 case UV2_HUB_PART_NUMBER_X:
117 uv_min_hub_revision_id += UV2_HUB_REVISION_BASE - 1;
118 break;
119 case UV3_HUB_PART_NUMBER:
120 case UV3_HUB_PART_NUMBER_X:
121 uv_min_hub_revision_id += UV3_HUB_REVISION_BASE;
122 break;
123 case UV4_HUB_PART_NUMBER:
124 uv_min_hub_revision_id += UV4_HUB_REVISION_BASE - 1;
125 break;
126 }
127
128 uv_hub_info->hub_revision = uv_min_hub_revision_id;
129 pnode = (node_id.s.node_id >> 1) & ((1 << m_n_config.s.n_skt) - 1);
130 return pnode;
131 }
132
133 static void __init early_get_apic_pnode_shift(void)
134 {
135 uvh_apicid.v = uv_early_read_mmr(UVH_APICID);
136 if (!uvh_apicid.v)
137 /*
138 * Old bios, use default value
139 */
140 uvh_apicid.s.pnode_shift = UV_APIC_PNODE_SHIFT;
141 }
142
143 /*
144 * Add an extra bit as dictated by bios to the destination apicid of
145 * interrupts potentially passing through the UV HUB. This prevents
146 * a deadlock between interrupts and IO port operations.
147 */
148 static void __init uv_set_apicid_hibit(void)
149 {
150 union uv1h_lb_target_physical_apic_id_mask_u apicid_mask;
151
152 if (is_uv1_hub()) {
153 apicid_mask.v =
154 uv_early_read_mmr(UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK);
155 uv_apicid_hibits =
156 apicid_mask.s1.bit_enables & UV_APICID_HIBIT_MASK;
157 }
158 }
159
160 static int __init uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
161 {
162 int pnodeid;
163 int uv_apic;
164
165 if (strncmp(oem_id, "SGI", 3) != 0)
166 return 0;
167
168 /*
169 * Determine UV arch type.
170 * SGI: UV100/1000
171 * SGI2: UV2000/3000
172 * SGI3: UV300 (truncated to 4 chars because of different varieties)
173 * SGI4: UV400 (truncated to 4 chars because of different varieties)
174 */
175 uv_hub_info->hub_revision =
176 !strncmp(oem_id, "SGI4", 4) ? UV4_HUB_REVISION_BASE :
177 !strncmp(oem_id, "SGI3", 4) ? UV3_HUB_REVISION_BASE :
178 !strcmp(oem_id, "SGI2") ? UV2_HUB_REVISION_BASE :
179 !strcmp(oem_id, "SGI") ? UV1_HUB_REVISION_BASE : 0;
180
181 if (uv_hub_info->hub_revision == 0)
182 goto badbios;
183
184 pnodeid = early_get_pnodeid();
185 early_get_apic_pnode_shift();
186 x86_platform.is_untracked_pat_range = uv_is_untracked_pat_range;
187 x86_platform.nmi_init = uv_nmi_init;
188
189 if (!strcmp(oem_table_id, "UVX")) { /* most common */
190 uv_system_type = UV_X2APIC;
191 uv_apic = 0;
192
193 } else if (!strcmp(oem_table_id, "UVH")) { /* only UV1 systems */
194 uv_system_type = UV_NON_UNIQUE_APIC;
195 __this_cpu_write(x2apic_extra_bits,
196 pnodeid << uvh_apicid.s.pnode_shift);
197 uv_set_apicid_hibit();
198 uv_apic = 1;
199
200 } else if (!strcmp(oem_table_id, "UVL")) { /* only used for */
201 uv_system_type = UV_LEGACY_APIC; /* very small systems */
202 uv_apic = 0;
203
204 } else {
205 goto badbios;
206 }
207
208 pr_info("UV: OEM IDs %s/%s, System/HUB Types %d/%d, uv_apic %d\n",
209 oem_id, oem_table_id, uv_system_type,
210 uv_min_hub_revision_id, uv_apic);
211
212 return uv_apic;
213
214 badbios:
215 pr_err("UV: OEM_ID:%s OEM_TABLE_ID:%s\n", oem_id, oem_table_id);
216 pr_err("Current BIOS not supported, update kernel and/or BIOS\n");
217 BUG();
218 }
219
220 enum uv_system_type get_uv_system_type(void)
221 {
222 return uv_system_type;
223 }
224
225 int is_uv_system(void)
226 {
227 return uv_system_type != UV_NONE;
228 }
229 EXPORT_SYMBOL_GPL(is_uv_system);
230
231 DEFINE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
232 EXPORT_PER_CPU_SYMBOL_GPL(__uv_hub_info);
233
234 struct uv_blade_info *uv_blade_info;
235 EXPORT_SYMBOL_GPL(uv_blade_info);
236
237 short *uv_node_to_blade;
238 EXPORT_SYMBOL_GPL(uv_node_to_blade);
239
240 short *uv_cpu_to_blade;
241 EXPORT_SYMBOL_GPL(uv_cpu_to_blade);
242
243 short uv_possible_blades;
244 EXPORT_SYMBOL_GPL(uv_possible_blades);
245
246 unsigned long sn_rtc_cycles_per_second;
247 EXPORT_SYMBOL(sn_rtc_cycles_per_second);
248
249 static int uv_wakeup_secondary(int phys_apicid, unsigned long start_rip)
250 {
251 unsigned long val;
252 int pnode;
253
254 pnode = uv_apicid_to_pnode(phys_apicid);
255 phys_apicid |= uv_apicid_hibits;
256 val = (1UL << UVH_IPI_INT_SEND_SHFT) |
257 (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
258 ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
259 APIC_DM_INIT;
260 uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
261
262 val = (1UL << UVH_IPI_INT_SEND_SHFT) |
263 (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
264 ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
265 APIC_DM_STARTUP;
266 uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
267
268 return 0;
269 }
270
271 static void uv_send_IPI_one(int cpu, int vector)
272 {
273 unsigned long apicid;
274 int pnode;
275
276 apicid = per_cpu(x86_cpu_to_apicid, cpu);
277 pnode = uv_apicid_to_pnode(apicid);
278 uv_hub_send_ipi(pnode, apicid, vector);
279 }
280
281 static void uv_send_IPI_mask(const struct cpumask *mask, int vector)
282 {
283 unsigned int cpu;
284
285 for_each_cpu(cpu, mask)
286 uv_send_IPI_one(cpu, vector);
287 }
288
289 static void uv_send_IPI_mask_allbutself(const struct cpumask *mask, int vector)
290 {
291 unsigned int this_cpu = smp_processor_id();
292 unsigned int cpu;
293
294 for_each_cpu(cpu, mask) {
295 if (cpu != this_cpu)
296 uv_send_IPI_one(cpu, vector);
297 }
298 }
299
300 static void uv_send_IPI_allbutself(int vector)
301 {
302 unsigned int this_cpu = smp_processor_id();
303 unsigned int cpu;
304
305 for_each_online_cpu(cpu) {
306 if (cpu != this_cpu)
307 uv_send_IPI_one(cpu, vector);
308 }
309 }
310
311 static void uv_send_IPI_all(int vector)
312 {
313 uv_send_IPI_mask(cpu_online_mask, vector);
314 }
315
316 static int uv_apic_id_valid(int apicid)
317 {
318 return 1;
319 }
320
321 static int uv_apic_id_registered(void)
322 {
323 return 1;
324 }
325
326 static void uv_init_apic_ldr(void)
327 {
328 }
329
330 static int
331 uv_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
332 const struct cpumask *andmask,
333 unsigned int *apicid)
334 {
335 int unsigned cpu;
336
337 /*
338 * We're using fixed IRQ delivery, can only return one phys APIC ID.
339 * May as well be the first.
340 */
341 for_each_cpu_and(cpu, cpumask, andmask) {
342 if (cpumask_test_cpu(cpu, cpu_online_mask))
343 break;
344 }
345
346 if (likely(cpu < nr_cpu_ids)) {
347 *apicid = per_cpu(x86_cpu_to_apicid, cpu) | uv_apicid_hibits;
348 return 0;
349 }
350
351 return -EINVAL;
352 }
353
354 static unsigned int x2apic_get_apic_id(unsigned long x)
355 {
356 unsigned int id;
357
358 WARN_ON(preemptible() && num_online_cpus() > 1);
359 id = x | __this_cpu_read(x2apic_extra_bits);
360
361 return id;
362 }
363
364 static unsigned long set_apic_id(unsigned int id)
365 {
366 unsigned long x;
367
368 /* maskout x2apic_extra_bits ? */
369 x = id;
370 return x;
371 }
372
373 static unsigned int uv_read_apic_id(void)
374 {
375
376 return x2apic_get_apic_id(apic_read(APIC_ID));
377 }
378
379 static int uv_phys_pkg_id(int initial_apicid, int index_msb)
380 {
381 return uv_read_apic_id() >> index_msb;
382 }
383
384 static void uv_send_IPI_self(int vector)
385 {
386 apic_write(APIC_SELF_IPI, vector);
387 }
388
389 static int uv_probe(void)
390 {
391 return apic == &apic_x2apic_uv_x;
392 }
393
394 static struct apic __refdata apic_x2apic_uv_x = {
395
396 .name = "UV large system",
397 .probe = uv_probe,
398 .acpi_madt_oem_check = uv_acpi_madt_oem_check,
399 .apic_id_valid = uv_apic_id_valid,
400 .apic_id_registered = uv_apic_id_registered,
401
402 .irq_delivery_mode = dest_Fixed,
403 .irq_dest_mode = 0, /* physical */
404
405 .target_cpus = online_target_cpus,
406 .disable_esr = 0,
407 .dest_logical = APIC_DEST_LOGICAL,
408 .check_apicid_used = NULL,
409
410 .vector_allocation_domain = default_vector_allocation_domain,
411 .init_apic_ldr = uv_init_apic_ldr,
412
413 .ioapic_phys_id_map = NULL,
414 .setup_apic_routing = NULL,
415 .cpu_present_to_apicid = default_cpu_present_to_apicid,
416 .apicid_to_cpu_present = NULL,
417 .check_phys_apicid_present = default_check_phys_apicid_present,
418 .phys_pkg_id = uv_phys_pkg_id,
419
420 .get_apic_id = x2apic_get_apic_id,
421 .set_apic_id = set_apic_id,
422 .apic_id_mask = 0xFFFFFFFFu,
423
424 .cpu_mask_to_apicid_and = uv_cpu_mask_to_apicid_and,
425
426 .send_IPI = uv_send_IPI_one,
427 .send_IPI_mask = uv_send_IPI_mask,
428 .send_IPI_mask_allbutself = uv_send_IPI_mask_allbutself,
429 .send_IPI_allbutself = uv_send_IPI_allbutself,
430 .send_IPI_all = uv_send_IPI_all,
431 .send_IPI_self = uv_send_IPI_self,
432
433 .wakeup_secondary_cpu = uv_wakeup_secondary,
434 .inquire_remote_apic = NULL,
435
436 .read = native_apic_msr_read,
437 .write = native_apic_msr_write,
438 .eoi_write = native_apic_msr_eoi_write,
439 .icr_read = native_x2apic_icr_read,
440 .icr_write = native_x2apic_icr_write,
441 .wait_icr_idle = native_x2apic_wait_icr_idle,
442 .safe_wait_icr_idle = native_safe_x2apic_wait_icr_idle,
443 };
444
445 static void set_x2apic_extra_bits(int pnode)
446 {
447 __this_cpu_write(x2apic_extra_bits, pnode << uvh_apicid.s.pnode_shift);
448 }
449
450 /*
451 * Called on boot cpu.
452 */
453 static __init int boot_pnode_to_blade(int pnode)
454 {
455 int blade;
456
457 for (blade = 0; blade < uv_num_possible_blades(); blade++)
458 if (pnode == uv_blade_info[blade].pnode)
459 return blade;
460 BUG();
461 }
462
463 struct redir_addr {
464 unsigned long redirect;
465 unsigned long alias;
466 };
467
468 #define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT
469
470 static __initdata struct redir_addr redir_addrs[] = {
471 {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR, UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR},
472 {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR, UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR},
473 {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR, UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR},
474 };
475
476 static unsigned char get_n_lshift(int m_val)
477 {
478 union uv3h_gr0_gam_gr_config_u m_gr_config;
479
480 if (is_uv1_hub())
481 return m_val;
482
483 if (is_uv2_hub())
484 return m_val == 40 ? 40 : 39;
485
486 m_gr_config.v = uv_read_local_mmr(UV3H_GR0_GAM_GR_CONFIG);
487 return m_gr_config.s3.m_skt;
488 }
489
490 static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size)
491 {
492 union uvh_rh_gam_alias210_overlay_config_2_mmr_u alias;
493 union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect;
494 int i;
495
496 for (i = 0; i < ARRAY_SIZE(redir_addrs); i++) {
497 alias.v = uv_read_local_mmr(redir_addrs[i].alias);
498 if (alias.s.enable && alias.s.base == 0) {
499 *size = (1UL << alias.s.m_alias);
500 redirect.v = uv_read_local_mmr(redir_addrs[i].redirect);
501 *base = (unsigned long)redirect.s.dest_base << DEST_SHIFT;
502 return;
503 }
504 }
505 *base = *size = 0;
506 }
507
508 enum map_type {map_wb, map_uc};
509
510 static __init void map_high(char *id, unsigned long base, int pshift,
511 int bshift, int max_pnode, enum map_type map_type)
512 {
513 unsigned long bytes, paddr;
514
515 paddr = base << pshift;
516 bytes = (1UL << bshift) * (max_pnode + 1);
517 if (!paddr) {
518 pr_info("UV: Map %s_HI base address NULL\n", id);
519 return;
520 }
521 pr_debug("UV: Map %s_HI 0x%lx - 0x%lx\n", id, paddr, paddr + bytes);
522 if (map_type == map_uc)
523 init_extra_mapping_uc(paddr, bytes);
524 else
525 init_extra_mapping_wb(paddr, bytes);
526 }
527
528 static __init void map_gru_distributed(unsigned long c)
529 {
530 union uvh_rh_gam_gru_overlay_config_mmr_u gru;
531 u64 paddr;
532 unsigned long bytes;
533 int nid;
534
535 gru.v = c;
536 /* only base bits 42:28 relevant in dist mode */
537 gru_dist_base = gru.v & 0x000007fff0000000UL;
538 if (!gru_dist_base) {
539 pr_info("UV: Map GRU_DIST base address NULL\n");
540 return;
541 }
542 bytes = 1UL << UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;
543 gru_dist_lmask = ((1UL << uv_hub_info->m_val) - 1) & ~(bytes - 1);
544 gru_dist_umask = ~((1UL << uv_hub_info->m_val) - 1);
545 gru_dist_base &= gru_dist_lmask; /* Clear bits above M */
546 for_each_online_node(nid) {
547 paddr = ((u64)uv_node_to_pnode(nid) << uv_hub_info->m_val) |
548 gru_dist_base;
549 init_extra_mapping_wb(paddr, bytes);
550 gru_first_node_paddr = min(paddr, gru_first_node_paddr);
551 gru_last_node_paddr = max(paddr, gru_last_node_paddr);
552 }
553 /* Save upper (63:M) bits of address only for is_GRU_range */
554 gru_first_node_paddr &= gru_dist_umask;
555 gru_last_node_paddr &= gru_dist_umask;
556 pr_debug("UV: Map GRU_DIST base 0x%016llx 0x%016llx - 0x%016llx\n",
557 gru_dist_base, gru_first_node_paddr, gru_last_node_paddr);
558 }
559
560 static __init void map_gru_high(int max_pnode)
561 {
562 union uvh_rh_gam_gru_overlay_config_mmr_u gru;
563 int shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;
564
565 gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR);
566 if (!gru.s.enable) {
567 pr_info("UV: GRU disabled\n");
568 return;
569 }
570
571 if (is_uv3_hub() && gru.s3.mode) {
572 map_gru_distributed(gru.v);
573 return;
574 }
575 map_high("GRU", gru.s.base, shift, shift, max_pnode, map_wb);
576 gru_start_paddr = ((u64)gru.s.base << shift);
577 gru_end_paddr = gru_start_paddr + (1UL << shift) * (max_pnode + 1);
578 }
579
580 static __init void map_mmr_high(int max_pnode)
581 {
582 union uvh_rh_gam_mmr_overlay_config_mmr_u mmr;
583 int shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT;
584
585 mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR);
586 if (mmr.s.enable)
587 map_high("MMR", mmr.s.base, shift, shift, max_pnode, map_uc);
588 else
589 pr_info("UV: MMR disabled\n");
590 }
591
592 /*
593 * This commonality works because both 0 & 1 versions of the MMIOH OVERLAY
594 * and REDIRECT MMR regs are exactly the same on UV3.
595 */
596 struct mmioh_config {
597 unsigned long overlay;
598 unsigned long redirect;
599 char *id;
600 };
601
602 static __initdata struct mmioh_config mmiohs[] = {
603 {
604 UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR,
605 UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR,
606 "MMIOH0"
607 },
608 {
609 UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR,
610 UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR,
611 "MMIOH1"
612 },
613 };
614
615 static __init void map_mmioh_high_uv3(int index, int min_pnode, int max_pnode)
616 {
617 union uv3h_rh_gam_mmioh_overlay_config0_mmr_u overlay;
618 unsigned long mmr;
619 unsigned long base;
620 int i, n, shift, m_io, max_io;
621 int nasid, lnasid, fi, li;
622 char *id;
623
624 id = mmiohs[index].id;
625 overlay.v = uv_read_local_mmr(mmiohs[index].overlay);
626 pr_info("UV: %s overlay 0x%lx base:0x%x m_io:%d\n",
627 id, overlay.v, overlay.s3.base, overlay.s3.m_io);
628 if (!overlay.s3.enable) {
629 pr_info("UV: %s disabled\n", id);
630 return;
631 }
632
633 shift = UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_BASE_SHFT;
634 base = (unsigned long)overlay.s3.base;
635 m_io = overlay.s3.m_io;
636 mmr = mmiohs[index].redirect;
637 n = UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH;
638 min_pnode *= 2; /* convert to NASID */
639 max_pnode *= 2;
640 max_io = lnasid = fi = li = -1;
641
642 for (i = 0; i < n; i++) {
643 union uv3h_rh_gam_mmioh_redirect_config0_mmr_u redirect;
644
645 redirect.v = uv_read_local_mmr(mmr + i * 8);
646 nasid = redirect.s3.nasid;
647 if (nasid < min_pnode || max_pnode < nasid)
648 nasid = -1; /* invalid NASID */
649
650 if (nasid == lnasid) {
651 li = i;
652 if (i != n-1) /* last entry check */
653 continue;
654 }
655
656 /* check if we have a cached (or last) redirect to print */
657 if (lnasid != -1 || (i == n-1 && nasid != -1)) {
658 unsigned long addr1, addr2;
659 int f, l;
660
661 if (lnasid == -1) {
662 f = l = i;
663 lnasid = nasid;
664 } else {
665 f = fi;
666 l = li;
667 }
668 addr1 = (base << shift) +
669 f * (unsigned long)(1 << m_io);
670 addr2 = (base << shift) +
671 (l + 1) * (unsigned long)(1 << m_io);
672 pr_info("UV: %s[%03d..%03d] NASID 0x%04x ADDR 0x%016lx - 0x%016lx\n",
673 id, fi, li, lnasid, addr1, addr2);
674 if (max_io < l)
675 max_io = l;
676 }
677 fi = li = i;
678 lnasid = nasid;
679 }
680
681 pr_info("UV: %s base:0x%lx shift:%d M_IO:%d MAX_IO:%d\n",
682 id, base, shift, m_io, max_io);
683
684 if (max_io >= 0)
685 map_high(id, base, shift, m_io, max_io, map_uc);
686 }
687
688 static __init void map_mmioh_high(int min_pnode, int max_pnode)
689 {
690 union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh;
691 unsigned long mmr, base;
692 int shift, enable, m_io, n_io;
693
694 if (is_uv3_hub()) {
695 /* Map both MMIOH Regions */
696 map_mmioh_high_uv3(0, min_pnode, max_pnode);
697 map_mmioh_high_uv3(1, min_pnode, max_pnode);
698 return;
699 }
700
701 if (is_uv1_hub()) {
702 mmr = UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR;
703 shift = UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
704 mmioh.v = uv_read_local_mmr(mmr);
705 enable = !!mmioh.s1.enable;
706 base = mmioh.s1.base;
707 m_io = mmioh.s1.m_io;
708 n_io = mmioh.s1.n_io;
709 } else if (is_uv2_hub()) {
710 mmr = UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR;
711 shift = UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
712 mmioh.v = uv_read_local_mmr(mmr);
713 enable = !!mmioh.s2.enable;
714 base = mmioh.s2.base;
715 m_io = mmioh.s2.m_io;
716 n_io = mmioh.s2.n_io;
717 } else
718 return;
719
720 if (enable) {
721 max_pnode &= (1 << n_io) - 1;
722 pr_info(
723 "UV: base:0x%lx shift:%d N_IO:%d M_IO:%d max_pnode:0x%x\n",
724 base, shift, m_io, n_io, max_pnode);
725 map_high("MMIOH", base, shift, m_io, max_pnode, map_uc);
726 } else {
727 pr_info("UV: MMIOH disabled\n");
728 }
729 }
730
731 static __init void map_low_mmrs(void)
732 {
733 init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE);
734 init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE);
735 }
736
737 static __init void uv_rtc_init(void)
738 {
739 long status;
740 u64 ticks_per_sec;
741
742 status = uv_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK,
743 &ticks_per_sec);
744 if (status != BIOS_STATUS_SUCCESS || ticks_per_sec < 100000) {
745 printk(KERN_WARNING
746 "unable to determine platform RTC clock frequency, "
747 "guessing.\n");
748 /* BIOS gives wrong value for clock freq. so guess */
749 sn_rtc_cycles_per_second = 1000000000000UL / 30000UL;
750 } else
751 sn_rtc_cycles_per_second = ticks_per_sec;
752 }
753
754 /*
755 * percpu heartbeat timer
756 */
757 static void uv_heartbeat(unsigned long ignored)
758 {
759 struct timer_list *timer = &uv_hub_info->scir.timer;
760 unsigned char bits = uv_hub_info->scir.state;
761
762 /* flip heartbeat bit */
763 bits ^= SCIR_CPU_HEARTBEAT;
764
765 /* is this cpu idle? */
766 if (idle_cpu(raw_smp_processor_id()))
767 bits &= ~SCIR_CPU_ACTIVITY;
768 else
769 bits |= SCIR_CPU_ACTIVITY;
770
771 /* update system controller interface reg */
772 uv_set_scir_bits(bits);
773
774 /* enable next timer period */
775 mod_timer_pinned(timer, jiffies + SCIR_CPU_HB_INTERVAL);
776 }
777
778 static void uv_heartbeat_enable(int cpu)
779 {
780 while (!uv_cpu_hub_info(cpu)->scir.enabled) {
781 struct timer_list *timer = &uv_cpu_hub_info(cpu)->scir.timer;
782
783 uv_set_cpu_scir_bits(cpu, SCIR_CPU_HEARTBEAT|SCIR_CPU_ACTIVITY);
784 setup_timer(timer, uv_heartbeat, cpu);
785 timer->expires = jiffies + SCIR_CPU_HB_INTERVAL;
786 add_timer_on(timer, cpu);
787 uv_cpu_hub_info(cpu)->scir.enabled = 1;
788
789 /* also ensure that boot cpu is enabled */
790 cpu = 0;
791 }
792 }
793
794 #ifdef CONFIG_HOTPLUG_CPU
795 static void uv_heartbeat_disable(int cpu)
796 {
797 if (uv_cpu_hub_info(cpu)->scir.enabled) {
798 uv_cpu_hub_info(cpu)->scir.enabled = 0;
799 del_timer(&uv_cpu_hub_info(cpu)->scir.timer);
800 }
801 uv_set_cpu_scir_bits(cpu, 0xff);
802 }
803
804 /*
805 * cpu hotplug notifier
806 */
807 static int uv_scir_cpu_notify(struct notifier_block *self, unsigned long action,
808 void *hcpu)
809 {
810 long cpu = (long)hcpu;
811
812 switch (action & ~CPU_TASKS_FROZEN) {
813 case CPU_DOWN_FAILED:
814 case CPU_ONLINE:
815 uv_heartbeat_enable(cpu);
816 break;
817 case CPU_DOWN_PREPARE:
818 uv_heartbeat_disable(cpu);
819 break;
820 default:
821 break;
822 }
823 return NOTIFY_OK;
824 }
825
826 static __init void uv_scir_register_cpu_notifier(void)
827 {
828 hotcpu_notifier(uv_scir_cpu_notify, 0);
829 }
830
831 #else /* !CONFIG_HOTPLUG_CPU */
832
833 static __init void uv_scir_register_cpu_notifier(void)
834 {
835 }
836
837 static __init int uv_init_heartbeat(void)
838 {
839 int cpu;
840
841 if (is_uv_system())
842 for_each_online_cpu(cpu)
843 uv_heartbeat_enable(cpu);
844 return 0;
845 }
846
847 late_initcall(uv_init_heartbeat);
848
849 #endif /* !CONFIG_HOTPLUG_CPU */
850
851 /* Direct Legacy VGA I/O traffic to designated IOH */
852 int uv_set_vga_state(struct pci_dev *pdev, bool decode,
853 unsigned int command_bits, u32 flags)
854 {
855 int domain, bus, rc;
856
857 PR_DEVEL("devfn %x decode %d cmd %x flags %d\n",
858 pdev->devfn, decode, command_bits, flags);
859
860 if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
861 return 0;
862
863 if ((command_bits & PCI_COMMAND_IO) == 0)
864 return 0;
865
866 domain = pci_domain_nr(pdev->bus);
867 bus = pdev->bus->number;
868
869 rc = uv_bios_set_legacy_vga_target(decode, domain, bus);
870 PR_DEVEL("vga decode %d %x:%x, rc: %d\n", decode, domain, bus, rc);
871
872 return rc;
873 }
874
875 /*
876 * Called on each cpu to initialize the per_cpu UV data area.
877 * FIXME: hotplug not supported yet
878 */
879 void uv_cpu_init(void)
880 {
881 /* CPU 0 initialization will be done via uv_system_init. */
882 if (!uv_blade_info)
883 return;
884
885 uv_blade_info[uv_numa_blade_id()].nr_online_cpus++;
886
887 if (get_uv_system_type() == UV_NON_UNIQUE_APIC)
888 set_x2apic_extra_bits(uv_hub_info->pnode);
889 }
890
891 void __init uv_system_init(void)
892 {
893 union uvh_rh_gam_config_mmr_u m_n_config;
894 union uvh_node_id_u node_id;
895 unsigned long gnode_upper, lowmem_redir_base, lowmem_redir_size;
896 int bytes, nid, cpu, lcpu, pnode, blade, i, j, m_val, n_val;
897 int gnode_extra, min_pnode = 999999, max_pnode = -1;
898 unsigned long mmr_base, present, paddr;
899 unsigned short pnode_mask;
900 unsigned char n_lshift;
901 char *hub = is_uv4_hub() ? "UV400" :
902 is_uv3_hub() ? "UV300" :
903 is_uv2_hub() ? "UV2000/3000" :
904 is_uv1_hub() ? "UV100/1000" : NULL;
905
906 if (!hub) {
907 pr_err("UV: Unknown/unsupported UV hub\n");
908 return;
909 }
910 pr_info("UV: Found %s hub\n", hub);
911
912 /* We now only need to map the MMRs on UV1 */
913 if (is_uv1_hub())
914 map_low_mmrs();
915
916 m_n_config.v = uv_read_local_mmr(UVH_RH_GAM_CONFIG_MMR );
917 m_val = m_n_config.s.m_skt;
918 n_val = m_n_config.s.n_skt;
919 pnode_mask = (1 << n_val) - 1;
920 n_lshift = get_n_lshift(m_val);
921 mmr_base =
922 uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) &
923 ~UV_MMR_ENABLE;
924
925 node_id.v = uv_read_local_mmr(UVH_NODE_ID);
926 gnode_extra = (node_id.s.node_id & ~((1 << n_val) - 1)) >> 1;
927 gnode_upper = ((unsigned long)gnode_extra << m_val);
928 pr_info("UV: N:%d M:%d pnode_mask:0x%x gnode_upper/extra:0x%lx/0x%x n_lshift 0x%x\n",
929 n_val, m_val, pnode_mask, gnode_upper, gnode_extra,
930 n_lshift);
931
932 pr_info("UV: global MMR base 0x%lx\n", mmr_base);
933
934 for(i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++)
935 uv_possible_blades +=
936 hweight64(uv_read_local_mmr( UVH_NODE_PRESENT_TABLE + i * 8));
937
938 /* uv_num_possible_blades() is really the hub count */
939 pr_info("UV: Found %d blades, %d hubs\n",
940 is_uv1_hub() ? uv_num_possible_blades() :
941 (uv_num_possible_blades() + 1) / 2,
942 uv_num_possible_blades());
943
944 bytes = sizeof(struct uv_blade_info) * uv_num_possible_blades();
945 uv_blade_info = kzalloc(bytes, GFP_KERNEL);
946 BUG_ON(!uv_blade_info);
947
948 for (blade = 0; blade < uv_num_possible_blades(); blade++)
949 uv_blade_info[blade].memory_nid = -1;
950
951 get_lowmem_redirect(&lowmem_redir_base, &lowmem_redir_size);
952
953 bytes = sizeof(uv_node_to_blade[0]) * num_possible_nodes();
954 uv_node_to_blade = kmalloc(bytes, GFP_KERNEL);
955 BUG_ON(!uv_node_to_blade);
956 memset(uv_node_to_blade, 255, bytes);
957
958 bytes = sizeof(uv_cpu_to_blade[0]) * num_possible_cpus();
959 uv_cpu_to_blade = kmalloc(bytes, GFP_KERNEL);
960 BUG_ON(!uv_cpu_to_blade);
961 memset(uv_cpu_to_blade, 255, bytes);
962
963 blade = 0;
964 for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) {
965 present = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8);
966 for (j = 0; j < 64; j++) {
967 if (!test_bit(j, &present))
968 continue;
969 pnode = (i * 64 + j) & pnode_mask;
970 uv_blade_info[blade].pnode = pnode;
971 uv_blade_info[blade].nr_possible_cpus = 0;
972 uv_blade_info[blade].nr_online_cpus = 0;
973 spin_lock_init(&uv_blade_info[blade].nmi_lock);
974 min_pnode = min(pnode, min_pnode);
975 max_pnode = max(pnode, max_pnode);
976 blade++;
977 }
978 }
979
980 uv_bios_init();
981 uv_bios_get_sn_info(0, &uv_type, &sn_partition_id, &sn_coherency_id,
982 &sn_region_size, &system_serial_number);
983 uv_rtc_init();
984
985 for_each_present_cpu(cpu) {
986 int apicid = per_cpu(x86_cpu_to_apicid, cpu);
987
988 nid = cpu_to_node(cpu);
989 /*
990 * apic_pnode_shift must be set before calling uv_apicid_to_pnode();
991 */
992 uv_cpu_hub_info(cpu)->pnode_mask = pnode_mask;
993 uv_cpu_hub_info(cpu)->apic_pnode_shift = uvh_apicid.s.pnode_shift;
994 uv_cpu_hub_info(cpu)->hub_revision = uv_hub_info->hub_revision;
995
996 uv_cpu_hub_info(cpu)->m_shift = 64 - m_val;
997 uv_cpu_hub_info(cpu)->n_lshift = n_lshift;
998
999 pnode = uv_apicid_to_pnode(apicid);
1000 blade = boot_pnode_to_blade(pnode);
1001 lcpu = uv_blade_info[blade].nr_possible_cpus;
1002 uv_blade_info[blade].nr_possible_cpus++;
1003
1004 /* Any node on the blade, else will contain -1. */
1005 uv_blade_info[blade].memory_nid = nid;
1006
1007 uv_cpu_hub_info(cpu)->lowmem_remap_base = lowmem_redir_base;
1008 uv_cpu_hub_info(cpu)->lowmem_remap_top = lowmem_redir_size;
1009 uv_cpu_hub_info(cpu)->m_val = m_val;
1010 uv_cpu_hub_info(cpu)->n_val = n_val;
1011 uv_cpu_hub_info(cpu)->numa_blade_id = blade;
1012 uv_cpu_hub_info(cpu)->blade_processor_id = lcpu;
1013 uv_cpu_hub_info(cpu)->pnode = pnode;
1014 uv_cpu_hub_info(cpu)->gpa_mask = (1UL << (m_val + n_val)) - 1;
1015 uv_cpu_hub_info(cpu)->gnode_upper = gnode_upper;
1016 uv_cpu_hub_info(cpu)->gnode_extra = gnode_extra;
1017 uv_cpu_hub_info(cpu)->global_mmr_base = mmr_base;
1018 uv_cpu_hub_info(cpu)->coherency_domain_number = sn_coherency_id;
1019 uv_cpu_hub_info(cpu)->scir.offset = uv_scir_offset(apicid);
1020 uv_node_to_blade[nid] = blade;
1021 uv_cpu_to_blade[cpu] = blade;
1022 }
1023
1024 /* Add blade/pnode info for nodes without cpus */
1025 for_each_online_node(nid) {
1026 if (uv_node_to_blade[nid] >= 0)
1027 continue;
1028 paddr = node_start_pfn(nid) << PAGE_SHIFT;
1029 pnode = uv_gpa_to_pnode(uv_soc_phys_ram_to_gpa(paddr));
1030 blade = boot_pnode_to_blade(pnode);
1031 uv_node_to_blade[nid] = blade;
1032 }
1033
1034 map_gru_high(max_pnode);
1035 map_mmr_high(max_pnode);
1036 map_mmioh_high(min_pnode, max_pnode);
1037
1038 uv_nmi_setup();
1039 uv_cpu_init();
1040 uv_scir_register_cpu_notifier();
1041 proc_mkdir("sgi_uv", NULL);
1042
1043 /* register Legacy VGA I/O redirection handler */
1044 pci_register_set_vga_state(uv_set_vga_state);
1045
1046 /*
1047 * For a kdump kernel the reset must be BOOT_ACPI, not BOOT_EFI, as
1048 * EFI is not enabled in the kdump kernel.
1049 */
1050 if (is_kdump_kernel())
1051 reboot_type = BOOT_ACPI;
1052 }
1053
1054 apic_driver(apic_x2apic_uv_x);
Linux kernel - Deliverables
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