2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/bootmem.h>
22 #include <linux/interrupt.h>
23 #include <linux/mc146818rtc.h>
24 #include <linux/kernel_stat.h>
25 #include <linux/sysdev.h>
26 #include <linux/ioport.h>
27 #include <linux/cpu.h>
28 #include <linux/clockchips.h>
29 #include <linux/acpi_pmtmr.h>
30 #include <linux/module.h>
31 #include <linux/dmi.h>
32 #include <linux/dmar.h>
34 #include <asm/atomic.h>
37 #include <asm/mpspec.h>
39 #include <asm/arch_hooks.h>
41 #include <asm/pgalloc.h>
42 #include <asm/i8253.h>
45 #include <asm/proto.h>
46 #include <asm/timex.h>
48 #include <asm/i8259.h>
50 #include <mach_apic.h>
51 #include <mach_apicdef.h>
57 #if ((SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F)
58 # error SPURIOUS_APIC_VECTOR definition error
63 * Knob to control our willingness to enable the local APIC.
67 static int force_enable_local_apic
;
69 * APIC command line parameters
71 static int __init
parse_lapic(char *arg
)
73 force_enable_local_apic
= 1;
76 early_param("lapic", parse_lapic
);
77 /* Local APIC was disabled by the BIOS and enabled by the kernel */
78 static int enabled_via_apicbase
;
83 static int apic_calibrate_pmtmr __initdata
;
84 static __init
int setup_apicpmtimer(char *s
)
86 apic_calibrate_pmtmr
= 1;
90 __setup("apicpmtimer", setup_apicpmtimer
);
99 /* x2apic enabled before OS handover */
100 int x2apic_preenabled
;
102 static __init
int setup_nox2apic(char *str
)
105 setup_clear_cpu_cap(X86_FEATURE_X2APIC
);
108 early_param("nox2apic", setup_nox2apic
);
111 unsigned long mp_lapic_addr
;
113 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
114 static int disable_apic_timer __cpuinitdata
;
115 /* Local APIC timer works in C2 */
116 int local_apic_timer_c2_ok
;
117 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok
);
119 int first_system_vector
= 0xfe;
121 char system_vectors
[NR_VECTORS
] = { [0 ... NR_VECTORS
-1] = SYS_VECTOR_FREE
};
124 * Debug level, exported for io_apic.c
126 unsigned int apic_verbosity
;
130 /* Have we found an MP table */
131 int smp_found_config
;
133 static struct resource lapic_resource
= {
134 .name
= "Local APIC",
135 .flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
,
138 static unsigned int calibration_result
;
140 static int lapic_next_event(unsigned long delta
,
141 struct clock_event_device
*evt
);
142 static void lapic_timer_setup(enum clock_event_mode mode
,
143 struct clock_event_device
*evt
);
144 static void lapic_timer_broadcast(cpumask_t mask
);
145 static void apic_pm_activate(void);
148 * The local apic timer can be used for any function which is CPU local.
150 static struct clock_event_device lapic_clockevent
= {
152 .features
= CLOCK_EVT_FEAT_PERIODIC
| CLOCK_EVT_FEAT_ONESHOT
153 | CLOCK_EVT_FEAT_C3STOP
| CLOCK_EVT_FEAT_DUMMY
,
155 .set_mode
= lapic_timer_setup
,
156 .set_next_event
= lapic_next_event
,
157 .broadcast
= lapic_timer_broadcast
,
161 static DEFINE_PER_CPU(struct clock_event_device
, lapic_events
);
163 static unsigned long apic_phys
;
166 * Get the LAPIC version
168 static inline int lapic_get_version(void)
170 return GET_APIC_VERSION(apic_read(APIC_LVR
));
174 * Check, if the APIC is integrated or a separate chip
176 static inline int lapic_is_integrated(void)
181 return APIC_INTEGRATED(lapic_get_version());
186 * Check, whether this is a modern or a first generation APIC
188 static int modern_apic(void)
190 /* AMD systems use old APIC versions, so check the CPU */
191 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
&&
192 boot_cpu_data
.x86
>= 0xf)
194 return lapic_get_version() >= 0x14;
198 * Paravirt kernels also might be using these below ops. So we still
199 * use generic apic_read()/apic_write(), which might be pointing to different
200 * ops in PARAVIRT case.
202 void xapic_wait_icr_idle(void)
204 while (apic_read(APIC_ICR
) & APIC_ICR_BUSY
)
208 u32
safe_xapic_wait_icr_idle(void)
215 send_status
= apic_read(APIC_ICR
) & APIC_ICR_BUSY
;
219 } while (timeout
++ < 1000);
224 void xapic_icr_write(u32 low
, u32 id
)
226 apic_write(APIC_ICR2
, SET_APIC_DEST_FIELD(id
));
227 apic_write(APIC_ICR
, low
);
230 u64
xapic_icr_read(void)
234 icr2
= apic_read(APIC_ICR2
);
235 icr1
= apic_read(APIC_ICR
);
237 return icr1
| ((u64
)icr2
<< 32);
240 static struct apic_ops xapic_ops
= {
241 .read
= native_apic_mem_read
,
242 .write
= native_apic_mem_write
,
243 .icr_read
= xapic_icr_read
,
244 .icr_write
= xapic_icr_write
,
245 .wait_icr_idle
= xapic_wait_icr_idle
,
246 .safe_wait_icr_idle
= safe_xapic_wait_icr_idle
,
249 struct apic_ops __read_mostly
*apic_ops
= &xapic_ops
;
250 EXPORT_SYMBOL_GPL(apic_ops
);
253 static void x2apic_wait_icr_idle(void)
255 /* no need to wait for icr idle in x2apic */
259 static u32
safe_x2apic_wait_icr_idle(void)
261 /* no need to wait for icr idle in x2apic */
265 void x2apic_icr_write(u32 low
, u32 id
)
267 wrmsrl(APIC_BASE_MSR
+ (APIC_ICR
>> 4), ((__u64
) id
) << 32 | low
);
270 u64
x2apic_icr_read(void)
274 rdmsrl(APIC_BASE_MSR
+ (APIC_ICR
>> 4), val
);
278 static struct apic_ops x2apic_ops
= {
279 .read
= native_apic_msr_read
,
280 .write
= native_apic_msr_write
,
281 .icr_read
= x2apic_icr_read
,
282 .icr_write
= x2apic_icr_write
,
283 .wait_icr_idle
= x2apic_wait_icr_idle
,
284 .safe_wait_icr_idle
= safe_x2apic_wait_icr_idle
,
289 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
291 void __cpuinit
enable_NMI_through_LVT0(void)
295 /* unmask and set to NMI */
298 /* Level triggered for 82489DX (32bit mode) */
299 if (!lapic_is_integrated())
300 v
|= APIC_LVT_LEVEL_TRIGGER
;
302 apic_write(APIC_LVT0
, v
);
307 * get_physical_broadcast - Get number of physical broadcast IDs
309 int get_physical_broadcast(void)
311 return modern_apic() ? 0xff : 0xf;
316 * lapic_get_maxlvt - get the maximum number of local vector table entries
318 int lapic_get_maxlvt(void)
322 v
= apic_read(APIC_LVR
);
324 * - we always have APIC integrated on 64bit mode
325 * - 82489DXs do not report # of LVT entries
327 return APIC_INTEGRATED(GET_APIC_VERSION(v
)) ? GET_APIC_MAXLVT(v
) : 2;
336 #define APIC_DIVISOR 1
338 #define APIC_DIVISOR 16
342 * This function sets up the local APIC timer, with a timeout of
343 * 'clocks' APIC bus clock. During calibration we actually call
344 * this function twice on the boot CPU, once with a bogus timeout
345 * value, second time for real. The other (noncalibrating) CPUs
346 * call this function only once, with the real, calibrated value.
348 * We do reads before writes even if unnecessary, to get around the
349 * P5 APIC double write bug.
351 static void __setup_APIC_LVTT(unsigned int clocks
, int oneshot
, int irqen
)
353 unsigned int lvtt_value
, tmp_value
;
355 lvtt_value
= LOCAL_TIMER_VECTOR
;
357 lvtt_value
|= APIC_LVT_TIMER_PERIODIC
;
358 if (!lapic_is_integrated())
359 lvtt_value
|= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV
);
362 lvtt_value
|= APIC_LVT_MASKED
;
364 apic_write(APIC_LVTT
, lvtt_value
);
369 tmp_value
= apic_read(APIC_TDCR
);
370 apic_write(APIC_TDCR
,
371 (tmp_value
& ~(APIC_TDR_DIV_1
| APIC_TDR_DIV_TMBASE
)) |
375 apic_write(APIC_TMICT
, clocks
/ APIC_DIVISOR
);
379 * Setup extended LVT, AMD specific (K8, family 10h)
381 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
382 * MCE interrupts are supported. Thus MCE offset must be set to 0.
384 * If mask=1, the LVT entry does not generate interrupts while mask=0
385 * enables the vector. See also the BKDGs.
388 #define APIC_EILVT_LVTOFF_MCE 0
389 #define APIC_EILVT_LVTOFF_IBS 1
391 static void setup_APIC_eilvt(u8 lvt_off
, u8 vector
, u8 msg_type
, u8 mask
)
393 unsigned long reg
= (lvt_off
<< 4) + APIC_EILVT0
;
394 unsigned int v
= (mask
<< 16) | (msg_type
<< 8) | vector
;
399 u8
setup_APIC_eilvt_mce(u8 vector
, u8 msg_type
, u8 mask
)
401 setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE
, vector
, msg_type
, mask
);
402 return APIC_EILVT_LVTOFF_MCE
;
405 u8
setup_APIC_eilvt_ibs(u8 vector
, u8 msg_type
, u8 mask
)
407 setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS
, vector
, msg_type
, mask
);
408 return APIC_EILVT_LVTOFF_IBS
;
410 EXPORT_SYMBOL_GPL(setup_APIC_eilvt_ibs
);
413 * Program the next event, relative to now
415 static int lapic_next_event(unsigned long delta
,
416 struct clock_event_device
*evt
)
418 apic_write(APIC_TMICT
, delta
);
423 * Setup the lapic timer in periodic or oneshot mode
425 static void lapic_timer_setup(enum clock_event_mode mode
,
426 struct clock_event_device
*evt
)
431 /* Lapic used as dummy for broadcast ? */
432 if (evt
->features
& CLOCK_EVT_FEAT_DUMMY
)
435 local_irq_save(flags
);
438 case CLOCK_EVT_MODE_PERIODIC
:
439 case CLOCK_EVT_MODE_ONESHOT
:
440 __setup_APIC_LVTT(calibration_result
,
441 mode
!= CLOCK_EVT_MODE_PERIODIC
, 1);
443 case CLOCK_EVT_MODE_UNUSED
:
444 case CLOCK_EVT_MODE_SHUTDOWN
:
445 v
= apic_read(APIC_LVTT
);
446 v
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
447 apic_write(APIC_LVTT
, v
);
449 case CLOCK_EVT_MODE_RESUME
:
450 /* Nothing to do here */
454 local_irq_restore(flags
);
458 * Local APIC timer broadcast function
460 static void lapic_timer_broadcast(cpumask_t mask
)
463 send_IPI_mask(mask
, LOCAL_TIMER_VECTOR
);
468 * Setup the local APIC timer for this CPU. Copy the initilized values
469 * of the boot CPU and register the clock event in the framework.
471 static void __cpuinit
setup_APIC_timer(void)
473 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
475 memcpy(levt
, &lapic_clockevent
, sizeof(*levt
));
476 levt
->cpumask
= cpumask_of_cpu(smp_processor_id());
478 clockevents_register_device(levt
);
482 * In this functions we calibrate APIC bus clocks to the external timer.
484 * We want to do the calibration only once since we want to have local timer
485 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
488 * This was previously done by reading the PIT/HPET and waiting for a wrap
489 * around to find out, that a tick has elapsed. I have a box, where the PIT
490 * readout is broken, so it never gets out of the wait loop again. This was
491 * also reported by others.
493 * Monitoring the jiffies value is inaccurate and the clockevents
494 * infrastructure allows us to do a simple substitution of the interrupt
497 * The calibration routine also uses the pm_timer when possible, as the PIT
498 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
499 * back to normal later in the boot process).
502 #define LAPIC_CAL_LOOPS (HZ/10)
504 static __initdata
int lapic_cal_loops
= -1;
505 static __initdata
long lapic_cal_t1
, lapic_cal_t2
;
506 static __initdata
unsigned long long lapic_cal_tsc1
, lapic_cal_tsc2
;
507 static __initdata
unsigned long lapic_cal_pm1
, lapic_cal_pm2
;
508 static __initdata
unsigned long lapic_cal_j1
, lapic_cal_j2
;
511 * Temporary interrupt handler.
513 static void __init
lapic_cal_handler(struct clock_event_device
*dev
)
515 unsigned long long tsc
= 0;
516 long tapic
= apic_read(APIC_TMCCT
);
517 unsigned long pm
= acpi_pm_read_early();
522 switch (lapic_cal_loops
++) {
524 lapic_cal_t1
= tapic
;
525 lapic_cal_tsc1
= tsc
;
527 lapic_cal_j1
= jiffies
;
530 case LAPIC_CAL_LOOPS
:
531 lapic_cal_t2
= tapic
;
532 lapic_cal_tsc2
= tsc
;
533 if (pm
< lapic_cal_pm1
)
534 pm
+= ACPI_PM_OVRRUN
;
536 lapic_cal_j2
= jiffies
;
541 static int __init
calibrate_APIC_clock(void)
543 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
544 const long pm_100ms
= PMTMR_TICKS_PER_SEC
/10;
545 const long pm_thresh
= pm_100ms
/100;
546 void (*real_handler
)(struct clock_event_device
*dev
);
547 unsigned long deltaj
;
549 int pm_referenced
= 0;
553 /* Replace the global interrupt handler */
554 real_handler
= global_clock_event
->event_handler
;
555 global_clock_event
->event_handler
= lapic_cal_handler
;
558 * Setup the APIC counter to 1e9. There is no way the lapic
559 * can underflow in the 100ms detection time frame
561 __setup_APIC_LVTT(1000000000, 0, 0);
563 /* Let the interrupts run */
566 while (lapic_cal_loops
<= LAPIC_CAL_LOOPS
)
571 /* Restore the real event handler */
572 global_clock_event
->event_handler
= real_handler
;
574 /* Build delta t1-t2 as apic timer counts down */
575 delta
= lapic_cal_t1
- lapic_cal_t2
;
576 apic_printk(APIC_VERBOSE
, "... lapic delta = %ld\n", delta
);
578 #ifdef CONFIG_X86_PM_TIMER
579 /* Check, if the PM timer is available */
580 deltapm
= lapic_cal_pm2
- lapic_cal_pm1
;
581 apic_printk(APIC_VERBOSE
, "... PM timer delta = %ld\n", deltapm
);
587 mult
= clocksource_hz2mult(PMTMR_TICKS_PER_SEC
, 22);
589 if (deltapm
> (pm_100ms
- pm_thresh
) &&
590 deltapm
< (pm_100ms
+ pm_thresh
)) {
591 apic_printk(APIC_VERBOSE
, "... PM timer result ok\n");
593 res
= (((u64
) deltapm
) * mult
) >> 22;
594 do_div(res
, 1000000);
595 printk(KERN_WARNING
"APIC calibration not consistent "
596 "with PM Timer: %ldms instead of 100ms\n",
598 /* Correct the lapic counter value */
599 res
= (((u64
) delta
) * pm_100ms
);
600 do_div(res
, deltapm
);
601 printk(KERN_INFO
"APIC delta adjusted to PM-Timer: "
602 "%lu (%ld)\n", (unsigned long) res
, delta
);
609 /* Calculate the scaled math multiplication factor */
610 lapic_clockevent
.mult
= div_sc(delta
, TICK_NSEC
* LAPIC_CAL_LOOPS
,
611 lapic_clockevent
.shift
);
612 lapic_clockevent
.max_delta_ns
=
613 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent
);
614 lapic_clockevent
.min_delta_ns
=
615 clockevent_delta2ns(0xF, &lapic_clockevent
);
617 calibration_result
= (delta
* APIC_DIVISOR
) / LAPIC_CAL_LOOPS
;
619 apic_printk(APIC_VERBOSE
, "..... delta %ld\n", delta
);
620 apic_printk(APIC_VERBOSE
, "..... mult: %ld\n", lapic_clockevent
.mult
);
621 apic_printk(APIC_VERBOSE
, "..... calibration result: %u\n",
625 delta
= (long)(lapic_cal_tsc2
- lapic_cal_tsc1
);
626 apic_printk(APIC_VERBOSE
, "..... CPU clock speed is "
628 (delta
/ LAPIC_CAL_LOOPS
) / (1000000 / HZ
),
629 (delta
/ LAPIC_CAL_LOOPS
) % (1000000 / HZ
));
632 apic_printk(APIC_VERBOSE
, "..... host bus clock speed is "
634 calibration_result
/ (1000000 / HZ
),
635 calibration_result
% (1000000 / HZ
));
638 * Do a sanity check on the APIC calibration result
640 if (calibration_result
< (1000000 / HZ
)) {
643 "APIC frequency too slow, disabling apic timer\n");
647 levt
->features
&= ~CLOCK_EVT_FEAT_DUMMY
;
649 /* We trust the pm timer based calibration */
650 if (!pm_referenced
) {
651 apic_printk(APIC_VERBOSE
, "... verify APIC timer\n");
654 * Setup the apic timer manually
656 levt
->event_handler
= lapic_cal_handler
;
657 lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC
, levt
);
658 lapic_cal_loops
= -1;
660 /* Let the interrupts run */
663 while (lapic_cal_loops
<= LAPIC_CAL_LOOPS
)
668 /* Stop the lapic timer */
669 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, levt
);
674 deltaj
= lapic_cal_j2
- lapic_cal_j1
;
675 apic_printk(APIC_VERBOSE
, "... jiffies delta = %lu\n", deltaj
);
677 /* Check, if the jiffies result is consistent */
678 if (deltaj
>= LAPIC_CAL_LOOPS
-2 && deltaj
<= LAPIC_CAL_LOOPS
+2)
679 apic_printk(APIC_VERBOSE
, "... jiffies result ok\n");
681 levt
->features
|= CLOCK_EVT_FEAT_DUMMY
;
685 if (levt
->features
& CLOCK_EVT_FEAT_DUMMY
) {
687 "APIC timer disabled due to verification failure.\n");
695 * Setup the boot APIC
697 * Calibrate and verify the result.
699 void __init
setup_boot_APIC_clock(void)
702 * The local apic timer can be disabled via the kernel
703 * commandline or from the CPU detection code. Register the lapic
704 * timer as a dummy clock event source on SMP systems, so the
705 * broadcast mechanism is used. On UP systems simply ignore it.
707 if (disable_apic_timer
) {
708 printk(KERN_INFO
"Disabling APIC timer\n");
709 /* No broadcast on UP ! */
710 if (num_possible_cpus() > 1) {
711 lapic_clockevent
.mult
= 1;
717 apic_printk(APIC_VERBOSE
, "Using local APIC timer interrupts.\n"
718 "calibrating APIC timer ...\n");
720 if (calibrate_APIC_clock()) {
721 /* No broadcast on UP ! */
722 if (num_possible_cpus() > 1)
728 * If nmi_watchdog is set to IO_APIC, we need the
729 * PIT/HPET going. Otherwise register lapic as a dummy
732 if (nmi_watchdog
!= NMI_IO_APIC
)
733 lapic_clockevent
.features
&= ~CLOCK_EVT_FEAT_DUMMY
;
735 printk(KERN_WARNING
"APIC timer registered as dummy,"
736 " due to nmi_watchdog=%d!\n", nmi_watchdog
);
738 /* Setup the lapic or request the broadcast */
742 void __cpuinit
setup_secondary_APIC_clock(void)
748 * The guts of the apic timer interrupt
750 static void local_apic_timer_interrupt(void)
752 int cpu
= smp_processor_id();
753 struct clock_event_device
*evt
= &per_cpu(lapic_events
, cpu
);
756 * Normally we should not be here till LAPIC has been initialized but
757 * in some cases like kdump, its possible that there is a pending LAPIC
758 * timer interrupt from previous kernel's context and is delivered in
759 * new kernel the moment interrupts are enabled.
761 * Interrupts are enabled early and LAPIC is setup much later, hence
762 * its possible that when we get here evt->event_handler is NULL.
763 * Check for event_handler being NULL and discard the interrupt as
766 if (!evt
->event_handler
) {
768 "Spurious LAPIC timer interrupt on cpu %d\n", cpu
);
770 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, evt
);
775 * the NMI deadlock-detector uses this.
778 add_pda(apic_timer_irqs
, 1);
780 per_cpu(irq_stat
, cpu
).apic_timer_irqs
++;
783 evt
->event_handler(evt
);
787 * Local APIC timer interrupt. This is the most natural way for doing
788 * local interrupts, but local timer interrupts can be emulated by
789 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
791 * [ if a single-CPU system runs an SMP kernel then we call the local
792 * interrupt as well. Thus we cannot inline the local irq ... ]
794 void smp_apic_timer_interrupt(struct pt_regs
*regs
)
796 struct pt_regs
*old_regs
= set_irq_regs(regs
);
799 * NOTE! We'd better ACK the irq immediately,
800 * because timer handling can be slow.
804 * update_process_times() expects us to have done irq_enter().
805 * Besides, if we don't timer interrupts ignore the global
806 * interrupt lock, which is the WrongThing (tm) to do.
812 local_apic_timer_interrupt();
815 set_irq_regs(old_regs
);
818 int setup_profiling_timer(unsigned int multiplier
)
824 * Local APIC start and shutdown
828 * clear_local_APIC - shutdown the local APIC
830 * This is called, when a CPU is disabled and before rebooting, so the state of
831 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
832 * leftovers during boot.
834 void clear_local_APIC(void)
839 /* APIC hasn't been mapped yet */
843 maxlvt
= lapic_get_maxlvt();
845 * Masking an LVT entry can trigger a local APIC error
846 * if the vector is zero. Mask LVTERR first to prevent this.
849 v
= ERROR_APIC_VECTOR
; /* any non-zero vector will do */
850 apic_write(APIC_LVTERR
, v
| APIC_LVT_MASKED
);
853 * Careful: we have to set masks only first to deassert
854 * any level-triggered sources.
856 v
= apic_read(APIC_LVTT
);
857 apic_write(APIC_LVTT
, v
| APIC_LVT_MASKED
);
858 v
= apic_read(APIC_LVT0
);
859 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
860 v
= apic_read(APIC_LVT1
);
861 apic_write(APIC_LVT1
, v
| APIC_LVT_MASKED
);
863 v
= apic_read(APIC_LVTPC
);
864 apic_write(APIC_LVTPC
, v
| APIC_LVT_MASKED
);
867 /* lets not touch this if we didn't frob it */
868 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(X86_MCE_INTEL)
870 v
= apic_read(APIC_LVTTHMR
);
871 apic_write(APIC_LVTTHMR
, v
| APIC_LVT_MASKED
);
875 * Clean APIC state for other OSs:
877 apic_write(APIC_LVTT
, APIC_LVT_MASKED
);
878 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
879 apic_write(APIC_LVT1
, APIC_LVT_MASKED
);
881 apic_write(APIC_LVTERR
, APIC_LVT_MASKED
);
883 apic_write(APIC_LVTPC
, APIC_LVT_MASKED
);
885 /* Integrated APIC (!82489DX) ? */
886 if (lapic_is_integrated()) {
888 /* Clear ESR due to Pentium errata 3AP and 11AP */
889 apic_write(APIC_ESR
, 0);
895 * disable_local_APIC - clear and disable the local APIC
897 void disable_local_APIC(void)
904 * Disable APIC (implies clearing of registers
907 value
= apic_read(APIC_SPIV
);
908 value
&= ~APIC_SPIV_APIC_ENABLED
;
909 apic_write(APIC_SPIV
, value
);
913 * When LAPIC was disabled by the BIOS and enabled by the kernel,
914 * restore the disabled state.
916 if (enabled_via_apicbase
) {
919 rdmsr(MSR_IA32_APICBASE
, l
, h
);
920 l
&= ~MSR_IA32_APICBASE_ENABLE
;
921 wrmsr(MSR_IA32_APICBASE
, l
, h
);
927 * If Linux enabled the LAPIC against the BIOS default disable it down before
928 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
929 * not power-off. Additionally clear all LVT entries before disable_local_APIC
930 * for the case where Linux didn't enable the LAPIC.
932 void lapic_shutdown(void)
939 local_irq_save(flags
);
942 if (!enabled_via_apicbase
)
946 disable_local_APIC();
949 local_irq_restore(flags
);
953 * This is to verify that we're looking at a real local APIC.
954 * Check these against your board if the CPUs aren't getting
955 * started for no apparent reason.
957 int __init
verify_local_APIC(void)
959 unsigned int reg0
, reg1
;
962 * The version register is read-only in a real APIC.
964 reg0
= apic_read(APIC_LVR
);
965 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg0
);
966 apic_write(APIC_LVR
, reg0
^ APIC_LVR_MASK
);
967 reg1
= apic_read(APIC_LVR
);
968 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg1
);
971 * The two version reads above should print the same
972 * numbers. If the second one is different, then we
973 * poke at a non-APIC.
979 * Check if the version looks reasonably.
981 reg1
= GET_APIC_VERSION(reg0
);
982 if (reg1
== 0x00 || reg1
== 0xff)
984 reg1
= lapic_get_maxlvt();
985 if (reg1
< 0x02 || reg1
== 0xff)
989 * The ID register is read/write in a real APIC.
991 reg0
= apic_read(APIC_ID
);
992 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg0
);
993 apic_write(APIC_ID
, reg0
^ APIC_ID_MASK
);
994 reg1
= apic_read(APIC_ID
);
995 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg1
);
996 apic_write(APIC_ID
, reg0
);
997 if (reg1
!= (reg0
^ APIC_ID_MASK
))
1001 * The next two are just to see if we have sane values.
1002 * They're only really relevant if we're in Virtual Wire
1003 * compatibility mode, but most boxes are anymore.
1005 reg0
= apic_read(APIC_LVT0
);
1006 apic_printk(APIC_DEBUG
, "Getting LVT0: %x\n", reg0
);
1007 reg1
= apic_read(APIC_LVT1
);
1008 apic_printk(APIC_DEBUG
, "Getting LVT1: %x\n", reg1
);
1014 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
1016 void __init
sync_Arb_IDs(void)
1019 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
1022 if (modern_apic() || boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
)
1028 apic_wait_icr_idle();
1030 apic_printk(APIC_DEBUG
, "Synchronizing Arb IDs.\n");
1031 apic_write(APIC_ICR
, APIC_DEST_ALLINC
|
1032 APIC_INT_LEVELTRIG
| APIC_DM_INIT
);
1036 * An initial setup of the virtual wire mode.
1038 void __init
init_bsp_APIC(void)
1043 * Don't do the setup now if we have a SMP BIOS as the
1044 * through-I/O-APIC virtual wire mode might be active.
1046 if (smp_found_config
|| !cpu_has_apic
)
1050 * Do not trust the local APIC being empty at bootup.
1057 value
= apic_read(APIC_SPIV
);
1058 value
&= ~APIC_VECTOR_MASK
;
1059 value
|= APIC_SPIV_APIC_ENABLED
;
1061 #ifdef CONFIG_X86_32
1062 /* This bit is reserved on P4/Xeon and should be cleared */
1063 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
) &&
1064 (boot_cpu_data
.x86
== 15))
1065 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
1068 value
|= APIC_SPIV_FOCUS_DISABLED
;
1069 value
|= SPURIOUS_APIC_VECTOR
;
1070 apic_write(APIC_SPIV
, value
);
1073 * Set up the virtual wire mode.
1075 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
1076 value
= APIC_DM_NMI
;
1077 if (!lapic_is_integrated()) /* 82489DX */
1078 value
|= APIC_LVT_LEVEL_TRIGGER
;
1079 apic_write(APIC_LVT1
, value
);
1082 static void __cpuinit
lapic_setup_esr(void)
1084 unsigned long oldvalue
, value
, maxlvt
;
1085 if (lapic_is_integrated() && !esr_disable
) {
1088 * Something untraceable is creating bad interrupts on
1089 * secondary quads ... for the moment, just leave the
1090 * ESR disabled - we can't do anything useful with the
1091 * errors anyway - mbligh
1093 printk(KERN_INFO
"Leaving ESR disabled.\n");
1097 maxlvt
= lapic_get_maxlvt();
1098 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
1099 apic_write(APIC_ESR
, 0);
1100 oldvalue
= apic_read(APIC_ESR
);
1102 /* enables sending errors */
1103 value
= ERROR_APIC_VECTOR
;
1104 apic_write(APIC_LVTERR
, value
);
1106 * spec says clear errors after enabling vector.
1109 apic_write(APIC_ESR
, 0);
1110 value
= apic_read(APIC_ESR
);
1111 if (value
!= oldvalue
)
1112 apic_printk(APIC_VERBOSE
, "ESR value before enabling "
1113 "vector: 0x%08lx after: 0x%08lx\n",
1116 printk(KERN_INFO
"No ESR for 82489DX.\n");
1122 * setup_local_APIC - setup the local APIC
1124 void __cpuinit
setup_local_APIC(void)
1129 #ifdef CONFIG_X86_32
1130 /* Pound the ESR really hard over the head with a big hammer - mbligh */
1132 apic_write(APIC_ESR
, 0);
1133 apic_write(APIC_ESR
, 0);
1134 apic_write(APIC_ESR
, 0);
1135 apic_write(APIC_ESR
, 0);
1142 * Double-check whether this APIC is really registered.
1143 * This is meaningless in clustered apic mode, so we skip it.
1145 if (!apic_id_registered())
1149 * Intel recommends to set DFR, LDR and TPR before enabling
1150 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
1151 * document number 292116). So here it goes...
1156 * Set Task Priority to 'accept all'. We never change this
1159 value
= apic_read(APIC_TASKPRI
);
1160 value
&= ~APIC_TPRI_MASK
;
1161 apic_write(APIC_TASKPRI
, value
);
1164 * After a crash, we no longer service the interrupts and a pending
1165 * interrupt from previous kernel might still have ISR bit set.
1167 * Most probably by now CPU has serviced that pending interrupt and
1168 * it might not have done the ack_APIC_irq() because it thought,
1169 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
1170 * does not clear the ISR bit and cpu thinks it has already serivced
1171 * the interrupt. Hence a vector might get locked. It was noticed
1172 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
1174 for (i
= APIC_ISR_NR
- 1; i
>= 0; i
--) {
1175 value
= apic_read(APIC_ISR
+ i
*0x10);
1176 for (j
= 31; j
>= 0; j
--) {
1183 * Now that we are all set up, enable the APIC
1185 value
= apic_read(APIC_SPIV
);
1186 value
&= ~APIC_VECTOR_MASK
;
1190 value
|= APIC_SPIV_APIC_ENABLED
;
1192 #ifdef CONFIG_X86_32
1194 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1195 * certain networking cards. If high frequency interrupts are
1196 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1197 * entry is masked/unmasked at a high rate as well then sooner or
1198 * later IOAPIC line gets 'stuck', no more interrupts are received
1199 * from the device. If focus CPU is disabled then the hang goes
1202 * [ This bug can be reproduced easily with a level-triggered
1203 * PCI Ne2000 networking cards and PII/PIII processors, dual
1207 * Actually disabling the focus CPU check just makes the hang less
1208 * frequent as it makes the interrupt distributon model be more
1209 * like LRU than MRU (the short-term load is more even across CPUs).
1210 * See also the comment in end_level_ioapic_irq(). --macro
1214 * - enable focus processor (bit==0)
1215 * - 64bit mode always use processor focus
1216 * so no need to set it
1218 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
1222 * Set spurious IRQ vector
1224 value
|= SPURIOUS_APIC_VECTOR
;
1225 apic_write(APIC_SPIV
, value
);
1228 * Set up LVT0, LVT1:
1230 * set up through-local-APIC on the BP's LINT0. This is not
1231 * strictly necessary in pure symmetric-IO mode, but sometimes
1232 * we delegate interrupts to the 8259A.
1235 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1237 value
= apic_read(APIC_LVT0
) & APIC_LVT_MASKED
;
1238 if (!smp_processor_id() && (pic_mode
|| !value
)) {
1239 value
= APIC_DM_EXTINT
;
1240 apic_printk(APIC_VERBOSE
, "enabled ExtINT on CPU#%d\n",
1241 smp_processor_id());
1243 value
= APIC_DM_EXTINT
| APIC_LVT_MASKED
;
1244 apic_printk(APIC_VERBOSE
, "masked ExtINT on CPU#%d\n",
1245 smp_processor_id());
1247 apic_write(APIC_LVT0
, value
);
1250 * only the BP should see the LINT1 NMI signal, obviously.
1252 if (!smp_processor_id())
1253 value
= APIC_DM_NMI
;
1255 value
= APIC_DM_NMI
| APIC_LVT_MASKED
;
1256 if (!lapic_is_integrated()) /* 82489DX */
1257 value
|= APIC_LVT_LEVEL_TRIGGER
;
1258 apic_write(APIC_LVT1
, value
);
1263 void __cpuinit
end_local_APIC_setup(void)
1267 #ifdef CONFIG_X86_32
1270 /* Disable the local apic timer */
1271 value
= apic_read(APIC_LVTT
);
1272 value
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
1273 apic_write(APIC_LVTT
, value
);
1277 setup_apic_nmi_watchdog(NULL
);
1282 void check_x2apic(void)
1286 rdmsr(MSR_IA32_APICBASE
, msr
, msr2
);
1288 if (msr
& X2APIC_ENABLE
) {
1289 printk("x2apic enabled by BIOS, switching to x2apic ops\n");
1290 x2apic_preenabled
= x2apic
= 1;
1291 apic_ops
= &x2apic_ops
;
1295 void enable_x2apic(void)
1299 rdmsr(MSR_IA32_APICBASE
, msr
, msr2
);
1300 if (!(msr
& X2APIC_ENABLE
)) {
1301 printk("Enabling x2apic\n");
1302 wrmsr(MSR_IA32_APICBASE
, msr
| X2APIC_ENABLE
, 0);
1306 void enable_IR_x2apic(void)
1308 #ifdef CONFIG_INTR_REMAP
1310 unsigned long flags
;
1312 if (!cpu_has_x2apic
)
1315 if (!x2apic_preenabled
&& disable_x2apic
) {
1317 "Skipped enabling x2apic and Interrupt-remapping "
1318 "because of nox2apic\n");
1322 if (x2apic_preenabled
&& disable_x2apic
)
1323 panic("Bios already enabled x2apic, can't enforce nox2apic");
1325 if (!x2apic_preenabled
&& skip_ioapic_setup
) {
1327 "Skipped enabling x2apic and Interrupt-remapping "
1328 "because of skipping io-apic setup\n");
1332 ret
= dmar_table_init();
1335 "dmar_table_init() failed with %d:\n", ret
);
1337 if (x2apic_preenabled
)
1338 panic("x2apic enabled by bios. But IR enabling failed");
1341 "Not enabling x2apic,Intr-remapping\n");
1345 local_irq_save(flags
);
1347 save_mask_IO_APIC_setup();
1349 ret
= enable_intr_remapping(1);
1351 if (ret
&& x2apic_preenabled
) {
1352 local_irq_restore(flags
);
1353 panic("x2apic enabled by bios. But IR enabling failed");
1361 apic_ops
= &x2apic_ops
;
1367 * IR enabling failed
1369 restore_IO_APIC_setup();
1371 reinit_intr_remapped_IO_APIC(x2apic_preenabled
);
1374 local_irq_restore(flags
);
1377 if (!x2apic_preenabled
)
1379 "Enabled x2apic and interrupt-remapping\n");
1382 "Enabled Interrupt-remapping\n");
1385 "Failed to enable Interrupt-remapping and x2apic\n");
1387 if (!cpu_has_x2apic
)
1390 if (x2apic_preenabled
)
1391 panic("x2apic enabled prior OS handover,"
1392 " enable CONFIG_INTR_REMAP");
1394 printk(KERN_INFO
"Enable CONFIG_INTR_REMAP for enabling intr-remapping "
1400 #endif /* HAVE_X2APIC */
1402 #ifdef CONFIG_X86_64
1404 * Detect and enable local APICs on non-SMP boards.
1405 * Original code written by Keir Fraser.
1406 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1407 * not correctly set up (usually the APIC timer won't work etc.)
1409 static int __init
detect_init_APIC(void)
1411 if (!cpu_has_apic
) {
1412 printk(KERN_INFO
"No local APIC present\n");
1416 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
1417 boot_cpu_physical_apicid
= 0;
1422 * Detect and initialize APIC
1424 static int __init
detect_init_APIC(void)
1428 /* Disabled by kernel option? */
1432 switch (boot_cpu_data
.x86_vendor
) {
1433 case X86_VENDOR_AMD
:
1434 if ((boot_cpu_data
.x86
== 6 && boot_cpu_data
.x86_model
> 1) ||
1435 (boot_cpu_data
.x86
== 15))
1438 case X86_VENDOR_INTEL
:
1439 if (boot_cpu_data
.x86
== 6 || boot_cpu_data
.x86
== 15 ||
1440 (boot_cpu_data
.x86
== 5 && cpu_has_apic
))
1447 if (!cpu_has_apic
) {
1449 * Over-ride BIOS and try to enable the local APIC only if
1450 * "lapic" specified.
1452 if (!force_enable_local_apic
) {
1453 printk(KERN_INFO
"Local APIC disabled by BIOS -- "
1454 "you can enable it with \"lapic\"\n");
1458 * Some BIOSes disable the local APIC in the APIC_BASE
1459 * MSR. This can only be done in software for Intel P6 or later
1460 * and AMD K7 (Model > 1) or later.
1462 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1463 if (!(l
& MSR_IA32_APICBASE_ENABLE
)) {
1465 "Local APIC disabled by BIOS -- reenabling.\n");
1466 l
&= ~MSR_IA32_APICBASE_BASE
;
1467 l
|= MSR_IA32_APICBASE_ENABLE
| APIC_DEFAULT_PHYS_BASE
;
1468 wrmsr(MSR_IA32_APICBASE
, l
, h
);
1469 enabled_via_apicbase
= 1;
1473 * The APIC feature bit should now be enabled
1476 features
= cpuid_edx(1);
1477 if (!(features
& (1 << X86_FEATURE_APIC
))) {
1478 printk(KERN_WARNING
"Could not enable APIC!\n");
1481 set_cpu_cap(&boot_cpu_data
, X86_FEATURE_APIC
);
1482 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
1484 /* The BIOS may have set up the APIC at some other address */
1485 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1486 if (l
& MSR_IA32_APICBASE_ENABLE
)
1487 mp_lapic_addr
= l
& MSR_IA32_APICBASE_BASE
;
1489 printk(KERN_INFO
"Found and enabled local APIC!\n");
1496 printk(KERN_INFO
"No local APIC present or hardware disabled\n");
1501 #ifdef CONFIG_X86_64
1502 void __init
early_init_lapic_mapping(void)
1504 unsigned long phys_addr
;
1507 * If no local APIC can be found then go out
1508 * : it means there is no mpatable and MADT
1510 if (!smp_found_config
)
1513 phys_addr
= mp_lapic_addr
;
1515 set_fixmap_nocache(FIX_APIC_BASE
, phys_addr
);
1516 apic_printk(APIC_VERBOSE
, "mapped APIC to %16lx (%16lx)\n",
1517 APIC_BASE
, phys_addr
);
1520 * Fetch the APIC ID of the BSP in case we have a
1521 * default configuration (or the MP table is broken).
1523 boot_cpu_physical_apicid
= read_apic_id();
1528 * init_apic_mappings - initialize APIC mappings
1530 void __init
init_apic_mappings(void)
1534 boot_cpu_physical_apicid
= read_apic_id();
1540 * If no local APIC can be found then set up a fake all
1541 * zeroes page to simulate the local APIC and another
1542 * one for the IO-APIC.
1544 if (!smp_found_config
&& detect_init_APIC()) {
1545 apic_phys
= (unsigned long) alloc_bootmem_pages(PAGE_SIZE
);
1546 apic_phys
= __pa(apic_phys
);
1548 apic_phys
= mp_lapic_addr
;
1550 set_fixmap_nocache(FIX_APIC_BASE
, apic_phys
);
1551 apic_printk(APIC_VERBOSE
, "mapped APIC to %16lx (%16lx)\n",
1552 APIC_BASE
, apic_phys
);
1555 * Fetch the APIC ID of the BSP in case we have a
1556 * default configuration (or the MP table is broken).
1558 if (boot_cpu_physical_apicid
== -1U)
1559 boot_cpu_physical_apicid
= read_apic_id();
1563 * This initializes the IO-APIC and APIC hardware if this is
1566 int apic_version
[MAX_APICS
];
1568 int __init
APIC_init_uniprocessor(void)
1570 #ifdef CONFIG_X86_64
1572 printk(KERN_INFO
"Apic disabled\n");
1575 if (!cpu_has_apic
) {
1577 printk(KERN_INFO
"Apic disabled by BIOS\n");
1581 if (!smp_found_config
&& !cpu_has_apic
)
1585 * Complain if the BIOS pretends there is one.
1587 if (!cpu_has_apic
&&
1588 APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
])) {
1589 printk(KERN_ERR
"BIOS bug, local APIC #%d not detected!...\n",
1590 boot_cpu_physical_apicid
);
1591 clear_cpu_cap(&boot_cpu_data
, X86_FEATURE_APIC
);
1599 #ifdef CONFIG_X86_64
1600 setup_apic_routing();
1603 verify_local_APIC();
1606 #ifdef CONFIG_X86_64
1607 apic_write(APIC_ID
, SET_APIC_ID(boot_cpu_physical_apicid
));
1610 * Hack: In case of kdump, after a crash, kernel might be booting
1611 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
1612 * might be zero if read from MP tables. Get it from LAPIC.
1614 # ifdef CONFIG_CRASH_DUMP
1615 boot_cpu_physical_apicid
= read_apic_id();
1618 physid_set_mask_of_physid(boot_cpu_physical_apicid
, &phys_cpu_present_map
);
1621 #ifdef CONFIG_X86_64
1623 * Now enable IO-APICs, actually call clear_IO_APIC
1624 * We need clear_IO_APIC before enabling vector on BP
1626 if (!skip_ioapic_setup
&& nr_ioapics
)
1630 #ifdef CONFIG_X86_IO_APIC
1631 if (!smp_found_config
|| skip_ioapic_setup
|| !nr_ioapics
)
1633 localise_nmi_watchdog();
1634 end_local_APIC_setup();
1636 #ifdef CONFIG_X86_IO_APIC
1637 if (smp_found_config
&& !skip_ioapic_setup
&& nr_ioapics
)
1639 # ifdef CONFIG_X86_64
1645 #ifdef CONFIG_X86_64
1646 setup_boot_APIC_clock();
1647 check_nmi_watchdog();
1656 * Local APIC interrupts
1660 * This interrupt should _never_ happen with our APIC/SMP architecture
1662 void smp_spurious_interrupt(struct pt_regs
*regs
)
1666 #ifdef CONFIG_X86_64
1671 * Check if this really is a spurious interrupt and ACK it
1672 * if it is a vectored one. Just in case...
1673 * Spurious interrupts should not be ACKed.
1675 v
= apic_read(APIC_ISR
+ ((SPURIOUS_APIC_VECTOR
& ~0x1f) >> 1));
1676 if (v
& (1 << (SPURIOUS_APIC_VECTOR
& 0x1f)))
1679 #ifdef CONFIG_X86_64
1680 add_pda(irq_spurious_count
, 1);
1682 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1683 printk(KERN_INFO
"spurious APIC interrupt on CPU#%d, "
1684 "should never happen.\n", smp_processor_id());
1685 __get_cpu_var(irq_stat
).irq_spurious_count
++;
1691 * This interrupt should never happen with our APIC/SMP architecture
1693 void smp_error_interrupt(struct pt_regs
*regs
)
1697 #ifdef CONFIG_X86_64
1701 /* First tickle the hardware, only then report what went on. -- REW */
1702 v
= apic_read(APIC_ESR
);
1703 apic_write(APIC_ESR
, 0);
1704 v1
= apic_read(APIC_ESR
);
1706 atomic_inc(&irq_err_count
);
1708 /* Here is what the APIC error bits mean:
1711 2: Send accept error
1712 3: Receive accept error
1714 5: Send illegal vector
1715 6: Received illegal vector
1716 7: Illegal register address
1718 printk(KERN_DEBUG
"APIC error on CPU%d: %02x(%02x)\n",
1719 smp_processor_id(), v
, v1
);
1724 * connect_bsp_APIC - attach the APIC to the interrupt system
1726 void __init
connect_bsp_APIC(void)
1728 #ifdef CONFIG_X86_32
1731 * Do not trust the local APIC being empty at bootup.
1735 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
1736 * local APIC to INT and NMI lines.
1738 apic_printk(APIC_VERBOSE
, "leaving PIC mode, "
1739 "enabling APIC mode.\n");
1748 * disconnect_bsp_APIC - detach the APIC from the interrupt system
1749 * @virt_wire_setup: indicates, whether virtual wire mode is selected
1751 * Virtual wire mode is necessary to deliver legacy interrupts even when the
1754 void disconnect_bsp_APIC(int virt_wire_setup
)
1758 #ifdef CONFIG_X86_32
1761 * Put the board back into PIC mode (has an effect only on
1762 * certain older boards). Note that APIC interrupts, including
1763 * IPIs, won't work beyond this point! The only exception are
1766 apic_printk(APIC_VERBOSE
, "disabling APIC mode, "
1767 "entering PIC mode.\n");
1774 /* Go back to Virtual Wire compatibility mode */
1776 /* For the spurious interrupt use vector F, and enable it */
1777 value
= apic_read(APIC_SPIV
);
1778 value
&= ~APIC_VECTOR_MASK
;
1779 value
|= APIC_SPIV_APIC_ENABLED
;
1781 apic_write(APIC_SPIV
, value
);
1783 if (!virt_wire_setup
) {
1785 * For LVT0 make it edge triggered, active high,
1786 * external and enabled
1788 value
= apic_read(APIC_LVT0
);
1789 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1790 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1791 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1792 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1793 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_EXTINT
);
1794 apic_write(APIC_LVT0
, value
);
1797 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
1801 * For LVT1 make it edge triggered, active high,
1804 value
= apic_read(APIC_LVT1
);
1805 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1806 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1807 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1808 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1809 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_NMI
);
1810 apic_write(APIC_LVT1
, value
);
1813 void __cpuinit
generic_processor_info(int apicid
, int version
)
1821 if (version
== 0x0) {
1822 printk(KERN_WARNING
"BIOS bug, APIC version is 0 for CPU#%d! "
1823 "fixing up to 0x10. (tell your hw vendor)\n",
1827 apic_version
[apicid
] = version
;
1829 if (num_processors
>= NR_CPUS
) {
1830 printk(KERN_WARNING
"WARNING: NR_CPUS limit of %i reached."
1831 " Processor ignored.\n", NR_CPUS
);
1836 cpus_complement(tmp_map
, cpu_present_map
);
1837 cpu
= first_cpu(tmp_map
);
1839 physid_set(apicid
, phys_cpu_present_map
);
1840 if (apicid
== boot_cpu_physical_apicid
) {
1842 * x86_bios_cpu_apicid is required to have processors listed
1843 * in same order as logical cpu numbers. Hence the first
1844 * entry is BSP, and so on.
1848 if (apicid
> max_physical_apicid
)
1849 max_physical_apicid
= apicid
;
1851 #ifdef CONFIG_X86_32
1853 * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y
1854 * but we need to work other dependencies like SMP_SUSPEND etc
1855 * before this can be done without some confusion.
1856 * if (CPU_HOTPLUG_ENABLED || num_processors > 8)
1857 * - Ashok Raj <ashok.raj@intel.com>
1859 if (max_physical_apicid
>= 8) {
1860 switch (boot_cpu_data
.x86_vendor
) {
1861 case X86_VENDOR_INTEL
:
1862 if (!APIC_XAPIC(version
)) {
1866 /* If P4 and above fall through */
1867 case X86_VENDOR_AMD
:
1873 #if defined(CONFIG_X86_SMP) || defined(CONFIG_X86_64)
1874 /* are we being called early in kernel startup? */
1875 if (early_per_cpu_ptr(x86_cpu_to_apicid
)) {
1876 u16
*cpu_to_apicid
= early_per_cpu_ptr(x86_cpu_to_apicid
);
1877 u16
*bios_cpu_apicid
= early_per_cpu_ptr(x86_bios_cpu_apicid
);
1879 cpu_to_apicid
[cpu
] = apicid
;
1880 bios_cpu_apicid
[cpu
] = apicid
;
1882 per_cpu(x86_cpu_to_apicid
, cpu
) = apicid
;
1883 per_cpu(x86_bios_cpu_apicid
, cpu
) = apicid
;
1887 cpu_set(cpu
, cpu_possible_map
);
1888 cpu_set(cpu
, cpu_present_map
);
1891 #ifdef CONFIG_X86_64
1892 int hard_smp_processor_id(void)
1894 return read_apic_id();
1905 * 'active' is true if the local APIC was enabled by us and
1906 * not the BIOS; this signifies that we are also responsible
1907 * for disabling it before entering apm/acpi suspend
1910 /* r/w apic fields */
1911 unsigned int apic_id
;
1912 unsigned int apic_taskpri
;
1913 unsigned int apic_ldr
;
1914 unsigned int apic_dfr
;
1915 unsigned int apic_spiv
;
1916 unsigned int apic_lvtt
;
1917 unsigned int apic_lvtpc
;
1918 unsigned int apic_lvt0
;
1919 unsigned int apic_lvt1
;
1920 unsigned int apic_lvterr
;
1921 unsigned int apic_tmict
;
1922 unsigned int apic_tdcr
;
1923 unsigned int apic_thmr
;
1926 static int lapic_suspend(struct sys_device
*dev
, pm_message_t state
)
1928 unsigned long flags
;
1931 if (!apic_pm_state
.active
)
1934 maxlvt
= lapic_get_maxlvt();
1936 apic_pm_state
.apic_id
= apic_read(APIC_ID
);
1937 apic_pm_state
.apic_taskpri
= apic_read(APIC_TASKPRI
);
1938 apic_pm_state
.apic_ldr
= apic_read(APIC_LDR
);
1939 apic_pm_state
.apic_dfr
= apic_read(APIC_DFR
);
1940 apic_pm_state
.apic_spiv
= apic_read(APIC_SPIV
);
1941 apic_pm_state
.apic_lvtt
= apic_read(APIC_LVTT
);
1943 apic_pm_state
.apic_lvtpc
= apic_read(APIC_LVTPC
);
1944 apic_pm_state
.apic_lvt0
= apic_read(APIC_LVT0
);
1945 apic_pm_state
.apic_lvt1
= apic_read(APIC_LVT1
);
1946 apic_pm_state
.apic_lvterr
= apic_read(APIC_LVTERR
);
1947 apic_pm_state
.apic_tmict
= apic_read(APIC_TMICT
);
1948 apic_pm_state
.apic_tdcr
= apic_read(APIC_TDCR
);
1949 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
1951 apic_pm_state
.apic_thmr
= apic_read(APIC_LVTTHMR
);
1954 local_irq_save(flags
);
1955 disable_local_APIC();
1956 local_irq_restore(flags
);
1960 static int lapic_resume(struct sys_device
*dev
)
1963 unsigned long flags
;
1966 if (!apic_pm_state
.active
)
1969 maxlvt
= lapic_get_maxlvt();
1971 local_irq_save(flags
);
1980 * Make sure the APICBASE points to the right address
1982 * FIXME! This will be wrong if we ever support suspend on
1983 * SMP! We'll need to do this as part of the CPU restore!
1985 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1986 l
&= ~MSR_IA32_APICBASE_BASE
;
1987 l
|= MSR_IA32_APICBASE_ENABLE
| mp_lapic_addr
;
1988 wrmsr(MSR_IA32_APICBASE
, l
, h
);
1991 apic_write(APIC_LVTERR
, ERROR_APIC_VECTOR
| APIC_LVT_MASKED
);
1992 apic_write(APIC_ID
, apic_pm_state
.apic_id
);
1993 apic_write(APIC_DFR
, apic_pm_state
.apic_dfr
);
1994 apic_write(APIC_LDR
, apic_pm_state
.apic_ldr
);
1995 apic_write(APIC_TASKPRI
, apic_pm_state
.apic_taskpri
);
1996 apic_write(APIC_SPIV
, apic_pm_state
.apic_spiv
);
1997 apic_write(APIC_LVT0
, apic_pm_state
.apic_lvt0
);
1998 apic_write(APIC_LVT1
, apic_pm_state
.apic_lvt1
);
1999 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
2001 apic_write(APIC_LVTTHMR
, apic_pm_state
.apic_thmr
);
2004 apic_write(APIC_LVTPC
, apic_pm_state
.apic_lvtpc
);
2005 apic_write(APIC_LVTT
, apic_pm_state
.apic_lvtt
);
2006 apic_write(APIC_TDCR
, apic_pm_state
.apic_tdcr
);
2007 apic_write(APIC_TMICT
, apic_pm_state
.apic_tmict
);
2008 apic_write(APIC_ESR
, 0);
2009 apic_read(APIC_ESR
);
2010 apic_write(APIC_LVTERR
, apic_pm_state
.apic_lvterr
);
2011 apic_write(APIC_ESR
, 0);
2012 apic_read(APIC_ESR
);
2014 local_irq_restore(flags
);
2020 * This device has no shutdown method - fully functioning local APICs
2021 * are needed on every CPU up until machine_halt/restart/poweroff.
2024 static struct sysdev_class lapic_sysclass
= {
2026 .resume
= lapic_resume
,
2027 .suspend
= lapic_suspend
,
2030 static struct sys_device device_lapic
= {
2032 .cls
= &lapic_sysclass
,
2035 static void __cpuinit
apic_pm_activate(void)
2037 apic_pm_state
.active
= 1;
2040 static int __init
init_lapic_sysfs(void)
2046 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
2048 error
= sysdev_class_register(&lapic_sysclass
);
2050 error
= sysdev_register(&device_lapic
);
2053 device_initcall(init_lapic_sysfs
);
2055 #else /* CONFIG_PM */
2057 static void apic_pm_activate(void) { }
2059 #endif /* CONFIG_PM */
2061 #ifdef CONFIG_X86_64
2063 * apic_is_clustered_box() -- Check if we can expect good TSC
2065 * Thus far, the major user of this is IBM's Summit2 series:
2067 * Clustered boxes may have unsynced TSC problems if they are
2068 * multi-chassis. Use available data to take a good guess.
2069 * If in doubt, go HPET.
2071 __cpuinit
int apic_is_clustered_box(void)
2073 int i
, clusters
, zeros
;
2075 u16
*bios_cpu_apicid
;
2076 DECLARE_BITMAP(clustermap
, NUM_APIC_CLUSTERS
);
2079 * there is not this kind of box with AMD CPU yet.
2080 * Some AMD box with quadcore cpu and 8 sockets apicid
2081 * will be [4, 0x23] or [8, 0x27] could be thought to
2082 * vsmp box still need checking...
2084 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
) && !is_vsmp_box())
2087 bios_cpu_apicid
= early_per_cpu_ptr(x86_bios_cpu_apicid
);
2088 bitmap_zero(clustermap
, NUM_APIC_CLUSTERS
);
2090 for (i
= 0; i
< NR_CPUS
; i
++) {
2091 /* are we being called early in kernel startup? */
2092 if (bios_cpu_apicid
) {
2093 id
= bios_cpu_apicid
[i
];
2095 else if (i
< nr_cpu_ids
) {
2097 id
= per_cpu(x86_bios_cpu_apicid
, i
);
2104 if (id
!= BAD_APICID
)
2105 __set_bit(APIC_CLUSTERID(id
), clustermap
);
2108 /* Problem: Partially populated chassis may not have CPUs in some of
2109 * the APIC clusters they have been allocated. Only present CPUs have
2110 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap.
2111 * Since clusters are allocated sequentially, count zeros only if
2112 * they are bounded by ones.
2116 for (i
= 0; i
< NUM_APIC_CLUSTERS
; i
++) {
2117 if (test_bit(i
, clustermap
)) {
2118 clusters
+= 1 + zeros
;
2124 /* ScaleMP vSMPowered boxes have one cluster per board and TSCs are
2125 * not guaranteed to be synced between boards
2127 if (is_vsmp_box() && clusters
> 1)
2131 * If clusters > 2, then should be multi-chassis.
2132 * May have to revisit this when multi-core + hyperthreaded CPUs come
2133 * out, but AFAIK this will work even for them.
2135 return (clusters
> 2);
2140 * APIC command line parameters
2142 static int __init
setup_disableapic(char *arg
)
2145 setup_clear_cpu_cap(X86_FEATURE_APIC
);
2148 early_param("disableapic", setup_disableapic
);
2150 /* same as disableapic, for compatibility */
2151 static int __init
setup_nolapic(char *arg
)
2153 return setup_disableapic(arg
);
2155 early_param("nolapic", setup_nolapic
);
2157 static int __init
parse_lapic_timer_c2_ok(char *arg
)
2159 local_apic_timer_c2_ok
= 1;
2162 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok
);
2164 static int __init
parse_disable_apic_timer(char *arg
)
2166 disable_apic_timer
= 1;
2169 early_param("noapictimer", parse_disable_apic_timer
);
2171 static int __init
parse_nolapic_timer(char *arg
)
2173 disable_apic_timer
= 1;
2176 early_param("nolapic_timer", parse_nolapic_timer
);
2178 static int __init
apic_set_verbosity(char *arg
)
2181 #ifdef CONFIG_X86_64
2182 skip_ioapic_setup
= 0;
2188 if (strcmp("debug", arg
) == 0)
2189 apic_verbosity
= APIC_DEBUG
;
2190 else if (strcmp("verbose", arg
) == 0)
2191 apic_verbosity
= APIC_VERBOSE
;
2193 printk(KERN_WARNING
"APIC Verbosity level %s not recognised"
2194 " use apic=verbose or apic=debug\n", arg
);
2200 early_param("apic", apic_set_verbosity
);
2202 static int __init
lapic_insert_resource(void)
2207 /* Put local APIC into the resource map. */
2208 lapic_resource
.start
= apic_phys
;
2209 lapic_resource
.end
= lapic_resource
.start
+ PAGE_SIZE
- 1;
2210 insert_resource(&iomem_resource
, &lapic_resource
);
2216 * need call insert after e820_reserve_resources()
2217 * that is using request_resource
2219 late_initcall(lapic_insert_resource
);