2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/bootmem.h>
22 #include <linux/interrupt.h>
23 #include <linux/mc146818rtc.h>
24 #include <linux/kernel_stat.h>
25 #include <linux/sysdev.h>
26 #include <linux/ioport.h>
27 #include <linux/cpu.h>
28 #include <linux/clockchips.h>
29 #include <linux/acpi_pmtmr.h>
30 #include <linux/module.h>
31 #include <linux/dmi.h>
32 #include <linux/dmar.h>
33 #include <linux/ftrace.h>
35 #include <asm/atomic.h>
38 #include <asm/mpspec.h>
40 #include <asm/arch_hooks.h>
42 #include <asm/pgalloc.h>
43 #include <asm/i8253.h>
46 #include <asm/proto.h>
47 #include <asm/timex.h>
49 #include <asm/i8259.h>
51 #include <mach_apic.h>
52 #include <mach_apicdef.h>
58 #if ((SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F)
59 # error SPURIOUS_APIC_VECTOR definition error
64 * Knob to control our willingness to enable the local APIC.
68 static int force_enable_local_apic
;
70 * APIC command line parameters
72 static int __init
parse_lapic(char *arg
)
74 force_enable_local_apic
= 1;
77 early_param("lapic", parse_lapic
);
78 /* Local APIC was disabled by the BIOS and enabled by the kernel */
79 static int enabled_via_apicbase
;
84 static int apic_calibrate_pmtmr __initdata
;
85 static __init
int setup_apicpmtimer(char *s
)
87 apic_calibrate_pmtmr
= 1;
91 __setup("apicpmtimer", setup_apicpmtimer
);
100 /* x2apic enabled before OS handover */
101 static int x2apic_preenabled
;
102 static int disable_x2apic
;
103 static __init
int setup_nox2apic(char *str
)
106 setup_clear_cpu_cap(X86_FEATURE_X2APIC
);
109 early_param("nox2apic", setup_nox2apic
);
112 unsigned long mp_lapic_addr
;
114 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
115 static int disable_apic_timer __cpuinitdata
;
116 /* Local APIC timer works in C2 */
117 int local_apic_timer_c2_ok
;
118 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok
);
120 int first_system_vector
= 0xfe;
123 * Debug level, exported for io_apic.c
125 unsigned int apic_verbosity
;
129 /* Have we found an MP table */
130 int smp_found_config
;
132 static struct resource lapic_resource
= {
133 .name
= "Local APIC",
134 .flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
,
137 static unsigned int calibration_result
;
139 static int lapic_next_event(unsigned long delta
,
140 struct clock_event_device
*evt
);
141 static void lapic_timer_setup(enum clock_event_mode mode
,
142 struct clock_event_device
*evt
);
143 static void lapic_timer_broadcast(const struct cpumask
*mask
);
144 static void apic_pm_activate(void);
147 * The local apic timer can be used for any function which is CPU local.
149 static struct clock_event_device lapic_clockevent
= {
151 .features
= CLOCK_EVT_FEAT_PERIODIC
| CLOCK_EVT_FEAT_ONESHOT
152 | CLOCK_EVT_FEAT_C3STOP
| CLOCK_EVT_FEAT_DUMMY
,
154 .set_mode
= lapic_timer_setup
,
155 .set_next_event
= lapic_next_event
,
156 .broadcast
= lapic_timer_broadcast
,
160 static DEFINE_PER_CPU(struct clock_event_device
, lapic_events
);
162 static unsigned long apic_phys
;
165 * Get the LAPIC version
167 static inline int lapic_get_version(void)
169 return GET_APIC_VERSION(apic_read(APIC_LVR
));
173 * Check, if the APIC is integrated or a separate chip
175 static inline int lapic_is_integrated(void)
180 return APIC_INTEGRATED(lapic_get_version());
185 * Check, whether this is a modern or a first generation APIC
187 static int modern_apic(void)
189 /* AMD systems use old APIC versions, so check the CPU */
190 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
&&
191 boot_cpu_data
.x86
>= 0xf)
193 return lapic_get_version() >= 0x14;
197 * Paravirt kernels also might be using these below ops. So we still
198 * use generic apic_read()/apic_write(), which might be pointing to different
199 * ops in PARAVIRT case.
201 void xapic_wait_icr_idle(void)
203 while (apic_read(APIC_ICR
) & APIC_ICR_BUSY
)
207 u32
safe_xapic_wait_icr_idle(void)
214 send_status
= apic_read(APIC_ICR
) & APIC_ICR_BUSY
;
218 } while (timeout
++ < 1000);
223 void xapic_icr_write(u32 low
, u32 id
)
225 apic_write(APIC_ICR2
, SET_APIC_DEST_FIELD(id
));
226 apic_write(APIC_ICR
, low
);
229 static u64
xapic_icr_read(void)
233 icr2
= apic_read(APIC_ICR2
);
234 icr1
= apic_read(APIC_ICR
);
236 return icr1
| ((u64
)icr2
<< 32);
239 static struct apic_ops xapic_ops
= {
240 .read
= native_apic_mem_read
,
241 .write
= native_apic_mem_write
,
242 .icr_read
= xapic_icr_read
,
243 .icr_write
= xapic_icr_write
,
244 .wait_icr_idle
= xapic_wait_icr_idle
,
245 .safe_wait_icr_idle
= safe_xapic_wait_icr_idle
,
248 struct apic_ops __read_mostly
*apic_ops
= &xapic_ops
;
249 EXPORT_SYMBOL_GPL(apic_ops
);
252 static void x2apic_wait_icr_idle(void)
254 /* no need to wait for icr idle in x2apic */
258 static u32
safe_x2apic_wait_icr_idle(void)
260 /* no need to wait for icr idle in x2apic */
264 void x2apic_icr_write(u32 low
, u32 id
)
266 wrmsrl(APIC_BASE_MSR
+ (APIC_ICR
>> 4), ((__u64
) id
) << 32 | low
);
269 static u64
x2apic_icr_read(void)
273 rdmsrl(APIC_BASE_MSR
+ (APIC_ICR
>> 4), val
);
277 static struct apic_ops x2apic_ops
= {
278 .read
= native_apic_msr_read
,
279 .write
= native_apic_msr_write
,
280 .icr_read
= x2apic_icr_read
,
281 .icr_write
= x2apic_icr_write
,
282 .wait_icr_idle
= x2apic_wait_icr_idle
,
283 .safe_wait_icr_idle
= safe_x2apic_wait_icr_idle
,
288 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
290 void __cpuinit
enable_NMI_through_LVT0(void)
294 /* unmask and set to NMI */
297 /* Level triggered for 82489DX (32bit mode) */
298 if (!lapic_is_integrated())
299 v
|= APIC_LVT_LEVEL_TRIGGER
;
301 apic_write(APIC_LVT0
, v
);
306 * get_physical_broadcast - Get number of physical broadcast IDs
308 int get_physical_broadcast(void)
310 return modern_apic() ? 0xff : 0xf;
315 * lapic_get_maxlvt - get the maximum number of local vector table entries
317 int lapic_get_maxlvt(void)
321 v
= apic_read(APIC_LVR
);
323 * - we always have APIC integrated on 64bit mode
324 * - 82489DXs do not report # of LVT entries
326 return APIC_INTEGRATED(GET_APIC_VERSION(v
)) ? GET_APIC_MAXLVT(v
) : 2;
334 #define APIC_DIVISOR 16
337 * This function sets up the local APIC timer, with a timeout of
338 * 'clocks' APIC bus clock. During calibration we actually call
339 * this function twice on the boot CPU, once with a bogus timeout
340 * value, second time for real. The other (noncalibrating) CPUs
341 * call this function only once, with the real, calibrated value.
343 * We do reads before writes even if unnecessary, to get around the
344 * P5 APIC double write bug.
346 static void __setup_APIC_LVTT(unsigned int clocks
, int oneshot
, int irqen
)
348 unsigned int lvtt_value
, tmp_value
;
350 lvtt_value
= LOCAL_TIMER_VECTOR
;
352 lvtt_value
|= APIC_LVT_TIMER_PERIODIC
;
353 if (!lapic_is_integrated())
354 lvtt_value
|= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV
);
357 lvtt_value
|= APIC_LVT_MASKED
;
359 apic_write(APIC_LVTT
, lvtt_value
);
364 tmp_value
= apic_read(APIC_TDCR
);
365 apic_write(APIC_TDCR
,
366 (tmp_value
& ~(APIC_TDR_DIV_1
| APIC_TDR_DIV_TMBASE
)) |
370 apic_write(APIC_TMICT
, clocks
/ APIC_DIVISOR
);
374 * Setup extended LVT, AMD specific (K8, family 10h)
376 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
377 * MCE interrupts are supported. Thus MCE offset must be set to 0.
379 * If mask=1, the LVT entry does not generate interrupts while mask=0
380 * enables the vector. See also the BKDGs.
383 #define APIC_EILVT_LVTOFF_MCE 0
384 #define APIC_EILVT_LVTOFF_IBS 1
386 static void setup_APIC_eilvt(u8 lvt_off
, u8 vector
, u8 msg_type
, u8 mask
)
388 unsigned long reg
= (lvt_off
<< 4) + APIC_EILVT0
;
389 unsigned int v
= (mask
<< 16) | (msg_type
<< 8) | vector
;
394 u8
setup_APIC_eilvt_mce(u8 vector
, u8 msg_type
, u8 mask
)
396 setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE
, vector
, msg_type
, mask
);
397 return APIC_EILVT_LVTOFF_MCE
;
400 u8
setup_APIC_eilvt_ibs(u8 vector
, u8 msg_type
, u8 mask
)
402 setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS
, vector
, msg_type
, mask
);
403 return APIC_EILVT_LVTOFF_IBS
;
405 EXPORT_SYMBOL_GPL(setup_APIC_eilvt_ibs
);
408 * Program the next event, relative to now
410 static int lapic_next_event(unsigned long delta
,
411 struct clock_event_device
*evt
)
413 apic_write(APIC_TMICT
, delta
);
418 * Setup the lapic timer in periodic or oneshot mode
420 static void lapic_timer_setup(enum clock_event_mode mode
,
421 struct clock_event_device
*evt
)
426 /* Lapic used as dummy for broadcast ? */
427 if (evt
->features
& CLOCK_EVT_FEAT_DUMMY
)
430 local_irq_save(flags
);
433 case CLOCK_EVT_MODE_PERIODIC
:
434 case CLOCK_EVT_MODE_ONESHOT
:
435 __setup_APIC_LVTT(calibration_result
,
436 mode
!= CLOCK_EVT_MODE_PERIODIC
, 1);
438 case CLOCK_EVT_MODE_UNUSED
:
439 case CLOCK_EVT_MODE_SHUTDOWN
:
440 v
= apic_read(APIC_LVTT
);
441 v
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
442 apic_write(APIC_LVTT
, v
);
443 apic_write(APIC_TMICT
, 0xffffffff);
445 case CLOCK_EVT_MODE_RESUME
:
446 /* Nothing to do here */
450 local_irq_restore(flags
);
454 * Local APIC timer broadcast function
456 static void lapic_timer_broadcast(const struct cpumask
*mask
)
459 send_IPI_mask(mask
, LOCAL_TIMER_VECTOR
);
464 * Setup the local APIC timer for this CPU. Copy the initilized values
465 * of the boot CPU and register the clock event in the framework.
467 static void __cpuinit
setup_APIC_timer(void)
469 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
471 memcpy(levt
, &lapic_clockevent
, sizeof(*levt
));
472 levt
->cpumask
= cpumask_of(smp_processor_id());
474 clockevents_register_device(levt
);
478 * In this functions we calibrate APIC bus clocks to the external timer.
480 * We want to do the calibration only once since we want to have local timer
481 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
484 * This was previously done by reading the PIT/HPET and waiting for a wrap
485 * around to find out, that a tick has elapsed. I have a box, where the PIT
486 * readout is broken, so it never gets out of the wait loop again. This was
487 * also reported by others.
489 * Monitoring the jiffies value is inaccurate and the clockevents
490 * infrastructure allows us to do a simple substitution of the interrupt
493 * The calibration routine also uses the pm_timer when possible, as the PIT
494 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
495 * back to normal later in the boot process).
498 #define LAPIC_CAL_LOOPS (HZ/10)
500 static __initdata
int lapic_cal_loops
= -1;
501 static __initdata
long lapic_cal_t1
, lapic_cal_t2
;
502 static __initdata
unsigned long long lapic_cal_tsc1
, lapic_cal_tsc2
;
503 static __initdata
unsigned long lapic_cal_pm1
, lapic_cal_pm2
;
504 static __initdata
unsigned long lapic_cal_j1
, lapic_cal_j2
;
507 * Temporary interrupt handler.
509 static void __init
lapic_cal_handler(struct clock_event_device
*dev
)
511 unsigned long long tsc
= 0;
512 long tapic
= apic_read(APIC_TMCCT
);
513 unsigned long pm
= acpi_pm_read_early();
518 switch (lapic_cal_loops
++) {
520 lapic_cal_t1
= tapic
;
521 lapic_cal_tsc1
= tsc
;
523 lapic_cal_j1
= jiffies
;
526 case LAPIC_CAL_LOOPS
:
527 lapic_cal_t2
= tapic
;
528 lapic_cal_tsc2
= tsc
;
529 if (pm
< lapic_cal_pm1
)
530 pm
+= ACPI_PM_OVRRUN
;
532 lapic_cal_j2
= jiffies
;
537 static int __init
calibrate_by_pmtimer(long deltapm
, long *delta
)
539 const long pm_100ms
= PMTMR_TICKS_PER_SEC
/ 10;
540 const long pm_thresh
= pm_100ms
/ 100;
544 #ifndef CONFIG_X86_PM_TIMER
548 apic_printk(APIC_VERBOSE
, "... PM timer delta = %ld\n", deltapm
);
550 /* Check, if the PM timer is available */
554 mult
= clocksource_hz2mult(PMTMR_TICKS_PER_SEC
, 22);
556 if (deltapm
> (pm_100ms
- pm_thresh
) &&
557 deltapm
< (pm_100ms
+ pm_thresh
)) {
558 apic_printk(APIC_VERBOSE
, "... PM timer result ok\n");
560 res
= (((u64
)deltapm
) * mult
) >> 22;
561 do_div(res
, 1000000);
562 pr_warning("APIC calibration not consistent "
563 "with PM Timer: %ldms instead of 100ms\n",
565 /* Correct the lapic counter value */
566 res
= (((u64
)(*delta
)) * pm_100ms
);
567 do_div(res
, deltapm
);
568 pr_info("APIC delta adjusted to PM-Timer: "
569 "%lu (%ld)\n", (unsigned long)res
, *delta
);
576 static int __init
calibrate_APIC_clock(void)
578 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
579 void (*real_handler
)(struct clock_event_device
*dev
);
580 unsigned long deltaj
;
582 int pm_referenced
= 0;
586 /* Replace the global interrupt handler */
587 real_handler
= global_clock_event
->event_handler
;
588 global_clock_event
->event_handler
= lapic_cal_handler
;
591 * Setup the APIC counter to maximum. There is no way the lapic
592 * can underflow in the 100ms detection time frame
594 __setup_APIC_LVTT(0xffffffff, 0, 0);
596 /* Let the interrupts run */
599 while (lapic_cal_loops
<= LAPIC_CAL_LOOPS
)
604 /* Restore the real event handler */
605 global_clock_event
->event_handler
= real_handler
;
607 /* Build delta t1-t2 as apic timer counts down */
608 delta
= lapic_cal_t1
- lapic_cal_t2
;
609 apic_printk(APIC_VERBOSE
, "... lapic delta = %ld\n", delta
);
611 /* we trust the PM based calibration if possible */
612 pm_referenced
= !calibrate_by_pmtimer(lapic_cal_pm2
- lapic_cal_pm1
,
615 /* Calculate the scaled math multiplication factor */
616 lapic_clockevent
.mult
= div_sc(delta
, TICK_NSEC
* LAPIC_CAL_LOOPS
,
617 lapic_clockevent
.shift
);
618 lapic_clockevent
.max_delta_ns
=
619 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent
);
620 lapic_clockevent
.min_delta_ns
=
621 clockevent_delta2ns(0xF, &lapic_clockevent
);
623 calibration_result
= (delta
* APIC_DIVISOR
) / LAPIC_CAL_LOOPS
;
625 apic_printk(APIC_VERBOSE
, "..... delta %ld\n", delta
);
626 apic_printk(APIC_VERBOSE
, "..... mult: %ld\n", lapic_clockevent
.mult
);
627 apic_printk(APIC_VERBOSE
, "..... calibration result: %u\n",
631 delta
= (long)(lapic_cal_tsc2
- lapic_cal_tsc1
);
632 apic_printk(APIC_VERBOSE
, "..... CPU clock speed is "
634 (delta
/ LAPIC_CAL_LOOPS
) / (1000000 / HZ
),
635 (delta
/ LAPIC_CAL_LOOPS
) % (1000000 / HZ
));
638 apic_printk(APIC_VERBOSE
, "..... host bus clock speed is "
640 calibration_result
/ (1000000 / HZ
),
641 calibration_result
% (1000000 / HZ
));
644 * Do a sanity check on the APIC calibration result
646 if (calibration_result
< (1000000 / HZ
)) {
648 pr_warning("APIC frequency too slow, disabling apic timer\n");
652 levt
->features
&= ~CLOCK_EVT_FEAT_DUMMY
;
655 * PM timer calibration failed or not turned on
656 * so lets try APIC timer based calibration
658 if (!pm_referenced
) {
659 apic_printk(APIC_VERBOSE
, "... verify APIC timer\n");
662 * Setup the apic timer manually
664 levt
->event_handler
= lapic_cal_handler
;
665 lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC
, levt
);
666 lapic_cal_loops
= -1;
668 /* Let the interrupts run */
671 while (lapic_cal_loops
<= LAPIC_CAL_LOOPS
)
674 /* Stop the lapic timer */
675 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, levt
);
678 deltaj
= lapic_cal_j2
- lapic_cal_j1
;
679 apic_printk(APIC_VERBOSE
, "... jiffies delta = %lu\n", deltaj
);
681 /* Check, if the jiffies result is consistent */
682 if (deltaj
>= LAPIC_CAL_LOOPS
-2 && deltaj
<= LAPIC_CAL_LOOPS
+2)
683 apic_printk(APIC_VERBOSE
, "... jiffies result ok\n");
685 levt
->features
|= CLOCK_EVT_FEAT_DUMMY
;
689 if (levt
->features
& CLOCK_EVT_FEAT_DUMMY
) {
690 pr_warning("APIC timer disabled due to verification failure.\n");
698 * Setup the boot APIC
700 * Calibrate and verify the result.
702 void __init
setup_boot_APIC_clock(void)
705 * The local apic timer can be disabled via the kernel
706 * commandline or from the CPU detection code. Register the lapic
707 * timer as a dummy clock event source on SMP systems, so the
708 * broadcast mechanism is used. On UP systems simply ignore it.
710 if (disable_apic_timer
) {
711 pr_info("Disabling APIC timer\n");
712 /* No broadcast on UP ! */
713 if (num_possible_cpus() > 1) {
714 lapic_clockevent
.mult
= 1;
720 apic_printk(APIC_VERBOSE
, "Using local APIC timer interrupts.\n"
721 "calibrating APIC timer ...\n");
723 if (calibrate_APIC_clock()) {
724 /* No broadcast on UP ! */
725 if (num_possible_cpus() > 1)
731 * If nmi_watchdog is set to IO_APIC, we need the
732 * PIT/HPET going. Otherwise register lapic as a dummy
735 if (nmi_watchdog
!= NMI_IO_APIC
)
736 lapic_clockevent
.features
&= ~CLOCK_EVT_FEAT_DUMMY
;
738 pr_warning("APIC timer registered as dummy,"
739 " due to nmi_watchdog=%d!\n", nmi_watchdog
);
741 /* Setup the lapic or request the broadcast */
745 void __cpuinit
setup_secondary_APIC_clock(void)
751 * The guts of the apic timer interrupt
753 static void local_apic_timer_interrupt(void)
755 int cpu
= smp_processor_id();
756 struct clock_event_device
*evt
= &per_cpu(lapic_events
, cpu
);
759 * Normally we should not be here till LAPIC has been initialized but
760 * in some cases like kdump, its possible that there is a pending LAPIC
761 * timer interrupt from previous kernel's context and is delivered in
762 * new kernel the moment interrupts are enabled.
764 * Interrupts are enabled early and LAPIC is setup much later, hence
765 * its possible that when we get here evt->event_handler is NULL.
766 * Check for event_handler being NULL and discard the interrupt as
769 if (!evt
->event_handler
) {
770 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu
);
772 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, evt
);
777 * the NMI deadlock-detector uses this.
779 inc_irq_stat(apic_timer_irqs
);
781 evt
->event_handler(evt
);
785 * Local APIC timer interrupt. This is the most natural way for doing
786 * local interrupts, but local timer interrupts can be emulated by
787 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
789 * [ if a single-CPU system runs an SMP kernel then we call the local
790 * interrupt as well. Thus we cannot inline the local irq ... ]
792 void __irq_entry
smp_apic_timer_interrupt(struct pt_regs
*regs
)
794 struct pt_regs
*old_regs
= set_irq_regs(regs
);
797 * NOTE! We'd better ACK the irq immediately,
798 * because timer handling can be slow.
802 * update_process_times() expects us to have done irq_enter().
803 * Besides, if we don't timer interrupts ignore the global
804 * interrupt lock, which is the WrongThing (tm) to do.
808 local_apic_timer_interrupt();
811 set_irq_regs(old_regs
);
814 int setup_profiling_timer(unsigned int multiplier
)
820 * Local APIC start and shutdown
824 * clear_local_APIC - shutdown the local APIC
826 * This is called, when a CPU is disabled and before rebooting, so the state of
827 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
828 * leftovers during boot.
830 void clear_local_APIC(void)
835 /* APIC hasn't been mapped yet */
839 maxlvt
= lapic_get_maxlvt();
841 * Masking an LVT entry can trigger a local APIC error
842 * if the vector is zero. Mask LVTERR first to prevent this.
845 v
= ERROR_APIC_VECTOR
; /* any non-zero vector will do */
846 apic_write(APIC_LVTERR
, v
| APIC_LVT_MASKED
);
849 * Careful: we have to set masks only first to deassert
850 * any level-triggered sources.
852 v
= apic_read(APIC_LVTT
);
853 apic_write(APIC_LVTT
, v
| APIC_LVT_MASKED
);
854 v
= apic_read(APIC_LVT0
);
855 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
856 v
= apic_read(APIC_LVT1
);
857 apic_write(APIC_LVT1
, v
| APIC_LVT_MASKED
);
859 v
= apic_read(APIC_LVTPC
);
860 apic_write(APIC_LVTPC
, v
| APIC_LVT_MASKED
);
863 /* lets not touch this if we didn't frob it */
864 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(X86_MCE_INTEL)
866 v
= apic_read(APIC_LVTTHMR
);
867 apic_write(APIC_LVTTHMR
, v
| APIC_LVT_MASKED
);
871 * Clean APIC state for other OSs:
873 apic_write(APIC_LVTT
, APIC_LVT_MASKED
);
874 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
875 apic_write(APIC_LVT1
, APIC_LVT_MASKED
);
877 apic_write(APIC_LVTERR
, APIC_LVT_MASKED
);
879 apic_write(APIC_LVTPC
, APIC_LVT_MASKED
);
881 /* Integrated APIC (!82489DX) ? */
882 if (lapic_is_integrated()) {
884 /* Clear ESR due to Pentium errata 3AP and 11AP */
885 apic_write(APIC_ESR
, 0);
891 * disable_local_APIC - clear and disable the local APIC
893 void disable_local_APIC(void)
900 * Disable APIC (implies clearing of registers
903 value
= apic_read(APIC_SPIV
);
904 value
&= ~APIC_SPIV_APIC_ENABLED
;
905 apic_write(APIC_SPIV
, value
);
909 * When LAPIC was disabled by the BIOS and enabled by the kernel,
910 * restore the disabled state.
912 if (enabled_via_apicbase
) {
915 rdmsr(MSR_IA32_APICBASE
, l
, h
);
916 l
&= ~MSR_IA32_APICBASE_ENABLE
;
917 wrmsr(MSR_IA32_APICBASE
, l
, h
);
923 * If Linux enabled the LAPIC against the BIOS default disable it down before
924 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
925 * not power-off. Additionally clear all LVT entries before disable_local_APIC
926 * for the case where Linux didn't enable the LAPIC.
928 void lapic_shutdown(void)
935 local_irq_save(flags
);
938 if (!enabled_via_apicbase
)
942 disable_local_APIC();
945 local_irq_restore(flags
);
949 * This is to verify that we're looking at a real local APIC.
950 * Check these against your board if the CPUs aren't getting
951 * started for no apparent reason.
953 int __init
verify_local_APIC(void)
955 unsigned int reg0
, reg1
;
958 * The version register is read-only in a real APIC.
960 reg0
= apic_read(APIC_LVR
);
961 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg0
);
962 apic_write(APIC_LVR
, reg0
^ APIC_LVR_MASK
);
963 reg1
= apic_read(APIC_LVR
);
964 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg1
);
967 * The two version reads above should print the same
968 * numbers. If the second one is different, then we
969 * poke at a non-APIC.
975 * Check if the version looks reasonably.
977 reg1
= GET_APIC_VERSION(reg0
);
978 if (reg1
== 0x00 || reg1
== 0xff)
980 reg1
= lapic_get_maxlvt();
981 if (reg1
< 0x02 || reg1
== 0xff)
985 * The ID register is read/write in a real APIC.
987 reg0
= apic_read(APIC_ID
);
988 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg0
);
989 apic_write(APIC_ID
, reg0
^ APIC_ID_MASK
);
990 reg1
= apic_read(APIC_ID
);
991 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg1
);
992 apic_write(APIC_ID
, reg0
);
993 if (reg1
!= (reg0
^ APIC_ID_MASK
))
997 * The next two are just to see if we have sane values.
998 * They're only really relevant if we're in Virtual Wire
999 * compatibility mode, but most boxes are anymore.
1001 reg0
= apic_read(APIC_LVT0
);
1002 apic_printk(APIC_DEBUG
, "Getting LVT0: %x\n", reg0
);
1003 reg1
= apic_read(APIC_LVT1
);
1004 apic_printk(APIC_DEBUG
, "Getting LVT1: %x\n", reg1
);
1010 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
1012 void __init
sync_Arb_IDs(void)
1015 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
1018 if (modern_apic() || boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
)
1024 apic_wait_icr_idle();
1026 apic_printk(APIC_DEBUG
, "Synchronizing Arb IDs.\n");
1027 apic_write(APIC_ICR
, APIC_DEST_ALLINC
|
1028 APIC_INT_LEVELTRIG
| APIC_DM_INIT
);
1032 * An initial setup of the virtual wire mode.
1034 void __init
init_bsp_APIC(void)
1039 * Don't do the setup now if we have a SMP BIOS as the
1040 * through-I/O-APIC virtual wire mode might be active.
1042 if (smp_found_config
|| !cpu_has_apic
)
1046 * Do not trust the local APIC being empty at bootup.
1053 value
= apic_read(APIC_SPIV
);
1054 value
&= ~APIC_VECTOR_MASK
;
1055 value
|= APIC_SPIV_APIC_ENABLED
;
1057 #ifdef CONFIG_X86_32
1058 /* This bit is reserved on P4/Xeon and should be cleared */
1059 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
) &&
1060 (boot_cpu_data
.x86
== 15))
1061 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
1064 value
|= APIC_SPIV_FOCUS_DISABLED
;
1065 value
|= SPURIOUS_APIC_VECTOR
;
1066 apic_write(APIC_SPIV
, value
);
1069 * Set up the virtual wire mode.
1071 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
1072 value
= APIC_DM_NMI
;
1073 if (!lapic_is_integrated()) /* 82489DX */
1074 value
|= APIC_LVT_LEVEL_TRIGGER
;
1075 apic_write(APIC_LVT1
, value
);
1078 static void __cpuinit
lapic_setup_esr(void)
1080 unsigned int oldvalue
, value
, maxlvt
;
1082 if (!lapic_is_integrated()) {
1083 pr_info("No ESR for 82489DX.\n");
1089 * Something untraceable is creating bad interrupts on
1090 * secondary quads ... for the moment, just leave the
1091 * ESR disabled - we can't do anything useful with the
1092 * errors anyway - mbligh
1094 pr_info("Leaving ESR disabled.\n");
1098 maxlvt
= lapic_get_maxlvt();
1099 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
1100 apic_write(APIC_ESR
, 0);
1101 oldvalue
= apic_read(APIC_ESR
);
1103 /* enables sending errors */
1104 value
= ERROR_APIC_VECTOR
;
1105 apic_write(APIC_LVTERR
, value
);
1108 * spec says clear errors after enabling vector.
1111 apic_write(APIC_ESR
, 0);
1112 value
= apic_read(APIC_ESR
);
1113 if (value
!= oldvalue
)
1114 apic_printk(APIC_VERBOSE
, "ESR value before enabling "
1115 "vector: 0x%08x after: 0x%08x\n",
1121 * setup_local_APIC - setup the local APIC
1123 void __cpuinit
setup_local_APIC(void)
1128 #ifdef CONFIG_X86_32
1129 /* Pound the ESR really hard over the head with a big hammer - mbligh */
1130 if (lapic_is_integrated() && esr_disable
) {
1131 apic_write(APIC_ESR
, 0);
1132 apic_write(APIC_ESR
, 0);
1133 apic_write(APIC_ESR
, 0);
1134 apic_write(APIC_ESR
, 0);
1141 * Double-check whether this APIC is really registered.
1142 * This is meaningless in clustered apic mode, so we skip it.
1144 if (!apic_id_registered())
1148 * Intel recommends to set DFR, LDR and TPR before enabling
1149 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
1150 * document number 292116). So here it goes...
1155 * Set Task Priority to 'accept all'. We never change this
1158 value
= apic_read(APIC_TASKPRI
);
1159 value
&= ~APIC_TPRI_MASK
;
1160 apic_write(APIC_TASKPRI
, value
);
1163 * After a crash, we no longer service the interrupts and a pending
1164 * interrupt from previous kernel might still have ISR bit set.
1166 * Most probably by now CPU has serviced that pending interrupt and
1167 * it might not have done the ack_APIC_irq() because it thought,
1168 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
1169 * does not clear the ISR bit and cpu thinks it has already serivced
1170 * the interrupt. Hence a vector might get locked. It was noticed
1171 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
1173 for (i
= APIC_ISR_NR
- 1; i
>= 0; i
--) {
1174 value
= apic_read(APIC_ISR
+ i
*0x10);
1175 for (j
= 31; j
>= 0; j
--) {
1182 * Now that we are all set up, enable the APIC
1184 value
= apic_read(APIC_SPIV
);
1185 value
&= ~APIC_VECTOR_MASK
;
1189 value
|= APIC_SPIV_APIC_ENABLED
;
1191 #ifdef CONFIG_X86_32
1193 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1194 * certain networking cards. If high frequency interrupts are
1195 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1196 * entry is masked/unmasked at a high rate as well then sooner or
1197 * later IOAPIC line gets 'stuck', no more interrupts are received
1198 * from the device. If focus CPU is disabled then the hang goes
1201 * [ This bug can be reproduced easily with a level-triggered
1202 * PCI Ne2000 networking cards and PII/PIII processors, dual
1206 * Actually disabling the focus CPU check just makes the hang less
1207 * frequent as it makes the interrupt distributon model be more
1208 * like LRU than MRU (the short-term load is more even across CPUs).
1209 * See also the comment in end_level_ioapic_irq(). --macro
1213 * - enable focus processor (bit==0)
1214 * - 64bit mode always use processor focus
1215 * so no need to set it
1217 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
1221 * Set spurious IRQ vector
1223 value
|= SPURIOUS_APIC_VECTOR
;
1224 apic_write(APIC_SPIV
, value
);
1227 * Set up LVT0, LVT1:
1229 * set up through-local-APIC on the BP's LINT0. This is not
1230 * strictly necessary in pure symmetric-IO mode, but sometimes
1231 * we delegate interrupts to the 8259A.
1234 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1236 value
= apic_read(APIC_LVT0
) & APIC_LVT_MASKED
;
1237 if (!smp_processor_id() && (pic_mode
|| !value
)) {
1238 value
= APIC_DM_EXTINT
;
1239 apic_printk(APIC_VERBOSE
, "enabled ExtINT on CPU#%d\n",
1240 smp_processor_id());
1242 value
= APIC_DM_EXTINT
| APIC_LVT_MASKED
;
1243 apic_printk(APIC_VERBOSE
, "masked ExtINT on CPU#%d\n",
1244 smp_processor_id());
1246 apic_write(APIC_LVT0
, value
);
1249 * only the BP should see the LINT1 NMI signal, obviously.
1251 if (!smp_processor_id())
1252 value
= APIC_DM_NMI
;
1254 value
= APIC_DM_NMI
| APIC_LVT_MASKED
;
1255 if (!lapic_is_integrated()) /* 82489DX */
1256 value
|= APIC_LVT_LEVEL_TRIGGER
;
1257 apic_write(APIC_LVT1
, value
);
1262 void __cpuinit
end_local_APIC_setup(void)
1266 #ifdef CONFIG_X86_32
1269 /* Disable the local apic timer */
1270 value
= apic_read(APIC_LVTT
);
1271 value
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
1272 apic_write(APIC_LVTT
, value
);
1276 setup_apic_nmi_watchdog(NULL
);
1281 void check_x2apic(void)
1285 rdmsr(MSR_IA32_APICBASE
, msr
, msr2
);
1287 if (msr
& X2APIC_ENABLE
) {
1288 pr_info("x2apic enabled by BIOS, switching to x2apic ops\n");
1289 x2apic_preenabled
= x2apic
= 1;
1290 apic_ops
= &x2apic_ops
;
1294 void enable_x2apic(void)
1298 rdmsr(MSR_IA32_APICBASE
, msr
, msr2
);
1299 if (!(msr
& X2APIC_ENABLE
)) {
1300 pr_info("Enabling x2apic\n");
1301 wrmsr(MSR_IA32_APICBASE
, msr
| X2APIC_ENABLE
, 0);
1305 void __init
enable_IR_x2apic(void)
1307 #ifdef CONFIG_INTR_REMAP
1309 unsigned long flags
;
1311 if (!cpu_has_x2apic
)
1314 if (!x2apic_preenabled
&& disable_x2apic
) {
1315 pr_info("Skipped enabling x2apic and Interrupt-remapping "
1316 "because of nox2apic\n");
1320 if (x2apic_preenabled
&& disable_x2apic
)
1321 panic("Bios already enabled x2apic, can't enforce nox2apic");
1323 if (!x2apic_preenabled
&& skip_ioapic_setup
) {
1324 pr_info("Skipped enabling x2apic and Interrupt-remapping "
1325 "because of skipping io-apic setup\n");
1329 ret
= dmar_table_init();
1331 pr_info("dmar_table_init() failed with %d:\n", ret
);
1333 if (x2apic_preenabled
)
1334 panic("x2apic enabled by bios. But IR enabling failed");
1336 pr_info("Not enabling x2apic,Intr-remapping\n");
1340 local_irq_save(flags
);
1343 ret
= save_mask_IO_APIC_setup();
1345 pr_info("Saving IO-APIC state failed: %d\n", ret
);
1349 ret
= enable_intr_remapping(1);
1351 if (ret
&& x2apic_preenabled
) {
1352 local_irq_restore(flags
);
1353 panic("x2apic enabled by bios. But IR enabling failed");
1361 apic_ops
= &x2apic_ops
;
1368 * IR enabling failed
1370 restore_IO_APIC_setup();
1372 reinit_intr_remapped_IO_APIC(x2apic_preenabled
);
1376 local_irq_restore(flags
);
1379 if (!x2apic_preenabled
)
1380 pr_info("Enabled x2apic and interrupt-remapping\n");
1382 pr_info("Enabled Interrupt-remapping\n");
1384 pr_err("Failed to enable Interrupt-remapping and x2apic\n");
1386 if (!cpu_has_x2apic
)
1389 if (x2apic_preenabled
)
1390 panic("x2apic enabled prior OS handover,"
1391 " enable CONFIG_INTR_REMAP");
1393 pr_info("Enable CONFIG_INTR_REMAP for enabling intr-remapping "
1399 #endif /* HAVE_X2APIC */
1401 #ifdef CONFIG_X86_64
1403 * Detect and enable local APICs on non-SMP boards.
1404 * Original code written by Keir Fraser.
1405 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1406 * not correctly set up (usually the APIC timer won't work etc.)
1408 static int __init
detect_init_APIC(void)
1410 if (!cpu_has_apic
) {
1411 pr_info("No local APIC present\n");
1415 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
1416 boot_cpu_physical_apicid
= 0;
1421 * Detect and initialize APIC
1423 static int __init
detect_init_APIC(void)
1427 /* Disabled by kernel option? */
1431 switch (boot_cpu_data
.x86_vendor
) {
1432 case X86_VENDOR_AMD
:
1433 if ((boot_cpu_data
.x86
== 6 && boot_cpu_data
.x86_model
> 1) ||
1434 (boot_cpu_data
.x86
== 15))
1437 case X86_VENDOR_INTEL
:
1438 if (boot_cpu_data
.x86
== 6 || boot_cpu_data
.x86
== 15 ||
1439 (boot_cpu_data
.x86
== 5 && cpu_has_apic
))
1446 if (!cpu_has_apic
) {
1448 * Over-ride BIOS and try to enable the local APIC only if
1449 * "lapic" specified.
1451 if (!force_enable_local_apic
) {
1452 pr_info("Local APIC disabled by BIOS -- "
1453 "you can enable it with \"lapic\"\n");
1457 * Some BIOSes disable the local APIC in the APIC_BASE
1458 * MSR. This can only be done in software for Intel P6 or later
1459 * and AMD K7 (Model > 1) or later.
1461 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1462 if (!(l
& MSR_IA32_APICBASE_ENABLE
)) {
1463 pr_info("Local APIC disabled by BIOS -- reenabling.\n");
1464 l
&= ~MSR_IA32_APICBASE_BASE
;
1465 l
|= MSR_IA32_APICBASE_ENABLE
| APIC_DEFAULT_PHYS_BASE
;
1466 wrmsr(MSR_IA32_APICBASE
, l
, h
);
1467 enabled_via_apicbase
= 1;
1471 * The APIC feature bit should now be enabled
1474 features
= cpuid_edx(1);
1475 if (!(features
& (1 << X86_FEATURE_APIC
))) {
1476 pr_warning("Could not enable APIC!\n");
1479 set_cpu_cap(&boot_cpu_data
, X86_FEATURE_APIC
);
1480 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
1482 /* The BIOS may have set up the APIC at some other address */
1483 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1484 if (l
& MSR_IA32_APICBASE_ENABLE
)
1485 mp_lapic_addr
= l
& MSR_IA32_APICBASE_BASE
;
1487 pr_info("Found and enabled local APIC!\n");
1494 pr_info("No local APIC present or hardware disabled\n");
1499 #ifdef CONFIG_X86_64
1500 void __init
early_init_lapic_mapping(void)
1502 unsigned long phys_addr
;
1505 * If no local APIC can be found then go out
1506 * : it means there is no mpatable and MADT
1508 if (!smp_found_config
)
1511 phys_addr
= mp_lapic_addr
;
1513 set_fixmap_nocache(FIX_APIC_BASE
, phys_addr
);
1514 apic_printk(APIC_VERBOSE
, "mapped APIC to %16lx (%16lx)\n",
1515 APIC_BASE
, phys_addr
);
1518 * Fetch the APIC ID of the BSP in case we have a
1519 * default configuration (or the MP table is broken).
1521 boot_cpu_physical_apicid
= read_apic_id();
1526 * init_apic_mappings - initialize APIC mappings
1528 void __init
init_apic_mappings(void)
1532 boot_cpu_physical_apicid
= read_apic_id();
1538 * If no local APIC can be found then set up a fake all
1539 * zeroes page to simulate the local APIC and another
1540 * one for the IO-APIC.
1542 if (!smp_found_config
&& detect_init_APIC()) {
1543 apic_phys
= (unsigned long) alloc_bootmem_pages(PAGE_SIZE
);
1544 apic_phys
= __pa(apic_phys
);
1546 apic_phys
= mp_lapic_addr
;
1548 set_fixmap_nocache(FIX_APIC_BASE
, apic_phys
);
1549 apic_printk(APIC_VERBOSE
, "mapped APIC to %08lx (%08lx)\n",
1550 APIC_BASE
, apic_phys
);
1553 * Fetch the APIC ID of the BSP in case we have a
1554 * default configuration (or the MP table is broken).
1556 if (boot_cpu_physical_apicid
== -1U)
1557 boot_cpu_physical_apicid
= read_apic_id();
1561 * This initializes the IO-APIC and APIC hardware if this is
1564 int apic_version
[MAX_APICS
];
1566 int __init
APIC_init_uniprocessor(void)
1568 #ifdef CONFIG_X86_64
1570 pr_info("Apic disabled\n");
1573 if (!cpu_has_apic
) {
1575 pr_info("Apic disabled by BIOS\n");
1579 if (!smp_found_config
&& !cpu_has_apic
)
1583 * Complain if the BIOS pretends there is one.
1585 if (!cpu_has_apic
&&
1586 APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
])) {
1587 pr_err("BIOS bug, local APIC 0x%x not detected!...\n",
1588 boot_cpu_physical_apicid
);
1589 clear_cpu_cap(&boot_cpu_data
, X86_FEATURE_APIC
);
1597 #ifdef CONFIG_X86_64
1598 setup_apic_routing();
1601 verify_local_APIC();
1604 #ifdef CONFIG_X86_64
1605 apic_write(APIC_ID
, SET_APIC_ID(boot_cpu_physical_apicid
));
1608 * Hack: In case of kdump, after a crash, kernel might be booting
1609 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
1610 * might be zero if read from MP tables. Get it from LAPIC.
1612 # ifdef CONFIG_CRASH_DUMP
1613 boot_cpu_physical_apicid
= read_apic_id();
1616 physid_set_mask_of_physid(boot_cpu_physical_apicid
, &phys_cpu_present_map
);
1619 #ifdef CONFIG_X86_64
1621 * Now enable IO-APICs, actually call clear_IO_APIC
1622 * We need clear_IO_APIC before enabling vector on BP
1624 if (!skip_ioapic_setup
&& nr_ioapics
)
1628 #ifdef CONFIG_X86_IO_APIC
1629 if (!smp_found_config
|| skip_ioapic_setup
|| !nr_ioapics
)
1631 localise_nmi_watchdog();
1632 end_local_APIC_setup();
1634 #ifdef CONFIG_X86_IO_APIC
1635 if (smp_found_config
&& !skip_ioapic_setup
&& nr_ioapics
)
1637 # ifdef CONFIG_X86_64
1643 #ifdef CONFIG_X86_64
1644 setup_boot_APIC_clock();
1645 check_nmi_watchdog();
1654 * Local APIC interrupts
1658 * This interrupt should _never_ happen with our APIC/SMP architecture
1660 void smp_spurious_interrupt(struct pt_regs
*regs
)
1667 * Check if this really is a spurious interrupt and ACK it
1668 * if it is a vectored one. Just in case...
1669 * Spurious interrupts should not be ACKed.
1671 v
= apic_read(APIC_ISR
+ ((SPURIOUS_APIC_VECTOR
& ~0x1f) >> 1));
1672 if (v
& (1 << (SPURIOUS_APIC_VECTOR
& 0x1f)))
1675 inc_irq_stat(irq_spurious_count
);
1677 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1678 pr_info("spurious APIC interrupt on CPU#%d, "
1679 "should never happen.\n", smp_processor_id());
1684 * This interrupt should never happen with our APIC/SMP architecture
1686 void smp_error_interrupt(struct pt_regs
*regs
)
1692 /* First tickle the hardware, only then report what went on. -- REW */
1693 v
= apic_read(APIC_ESR
);
1694 apic_write(APIC_ESR
, 0);
1695 v1
= apic_read(APIC_ESR
);
1697 atomic_inc(&irq_err_count
);
1700 * Here is what the APIC error bits mean:
1702 * 1: Receive CS error
1703 * 2: Send accept error
1704 * 3: Receive accept error
1706 * 5: Send illegal vector
1707 * 6: Received illegal vector
1708 * 7: Illegal register address
1710 pr_debug("APIC error on CPU%d: %02x(%02x)\n",
1711 smp_processor_id(), v
, v1
);
1716 * connect_bsp_APIC - attach the APIC to the interrupt system
1718 void __init
connect_bsp_APIC(void)
1720 #ifdef CONFIG_X86_32
1723 * Do not trust the local APIC being empty at bootup.
1727 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
1728 * local APIC to INT and NMI lines.
1730 apic_printk(APIC_VERBOSE
, "leaving PIC mode, "
1731 "enabling APIC mode.\n");
1740 * disconnect_bsp_APIC - detach the APIC from the interrupt system
1741 * @virt_wire_setup: indicates, whether virtual wire mode is selected
1743 * Virtual wire mode is necessary to deliver legacy interrupts even when the
1746 void disconnect_bsp_APIC(int virt_wire_setup
)
1750 #ifdef CONFIG_X86_32
1753 * Put the board back into PIC mode (has an effect only on
1754 * certain older boards). Note that APIC interrupts, including
1755 * IPIs, won't work beyond this point! The only exception are
1758 apic_printk(APIC_VERBOSE
, "disabling APIC mode, "
1759 "entering PIC mode.\n");
1766 /* Go back to Virtual Wire compatibility mode */
1768 /* For the spurious interrupt use vector F, and enable it */
1769 value
= apic_read(APIC_SPIV
);
1770 value
&= ~APIC_VECTOR_MASK
;
1771 value
|= APIC_SPIV_APIC_ENABLED
;
1773 apic_write(APIC_SPIV
, value
);
1775 if (!virt_wire_setup
) {
1777 * For LVT0 make it edge triggered, active high,
1778 * external and enabled
1780 value
= apic_read(APIC_LVT0
);
1781 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1782 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1783 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1784 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1785 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_EXTINT
);
1786 apic_write(APIC_LVT0
, value
);
1789 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
1793 * For LVT1 make it edge triggered, active high,
1796 value
= apic_read(APIC_LVT1
);
1797 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1798 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1799 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1800 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1801 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_NMI
);
1802 apic_write(APIC_LVT1
, value
);
1805 void __cpuinit
generic_processor_info(int apicid
, int version
)
1812 if (version
== 0x0) {
1813 pr_warning("BIOS bug, APIC version is 0 for CPU#%d! "
1814 "fixing up to 0x10. (tell your hw vendor)\n",
1818 apic_version
[apicid
] = version
;
1820 if (num_processors
>= nr_cpu_ids
) {
1821 int max
= nr_cpu_ids
;
1822 int thiscpu
= max
+ disabled_cpus
;
1825 "ACPI: NR_CPUS/possible_cpus limit of %i reached."
1826 " Processor %d/0x%x ignored.\n", max
, thiscpu
, apicid
);
1833 cpu
= cpumask_next_zero(-1, cpu_present_mask
);
1835 physid_set(apicid
, phys_cpu_present_map
);
1836 if (apicid
== boot_cpu_physical_apicid
) {
1838 * x86_bios_cpu_apicid is required to have processors listed
1839 * in same order as logical cpu numbers. Hence the first
1840 * entry is BSP, and so on.
1844 if (apicid
> max_physical_apicid
)
1845 max_physical_apicid
= apicid
;
1847 #ifdef CONFIG_X86_32
1849 * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y
1850 * but we need to work other dependencies like SMP_SUSPEND etc
1851 * before this can be done without some confusion.
1852 * if (CPU_HOTPLUG_ENABLED || num_processors > 8)
1853 * - Ashok Raj <ashok.raj@intel.com>
1855 if (max_physical_apicid
>= 8) {
1856 switch (boot_cpu_data
.x86_vendor
) {
1857 case X86_VENDOR_INTEL
:
1858 if (!APIC_XAPIC(version
)) {
1862 /* If P4 and above fall through */
1863 case X86_VENDOR_AMD
:
1869 #if defined(CONFIG_X86_SMP) || defined(CONFIG_X86_64)
1870 /* are we being called early in kernel startup? */
1871 if (early_per_cpu_ptr(x86_cpu_to_apicid
)) {
1872 u16
*cpu_to_apicid
= early_per_cpu_ptr(x86_cpu_to_apicid
);
1873 u16
*bios_cpu_apicid
= early_per_cpu_ptr(x86_bios_cpu_apicid
);
1875 cpu_to_apicid
[cpu
] = apicid
;
1876 bios_cpu_apicid
[cpu
] = apicid
;
1878 per_cpu(x86_cpu_to_apicid
, cpu
) = apicid
;
1879 per_cpu(x86_bios_cpu_apicid
, cpu
) = apicid
;
1883 set_cpu_possible(cpu
, true);
1884 set_cpu_present(cpu
, true);
1887 #ifdef CONFIG_X86_64
1888 int hard_smp_processor_id(void)
1890 return read_apic_id();
1901 * 'active' is true if the local APIC was enabled by us and
1902 * not the BIOS; this signifies that we are also responsible
1903 * for disabling it before entering apm/acpi suspend
1906 /* r/w apic fields */
1907 unsigned int apic_id
;
1908 unsigned int apic_taskpri
;
1909 unsigned int apic_ldr
;
1910 unsigned int apic_dfr
;
1911 unsigned int apic_spiv
;
1912 unsigned int apic_lvtt
;
1913 unsigned int apic_lvtpc
;
1914 unsigned int apic_lvt0
;
1915 unsigned int apic_lvt1
;
1916 unsigned int apic_lvterr
;
1917 unsigned int apic_tmict
;
1918 unsigned int apic_tdcr
;
1919 unsigned int apic_thmr
;
1922 static int lapic_suspend(struct sys_device
*dev
, pm_message_t state
)
1924 unsigned long flags
;
1927 if (!apic_pm_state
.active
)
1930 maxlvt
= lapic_get_maxlvt();
1932 apic_pm_state
.apic_id
= apic_read(APIC_ID
);
1933 apic_pm_state
.apic_taskpri
= apic_read(APIC_TASKPRI
);
1934 apic_pm_state
.apic_ldr
= apic_read(APIC_LDR
);
1935 apic_pm_state
.apic_dfr
= apic_read(APIC_DFR
);
1936 apic_pm_state
.apic_spiv
= apic_read(APIC_SPIV
);
1937 apic_pm_state
.apic_lvtt
= apic_read(APIC_LVTT
);
1939 apic_pm_state
.apic_lvtpc
= apic_read(APIC_LVTPC
);
1940 apic_pm_state
.apic_lvt0
= apic_read(APIC_LVT0
);
1941 apic_pm_state
.apic_lvt1
= apic_read(APIC_LVT1
);
1942 apic_pm_state
.apic_lvterr
= apic_read(APIC_LVTERR
);
1943 apic_pm_state
.apic_tmict
= apic_read(APIC_TMICT
);
1944 apic_pm_state
.apic_tdcr
= apic_read(APIC_TDCR
);
1945 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
1947 apic_pm_state
.apic_thmr
= apic_read(APIC_LVTTHMR
);
1950 local_irq_save(flags
);
1951 disable_local_APIC();
1952 local_irq_restore(flags
);
1956 static int lapic_resume(struct sys_device
*dev
)
1959 unsigned long flags
;
1962 if (!apic_pm_state
.active
)
1965 maxlvt
= lapic_get_maxlvt();
1967 local_irq_save(flags
);
1976 * Make sure the APICBASE points to the right address
1978 * FIXME! This will be wrong if we ever support suspend on
1979 * SMP! We'll need to do this as part of the CPU restore!
1981 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1982 l
&= ~MSR_IA32_APICBASE_BASE
;
1983 l
|= MSR_IA32_APICBASE_ENABLE
| mp_lapic_addr
;
1984 wrmsr(MSR_IA32_APICBASE
, l
, h
);
1987 apic_write(APIC_LVTERR
, ERROR_APIC_VECTOR
| APIC_LVT_MASKED
);
1988 apic_write(APIC_ID
, apic_pm_state
.apic_id
);
1989 apic_write(APIC_DFR
, apic_pm_state
.apic_dfr
);
1990 apic_write(APIC_LDR
, apic_pm_state
.apic_ldr
);
1991 apic_write(APIC_TASKPRI
, apic_pm_state
.apic_taskpri
);
1992 apic_write(APIC_SPIV
, apic_pm_state
.apic_spiv
);
1993 apic_write(APIC_LVT0
, apic_pm_state
.apic_lvt0
);
1994 apic_write(APIC_LVT1
, apic_pm_state
.apic_lvt1
);
1995 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
1997 apic_write(APIC_LVTTHMR
, apic_pm_state
.apic_thmr
);
2000 apic_write(APIC_LVTPC
, apic_pm_state
.apic_lvtpc
);
2001 apic_write(APIC_LVTT
, apic_pm_state
.apic_lvtt
);
2002 apic_write(APIC_TDCR
, apic_pm_state
.apic_tdcr
);
2003 apic_write(APIC_TMICT
, apic_pm_state
.apic_tmict
);
2004 apic_write(APIC_ESR
, 0);
2005 apic_read(APIC_ESR
);
2006 apic_write(APIC_LVTERR
, apic_pm_state
.apic_lvterr
);
2007 apic_write(APIC_ESR
, 0);
2008 apic_read(APIC_ESR
);
2010 local_irq_restore(flags
);
2016 * This device has no shutdown method - fully functioning local APICs
2017 * are needed on every CPU up until machine_halt/restart/poweroff.
2020 static struct sysdev_class lapic_sysclass
= {
2022 .resume
= lapic_resume
,
2023 .suspend
= lapic_suspend
,
2026 static struct sys_device device_lapic
= {
2028 .cls
= &lapic_sysclass
,
2031 static void __cpuinit
apic_pm_activate(void)
2033 apic_pm_state
.active
= 1;
2036 static int __init
init_lapic_sysfs(void)
2042 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
2044 error
= sysdev_class_register(&lapic_sysclass
);
2046 error
= sysdev_register(&device_lapic
);
2049 device_initcall(init_lapic_sysfs
);
2051 #else /* CONFIG_PM */
2053 static void apic_pm_activate(void) { }
2055 #endif /* CONFIG_PM */
2057 #ifdef CONFIG_X86_64
2059 * apic_is_clustered_box() -- Check if we can expect good TSC
2061 * Thus far, the major user of this is IBM's Summit2 series:
2063 * Clustered boxes may have unsynced TSC problems if they are
2064 * multi-chassis. Use available data to take a good guess.
2065 * If in doubt, go HPET.
2067 __cpuinit
int apic_is_clustered_box(void)
2069 int i
, clusters
, zeros
;
2071 u16
*bios_cpu_apicid
;
2072 DECLARE_BITMAP(clustermap
, NUM_APIC_CLUSTERS
);
2075 * there is not this kind of box with AMD CPU yet.
2076 * Some AMD box with quadcore cpu and 8 sockets apicid
2077 * will be [4, 0x23] or [8, 0x27] could be thought to
2078 * vsmp box still need checking...
2080 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
) && !is_vsmp_box())
2083 bios_cpu_apicid
= early_per_cpu_ptr(x86_bios_cpu_apicid
);
2084 bitmap_zero(clustermap
, NUM_APIC_CLUSTERS
);
2086 for (i
= 0; i
< nr_cpu_ids
; i
++) {
2087 /* are we being called early in kernel startup? */
2088 if (bios_cpu_apicid
) {
2089 id
= bios_cpu_apicid
[i
];
2091 else if (i
< nr_cpu_ids
) {
2093 id
= per_cpu(x86_bios_cpu_apicid
, i
);
2100 if (id
!= BAD_APICID
)
2101 __set_bit(APIC_CLUSTERID(id
), clustermap
);
2104 /* Problem: Partially populated chassis may not have CPUs in some of
2105 * the APIC clusters they have been allocated. Only present CPUs have
2106 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap.
2107 * Since clusters are allocated sequentially, count zeros only if
2108 * they are bounded by ones.
2112 for (i
= 0; i
< NUM_APIC_CLUSTERS
; i
++) {
2113 if (test_bit(i
, clustermap
)) {
2114 clusters
+= 1 + zeros
;
2120 /* ScaleMP vSMPowered boxes have one cluster per board and TSCs are
2121 * not guaranteed to be synced between boards
2123 if (is_vsmp_box() && clusters
> 1)
2127 * If clusters > 2, then should be multi-chassis.
2128 * May have to revisit this when multi-core + hyperthreaded CPUs come
2129 * out, but AFAIK this will work even for them.
2131 return (clusters
> 2);
2136 * APIC command line parameters
2138 static int __init
setup_disableapic(char *arg
)
2141 setup_clear_cpu_cap(X86_FEATURE_APIC
);
2144 early_param("disableapic", setup_disableapic
);
2146 /* same as disableapic, for compatibility */
2147 static int __init
setup_nolapic(char *arg
)
2149 return setup_disableapic(arg
);
2151 early_param("nolapic", setup_nolapic
);
2153 static int __init
parse_lapic_timer_c2_ok(char *arg
)
2155 local_apic_timer_c2_ok
= 1;
2158 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok
);
2160 static int __init
parse_disable_apic_timer(char *arg
)
2162 disable_apic_timer
= 1;
2165 early_param("noapictimer", parse_disable_apic_timer
);
2167 static int __init
parse_nolapic_timer(char *arg
)
2169 disable_apic_timer
= 1;
2172 early_param("nolapic_timer", parse_nolapic_timer
);
2174 static int __init
apic_set_verbosity(char *arg
)
2177 #ifdef CONFIG_X86_64
2178 skip_ioapic_setup
= 0;
2184 if (strcmp("debug", arg
) == 0)
2185 apic_verbosity
= APIC_DEBUG
;
2186 else if (strcmp("verbose", arg
) == 0)
2187 apic_verbosity
= APIC_VERBOSE
;
2189 pr_warning("APIC Verbosity level %s not recognised"
2190 " use apic=verbose or apic=debug\n", arg
);
2196 early_param("apic", apic_set_verbosity
);
2198 static int __init
lapic_insert_resource(void)
2203 /* Put local APIC into the resource map. */
2204 lapic_resource
.start
= apic_phys
;
2205 lapic_resource
.end
= lapic_resource
.start
+ PAGE_SIZE
- 1;
2206 insert_resource(&iomem_resource
, &lapic_resource
);
2212 * need call insert after e820_reserve_resources()
2213 * that is using request_resource
2215 late_initcall(lapic_insert_resource
);