2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/bootmem.h>
22 #include <linux/interrupt.h>
23 #include <linux/mc146818rtc.h>
24 #include <linux/kernel_stat.h>
25 #include <linux/sysdev.h>
26 #include <linux/ioport.h>
27 #include <linux/cpu.h>
28 #include <linux/clockchips.h>
29 #include <linux/acpi_pmtmr.h>
30 #include <linux/module.h>
31 #include <linux/dmi.h>
32 #include <linux/dmar.h>
33 #include <linux/ftrace.h>
34 #include <linux/smp.h>
35 #include <linux/nmi.h>
36 #include <linux/timex.h>
38 #include <asm/atomic.h>
40 #include <asm/mpspec.h>
42 #include <asm/arch_hooks.h>
44 #include <asm/pgalloc.h>
45 #include <asm/i8253.h>
47 #include <asm/proto.h>
49 #include <asm/i8259.h>
52 #include <mach_apic.h>
53 #include <mach_apicdef.h>
59 #if ((SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F)
60 # error SPURIOUS_APIC_VECTOR definition error
63 unsigned int num_processors
;
64 unsigned disabled_cpus __cpuinitdata
;
65 /* Processor that is doing the boot up */
66 unsigned int boot_cpu_physical_apicid
= -1U;
67 EXPORT_SYMBOL(boot_cpu_physical_apicid
);
68 unsigned int max_physical_apicid
;
70 /* Bitmask of physically existing CPUs */
71 physid_mask_t phys_cpu_present_map
;
74 * Map cpu index to physical APIC ID
76 DEFINE_EARLY_PER_CPU(u16
, x86_cpu_to_apicid
, BAD_APICID
);
77 DEFINE_EARLY_PER_CPU(u16
, x86_bios_cpu_apicid
, BAD_APICID
);
78 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid
);
79 EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid
);
83 * Knob to control our willingness to enable the local APIC.
87 static int force_enable_local_apic
;
89 * APIC command line parameters
91 static int __init
parse_lapic(char *arg
)
93 force_enable_local_apic
= 1;
96 early_param("lapic", parse_lapic
);
97 /* Local APIC was disabled by the BIOS and enabled by the kernel */
98 static int enabled_via_apicbase
;
103 static int apic_calibrate_pmtmr __initdata
;
104 static __init
int setup_apicpmtimer(char *s
)
106 apic_calibrate_pmtmr
= 1;
110 __setup("apicpmtimer", setup_apicpmtimer
);
119 /* x2apic enabled before OS handover */
120 static int x2apic_preenabled
;
121 static int disable_x2apic
;
122 static __init
int setup_nox2apic(char *str
)
125 setup_clear_cpu_cap(X86_FEATURE_X2APIC
);
128 early_param("nox2apic", setup_nox2apic
);
131 unsigned long mp_lapic_addr
;
133 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
134 static int disable_apic_timer __cpuinitdata
;
135 /* Local APIC timer works in C2 */
136 int local_apic_timer_c2_ok
;
137 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok
);
139 int first_system_vector
= 0xfe;
142 * Debug level, exported for io_apic.c
144 unsigned int apic_verbosity
;
148 /* Have we found an MP table */
149 int smp_found_config
;
151 static struct resource lapic_resource
= {
152 .name
= "Local APIC",
153 .flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
,
156 static unsigned int calibration_result
;
158 static int lapic_next_event(unsigned long delta
,
159 struct clock_event_device
*evt
);
160 static void lapic_timer_setup(enum clock_event_mode mode
,
161 struct clock_event_device
*evt
);
162 static void lapic_timer_broadcast(const struct cpumask
*mask
);
163 static void apic_pm_activate(void);
166 * The local apic timer can be used for any function which is CPU local.
168 static struct clock_event_device lapic_clockevent
= {
170 .features
= CLOCK_EVT_FEAT_PERIODIC
| CLOCK_EVT_FEAT_ONESHOT
171 | CLOCK_EVT_FEAT_C3STOP
| CLOCK_EVT_FEAT_DUMMY
,
173 .set_mode
= lapic_timer_setup
,
174 .set_next_event
= lapic_next_event
,
175 .broadcast
= lapic_timer_broadcast
,
179 static DEFINE_PER_CPU(struct clock_event_device
, lapic_events
);
181 static unsigned long apic_phys
;
184 * Get the LAPIC version
186 static inline int lapic_get_version(void)
188 return GET_APIC_VERSION(apic_read(APIC_LVR
));
192 * Check, if the APIC is integrated or a separate chip
194 static inline int lapic_is_integrated(void)
199 return APIC_INTEGRATED(lapic_get_version());
204 * Check, whether this is a modern or a first generation APIC
206 static int modern_apic(void)
208 /* AMD systems use old APIC versions, so check the CPU */
209 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
&&
210 boot_cpu_data
.x86
>= 0xf)
212 return lapic_get_version() >= 0x14;
216 * Paravirt kernels also might be using these below ops. So we still
217 * use generic apic_read()/apic_write(), which might be pointing to different
218 * ops in PARAVIRT case.
220 void xapic_wait_icr_idle(void)
222 while (apic_read(APIC_ICR
) & APIC_ICR_BUSY
)
226 u32
safe_xapic_wait_icr_idle(void)
233 send_status
= apic_read(APIC_ICR
) & APIC_ICR_BUSY
;
237 } while (timeout
++ < 1000);
242 void xapic_icr_write(u32 low
, u32 id
)
244 apic_write(APIC_ICR2
, SET_APIC_DEST_FIELD(id
));
245 apic_write(APIC_ICR
, low
);
248 static u64
xapic_icr_read(void)
252 icr2
= apic_read(APIC_ICR2
);
253 icr1
= apic_read(APIC_ICR
);
255 return icr1
| ((u64
)icr2
<< 32);
258 static struct apic_ops xapic_ops
= {
259 .read
= native_apic_mem_read
,
260 .write
= native_apic_mem_write
,
261 .icr_read
= xapic_icr_read
,
262 .icr_write
= xapic_icr_write
,
263 .wait_icr_idle
= xapic_wait_icr_idle
,
264 .safe_wait_icr_idle
= safe_xapic_wait_icr_idle
,
267 struct apic_ops __read_mostly
*apic_ops
= &xapic_ops
;
268 EXPORT_SYMBOL_GPL(apic_ops
);
271 static void x2apic_wait_icr_idle(void)
273 /* no need to wait for icr idle in x2apic */
277 static u32
safe_x2apic_wait_icr_idle(void)
279 /* no need to wait for icr idle in x2apic */
283 void x2apic_icr_write(u32 low
, u32 id
)
285 wrmsrl(APIC_BASE_MSR
+ (APIC_ICR
>> 4), ((__u64
) id
) << 32 | low
);
288 static u64
x2apic_icr_read(void)
292 rdmsrl(APIC_BASE_MSR
+ (APIC_ICR
>> 4), val
);
296 static struct apic_ops x2apic_ops
= {
297 .read
= native_apic_msr_read
,
298 .write
= native_apic_msr_write
,
299 .icr_read
= x2apic_icr_read
,
300 .icr_write
= x2apic_icr_write
,
301 .wait_icr_idle
= x2apic_wait_icr_idle
,
302 .safe_wait_icr_idle
= safe_x2apic_wait_icr_idle
,
307 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
309 void __cpuinit
enable_NMI_through_LVT0(void)
313 /* unmask and set to NMI */
316 /* Level triggered for 82489DX (32bit mode) */
317 if (!lapic_is_integrated())
318 v
|= APIC_LVT_LEVEL_TRIGGER
;
320 apic_write(APIC_LVT0
, v
);
325 * get_physical_broadcast - Get number of physical broadcast IDs
327 int get_physical_broadcast(void)
329 return modern_apic() ? 0xff : 0xf;
334 * lapic_get_maxlvt - get the maximum number of local vector table entries
336 int lapic_get_maxlvt(void)
340 v
= apic_read(APIC_LVR
);
342 * - we always have APIC integrated on 64bit mode
343 * - 82489DXs do not report # of LVT entries
345 return APIC_INTEGRATED(GET_APIC_VERSION(v
)) ? GET_APIC_MAXLVT(v
) : 2;
353 #define APIC_DIVISOR 16
356 * This function sets up the local APIC timer, with a timeout of
357 * 'clocks' APIC bus clock. During calibration we actually call
358 * this function twice on the boot CPU, once with a bogus timeout
359 * value, second time for real. The other (noncalibrating) CPUs
360 * call this function only once, with the real, calibrated value.
362 * We do reads before writes even if unnecessary, to get around the
363 * P5 APIC double write bug.
365 static void __setup_APIC_LVTT(unsigned int clocks
, int oneshot
, int irqen
)
367 unsigned int lvtt_value
, tmp_value
;
369 lvtt_value
= LOCAL_TIMER_VECTOR
;
371 lvtt_value
|= APIC_LVT_TIMER_PERIODIC
;
372 if (!lapic_is_integrated())
373 lvtt_value
|= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV
);
376 lvtt_value
|= APIC_LVT_MASKED
;
378 apic_write(APIC_LVTT
, lvtt_value
);
383 tmp_value
= apic_read(APIC_TDCR
);
384 apic_write(APIC_TDCR
,
385 (tmp_value
& ~(APIC_TDR_DIV_1
| APIC_TDR_DIV_TMBASE
)) |
389 apic_write(APIC_TMICT
, clocks
/ APIC_DIVISOR
);
393 * Setup extended LVT, AMD specific (K8, family 10h)
395 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
396 * MCE interrupts are supported. Thus MCE offset must be set to 0.
398 * If mask=1, the LVT entry does not generate interrupts while mask=0
399 * enables the vector. See also the BKDGs.
402 #define APIC_EILVT_LVTOFF_MCE 0
403 #define APIC_EILVT_LVTOFF_IBS 1
405 static void setup_APIC_eilvt(u8 lvt_off
, u8 vector
, u8 msg_type
, u8 mask
)
407 unsigned long reg
= (lvt_off
<< 4) + APIC_EILVT0
;
408 unsigned int v
= (mask
<< 16) | (msg_type
<< 8) | vector
;
413 u8
setup_APIC_eilvt_mce(u8 vector
, u8 msg_type
, u8 mask
)
415 setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE
, vector
, msg_type
, mask
);
416 return APIC_EILVT_LVTOFF_MCE
;
419 u8
setup_APIC_eilvt_ibs(u8 vector
, u8 msg_type
, u8 mask
)
421 setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS
, vector
, msg_type
, mask
);
422 return APIC_EILVT_LVTOFF_IBS
;
424 EXPORT_SYMBOL_GPL(setup_APIC_eilvt_ibs
);
427 * Program the next event, relative to now
429 static int lapic_next_event(unsigned long delta
,
430 struct clock_event_device
*evt
)
432 apic_write(APIC_TMICT
, delta
);
437 * Setup the lapic timer in periodic or oneshot mode
439 static void lapic_timer_setup(enum clock_event_mode mode
,
440 struct clock_event_device
*evt
)
445 /* Lapic used as dummy for broadcast ? */
446 if (evt
->features
& CLOCK_EVT_FEAT_DUMMY
)
449 local_irq_save(flags
);
452 case CLOCK_EVT_MODE_PERIODIC
:
453 case CLOCK_EVT_MODE_ONESHOT
:
454 __setup_APIC_LVTT(calibration_result
,
455 mode
!= CLOCK_EVT_MODE_PERIODIC
, 1);
457 case CLOCK_EVT_MODE_UNUSED
:
458 case CLOCK_EVT_MODE_SHUTDOWN
:
459 v
= apic_read(APIC_LVTT
);
460 v
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
461 apic_write(APIC_LVTT
, v
);
462 apic_write(APIC_TMICT
, 0xffffffff);
464 case CLOCK_EVT_MODE_RESUME
:
465 /* Nothing to do here */
469 local_irq_restore(flags
);
473 * Local APIC timer broadcast function
475 static void lapic_timer_broadcast(const struct cpumask
*mask
)
478 send_IPI_mask(mask
, LOCAL_TIMER_VECTOR
);
483 * Setup the local APIC timer for this CPU. Copy the initilized values
484 * of the boot CPU and register the clock event in the framework.
486 static void __cpuinit
setup_APIC_timer(void)
488 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
490 memcpy(levt
, &lapic_clockevent
, sizeof(*levt
));
491 levt
->cpumask
= cpumask_of(smp_processor_id());
493 clockevents_register_device(levt
);
497 * In this functions we calibrate APIC bus clocks to the external timer.
499 * We want to do the calibration only once since we want to have local timer
500 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
503 * This was previously done by reading the PIT/HPET and waiting for a wrap
504 * around to find out, that a tick has elapsed. I have a box, where the PIT
505 * readout is broken, so it never gets out of the wait loop again. This was
506 * also reported by others.
508 * Monitoring the jiffies value is inaccurate and the clockevents
509 * infrastructure allows us to do a simple substitution of the interrupt
512 * The calibration routine also uses the pm_timer when possible, as the PIT
513 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
514 * back to normal later in the boot process).
517 #define LAPIC_CAL_LOOPS (HZ/10)
519 static __initdata
int lapic_cal_loops
= -1;
520 static __initdata
long lapic_cal_t1
, lapic_cal_t2
;
521 static __initdata
unsigned long long lapic_cal_tsc1
, lapic_cal_tsc2
;
522 static __initdata
unsigned long lapic_cal_pm1
, lapic_cal_pm2
;
523 static __initdata
unsigned long lapic_cal_j1
, lapic_cal_j2
;
526 * Temporary interrupt handler.
528 static void __init
lapic_cal_handler(struct clock_event_device
*dev
)
530 unsigned long long tsc
= 0;
531 long tapic
= apic_read(APIC_TMCCT
);
532 unsigned long pm
= acpi_pm_read_early();
537 switch (lapic_cal_loops
++) {
539 lapic_cal_t1
= tapic
;
540 lapic_cal_tsc1
= tsc
;
542 lapic_cal_j1
= jiffies
;
545 case LAPIC_CAL_LOOPS
:
546 lapic_cal_t2
= tapic
;
547 lapic_cal_tsc2
= tsc
;
548 if (pm
< lapic_cal_pm1
)
549 pm
+= ACPI_PM_OVRRUN
;
551 lapic_cal_j2
= jiffies
;
556 static int __init
calibrate_by_pmtimer(long deltapm
, long *delta
)
558 const long pm_100ms
= PMTMR_TICKS_PER_SEC
/ 10;
559 const long pm_thresh
= pm_100ms
/ 100;
563 #ifndef CONFIG_X86_PM_TIMER
567 apic_printk(APIC_VERBOSE
, "... PM timer delta = %ld\n", deltapm
);
569 /* Check, if the PM timer is available */
573 mult
= clocksource_hz2mult(PMTMR_TICKS_PER_SEC
, 22);
575 if (deltapm
> (pm_100ms
- pm_thresh
) &&
576 deltapm
< (pm_100ms
+ pm_thresh
)) {
577 apic_printk(APIC_VERBOSE
, "... PM timer result ok\n");
579 res
= (((u64
)deltapm
) * mult
) >> 22;
580 do_div(res
, 1000000);
581 pr_warning("APIC calibration not consistent "
582 "with PM Timer: %ldms instead of 100ms\n",
584 /* Correct the lapic counter value */
585 res
= (((u64
)(*delta
)) * pm_100ms
);
586 do_div(res
, deltapm
);
587 pr_info("APIC delta adjusted to PM-Timer: "
588 "%lu (%ld)\n", (unsigned long)res
, *delta
);
595 static int __init
calibrate_APIC_clock(void)
597 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
598 void (*real_handler
)(struct clock_event_device
*dev
);
599 unsigned long deltaj
;
601 int pm_referenced
= 0;
605 /* Replace the global interrupt handler */
606 real_handler
= global_clock_event
->event_handler
;
607 global_clock_event
->event_handler
= lapic_cal_handler
;
610 * Setup the APIC counter to maximum. There is no way the lapic
611 * can underflow in the 100ms detection time frame
613 __setup_APIC_LVTT(0xffffffff, 0, 0);
615 /* Let the interrupts run */
618 while (lapic_cal_loops
<= LAPIC_CAL_LOOPS
)
623 /* Restore the real event handler */
624 global_clock_event
->event_handler
= real_handler
;
626 /* Build delta t1-t2 as apic timer counts down */
627 delta
= lapic_cal_t1
- lapic_cal_t2
;
628 apic_printk(APIC_VERBOSE
, "... lapic delta = %ld\n", delta
);
630 /* we trust the PM based calibration if possible */
631 pm_referenced
= !calibrate_by_pmtimer(lapic_cal_pm2
- lapic_cal_pm1
,
634 /* Calculate the scaled math multiplication factor */
635 lapic_clockevent
.mult
= div_sc(delta
, TICK_NSEC
* LAPIC_CAL_LOOPS
,
636 lapic_clockevent
.shift
);
637 lapic_clockevent
.max_delta_ns
=
638 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent
);
639 lapic_clockevent
.min_delta_ns
=
640 clockevent_delta2ns(0xF, &lapic_clockevent
);
642 calibration_result
= (delta
* APIC_DIVISOR
) / LAPIC_CAL_LOOPS
;
644 apic_printk(APIC_VERBOSE
, "..... delta %ld\n", delta
);
645 apic_printk(APIC_VERBOSE
, "..... mult: %ld\n", lapic_clockevent
.mult
);
646 apic_printk(APIC_VERBOSE
, "..... calibration result: %u\n",
650 delta
= (long)(lapic_cal_tsc2
- lapic_cal_tsc1
);
651 apic_printk(APIC_VERBOSE
, "..... CPU clock speed is "
653 (delta
/ LAPIC_CAL_LOOPS
) / (1000000 / HZ
),
654 (delta
/ LAPIC_CAL_LOOPS
) % (1000000 / HZ
));
657 apic_printk(APIC_VERBOSE
, "..... host bus clock speed is "
659 calibration_result
/ (1000000 / HZ
),
660 calibration_result
% (1000000 / HZ
));
663 * Do a sanity check on the APIC calibration result
665 if (calibration_result
< (1000000 / HZ
)) {
667 pr_warning("APIC frequency too slow, disabling apic timer\n");
671 levt
->features
&= ~CLOCK_EVT_FEAT_DUMMY
;
674 * PM timer calibration failed or not turned on
675 * so lets try APIC timer based calibration
677 if (!pm_referenced
) {
678 apic_printk(APIC_VERBOSE
, "... verify APIC timer\n");
681 * Setup the apic timer manually
683 levt
->event_handler
= lapic_cal_handler
;
684 lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC
, levt
);
685 lapic_cal_loops
= -1;
687 /* Let the interrupts run */
690 while (lapic_cal_loops
<= LAPIC_CAL_LOOPS
)
693 /* Stop the lapic timer */
694 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, levt
);
697 deltaj
= lapic_cal_j2
- lapic_cal_j1
;
698 apic_printk(APIC_VERBOSE
, "... jiffies delta = %lu\n", deltaj
);
700 /* Check, if the jiffies result is consistent */
701 if (deltaj
>= LAPIC_CAL_LOOPS
-2 && deltaj
<= LAPIC_CAL_LOOPS
+2)
702 apic_printk(APIC_VERBOSE
, "... jiffies result ok\n");
704 levt
->features
|= CLOCK_EVT_FEAT_DUMMY
;
708 if (levt
->features
& CLOCK_EVT_FEAT_DUMMY
) {
709 pr_warning("APIC timer disabled due to verification failure\n");
717 * Setup the boot APIC
719 * Calibrate and verify the result.
721 void __init
setup_boot_APIC_clock(void)
724 * The local apic timer can be disabled via the kernel
725 * commandline or from the CPU detection code. Register the lapic
726 * timer as a dummy clock event source on SMP systems, so the
727 * broadcast mechanism is used. On UP systems simply ignore it.
729 if (disable_apic_timer
) {
730 pr_info("Disabling APIC timer\n");
731 /* No broadcast on UP ! */
732 if (num_possible_cpus() > 1) {
733 lapic_clockevent
.mult
= 1;
739 apic_printk(APIC_VERBOSE
, "Using local APIC timer interrupts.\n"
740 "calibrating APIC timer ...\n");
742 if (calibrate_APIC_clock()) {
743 /* No broadcast on UP ! */
744 if (num_possible_cpus() > 1)
750 * If nmi_watchdog is set to IO_APIC, we need the
751 * PIT/HPET going. Otherwise register lapic as a dummy
754 if (nmi_watchdog
!= NMI_IO_APIC
)
755 lapic_clockevent
.features
&= ~CLOCK_EVT_FEAT_DUMMY
;
757 pr_warning("APIC timer registered as dummy,"
758 " due to nmi_watchdog=%d!\n", nmi_watchdog
);
760 /* Setup the lapic or request the broadcast */
764 void __cpuinit
setup_secondary_APIC_clock(void)
770 * The guts of the apic timer interrupt
772 static void local_apic_timer_interrupt(void)
774 int cpu
= smp_processor_id();
775 struct clock_event_device
*evt
= &per_cpu(lapic_events
, cpu
);
778 * Normally we should not be here till LAPIC has been initialized but
779 * in some cases like kdump, its possible that there is a pending LAPIC
780 * timer interrupt from previous kernel's context and is delivered in
781 * new kernel the moment interrupts are enabled.
783 * Interrupts are enabled early and LAPIC is setup much later, hence
784 * its possible that when we get here evt->event_handler is NULL.
785 * Check for event_handler being NULL and discard the interrupt as
788 if (!evt
->event_handler
) {
789 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu
);
791 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, evt
);
796 * the NMI deadlock-detector uses this.
798 inc_irq_stat(apic_timer_irqs
);
800 evt
->event_handler(evt
);
804 * Local APIC timer interrupt. This is the most natural way for doing
805 * local interrupts, but local timer interrupts can be emulated by
806 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
808 * [ if a single-CPU system runs an SMP kernel then we call the local
809 * interrupt as well. Thus we cannot inline the local irq ... ]
811 void __irq_entry
smp_apic_timer_interrupt(struct pt_regs
*regs
)
813 struct pt_regs
*old_regs
= set_irq_regs(regs
);
816 * NOTE! We'd better ACK the irq immediately,
817 * because timer handling can be slow.
821 * update_process_times() expects us to have done irq_enter().
822 * Besides, if we don't timer interrupts ignore the global
823 * interrupt lock, which is the WrongThing (tm) to do.
827 local_apic_timer_interrupt();
830 set_irq_regs(old_regs
);
833 int setup_profiling_timer(unsigned int multiplier
)
839 * Local APIC start and shutdown
843 * clear_local_APIC - shutdown the local APIC
845 * This is called, when a CPU is disabled and before rebooting, so the state of
846 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
847 * leftovers during boot.
849 void clear_local_APIC(void)
854 /* APIC hasn't been mapped yet */
858 maxlvt
= lapic_get_maxlvt();
860 * Masking an LVT entry can trigger a local APIC error
861 * if the vector is zero. Mask LVTERR first to prevent this.
864 v
= ERROR_APIC_VECTOR
; /* any non-zero vector will do */
865 apic_write(APIC_LVTERR
, v
| APIC_LVT_MASKED
);
868 * Careful: we have to set masks only first to deassert
869 * any level-triggered sources.
871 v
= apic_read(APIC_LVTT
);
872 apic_write(APIC_LVTT
, v
| APIC_LVT_MASKED
);
873 v
= apic_read(APIC_LVT0
);
874 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
875 v
= apic_read(APIC_LVT1
);
876 apic_write(APIC_LVT1
, v
| APIC_LVT_MASKED
);
878 v
= apic_read(APIC_LVTPC
);
879 apic_write(APIC_LVTPC
, v
| APIC_LVT_MASKED
);
882 /* lets not touch this if we didn't frob it */
883 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(X86_MCE_INTEL)
885 v
= apic_read(APIC_LVTTHMR
);
886 apic_write(APIC_LVTTHMR
, v
| APIC_LVT_MASKED
);
890 * Clean APIC state for other OSs:
892 apic_write(APIC_LVTT
, APIC_LVT_MASKED
);
893 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
894 apic_write(APIC_LVT1
, APIC_LVT_MASKED
);
896 apic_write(APIC_LVTERR
, APIC_LVT_MASKED
);
898 apic_write(APIC_LVTPC
, APIC_LVT_MASKED
);
900 /* Integrated APIC (!82489DX) ? */
901 if (lapic_is_integrated()) {
903 /* Clear ESR due to Pentium errata 3AP and 11AP */
904 apic_write(APIC_ESR
, 0);
910 * disable_local_APIC - clear and disable the local APIC
912 void disable_local_APIC(void)
916 /* APIC hasn't been mapped yet */
923 * Disable APIC (implies clearing of registers
926 value
= apic_read(APIC_SPIV
);
927 value
&= ~APIC_SPIV_APIC_ENABLED
;
928 apic_write(APIC_SPIV
, value
);
932 * When LAPIC was disabled by the BIOS and enabled by the kernel,
933 * restore the disabled state.
935 if (enabled_via_apicbase
) {
938 rdmsr(MSR_IA32_APICBASE
, l
, h
);
939 l
&= ~MSR_IA32_APICBASE_ENABLE
;
940 wrmsr(MSR_IA32_APICBASE
, l
, h
);
946 * If Linux enabled the LAPIC against the BIOS default disable it down before
947 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
948 * not power-off. Additionally clear all LVT entries before disable_local_APIC
949 * for the case where Linux didn't enable the LAPIC.
951 void lapic_shutdown(void)
958 local_irq_save(flags
);
961 if (!enabled_via_apicbase
)
965 disable_local_APIC();
968 local_irq_restore(flags
);
972 * This is to verify that we're looking at a real local APIC.
973 * Check these against your board if the CPUs aren't getting
974 * started for no apparent reason.
976 int __init
verify_local_APIC(void)
978 unsigned int reg0
, reg1
;
981 * The version register is read-only in a real APIC.
983 reg0
= apic_read(APIC_LVR
);
984 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg0
);
985 apic_write(APIC_LVR
, reg0
^ APIC_LVR_MASK
);
986 reg1
= apic_read(APIC_LVR
);
987 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg1
);
990 * The two version reads above should print the same
991 * numbers. If the second one is different, then we
992 * poke at a non-APIC.
998 * Check if the version looks reasonably.
1000 reg1
= GET_APIC_VERSION(reg0
);
1001 if (reg1
== 0x00 || reg1
== 0xff)
1003 reg1
= lapic_get_maxlvt();
1004 if (reg1
< 0x02 || reg1
== 0xff)
1008 * The ID register is read/write in a real APIC.
1010 reg0
= apic_read(APIC_ID
);
1011 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg0
);
1012 apic_write(APIC_ID
, reg0
^ APIC_ID_MASK
);
1013 reg1
= apic_read(APIC_ID
);
1014 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg1
);
1015 apic_write(APIC_ID
, reg0
);
1016 if (reg1
!= (reg0
^ APIC_ID_MASK
))
1020 * The next two are just to see if we have sane values.
1021 * They're only really relevant if we're in Virtual Wire
1022 * compatibility mode, but most boxes are anymore.
1024 reg0
= apic_read(APIC_LVT0
);
1025 apic_printk(APIC_DEBUG
, "Getting LVT0: %x\n", reg0
);
1026 reg1
= apic_read(APIC_LVT1
);
1027 apic_printk(APIC_DEBUG
, "Getting LVT1: %x\n", reg1
);
1033 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
1035 void __init
sync_Arb_IDs(void)
1038 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
1041 if (modern_apic() || boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
)
1047 apic_wait_icr_idle();
1049 apic_printk(APIC_DEBUG
, "Synchronizing Arb IDs.\n");
1050 apic_write(APIC_ICR
, APIC_DEST_ALLINC
|
1051 APIC_INT_LEVELTRIG
| APIC_DM_INIT
);
1055 * An initial setup of the virtual wire mode.
1057 void __init
init_bsp_APIC(void)
1062 * Don't do the setup now if we have a SMP BIOS as the
1063 * through-I/O-APIC virtual wire mode might be active.
1065 if (smp_found_config
|| !cpu_has_apic
)
1069 * Do not trust the local APIC being empty at bootup.
1076 value
= apic_read(APIC_SPIV
);
1077 value
&= ~APIC_VECTOR_MASK
;
1078 value
|= APIC_SPIV_APIC_ENABLED
;
1080 #ifdef CONFIG_X86_32
1081 /* This bit is reserved on P4/Xeon and should be cleared */
1082 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
) &&
1083 (boot_cpu_data
.x86
== 15))
1084 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
1087 value
|= APIC_SPIV_FOCUS_DISABLED
;
1088 value
|= SPURIOUS_APIC_VECTOR
;
1089 apic_write(APIC_SPIV
, value
);
1092 * Set up the virtual wire mode.
1094 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
1095 value
= APIC_DM_NMI
;
1096 if (!lapic_is_integrated()) /* 82489DX */
1097 value
|= APIC_LVT_LEVEL_TRIGGER
;
1098 apic_write(APIC_LVT1
, value
);
1101 static void __cpuinit
lapic_setup_esr(void)
1103 unsigned int oldvalue
, value
, maxlvt
;
1105 if (!lapic_is_integrated()) {
1106 pr_info("No ESR for 82489DX.\n");
1110 if (apic
->disable_esr
) {
1112 * Something untraceable is creating bad interrupts on
1113 * secondary quads ... for the moment, just leave the
1114 * ESR disabled - we can't do anything useful with the
1115 * errors anyway - mbligh
1117 pr_info("Leaving ESR disabled.\n");
1121 maxlvt
= lapic_get_maxlvt();
1122 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
1123 apic_write(APIC_ESR
, 0);
1124 oldvalue
= apic_read(APIC_ESR
);
1126 /* enables sending errors */
1127 value
= ERROR_APIC_VECTOR
;
1128 apic_write(APIC_LVTERR
, value
);
1131 * spec says clear errors after enabling vector.
1134 apic_write(APIC_ESR
, 0);
1135 value
= apic_read(APIC_ESR
);
1136 if (value
!= oldvalue
)
1137 apic_printk(APIC_VERBOSE
, "ESR value before enabling "
1138 "vector: 0x%08x after: 0x%08x\n",
1144 * setup_local_APIC - setup the local APIC
1146 void __cpuinit
setup_local_APIC(void)
1152 #ifdef CONFIG_X86_IO_APIC
1153 disable_ioapic_setup();
1158 #ifdef CONFIG_X86_32
1159 /* Pound the ESR really hard over the head with a big hammer - mbligh */
1160 if (lapic_is_integrated() && apic
->disable_esr
) {
1161 apic_write(APIC_ESR
, 0);
1162 apic_write(APIC_ESR
, 0);
1163 apic_write(APIC_ESR
, 0);
1164 apic_write(APIC_ESR
, 0);
1171 * Double-check whether this APIC is really registered.
1172 * This is meaningless in clustered apic mode, so we skip it.
1174 if (!apic
->apic_id_registered())
1178 * Intel recommends to set DFR, LDR and TPR before enabling
1179 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
1180 * document number 292116). So here it goes...
1182 apic
->init_apic_ldr();
1185 * Set Task Priority to 'accept all'. We never change this
1188 value
= apic_read(APIC_TASKPRI
);
1189 value
&= ~APIC_TPRI_MASK
;
1190 apic_write(APIC_TASKPRI
, value
);
1193 * After a crash, we no longer service the interrupts and a pending
1194 * interrupt from previous kernel might still have ISR bit set.
1196 * Most probably by now CPU has serviced that pending interrupt and
1197 * it might not have done the ack_APIC_irq() because it thought,
1198 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
1199 * does not clear the ISR bit and cpu thinks it has already serivced
1200 * the interrupt. Hence a vector might get locked. It was noticed
1201 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
1203 for (i
= APIC_ISR_NR
- 1; i
>= 0; i
--) {
1204 value
= apic_read(APIC_ISR
+ i
*0x10);
1205 for (j
= 31; j
>= 0; j
--) {
1212 * Now that we are all set up, enable the APIC
1214 value
= apic_read(APIC_SPIV
);
1215 value
&= ~APIC_VECTOR_MASK
;
1219 value
|= APIC_SPIV_APIC_ENABLED
;
1221 #ifdef CONFIG_X86_32
1223 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1224 * certain networking cards. If high frequency interrupts are
1225 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1226 * entry is masked/unmasked at a high rate as well then sooner or
1227 * later IOAPIC line gets 'stuck', no more interrupts are received
1228 * from the device. If focus CPU is disabled then the hang goes
1231 * [ This bug can be reproduced easily with a level-triggered
1232 * PCI Ne2000 networking cards and PII/PIII processors, dual
1236 * Actually disabling the focus CPU check just makes the hang less
1237 * frequent as it makes the interrupt distributon model be more
1238 * like LRU than MRU (the short-term load is more even across CPUs).
1239 * See also the comment in end_level_ioapic_irq(). --macro
1243 * - enable focus processor (bit==0)
1244 * - 64bit mode always use processor focus
1245 * so no need to set it
1247 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
1251 * Set spurious IRQ vector
1253 value
|= SPURIOUS_APIC_VECTOR
;
1254 apic_write(APIC_SPIV
, value
);
1257 * Set up LVT0, LVT1:
1259 * set up through-local-APIC on the BP's LINT0. This is not
1260 * strictly necessary in pure symmetric-IO mode, but sometimes
1261 * we delegate interrupts to the 8259A.
1264 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1266 value
= apic_read(APIC_LVT0
) & APIC_LVT_MASKED
;
1267 if (!smp_processor_id() && (pic_mode
|| !value
)) {
1268 value
= APIC_DM_EXTINT
;
1269 apic_printk(APIC_VERBOSE
, "enabled ExtINT on CPU#%d\n",
1270 smp_processor_id());
1272 value
= APIC_DM_EXTINT
| APIC_LVT_MASKED
;
1273 apic_printk(APIC_VERBOSE
, "masked ExtINT on CPU#%d\n",
1274 smp_processor_id());
1276 apic_write(APIC_LVT0
, value
);
1279 * only the BP should see the LINT1 NMI signal, obviously.
1281 if (!smp_processor_id())
1282 value
= APIC_DM_NMI
;
1284 value
= APIC_DM_NMI
| APIC_LVT_MASKED
;
1285 if (!lapic_is_integrated()) /* 82489DX */
1286 value
|= APIC_LVT_LEVEL_TRIGGER
;
1287 apic_write(APIC_LVT1
, value
);
1292 void __cpuinit
end_local_APIC_setup(void)
1296 #ifdef CONFIG_X86_32
1299 /* Disable the local apic timer */
1300 value
= apic_read(APIC_LVTT
);
1301 value
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
1302 apic_write(APIC_LVTT
, value
);
1306 setup_apic_nmi_watchdog(NULL
);
1311 void check_x2apic(void)
1315 rdmsr(MSR_IA32_APICBASE
, msr
, msr2
);
1317 if (msr
& X2APIC_ENABLE
) {
1318 pr_info("x2apic enabled by BIOS, switching to x2apic ops\n");
1319 x2apic_preenabled
= x2apic
= 1;
1320 apic_ops
= &x2apic_ops
;
1324 void enable_x2apic(void)
1328 rdmsr(MSR_IA32_APICBASE
, msr
, msr2
);
1329 if (!(msr
& X2APIC_ENABLE
)) {
1330 pr_info("Enabling x2apic\n");
1331 wrmsr(MSR_IA32_APICBASE
, msr
| X2APIC_ENABLE
, 0);
1335 void __init
enable_IR_x2apic(void)
1337 #ifdef CONFIG_INTR_REMAP
1339 unsigned long flags
;
1341 if (!cpu_has_x2apic
)
1344 if (!x2apic_preenabled
&& disable_x2apic
) {
1345 pr_info("Skipped enabling x2apic and Interrupt-remapping "
1346 "because of nox2apic\n");
1350 if (x2apic_preenabled
&& disable_x2apic
)
1351 panic("Bios already enabled x2apic, can't enforce nox2apic");
1353 if (!x2apic_preenabled
&& skip_ioapic_setup
) {
1354 pr_info("Skipped enabling x2apic and Interrupt-remapping "
1355 "because of skipping io-apic setup\n");
1359 ret
= dmar_table_init();
1361 pr_info("dmar_table_init() failed with %d:\n", ret
);
1363 if (x2apic_preenabled
)
1364 panic("x2apic enabled by bios. But IR enabling failed");
1366 pr_info("Not enabling x2apic,Intr-remapping\n");
1370 local_irq_save(flags
);
1373 ret
= save_mask_IO_APIC_setup();
1375 pr_info("Saving IO-APIC state failed: %d\n", ret
);
1379 ret
= enable_intr_remapping(1);
1381 if (ret
&& x2apic_preenabled
) {
1382 local_irq_restore(flags
);
1383 panic("x2apic enabled by bios. But IR enabling failed");
1391 apic_ops
= &x2apic_ops
;
1398 * IR enabling failed
1400 restore_IO_APIC_setup();
1402 reinit_intr_remapped_IO_APIC(x2apic_preenabled
);
1406 local_irq_restore(flags
);
1409 if (!x2apic_preenabled
)
1410 pr_info("Enabled x2apic and interrupt-remapping\n");
1412 pr_info("Enabled Interrupt-remapping\n");
1414 pr_err("Failed to enable Interrupt-remapping and x2apic\n");
1416 if (!cpu_has_x2apic
)
1419 if (x2apic_preenabled
)
1420 panic("x2apic enabled prior OS handover,"
1421 " enable CONFIG_INTR_REMAP");
1423 pr_info("Enable CONFIG_INTR_REMAP for enabling intr-remapping "
1429 #endif /* HAVE_X2APIC */
1431 #ifdef CONFIG_X86_64
1433 * Detect and enable local APICs on non-SMP boards.
1434 * Original code written by Keir Fraser.
1435 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1436 * not correctly set up (usually the APIC timer won't work etc.)
1438 static int __init
detect_init_APIC(void)
1440 if (!cpu_has_apic
) {
1441 pr_info("No local APIC present\n");
1445 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
1446 boot_cpu_physical_apicid
= 0;
1451 * Detect and initialize APIC
1453 static int __init
detect_init_APIC(void)
1457 /* Disabled by kernel option? */
1461 switch (boot_cpu_data
.x86_vendor
) {
1462 case X86_VENDOR_AMD
:
1463 if ((boot_cpu_data
.x86
== 6 && boot_cpu_data
.x86_model
> 1) ||
1464 (boot_cpu_data
.x86
== 15))
1467 case X86_VENDOR_INTEL
:
1468 if (boot_cpu_data
.x86
== 6 || boot_cpu_data
.x86
== 15 ||
1469 (boot_cpu_data
.x86
== 5 && cpu_has_apic
))
1476 if (!cpu_has_apic
) {
1478 * Over-ride BIOS and try to enable the local APIC only if
1479 * "lapic" specified.
1481 if (!force_enable_local_apic
) {
1482 pr_info("Local APIC disabled by BIOS -- "
1483 "you can enable it with \"lapic\"\n");
1487 * Some BIOSes disable the local APIC in the APIC_BASE
1488 * MSR. This can only be done in software for Intel P6 or later
1489 * and AMD K7 (Model > 1) or later.
1491 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1492 if (!(l
& MSR_IA32_APICBASE_ENABLE
)) {
1493 pr_info("Local APIC disabled by BIOS -- reenabling.\n");
1494 l
&= ~MSR_IA32_APICBASE_BASE
;
1495 l
|= MSR_IA32_APICBASE_ENABLE
| APIC_DEFAULT_PHYS_BASE
;
1496 wrmsr(MSR_IA32_APICBASE
, l
, h
);
1497 enabled_via_apicbase
= 1;
1501 * The APIC feature bit should now be enabled
1504 features
= cpuid_edx(1);
1505 if (!(features
& (1 << X86_FEATURE_APIC
))) {
1506 pr_warning("Could not enable APIC!\n");
1509 set_cpu_cap(&boot_cpu_data
, X86_FEATURE_APIC
);
1510 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
1512 /* The BIOS may have set up the APIC at some other address */
1513 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1514 if (l
& MSR_IA32_APICBASE_ENABLE
)
1515 mp_lapic_addr
= l
& MSR_IA32_APICBASE_BASE
;
1517 pr_info("Found and enabled local APIC!\n");
1524 pr_info("No local APIC present or hardware disabled\n");
1529 #ifdef CONFIG_X86_64
1530 void __init
early_init_lapic_mapping(void)
1532 unsigned long phys_addr
;
1535 * If no local APIC can be found then go out
1536 * : it means there is no mpatable and MADT
1538 if (!smp_found_config
)
1541 phys_addr
= mp_lapic_addr
;
1543 set_fixmap_nocache(FIX_APIC_BASE
, phys_addr
);
1544 apic_printk(APIC_VERBOSE
, "mapped APIC to %16lx (%16lx)\n",
1545 APIC_BASE
, phys_addr
);
1548 * Fetch the APIC ID of the BSP in case we have a
1549 * default configuration (or the MP table is broken).
1551 boot_cpu_physical_apicid
= read_apic_id();
1556 * init_apic_mappings - initialize APIC mappings
1558 void __init
init_apic_mappings(void)
1562 boot_cpu_physical_apicid
= read_apic_id();
1568 * If no local APIC can be found then set up a fake all
1569 * zeroes page to simulate the local APIC and another
1570 * one for the IO-APIC.
1572 if (!smp_found_config
&& detect_init_APIC()) {
1573 apic_phys
= (unsigned long) alloc_bootmem_pages(PAGE_SIZE
);
1574 apic_phys
= __pa(apic_phys
);
1576 apic_phys
= mp_lapic_addr
;
1578 set_fixmap_nocache(FIX_APIC_BASE
, apic_phys
);
1579 apic_printk(APIC_VERBOSE
, "mapped APIC to %08lx (%08lx)\n",
1580 APIC_BASE
, apic_phys
);
1583 * Fetch the APIC ID of the BSP in case we have a
1584 * default configuration (or the MP table is broken).
1586 if (boot_cpu_physical_apicid
== -1U)
1587 boot_cpu_physical_apicid
= read_apic_id();
1591 * This initializes the IO-APIC and APIC hardware if this is
1594 int apic_version
[MAX_APICS
];
1596 int __init
APIC_init_uniprocessor(void)
1599 pr_info("Apic disabled\n");
1602 #ifdef CONFIG_X86_64
1603 if (!cpu_has_apic
) {
1605 pr_info("Apic disabled by BIOS\n");
1609 if (!smp_found_config
&& !cpu_has_apic
)
1613 * Complain if the BIOS pretends there is one.
1615 if (!cpu_has_apic
&&
1616 APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
])) {
1617 pr_err("BIOS bug, local APIC 0x%x not detected!...\n",
1618 boot_cpu_physical_apicid
);
1619 clear_cpu_cap(&boot_cpu_data
, X86_FEATURE_APIC
);
1627 #ifdef CONFIG_X86_64
1628 setup_apic_routing();
1631 verify_local_APIC();
1634 #ifdef CONFIG_X86_64
1635 apic_write(APIC_ID
, SET_APIC_ID(boot_cpu_physical_apicid
));
1638 * Hack: In case of kdump, after a crash, kernel might be booting
1639 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
1640 * might be zero if read from MP tables. Get it from LAPIC.
1642 # ifdef CONFIG_CRASH_DUMP
1643 boot_cpu_physical_apicid
= read_apic_id();
1646 physid_set_mask_of_physid(boot_cpu_physical_apicid
, &phys_cpu_present_map
);
1649 #ifdef CONFIG_X86_64
1651 * Now enable IO-APICs, actually call clear_IO_APIC
1652 * We need clear_IO_APIC before enabling vector on BP
1654 if (!skip_ioapic_setup
&& nr_ioapics
)
1658 #ifdef CONFIG_X86_IO_APIC
1659 if (!smp_found_config
|| skip_ioapic_setup
|| !nr_ioapics
)
1661 localise_nmi_watchdog();
1662 end_local_APIC_setup();
1664 #ifdef CONFIG_X86_IO_APIC
1665 if (smp_found_config
&& !skip_ioapic_setup
&& nr_ioapics
)
1667 # ifdef CONFIG_X86_64
1673 #ifdef CONFIG_X86_64
1674 setup_boot_APIC_clock();
1675 check_nmi_watchdog();
1684 * Local APIC interrupts
1688 * This interrupt should _never_ happen with our APIC/SMP architecture
1690 void smp_spurious_interrupt(struct pt_regs
*regs
)
1697 * Check if this really is a spurious interrupt and ACK it
1698 * if it is a vectored one. Just in case...
1699 * Spurious interrupts should not be ACKed.
1701 v
= apic_read(APIC_ISR
+ ((SPURIOUS_APIC_VECTOR
& ~0x1f) >> 1));
1702 if (v
& (1 << (SPURIOUS_APIC_VECTOR
& 0x1f)))
1705 inc_irq_stat(irq_spurious_count
);
1707 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1708 pr_info("spurious APIC interrupt on CPU#%d, "
1709 "should never happen.\n", smp_processor_id());
1714 * This interrupt should never happen with our APIC/SMP architecture
1716 void smp_error_interrupt(struct pt_regs
*regs
)
1722 /* First tickle the hardware, only then report what went on. -- REW */
1723 v
= apic_read(APIC_ESR
);
1724 apic_write(APIC_ESR
, 0);
1725 v1
= apic_read(APIC_ESR
);
1727 atomic_inc(&irq_err_count
);
1730 * Here is what the APIC error bits mean:
1732 * 1: Receive CS error
1733 * 2: Send accept error
1734 * 3: Receive accept error
1736 * 5: Send illegal vector
1737 * 6: Received illegal vector
1738 * 7: Illegal register address
1740 pr_debug("APIC error on CPU%d: %02x(%02x)\n",
1741 smp_processor_id(), v
, v1
);
1746 * connect_bsp_APIC - attach the APIC to the interrupt system
1748 void __init
connect_bsp_APIC(void)
1750 #ifdef CONFIG_X86_32
1753 * Do not trust the local APIC being empty at bootup.
1757 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
1758 * local APIC to INT and NMI lines.
1760 apic_printk(APIC_VERBOSE
, "leaving PIC mode, "
1761 "enabling APIC mode.\n");
1770 * disconnect_bsp_APIC - detach the APIC from the interrupt system
1771 * @virt_wire_setup: indicates, whether virtual wire mode is selected
1773 * Virtual wire mode is necessary to deliver legacy interrupts even when the
1776 void disconnect_bsp_APIC(int virt_wire_setup
)
1780 #ifdef CONFIG_X86_32
1783 * Put the board back into PIC mode (has an effect only on
1784 * certain older boards). Note that APIC interrupts, including
1785 * IPIs, won't work beyond this point! The only exception are
1788 apic_printk(APIC_VERBOSE
, "disabling APIC mode, "
1789 "entering PIC mode.\n");
1796 /* Go back to Virtual Wire compatibility mode */
1798 /* For the spurious interrupt use vector F, and enable it */
1799 value
= apic_read(APIC_SPIV
);
1800 value
&= ~APIC_VECTOR_MASK
;
1801 value
|= APIC_SPIV_APIC_ENABLED
;
1803 apic_write(APIC_SPIV
, value
);
1805 if (!virt_wire_setup
) {
1807 * For LVT0 make it edge triggered, active high,
1808 * external and enabled
1810 value
= apic_read(APIC_LVT0
);
1811 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1812 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1813 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1814 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1815 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_EXTINT
);
1816 apic_write(APIC_LVT0
, value
);
1819 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
1823 * For LVT1 make it edge triggered, active high,
1826 value
= apic_read(APIC_LVT1
);
1827 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1828 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1829 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1830 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1831 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_NMI
);
1832 apic_write(APIC_LVT1
, value
);
1835 void __cpuinit
generic_processor_info(int apicid
, int version
)
1842 if (version
== 0x0) {
1843 pr_warning("BIOS bug, APIC version is 0 for CPU#%d! "
1844 "fixing up to 0x10. (tell your hw vendor)\n",
1848 apic_version
[apicid
] = version
;
1850 if (num_processors
>= nr_cpu_ids
) {
1851 int max
= nr_cpu_ids
;
1852 int thiscpu
= max
+ disabled_cpus
;
1855 "ACPI: NR_CPUS/possible_cpus limit of %i reached."
1856 " Processor %d/0x%x ignored.\n", max
, thiscpu
, apicid
);
1863 cpu
= cpumask_next_zero(-1, cpu_present_mask
);
1865 if (version
!= apic_version
[boot_cpu_physical_apicid
])
1867 "ACPI: apic version mismatch, bootcpu: %x cpu %d: %x\n",
1868 apic_version
[boot_cpu_physical_apicid
], cpu
, version
);
1870 physid_set(apicid
, phys_cpu_present_map
);
1871 if (apicid
== boot_cpu_physical_apicid
) {
1873 * x86_bios_cpu_apicid is required to have processors listed
1874 * in same order as logical cpu numbers. Hence the first
1875 * entry is BSP, and so on.
1879 if (apicid
> max_physical_apicid
)
1880 max_physical_apicid
= apicid
;
1882 #ifdef CONFIG_X86_32
1884 * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y
1885 * but we need to work other dependencies like SMP_SUSPEND etc
1886 * before this can be done without some confusion.
1887 * if (CPU_HOTPLUG_ENABLED || num_processors > 8)
1888 * - Ashok Raj <ashok.raj@intel.com>
1890 if (max_physical_apicid
>= 8) {
1891 switch (boot_cpu_data
.x86_vendor
) {
1892 case X86_VENDOR_INTEL
:
1893 if (!APIC_XAPIC(version
)) {
1897 /* If P4 and above fall through */
1898 case X86_VENDOR_AMD
:
1904 #if defined(CONFIG_X86_SMP) || defined(CONFIG_X86_64)
1905 early_per_cpu(x86_cpu_to_apicid
, cpu
) = apicid
;
1906 early_per_cpu(x86_bios_cpu_apicid
, cpu
) = apicid
;
1909 set_cpu_possible(cpu
, true);
1910 set_cpu_present(cpu
, true);
1913 #ifdef CONFIG_X86_64
1914 int hard_smp_processor_id(void)
1916 return read_apic_id();
1927 * 'active' is true if the local APIC was enabled by us and
1928 * not the BIOS; this signifies that we are also responsible
1929 * for disabling it before entering apm/acpi suspend
1932 /* r/w apic fields */
1933 unsigned int apic_id
;
1934 unsigned int apic_taskpri
;
1935 unsigned int apic_ldr
;
1936 unsigned int apic_dfr
;
1937 unsigned int apic_spiv
;
1938 unsigned int apic_lvtt
;
1939 unsigned int apic_lvtpc
;
1940 unsigned int apic_lvt0
;
1941 unsigned int apic_lvt1
;
1942 unsigned int apic_lvterr
;
1943 unsigned int apic_tmict
;
1944 unsigned int apic_tdcr
;
1945 unsigned int apic_thmr
;
1948 static int lapic_suspend(struct sys_device
*dev
, pm_message_t state
)
1950 unsigned long flags
;
1953 if (!apic_pm_state
.active
)
1956 maxlvt
= lapic_get_maxlvt();
1958 apic_pm_state
.apic_id
= apic_read(APIC_ID
);
1959 apic_pm_state
.apic_taskpri
= apic_read(APIC_TASKPRI
);
1960 apic_pm_state
.apic_ldr
= apic_read(APIC_LDR
);
1961 apic_pm_state
.apic_dfr
= apic_read(APIC_DFR
);
1962 apic_pm_state
.apic_spiv
= apic_read(APIC_SPIV
);
1963 apic_pm_state
.apic_lvtt
= apic_read(APIC_LVTT
);
1965 apic_pm_state
.apic_lvtpc
= apic_read(APIC_LVTPC
);
1966 apic_pm_state
.apic_lvt0
= apic_read(APIC_LVT0
);
1967 apic_pm_state
.apic_lvt1
= apic_read(APIC_LVT1
);
1968 apic_pm_state
.apic_lvterr
= apic_read(APIC_LVTERR
);
1969 apic_pm_state
.apic_tmict
= apic_read(APIC_TMICT
);
1970 apic_pm_state
.apic_tdcr
= apic_read(APIC_TDCR
);
1971 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
1973 apic_pm_state
.apic_thmr
= apic_read(APIC_LVTTHMR
);
1976 local_irq_save(flags
);
1977 disable_local_APIC();
1978 local_irq_restore(flags
);
1982 static int lapic_resume(struct sys_device
*dev
)
1985 unsigned long flags
;
1988 if (!apic_pm_state
.active
)
1991 maxlvt
= lapic_get_maxlvt();
1993 local_irq_save(flags
);
2002 * Make sure the APICBASE points to the right address
2004 * FIXME! This will be wrong if we ever support suspend on
2005 * SMP! We'll need to do this as part of the CPU restore!
2007 rdmsr(MSR_IA32_APICBASE
, l
, h
);
2008 l
&= ~MSR_IA32_APICBASE_BASE
;
2009 l
|= MSR_IA32_APICBASE_ENABLE
| mp_lapic_addr
;
2010 wrmsr(MSR_IA32_APICBASE
, l
, h
);
2013 apic_write(APIC_LVTERR
, ERROR_APIC_VECTOR
| APIC_LVT_MASKED
);
2014 apic_write(APIC_ID
, apic_pm_state
.apic_id
);
2015 apic_write(APIC_DFR
, apic_pm_state
.apic_dfr
);
2016 apic_write(APIC_LDR
, apic_pm_state
.apic_ldr
);
2017 apic_write(APIC_TASKPRI
, apic_pm_state
.apic_taskpri
);
2018 apic_write(APIC_SPIV
, apic_pm_state
.apic_spiv
);
2019 apic_write(APIC_LVT0
, apic_pm_state
.apic_lvt0
);
2020 apic_write(APIC_LVT1
, apic_pm_state
.apic_lvt1
);
2021 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
2023 apic_write(APIC_LVTTHMR
, apic_pm_state
.apic_thmr
);
2026 apic_write(APIC_LVTPC
, apic_pm_state
.apic_lvtpc
);
2027 apic_write(APIC_LVTT
, apic_pm_state
.apic_lvtt
);
2028 apic_write(APIC_TDCR
, apic_pm_state
.apic_tdcr
);
2029 apic_write(APIC_TMICT
, apic_pm_state
.apic_tmict
);
2030 apic_write(APIC_ESR
, 0);
2031 apic_read(APIC_ESR
);
2032 apic_write(APIC_LVTERR
, apic_pm_state
.apic_lvterr
);
2033 apic_write(APIC_ESR
, 0);
2034 apic_read(APIC_ESR
);
2036 local_irq_restore(flags
);
2042 * This device has no shutdown method - fully functioning local APICs
2043 * are needed on every CPU up until machine_halt/restart/poweroff.
2046 static struct sysdev_class lapic_sysclass
= {
2048 .resume
= lapic_resume
,
2049 .suspend
= lapic_suspend
,
2052 static struct sys_device device_lapic
= {
2054 .cls
= &lapic_sysclass
,
2057 static void __cpuinit
apic_pm_activate(void)
2059 apic_pm_state
.active
= 1;
2062 static int __init
init_lapic_sysfs(void)
2068 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
2070 error
= sysdev_class_register(&lapic_sysclass
);
2072 error
= sysdev_register(&device_lapic
);
2075 device_initcall(init_lapic_sysfs
);
2077 #else /* CONFIG_PM */
2079 static void apic_pm_activate(void) { }
2081 #endif /* CONFIG_PM */
2083 #ifdef CONFIG_X86_64
2085 * apic_is_clustered_box() -- Check if we can expect good TSC
2087 * Thus far, the major user of this is IBM's Summit2 series:
2089 * Clustered boxes may have unsynced TSC problems if they are
2090 * multi-chassis. Use available data to take a good guess.
2091 * If in doubt, go HPET.
2093 __cpuinit
int apic_is_clustered_box(void)
2095 int i
, clusters
, zeros
;
2097 u16
*bios_cpu_apicid
;
2098 DECLARE_BITMAP(clustermap
, NUM_APIC_CLUSTERS
);
2101 * there is not this kind of box with AMD CPU yet.
2102 * Some AMD box with quadcore cpu and 8 sockets apicid
2103 * will be [4, 0x23] or [8, 0x27] could be thought to
2104 * vsmp box still need checking...
2106 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
) && !is_vsmp_box())
2109 bios_cpu_apicid
= early_per_cpu_ptr(x86_bios_cpu_apicid
);
2110 bitmap_zero(clustermap
, NUM_APIC_CLUSTERS
);
2112 for (i
= 0; i
< nr_cpu_ids
; i
++) {
2113 /* are we being called early in kernel startup? */
2114 if (bios_cpu_apicid
) {
2115 id
= bios_cpu_apicid
[i
];
2116 } else if (i
< nr_cpu_ids
) {
2118 id
= per_cpu(x86_bios_cpu_apicid
, i
);
2124 if (id
!= BAD_APICID
)
2125 __set_bit(APIC_CLUSTERID(id
), clustermap
);
2128 /* Problem: Partially populated chassis may not have CPUs in some of
2129 * the APIC clusters they have been allocated. Only present CPUs have
2130 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap.
2131 * Since clusters are allocated sequentially, count zeros only if
2132 * they are bounded by ones.
2136 for (i
= 0; i
< NUM_APIC_CLUSTERS
; i
++) {
2137 if (test_bit(i
, clustermap
)) {
2138 clusters
+= 1 + zeros
;
2144 /* ScaleMP vSMPowered boxes have one cluster per board and TSCs are
2145 * not guaranteed to be synced between boards
2147 if (is_vsmp_box() && clusters
> 1)
2151 * If clusters > 2, then should be multi-chassis.
2152 * May have to revisit this when multi-core + hyperthreaded CPUs come
2153 * out, but AFAIK this will work even for them.
2155 return (clusters
> 2);
2160 * APIC command line parameters
2162 static int __init
setup_disableapic(char *arg
)
2165 setup_clear_cpu_cap(X86_FEATURE_APIC
);
2168 early_param("disableapic", setup_disableapic
);
2170 /* same as disableapic, for compatibility */
2171 static int __init
setup_nolapic(char *arg
)
2173 return setup_disableapic(arg
);
2175 early_param("nolapic", setup_nolapic
);
2177 static int __init
parse_lapic_timer_c2_ok(char *arg
)
2179 local_apic_timer_c2_ok
= 1;
2182 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok
);
2184 static int __init
parse_disable_apic_timer(char *arg
)
2186 disable_apic_timer
= 1;
2189 early_param("noapictimer", parse_disable_apic_timer
);
2191 static int __init
parse_nolapic_timer(char *arg
)
2193 disable_apic_timer
= 1;
2196 early_param("nolapic_timer", parse_nolapic_timer
);
2198 static int __init
apic_set_verbosity(char *arg
)
2201 #ifdef CONFIG_X86_64
2202 skip_ioapic_setup
= 0;
2208 if (strcmp("debug", arg
) == 0)
2209 apic_verbosity
= APIC_DEBUG
;
2210 else if (strcmp("verbose", arg
) == 0)
2211 apic_verbosity
= APIC_VERBOSE
;
2213 pr_warning("APIC Verbosity level %s not recognised"
2214 " use apic=verbose or apic=debug\n", arg
);
2220 early_param("apic", apic_set_verbosity
);
2222 static int __init
lapic_insert_resource(void)
2227 /* Put local APIC into the resource map. */
2228 lapic_resource
.start
= apic_phys
;
2229 lapic_resource
.end
= lapic_resource
.start
+ PAGE_SIZE
- 1;
2230 insert_resource(&iomem_resource
, &lapic_resource
);
2236 * need call insert after e820_reserve_resources()
2237 * that is using request_resource
2239 late_initcall(lapic_insert_resource
);