2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/bootmem.h>
22 #include <linux/interrupt.h>
23 #include <linux/mc146818rtc.h>
24 #include <linux/kernel_stat.h>
25 #include <linux/sysdev.h>
26 #include <linux/ioport.h>
27 #include <linux/cpu.h>
28 #include <linux/clockchips.h>
29 #include <linux/acpi_pmtmr.h>
30 #include <linux/module.h>
31 #include <linux/dmi.h>
32 #include <linux/dmar.h>
34 #include <asm/atomic.h>
37 #include <asm/mpspec.h>
39 #include <asm/arch_hooks.h>
41 #include <asm/pgalloc.h>
42 #include <asm/i8253.h>
45 #include <asm/proto.h>
46 #include <asm/timex.h>
48 #include <asm/i8259.h>
50 #include <mach_apic.h>
51 #include <mach_apicdef.h>
57 #if ((SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F)
58 # error SPURIOUS_APIC_VECTOR definition error
63 * Knob to control our willingness to enable the local APIC.
67 static int force_enable_local_apic
;
69 * APIC command line parameters
71 static int __init
parse_lapic(char *arg
)
73 force_enable_local_apic
= 1;
76 early_param("lapic", parse_lapic
);
77 /* Local APIC was disabled by the BIOS and enabled by the kernel */
78 static int enabled_via_apicbase
;
83 static int apic_calibrate_pmtmr __initdata
;
84 static __init
int setup_apicpmtimer(char *s
)
86 apic_calibrate_pmtmr
= 1;
90 __setup("apicpmtimer", setup_apicpmtimer
);
93 unsigned long mp_lapic_addr
;
95 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
96 static int disable_apic_timer __cpuinitdata
;
97 /* Local APIC timer works in C2 */
98 int local_apic_timer_c2_ok
;
99 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok
);
101 int first_system_vector
= 0xfe;
103 char system_vectors
[NR_VECTORS
] = { [0 ... NR_VECTORS
-1] = SYS_VECTOR_FREE
};
106 * Debug level, exported for io_apic.c
108 unsigned int apic_verbosity
;
112 /* Have we found an MP table */
113 int smp_found_config
;
115 static struct resource lapic_resource
= {
116 .name
= "Local APIC",
117 .flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
,
120 static unsigned int calibration_result
;
122 static int lapic_next_event(unsigned long delta
,
123 struct clock_event_device
*evt
);
124 static void lapic_timer_setup(enum clock_event_mode mode
,
125 struct clock_event_device
*evt
);
126 static void lapic_timer_broadcast(cpumask_t mask
);
127 static void apic_pm_activate(void);
130 * The local apic timer can be used for any function which is CPU local.
132 static struct clock_event_device lapic_clockevent
= {
134 .features
= CLOCK_EVT_FEAT_PERIODIC
| CLOCK_EVT_FEAT_ONESHOT
135 | CLOCK_EVT_FEAT_C3STOP
| CLOCK_EVT_FEAT_DUMMY
,
137 .set_mode
= lapic_timer_setup
,
138 .set_next_event
= lapic_next_event
,
139 .broadcast
= lapic_timer_broadcast
,
143 static DEFINE_PER_CPU(struct clock_event_device
, lapic_events
);
145 static unsigned long apic_phys
;
148 * Get the LAPIC version
150 static inline int lapic_get_version(void)
152 return GET_APIC_VERSION(apic_read(APIC_LVR
));
156 * Check, if the APIC is integrated or a separate chip
158 static inline int lapic_is_integrated(void)
163 return APIC_INTEGRATED(lapic_get_version());
168 * Check, whether this is a modern or a first generation APIC
170 static int modern_apic(void)
172 /* AMD systems use old APIC versions, so check the CPU */
173 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
&&
174 boot_cpu_data
.x86
>= 0xf)
176 return lapic_get_version() >= 0x14;
180 * Paravirt kernels also might be using these below ops. So we still
181 * use generic apic_read()/apic_write(), which might be pointing to different
182 * ops in PARAVIRT case.
184 void xapic_wait_icr_idle(void)
186 while (apic_read(APIC_ICR
) & APIC_ICR_BUSY
)
190 u32
safe_xapic_wait_icr_idle(void)
197 send_status
= apic_read(APIC_ICR
) & APIC_ICR_BUSY
;
201 } while (timeout
++ < 1000);
206 void xapic_icr_write(u32 low
, u32 id
)
208 apic_write(APIC_ICR2
, SET_APIC_DEST_FIELD(id
));
209 apic_write(APIC_ICR
, low
);
212 u64
xapic_icr_read(void)
216 icr2
= apic_read(APIC_ICR2
);
217 icr1
= apic_read(APIC_ICR
);
219 return icr1
| ((u64
)icr2
<< 32);
222 static struct apic_ops xapic_ops
= {
223 .read
= native_apic_mem_read
,
224 .write
= native_apic_mem_write
,
225 .icr_read
= xapic_icr_read
,
226 .icr_write
= xapic_icr_write
,
227 .wait_icr_idle
= xapic_wait_icr_idle
,
228 .safe_wait_icr_idle
= safe_xapic_wait_icr_idle
,
231 struct apic_ops __read_mostly
*apic_ops
= &xapic_ops
;
232 EXPORT_SYMBOL_GPL(apic_ops
);
235 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
237 void __cpuinit
enable_NMI_through_LVT0(void)
241 /* unmask and set to NMI */
244 /* Level triggered for 82489DX (32bit mode) */
245 if (!lapic_is_integrated())
246 v
|= APIC_LVT_LEVEL_TRIGGER
;
248 apic_write(APIC_LVT0
, v
);
253 * get_physical_broadcast - Get number of physical broadcast IDs
255 int get_physical_broadcast(void)
257 return modern_apic() ? 0xff : 0xf;
262 * lapic_get_maxlvt - get the maximum number of local vector table entries
264 int lapic_get_maxlvt(void)
268 v
= apic_read(APIC_LVR
);
270 * - we always have APIC integrated on 64bit mode
271 * - 82489DXs do not report # of LVT entries
273 return APIC_INTEGRATED(GET_APIC_VERSION(v
)) ? GET_APIC_MAXLVT(v
) : 2;
282 #define APIC_DIVISOR 1
284 #define APIC_DIVISOR 16
288 * This function sets up the local APIC timer, with a timeout of
289 * 'clocks' APIC bus clock. During calibration we actually call
290 * this function twice on the boot CPU, once with a bogus timeout
291 * value, second time for real. The other (noncalibrating) CPUs
292 * call this function only once, with the real, calibrated value.
294 * We do reads before writes even if unnecessary, to get around the
295 * P5 APIC double write bug.
297 static void __setup_APIC_LVTT(unsigned int clocks
, int oneshot
, int irqen
)
299 unsigned int lvtt_value
, tmp_value
;
301 lvtt_value
= LOCAL_TIMER_VECTOR
;
303 lvtt_value
|= APIC_LVT_TIMER_PERIODIC
;
304 if (!lapic_is_integrated())
305 lvtt_value
|= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV
);
308 lvtt_value
|= APIC_LVT_MASKED
;
310 apic_write(APIC_LVTT
, lvtt_value
);
315 tmp_value
= apic_read(APIC_TDCR
);
316 apic_write(APIC_TDCR
,
317 (tmp_value
& ~(APIC_TDR_DIV_1
| APIC_TDR_DIV_TMBASE
)) |
321 apic_write(APIC_TMICT
, clocks
/ APIC_DIVISOR
);
325 * Setup extended LVT, AMD specific (K8, family 10h)
327 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
328 * MCE interrupts are supported. Thus MCE offset must be set to 0.
330 * If mask=1, the LVT entry does not generate interrupts while mask=0
331 * enables the vector. See also the BKDGs.
334 #define APIC_EILVT_LVTOFF_MCE 0
335 #define APIC_EILVT_LVTOFF_IBS 1
337 static void setup_APIC_eilvt(u8 lvt_off
, u8 vector
, u8 msg_type
, u8 mask
)
339 unsigned long reg
= (lvt_off
<< 4) + APIC_EILVT0
;
340 unsigned int v
= (mask
<< 16) | (msg_type
<< 8) | vector
;
345 u8
setup_APIC_eilvt_mce(u8 vector
, u8 msg_type
, u8 mask
)
347 setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE
, vector
, msg_type
, mask
);
348 return APIC_EILVT_LVTOFF_MCE
;
351 u8
setup_APIC_eilvt_ibs(u8 vector
, u8 msg_type
, u8 mask
)
353 setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS
, vector
, msg_type
, mask
);
354 return APIC_EILVT_LVTOFF_IBS
;
356 EXPORT_SYMBOL_GPL(setup_APIC_eilvt_ibs
);
359 * Program the next event, relative to now
361 static int lapic_next_event(unsigned long delta
,
362 struct clock_event_device
*evt
)
364 apic_write(APIC_TMICT
, delta
);
369 * Setup the lapic timer in periodic or oneshot mode
371 static void lapic_timer_setup(enum clock_event_mode mode
,
372 struct clock_event_device
*evt
)
377 /* Lapic used as dummy for broadcast ? */
378 if (evt
->features
& CLOCK_EVT_FEAT_DUMMY
)
381 local_irq_save(flags
);
384 case CLOCK_EVT_MODE_PERIODIC
:
385 case CLOCK_EVT_MODE_ONESHOT
:
386 __setup_APIC_LVTT(calibration_result
,
387 mode
!= CLOCK_EVT_MODE_PERIODIC
, 1);
389 case CLOCK_EVT_MODE_UNUSED
:
390 case CLOCK_EVT_MODE_SHUTDOWN
:
391 v
= apic_read(APIC_LVTT
);
392 v
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
393 apic_write(APIC_LVTT
, v
);
395 case CLOCK_EVT_MODE_RESUME
:
396 /* Nothing to do here */
400 local_irq_restore(flags
);
404 * Local APIC timer broadcast function
406 static void lapic_timer_broadcast(cpumask_t mask
)
409 send_IPI_mask(mask
, LOCAL_TIMER_VECTOR
);
414 * Setup the local APIC timer for this CPU. Copy the initilized values
415 * of the boot CPU and register the clock event in the framework.
417 static void __cpuinit
setup_APIC_timer(void)
419 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
421 memcpy(levt
, &lapic_clockevent
, sizeof(*levt
));
422 levt
->cpumask
= cpumask_of_cpu(smp_processor_id());
424 clockevents_register_device(levt
);
429 * In this function we calibrate APIC bus clocks to the external
430 * timer. Unfortunately we cannot use jiffies and the timer irq
431 * to calibrate, since some later bootup code depends on getting
432 * the first irq? Ugh.
434 * We want to do the calibration only once since we
435 * want to have local timer irqs syncron. CPUs connected
436 * by the same APIC bus have the very same bus frequency.
437 * And we want to have irqs off anyways, no accidental
441 #define TICK_COUNT 100000000
443 static int __init
calibrate_APIC_clock(void)
445 unsigned apic
, apic_start
;
446 unsigned long tsc
, tsc_start
;
452 * Put whatever arbitrary (but long enough) timeout
453 * value into the APIC clock, we just want to get the
454 * counter running for calibration.
456 * No interrupt enable !
458 __setup_APIC_LVTT(250000000, 0, 0);
460 apic_start
= apic_read(APIC_TMCCT
);
461 #ifdef CONFIG_X86_PM_TIMER
462 if (apic_calibrate_pmtmr
&& pmtmr_ioport
) {
463 pmtimer_wait(5000); /* 5ms wait */
464 apic
= apic_read(APIC_TMCCT
);
465 result
= (apic_start
- apic
) * 1000L / 5;
472 apic
= apic_read(APIC_TMCCT
);
474 } while ((tsc
- tsc_start
) < TICK_COUNT
&&
475 (apic_start
- apic
) < TICK_COUNT
);
477 result
= (apic_start
- apic
) * 1000L * tsc_khz
/
483 printk(KERN_DEBUG
"APIC timer calibration result %d\n", result
);
485 printk(KERN_INFO
"Detected %d.%03d MHz APIC timer.\n",
486 result
/ 1000 / 1000, result
/ 1000 % 1000);
488 /* Calculate the scaled math multiplication factor */
489 lapic_clockevent
.mult
= div_sc(result
, NSEC_PER_SEC
,
490 lapic_clockevent
.shift
);
491 lapic_clockevent
.max_delta_ns
=
492 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent
);
493 lapic_clockevent
.min_delta_ns
=
494 clockevent_delta2ns(0xF, &lapic_clockevent
);
496 calibration_result
= (result
* APIC_DIVISOR
) / HZ
;
499 * Do a sanity check on the APIC calibration result
501 if (calibration_result
< (1000000 / HZ
)) {
503 "APIC frequency too slow, disabling apic timer\n");
512 * In this functions we calibrate APIC bus clocks to the external timer.
514 * We want to do the calibration only once since we want to have local timer
515 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
518 * This was previously done by reading the PIT/HPET and waiting for a wrap
519 * around to find out, that a tick has elapsed. I have a box, where the PIT
520 * readout is broken, so it never gets out of the wait loop again. This was
521 * also reported by others.
523 * Monitoring the jiffies value is inaccurate and the clockevents
524 * infrastructure allows us to do a simple substitution of the interrupt
527 * The calibration routine also uses the pm_timer when possible, as the PIT
528 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
529 * back to normal later in the boot process).
532 #define LAPIC_CAL_LOOPS (HZ/10)
534 static __initdata
int lapic_cal_loops
= -1;
535 static __initdata
long lapic_cal_t1
, lapic_cal_t2
;
536 static __initdata
unsigned long long lapic_cal_tsc1
, lapic_cal_tsc2
;
537 static __initdata
unsigned long lapic_cal_pm1
, lapic_cal_pm2
;
538 static __initdata
unsigned long lapic_cal_j1
, lapic_cal_j2
;
541 * Temporary interrupt handler.
543 static void __init
lapic_cal_handler(struct clock_event_device
*dev
)
545 unsigned long long tsc
= 0;
546 long tapic
= apic_read(APIC_TMCCT
);
547 unsigned long pm
= acpi_pm_read_early();
552 switch (lapic_cal_loops
++) {
554 lapic_cal_t1
= tapic
;
555 lapic_cal_tsc1
= tsc
;
557 lapic_cal_j1
= jiffies
;
560 case LAPIC_CAL_LOOPS
:
561 lapic_cal_t2
= tapic
;
562 lapic_cal_tsc2
= tsc
;
563 if (pm
< lapic_cal_pm1
)
564 pm
+= ACPI_PM_OVRRUN
;
566 lapic_cal_j2
= jiffies
;
571 static int __init
calibrate_APIC_clock(void)
573 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
574 const long pm_100ms
= PMTMR_TICKS_PER_SEC
/10;
575 const long pm_thresh
= pm_100ms
/100;
576 void (*real_handler
)(struct clock_event_device
*dev
);
577 unsigned long deltaj
;
579 int pm_referenced
= 0;
583 /* Replace the global interrupt handler */
584 real_handler
= global_clock_event
->event_handler
;
585 global_clock_event
->event_handler
= lapic_cal_handler
;
588 * Setup the APIC counter to 1e9. There is no way the lapic
589 * can underflow in the 100ms detection time frame
591 __setup_APIC_LVTT(1000000000, 0, 0);
593 /* Let the interrupts run */
596 while (lapic_cal_loops
<= LAPIC_CAL_LOOPS
)
601 /* Restore the real event handler */
602 global_clock_event
->event_handler
= real_handler
;
604 /* Build delta t1-t2 as apic timer counts down */
605 delta
= lapic_cal_t1
- lapic_cal_t2
;
606 apic_printk(APIC_VERBOSE
, "... lapic delta = %ld\n", delta
);
608 /* Check, if the PM timer is available */
609 deltapm
= lapic_cal_pm2
- lapic_cal_pm1
;
610 apic_printk(APIC_VERBOSE
, "... PM timer delta = %ld\n", deltapm
);
616 mult
= clocksource_hz2mult(PMTMR_TICKS_PER_SEC
, 22);
618 if (deltapm
> (pm_100ms
- pm_thresh
) &&
619 deltapm
< (pm_100ms
+ pm_thresh
)) {
620 apic_printk(APIC_VERBOSE
, "... PM timer result ok\n");
622 res
= (((u64
) deltapm
) * mult
) >> 22;
623 do_div(res
, 1000000);
624 printk(KERN_WARNING
"APIC calibration not consistent "
625 "with PM Timer: %ldms instead of 100ms\n",
627 /* Correct the lapic counter value */
628 res
= (((u64
) delta
) * pm_100ms
);
629 do_div(res
, deltapm
);
630 printk(KERN_INFO
"APIC delta adjusted to PM-Timer: "
631 "%lu (%ld)\n", (unsigned long) res
, delta
);
637 /* Calculate the scaled math multiplication factor */
638 lapic_clockevent
.mult
= div_sc(delta
, TICK_NSEC
* LAPIC_CAL_LOOPS
,
639 lapic_clockevent
.shift
);
640 lapic_clockevent
.max_delta_ns
=
641 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent
);
642 lapic_clockevent
.min_delta_ns
=
643 clockevent_delta2ns(0xF, &lapic_clockevent
);
645 calibration_result
= (delta
* APIC_DIVISOR
) / LAPIC_CAL_LOOPS
;
647 apic_printk(APIC_VERBOSE
, "..... delta %ld\n", delta
);
648 apic_printk(APIC_VERBOSE
, "..... mult: %ld\n", lapic_clockevent
.mult
);
649 apic_printk(APIC_VERBOSE
, "..... calibration result: %u\n",
653 delta
= (long)(lapic_cal_tsc2
- lapic_cal_tsc1
);
654 apic_printk(APIC_VERBOSE
, "..... CPU clock speed is "
656 (delta
/ LAPIC_CAL_LOOPS
) / (1000000 / HZ
),
657 (delta
/ LAPIC_CAL_LOOPS
) % (1000000 / HZ
));
660 apic_printk(APIC_VERBOSE
, "..... host bus clock speed is "
662 calibration_result
/ (1000000 / HZ
),
663 calibration_result
% (1000000 / HZ
));
666 * Do a sanity check on the APIC calibration result
668 if (calibration_result
< (1000000 / HZ
)) {
671 "APIC frequency too slow, disabling apic timer\n");
675 levt
->features
&= ~CLOCK_EVT_FEAT_DUMMY
;
677 /* We trust the pm timer based calibration */
678 if (!pm_referenced
) {
679 apic_printk(APIC_VERBOSE
, "... verify APIC timer\n");
682 * Setup the apic timer manually
684 levt
->event_handler
= lapic_cal_handler
;
685 lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC
, levt
);
686 lapic_cal_loops
= -1;
688 /* Let the interrupts run */
691 while (lapic_cal_loops
<= LAPIC_CAL_LOOPS
)
696 /* Stop the lapic timer */
697 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, levt
);
702 deltaj
= lapic_cal_j2
- lapic_cal_j1
;
703 apic_printk(APIC_VERBOSE
, "... jiffies delta = %lu\n", deltaj
);
705 /* Check, if the jiffies result is consistent */
706 if (deltaj
>= LAPIC_CAL_LOOPS
-2 && deltaj
<= LAPIC_CAL_LOOPS
+2)
707 apic_printk(APIC_VERBOSE
, "... jiffies result ok\n");
709 levt
->features
|= CLOCK_EVT_FEAT_DUMMY
;
713 if (levt
->features
& CLOCK_EVT_FEAT_DUMMY
) {
715 "APIC timer disabled due to verification failure.\n");
725 * Setup the boot APIC
727 * Calibrate and verify the result.
729 void __init
setup_boot_APIC_clock(void)
732 * The local apic timer can be disabled via the kernel
733 * commandline or from the CPU detection code. Register the lapic
734 * timer as a dummy clock event source on SMP systems, so the
735 * broadcast mechanism is used. On UP systems simply ignore it.
737 if (disable_apic_timer
) {
738 printk(KERN_INFO
"Disabling APIC timer\n");
739 /* No broadcast on UP ! */
740 if (num_possible_cpus() > 1) {
741 lapic_clockevent
.mult
= 1;
747 apic_printk(APIC_VERBOSE
, "Using local APIC timer interrupts.\n"
748 "calibrating APIC timer ...\n");
750 if (calibrate_APIC_clock()) {
751 /* No broadcast on UP ! */
752 if (num_possible_cpus() > 1)
758 * If nmi_watchdog is set to IO_APIC, we need the
759 * PIT/HPET going. Otherwise register lapic as a dummy
762 if (nmi_watchdog
!= NMI_IO_APIC
)
763 lapic_clockevent
.features
&= ~CLOCK_EVT_FEAT_DUMMY
;
765 printk(KERN_WARNING
"APIC timer registered as dummy,"
766 " due to nmi_watchdog=%d!\n", nmi_watchdog
);
768 /* Setup the lapic or request the broadcast */
772 void __cpuinit
setup_secondary_APIC_clock(void)
778 * The guts of the apic timer interrupt
780 static void local_apic_timer_interrupt(void)
782 int cpu
= smp_processor_id();
783 struct clock_event_device
*evt
= &per_cpu(lapic_events
, cpu
);
786 * Normally we should not be here till LAPIC has been initialized but
787 * in some cases like kdump, its possible that there is a pending LAPIC
788 * timer interrupt from previous kernel's context and is delivered in
789 * new kernel the moment interrupts are enabled.
791 * Interrupts are enabled early and LAPIC is setup much later, hence
792 * its possible that when we get here evt->event_handler is NULL.
793 * Check for event_handler being NULL and discard the interrupt as
796 if (!evt
->event_handler
) {
798 "Spurious LAPIC timer interrupt on cpu %d\n", cpu
);
800 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, evt
);
805 * the NMI deadlock-detector uses this.
808 add_pda(apic_timer_irqs
, 1);
810 per_cpu(irq_stat
, cpu
).apic_timer_irqs
++;
813 evt
->event_handler(evt
);
817 * Local APIC timer interrupt. This is the most natural way for doing
818 * local interrupts, but local timer interrupts can be emulated by
819 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
821 * [ if a single-CPU system runs an SMP kernel then we call the local
822 * interrupt as well. Thus we cannot inline the local irq ... ]
824 void smp_apic_timer_interrupt(struct pt_regs
*regs
)
826 struct pt_regs
*old_regs
= set_irq_regs(regs
);
829 * NOTE! We'd better ACK the irq immediately,
830 * because timer handling can be slow.
834 * update_process_times() expects us to have done irq_enter().
835 * Besides, if we don't timer interrupts ignore the global
836 * interrupt lock, which is the WrongThing (tm) to do.
842 local_apic_timer_interrupt();
845 set_irq_regs(old_regs
);
848 int setup_profiling_timer(unsigned int multiplier
)
854 * Local APIC start and shutdown
858 * clear_local_APIC - shutdown the local APIC
860 * This is called, when a CPU is disabled and before rebooting, so the state of
861 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
862 * leftovers during boot.
864 void clear_local_APIC(void)
869 /* APIC hasn't been mapped yet */
873 maxlvt
= lapic_get_maxlvt();
875 * Masking an LVT entry can trigger a local APIC error
876 * if the vector is zero. Mask LVTERR first to prevent this.
879 v
= ERROR_APIC_VECTOR
; /* any non-zero vector will do */
880 apic_write(APIC_LVTERR
, v
| APIC_LVT_MASKED
);
883 * Careful: we have to set masks only first to deassert
884 * any level-triggered sources.
886 v
= apic_read(APIC_LVTT
);
887 apic_write(APIC_LVTT
, v
| APIC_LVT_MASKED
);
888 v
= apic_read(APIC_LVT0
);
889 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
890 v
= apic_read(APIC_LVT1
);
891 apic_write(APIC_LVT1
, v
| APIC_LVT_MASKED
);
893 v
= apic_read(APIC_LVTPC
);
894 apic_write(APIC_LVTPC
, v
| APIC_LVT_MASKED
);
897 /* lets not touch this if we didn't frob it */
898 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(X86_MCE_INTEL)
900 v
= apic_read(APIC_LVTTHMR
);
901 apic_write(APIC_LVTTHMR
, v
| APIC_LVT_MASKED
);
905 * Clean APIC state for other OSs:
907 apic_write(APIC_LVTT
, APIC_LVT_MASKED
);
908 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
909 apic_write(APIC_LVT1
, APIC_LVT_MASKED
);
911 apic_write(APIC_LVTERR
, APIC_LVT_MASKED
);
913 apic_write(APIC_LVTPC
, APIC_LVT_MASKED
);
915 /* Integrated APIC (!82489DX) ? */
916 if (lapic_is_integrated()) {
918 /* Clear ESR due to Pentium errata 3AP and 11AP */
919 apic_write(APIC_ESR
, 0);
925 * disable_local_APIC - clear and disable the local APIC
927 void disable_local_APIC(void)
934 * Disable APIC (implies clearing of registers
937 value
= apic_read(APIC_SPIV
);
938 value
&= ~APIC_SPIV_APIC_ENABLED
;
939 apic_write(APIC_SPIV
, value
);
943 * When LAPIC was disabled by the BIOS and enabled by the kernel,
944 * restore the disabled state.
946 if (enabled_via_apicbase
) {
949 rdmsr(MSR_IA32_APICBASE
, l
, h
);
950 l
&= ~MSR_IA32_APICBASE_ENABLE
;
951 wrmsr(MSR_IA32_APICBASE
, l
, h
);
957 * If Linux enabled the LAPIC against the BIOS default disable it down before
958 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
959 * not power-off. Additionally clear all LVT entries before disable_local_APIC
960 * for the case where Linux didn't enable the LAPIC.
962 void lapic_shutdown(void)
969 local_irq_save(flags
);
972 if (!enabled_via_apicbase
)
976 disable_local_APIC();
979 local_irq_restore(flags
);
983 * This is to verify that we're looking at a real local APIC.
984 * Check these against your board if the CPUs aren't getting
985 * started for no apparent reason.
987 int __init
verify_local_APIC(void)
989 unsigned int reg0
, reg1
;
992 * The version register is read-only in a real APIC.
994 reg0
= apic_read(APIC_LVR
);
995 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg0
);
996 apic_write(APIC_LVR
, reg0
^ APIC_LVR_MASK
);
997 reg1
= apic_read(APIC_LVR
);
998 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg1
);
1001 * The two version reads above should print the same
1002 * numbers. If the second one is different, then we
1003 * poke at a non-APIC.
1009 * Check if the version looks reasonably.
1011 reg1
= GET_APIC_VERSION(reg0
);
1012 if (reg1
== 0x00 || reg1
== 0xff)
1014 reg1
= lapic_get_maxlvt();
1015 if (reg1
< 0x02 || reg1
== 0xff)
1019 * The ID register is read/write in a real APIC.
1021 reg0
= apic_read(APIC_ID
);
1022 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg0
);
1023 apic_write(APIC_ID
, reg0
^ APIC_ID_MASK
);
1024 reg1
= apic_read(APIC_ID
);
1025 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg1
);
1026 apic_write(APIC_ID
, reg0
);
1027 if (reg1
!= (reg0
^ APIC_ID_MASK
))
1031 * The next two are just to see if we have sane values.
1032 * They're only really relevant if we're in Virtual Wire
1033 * compatibility mode, but most boxes are anymore.
1035 reg0
= apic_read(APIC_LVT0
);
1036 apic_printk(APIC_DEBUG
, "Getting LVT0: %x\n", reg0
);
1037 reg1
= apic_read(APIC_LVT1
);
1038 apic_printk(APIC_DEBUG
, "Getting LVT1: %x\n", reg1
);
1044 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
1046 void __init
sync_Arb_IDs(void)
1049 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
1052 if (modern_apic() || boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
)
1058 apic_wait_icr_idle();
1060 apic_printk(APIC_DEBUG
, "Synchronizing Arb IDs.\n");
1061 apic_write(APIC_ICR
, APIC_DEST_ALLINC
|
1062 APIC_INT_LEVELTRIG
| APIC_DM_INIT
);
1066 * An initial setup of the virtual wire mode.
1068 void __init
init_bsp_APIC(void)
1073 * Don't do the setup now if we have a SMP BIOS as the
1074 * through-I/O-APIC virtual wire mode might be active.
1076 if (smp_found_config
|| !cpu_has_apic
)
1080 * Do not trust the local APIC being empty at bootup.
1087 value
= apic_read(APIC_SPIV
);
1088 value
&= ~APIC_VECTOR_MASK
;
1089 value
|= APIC_SPIV_APIC_ENABLED
;
1091 #ifdef CONFIG_X86_32
1092 /* This bit is reserved on P4/Xeon and should be cleared */
1093 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
) &&
1094 (boot_cpu_data
.x86
== 15))
1095 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
1098 value
|= APIC_SPIV_FOCUS_DISABLED
;
1099 value
|= SPURIOUS_APIC_VECTOR
;
1100 apic_write(APIC_SPIV
, value
);
1103 * Set up the virtual wire mode.
1105 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
1106 value
= APIC_DM_NMI
;
1107 if (!lapic_is_integrated()) /* 82489DX */
1108 value
|= APIC_LVT_LEVEL_TRIGGER
;
1109 apic_write(APIC_LVT1
, value
);
1112 static void __cpuinit
lapic_setup_esr(void)
1114 unsigned long oldvalue
, value
, maxlvt
;
1115 if (lapic_is_integrated() && !esr_disable
) {
1118 * Something untraceable is creating bad interrupts on
1119 * secondary quads ... for the moment, just leave the
1120 * ESR disabled - we can't do anything useful with the
1121 * errors anyway - mbligh
1123 printk(KERN_INFO
"Leaving ESR disabled.\n");
1127 maxlvt
= lapic_get_maxlvt();
1128 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
1129 apic_write(APIC_ESR
, 0);
1130 oldvalue
= apic_read(APIC_ESR
);
1132 /* enables sending errors */
1133 value
= ERROR_APIC_VECTOR
;
1134 apic_write(APIC_LVTERR
, value
);
1136 * spec says clear errors after enabling vector.
1139 apic_write(APIC_ESR
, 0);
1140 value
= apic_read(APIC_ESR
);
1141 if (value
!= oldvalue
)
1142 apic_printk(APIC_VERBOSE
, "ESR value before enabling "
1143 "vector: 0x%08lx after: 0x%08lx\n",
1146 printk(KERN_INFO
"No ESR for 82489DX.\n");
1152 * setup_local_APIC - setup the local APIC
1154 void __cpuinit
setup_local_APIC(void)
1159 #ifdef CONFIG_X86_32
1160 /* Pound the ESR really hard over the head with a big hammer - mbligh */
1162 apic_write(APIC_ESR
, 0);
1163 apic_write(APIC_ESR
, 0);
1164 apic_write(APIC_ESR
, 0);
1165 apic_write(APIC_ESR
, 0);
1172 * Double-check whether this APIC is really registered.
1173 * This is meaningless in clustered apic mode, so we skip it.
1175 if (!apic_id_registered())
1179 * Intel recommends to set DFR, LDR and TPR before enabling
1180 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
1181 * document number 292116). So here it goes...
1186 * Set Task Priority to 'accept all'. We never change this
1189 value
= apic_read(APIC_TASKPRI
);
1190 value
&= ~APIC_TPRI_MASK
;
1191 apic_write(APIC_TASKPRI
, value
);
1194 * After a crash, we no longer service the interrupts and a pending
1195 * interrupt from previous kernel might still have ISR bit set.
1197 * Most probably by now CPU has serviced that pending interrupt and
1198 * it might not have done the ack_APIC_irq() because it thought,
1199 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
1200 * does not clear the ISR bit and cpu thinks it has already serivced
1201 * the interrupt. Hence a vector might get locked. It was noticed
1202 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
1204 for (i
= APIC_ISR_NR
- 1; i
>= 0; i
--) {
1205 value
= apic_read(APIC_ISR
+ i
*0x10);
1206 for (j
= 31; j
>= 0; j
--) {
1213 * Now that we are all set up, enable the APIC
1215 value
= apic_read(APIC_SPIV
);
1216 value
&= ~APIC_VECTOR_MASK
;
1220 value
|= APIC_SPIV_APIC_ENABLED
;
1222 #ifdef CONFIG_X86_32
1224 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1225 * certain networking cards. If high frequency interrupts are
1226 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1227 * entry is masked/unmasked at a high rate as well then sooner or
1228 * later IOAPIC line gets 'stuck', no more interrupts are received
1229 * from the device. If focus CPU is disabled then the hang goes
1232 * [ This bug can be reproduced easily with a level-triggered
1233 * PCI Ne2000 networking cards and PII/PIII processors, dual
1237 * Actually disabling the focus CPU check just makes the hang less
1238 * frequent as it makes the interrupt distributon model be more
1239 * like LRU than MRU (the short-term load is more even across CPUs).
1240 * See also the comment in end_level_ioapic_irq(). --macro
1244 * - enable focus processor (bit==0)
1245 * - 64bit mode always use processor focus
1246 * so no need to set it
1248 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
1252 * Set spurious IRQ vector
1254 value
|= SPURIOUS_APIC_VECTOR
;
1255 apic_write(APIC_SPIV
, value
);
1258 * Set up LVT0, LVT1:
1260 * set up through-local-APIC on the BP's LINT0. This is not
1261 * strictly necessary in pure symmetric-IO mode, but sometimes
1262 * we delegate interrupts to the 8259A.
1265 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1267 value
= apic_read(APIC_LVT0
) & APIC_LVT_MASKED
;
1268 if (!smp_processor_id() && (pic_mode
|| !value
)) {
1269 value
= APIC_DM_EXTINT
;
1270 apic_printk(APIC_VERBOSE
, "enabled ExtINT on CPU#%d\n",
1271 smp_processor_id());
1273 value
= APIC_DM_EXTINT
| APIC_LVT_MASKED
;
1274 apic_printk(APIC_VERBOSE
, "masked ExtINT on CPU#%d\n",
1275 smp_processor_id());
1277 apic_write(APIC_LVT0
, value
);
1280 * only the BP should see the LINT1 NMI signal, obviously.
1282 if (!smp_processor_id())
1283 value
= APIC_DM_NMI
;
1285 value
= APIC_DM_NMI
| APIC_LVT_MASKED
;
1286 if (!lapic_is_integrated()) /* 82489DX */
1287 value
|= APIC_LVT_LEVEL_TRIGGER
;
1288 apic_write(APIC_LVT1
, value
);
1293 void __cpuinit
end_local_APIC_setup(void)
1297 #ifdef CONFIG_X86_32
1300 /* Disable the local apic timer */
1301 value
= apic_read(APIC_LVTT
);
1302 value
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
1303 apic_write(APIC_LVTT
, value
);
1307 setup_apic_nmi_watchdog(NULL
);
1311 #ifdef CONFIG_X86_64
1313 * Detect and enable local APICs on non-SMP boards.
1314 * Original code written by Keir Fraser.
1315 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1316 * not correctly set up (usually the APIC timer won't work etc.)
1318 static int __init
detect_init_APIC(void)
1320 if (!cpu_has_apic
) {
1321 printk(KERN_INFO
"No local APIC present\n");
1325 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
1326 boot_cpu_physical_apicid
= 0;
1331 * Detect and initialize APIC
1333 static int __init
detect_init_APIC(void)
1337 /* Disabled by kernel option? */
1341 switch (boot_cpu_data
.x86_vendor
) {
1342 case X86_VENDOR_AMD
:
1343 if ((boot_cpu_data
.x86
== 6 && boot_cpu_data
.x86_model
> 1) ||
1344 (boot_cpu_data
.x86
== 15))
1347 case X86_VENDOR_INTEL
:
1348 if (boot_cpu_data
.x86
== 6 || boot_cpu_data
.x86
== 15 ||
1349 (boot_cpu_data
.x86
== 5 && cpu_has_apic
))
1356 if (!cpu_has_apic
) {
1358 * Over-ride BIOS and try to enable the local APIC only if
1359 * "lapic" specified.
1361 if (!force_enable_local_apic
) {
1362 printk(KERN_INFO
"Local APIC disabled by BIOS -- "
1363 "you can enable it with \"lapic\"\n");
1367 * Some BIOSes disable the local APIC in the APIC_BASE
1368 * MSR. This can only be done in software for Intel P6 or later
1369 * and AMD K7 (Model > 1) or later.
1371 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1372 if (!(l
& MSR_IA32_APICBASE_ENABLE
)) {
1374 "Local APIC disabled by BIOS -- reenabling.\n");
1375 l
&= ~MSR_IA32_APICBASE_BASE
;
1376 l
|= MSR_IA32_APICBASE_ENABLE
| APIC_DEFAULT_PHYS_BASE
;
1377 wrmsr(MSR_IA32_APICBASE
, l
, h
);
1378 enabled_via_apicbase
= 1;
1382 * The APIC feature bit should now be enabled
1385 features
= cpuid_edx(1);
1386 if (!(features
& (1 << X86_FEATURE_APIC
))) {
1387 printk(KERN_WARNING
"Could not enable APIC!\n");
1390 set_cpu_cap(&boot_cpu_data
, X86_FEATURE_APIC
);
1391 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
1393 /* The BIOS may have set up the APIC at some other address */
1394 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1395 if (l
& MSR_IA32_APICBASE_ENABLE
)
1396 mp_lapic_addr
= l
& MSR_IA32_APICBASE_BASE
;
1398 printk(KERN_INFO
"Found and enabled local APIC!\n");
1405 printk(KERN_INFO
"No local APIC present or hardware disabled\n");
1410 #ifdef CONFIG_X86_64
1411 void __init
early_init_lapic_mapping(void)
1413 unsigned long phys_addr
;
1416 * If no local APIC can be found then go out
1417 * : it means there is no mpatable and MADT
1419 if (!smp_found_config
)
1422 phys_addr
= mp_lapic_addr
;
1424 set_fixmap_nocache(FIX_APIC_BASE
, phys_addr
);
1425 apic_printk(APIC_VERBOSE
, "mapped APIC to %16lx (%16lx)\n",
1426 APIC_BASE
, phys_addr
);
1429 * Fetch the APIC ID of the BSP in case we have a
1430 * default configuration (or the MP table is broken).
1432 boot_cpu_physical_apicid
= read_apic_id();
1437 * init_apic_mappings - initialize APIC mappings
1439 void __init
init_apic_mappings(void)
1442 * If no local APIC can be found then set up a fake all
1443 * zeroes page to simulate the local APIC and another
1444 * one for the IO-APIC.
1446 if (!smp_found_config
&& detect_init_APIC()) {
1447 apic_phys
= (unsigned long) alloc_bootmem_pages(PAGE_SIZE
);
1448 apic_phys
= __pa(apic_phys
);
1450 apic_phys
= mp_lapic_addr
;
1452 set_fixmap_nocache(FIX_APIC_BASE
, apic_phys
);
1453 apic_printk(APIC_VERBOSE
, "mapped APIC to %16lx (%16lx)\n",
1454 APIC_BASE
, apic_phys
);
1457 * Fetch the APIC ID of the BSP in case we have a
1458 * default configuration (or the MP table is broken).
1460 if (boot_cpu_physical_apicid
== -1U)
1461 boot_cpu_physical_apicid
= read_apic_id();
1465 * This initializes the IO-APIC and APIC hardware if this is
1468 int apic_version
[MAX_APICS
];
1470 int __init
APIC_init_uniprocessor(void)
1472 #ifdef CONFIG_X86_64
1474 printk(KERN_INFO
"Apic disabled\n");
1477 if (!cpu_has_apic
) {
1479 printk(KERN_INFO
"Apic disabled by BIOS\n");
1483 if (!smp_found_config
&& !cpu_has_apic
)
1487 * Complain if the BIOS pretends there is one.
1489 if (!cpu_has_apic
&&
1490 APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
])) {
1491 printk(KERN_ERR
"BIOS bug, local APIC #%d not detected!...\n",
1492 boot_cpu_physical_apicid
);
1493 clear_cpu_cap(&boot_cpu_data
, X86_FEATURE_APIC
);
1501 #ifdef CONFIG_X86_64
1502 setup_apic_routing();
1504 verify_local_APIC();
1507 #ifdef CONFIG_X86_64
1508 apic_write(APIC_ID
, SET_APIC_ID(boot_cpu_physical_apicid
));
1511 * Hack: In case of kdump, after a crash, kernel might be booting
1512 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
1513 * might be zero if read from MP tables. Get it from LAPIC.
1515 # ifdef CONFIG_CRASH_DUMP
1516 boot_cpu_physical_apicid
= read_apic_id();
1519 physid_set_mask_of_physid(boot_cpu_physical_apicid
, &phys_cpu_present_map
);
1522 #ifdef CONFIG_X86_64
1524 * Now enable IO-APICs, actually call clear_IO_APIC
1525 * We need clear_IO_APIC before enabling vector on BP
1527 if (!skip_ioapic_setup
&& nr_ioapics
)
1531 #ifdef CONFIG_X86_IO_APIC
1532 if (!smp_found_config
|| skip_ioapic_setup
|| !nr_ioapics
)
1534 localise_nmi_watchdog();
1535 end_local_APIC_setup();
1537 #ifdef CONFIG_X86_IO_APIC
1538 if (smp_found_config
&& !skip_ioapic_setup
&& nr_ioapics
)
1540 # ifdef CONFIG_X86_64
1546 #ifdef CONFIG_X86_64
1547 setup_boot_APIC_clock();
1548 check_nmi_watchdog();
1557 * Local APIC interrupts
1561 * This interrupt should _never_ happen with our APIC/SMP architecture
1563 #ifdef CONFIG_X86_64
1564 asmlinkage
void smp_spurious_interrupt(void)
1566 void smp_spurious_interrupt(struct pt_regs
*regs
)
1571 #ifdef CONFIG_X86_64
1576 * Check if this really is a spurious interrupt and ACK it
1577 * if it is a vectored one. Just in case...
1578 * Spurious interrupts should not be ACKed.
1580 v
= apic_read(APIC_ISR
+ ((SPURIOUS_APIC_VECTOR
& ~0x1f) >> 1));
1581 if (v
& (1 << (SPURIOUS_APIC_VECTOR
& 0x1f)))
1584 #ifdef CONFIG_X86_64
1585 add_pda(irq_spurious_count
, 1);
1587 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1588 printk(KERN_INFO
"spurious APIC interrupt on CPU#%d, "
1589 "should never happen.\n", smp_processor_id());
1590 __get_cpu_var(irq_stat
).irq_spurious_count
++;
1596 * This interrupt should never happen with our APIC/SMP architecture
1598 #ifdef CONFIG_X86_64
1599 asmlinkage
void smp_error_interrupt(void)
1601 void smp_error_interrupt(struct pt_regs
*regs
)
1606 #ifdef CONFIG_X86_64
1610 /* First tickle the hardware, only then report what went on. -- REW */
1611 v
= apic_read(APIC_ESR
);
1612 apic_write(APIC_ESR
, 0);
1613 v1
= apic_read(APIC_ESR
);
1615 atomic_inc(&irq_err_count
);
1617 /* Here is what the APIC error bits mean:
1620 2: Send accept error
1621 3: Receive accept error
1623 5: Send illegal vector
1624 6: Received illegal vector
1625 7: Illegal register address
1627 printk(KERN_DEBUG
"APIC error on CPU%d: %02x(%02x)\n",
1628 smp_processor_id(), v
, v1
);
1633 * connect_bsp_APIC - attach the APIC to the interrupt system
1635 void __init
connect_bsp_APIC(void)
1637 #ifdef CONFIG_X86_32
1640 * Do not trust the local APIC being empty at bootup.
1644 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
1645 * local APIC to INT and NMI lines.
1647 apic_printk(APIC_VERBOSE
, "leaving PIC mode, "
1648 "enabling APIC mode.\n");
1657 * disconnect_bsp_APIC - detach the APIC from the interrupt system
1658 * @virt_wire_setup: indicates, whether virtual wire mode is selected
1660 * Virtual wire mode is necessary to deliver legacy interrupts even when the
1663 void disconnect_bsp_APIC(int virt_wire_setup
)
1667 #ifdef CONFIG_X86_32
1670 * Put the board back into PIC mode (has an effect only on
1671 * certain older boards). Note that APIC interrupts, including
1672 * IPIs, won't work beyond this point! The only exception are
1675 apic_printk(APIC_VERBOSE
, "disabling APIC mode, "
1676 "entering PIC mode.\n");
1683 /* Go back to Virtual Wire compatibility mode */
1685 /* For the spurious interrupt use vector F, and enable it */
1686 value
= apic_read(APIC_SPIV
);
1687 value
&= ~APIC_VECTOR_MASK
;
1688 value
|= APIC_SPIV_APIC_ENABLED
;
1690 apic_write(APIC_SPIV
, value
);
1692 if (!virt_wire_setup
) {
1694 * For LVT0 make it edge triggered, active high,
1695 * external and enabled
1697 value
= apic_read(APIC_LVT0
);
1698 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1699 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1700 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1701 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1702 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_EXTINT
);
1703 apic_write(APIC_LVT0
, value
);
1706 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
1710 * For LVT1 make it edge triggered, active high,
1713 value
= apic_read(APIC_LVT1
);
1714 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1715 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1716 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1717 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1718 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_NMI
);
1719 apic_write(APIC_LVT1
, value
);
1722 void __cpuinit
generic_processor_info(int apicid
, int version
)
1730 if (version
== 0x0) {
1731 printk(KERN_WARNING
"BIOS bug, APIC version is 0 for CPU#%d! "
1732 "fixing up to 0x10. (tell your hw vendor)\n",
1736 apic_version
[apicid
] = version
;
1738 if (num_processors
>= NR_CPUS
) {
1739 printk(KERN_WARNING
"WARNING: NR_CPUS limit of %i reached."
1740 " Processor ignored.\n", NR_CPUS
);
1745 cpus_complement(tmp_map
, cpu_present_map
);
1746 cpu
= first_cpu(tmp_map
);
1748 physid_set(apicid
, phys_cpu_present_map
);
1749 if (apicid
== boot_cpu_physical_apicid
) {
1751 * x86_bios_cpu_apicid is required to have processors listed
1752 * in same order as logical cpu numbers. Hence the first
1753 * entry is BSP, and so on.
1757 if (apicid
> max_physical_apicid
)
1758 max_physical_apicid
= apicid
;
1760 #ifdef CONFIG_X86_32
1762 * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y
1763 * but we need to work other dependencies like SMP_SUSPEND etc
1764 * before this can be done without some confusion.
1765 * if (CPU_HOTPLUG_ENABLED || num_processors > 8)
1766 * - Ashok Raj <ashok.raj@intel.com>
1768 if (max_physical_apicid
>= 8) {
1769 switch (boot_cpu_data
.x86_vendor
) {
1770 case X86_VENDOR_INTEL
:
1771 if (!APIC_XAPIC(version
)) {
1775 /* If P4 and above fall through */
1776 case X86_VENDOR_AMD
:
1782 #if defined(CONFIG_X86_SMP) || defined(CONFIG_X86_64)
1783 /* are we being called early in kernel startup? */
1784 if (early_per_cpu_ptr(x86_cpu_to_apicid
)) {
1785 u16
*cpu_to_apicid
= early_per_cpu_ptr(x86_cpu_to_apicid
);
1786 u16
*bios_cpu_apicid
= early_per_cpu_ptr(x86_bios_cpu_apicid
);
1788 cpu_to_apicid
[cpu
] = apicid
;
1789 bios_cpu_apicid
[cpu
] = apicid
;
1791 per_cpu(x86_cpu_to_apicid
, cpu
) = apicid
;
1792 per_cpu(x86_bios_cpu_apicid
, cpu
) = apicid
;
1796 cpu_set(cpu
, cpu_possible_map
);
1797 cpu_set(cpu
, cpu_present_map
);
1800 #ifdef CONFIG_X86_64
1801 int hard_smp_processor_id(void)
1803 return read_apic_id();
1814 * 'active' is true if the local APIC was enabled by us and
1815 * not the BIOS; this signifies that we are also responsible
1816 * for disabling it before entering apm/acpi suspend
1819 /* r/w apic fields */
1820 unsigned int apic_id
;
1821 unsigned int apic_taskpri
;
1822 unsigned int apic_ldr
;
1823 unsigned int apic_dfr
;
1824 unsigned int apic_spiv
;
1825 unsigned int apic_lvtt
;
1826 unsigned int apic_lvtpc
;
1827 unsigned int apic_lvt0
;
1828 unsigned int apic_lvt1
;
1829 unsigned int apic_lvterr
;
1830 unsigned int apic_tmict
;
1831 unsigned int apic_tdcr
;
1832 unsigned int apic_thmr
;
1835 static int lapic_suspend(struct sys_device
*dev
, pm_message_t state
)
1837 unsigned long flags
;
1840 if (!apic_pm_state
.active
)
1843 maxlvt
= lapic_get_maxlvt();
1845 apic_pm_state
.apic_id
= apic_read(APIC_ID
);
1846 apic_pm_state
.apic_taskpri
= apic_read(APIC_TASKPRI
);
1847 apic_pm_state
.apic_ldr
= apic_read(APIC_LDR
);
1848 apic_pm_state
.apic_dfr
= apic_read(APIC_DFR
);
1849 apic_pm_state
.apic_spiv
= apic_read(APIC_SPIV
);
1850 apic_pm_state
.apic_lvtt
= apic_read(APIC_LVTT
);
1852 apic_pm_state
.apic_lvtpc
= apic_read(APIC_LVTPC
);
1853 apic_pm_state
.apic_lvt0
= apic_read(APIC_LVT0
);
1854 apic_pm_state
.apic_lvt1
= apic_read(APIC_LVT1
);
1855 apic_pm_state
.apic_lvterr
= apic_read(APIC_LVTERR
);
1856 apic_pm_state
.apic_tmict
= apic_read(APIC_TMICT
);
1857 apic_pm_state
.apic_tdcr
= apic_read(APIC_TDCR
);
1858 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
1860 apic_pm_state
.apic_thmr
= apic_read(APIC_LVTTHMR
);
1863 local_irq_save(flags
);
1864 disable_local_APIC();
1865 local_irq_restore(flags
);
1869 static int lapic_resume(struct sys_device
*dev
)
1872 unsigned long flags
;
1875 if (!apic_pm_state
.active
)
1878 maxlvt
= lapic_get_maxlvt();
1880 local_irq_save(flags
);
1884 * Make sure the APICBASE points to the right address
1886 * FIXME! This will be wrong if we ever support suspend on
1887 * SMP! We'll need to do this as part of the CPU restore!
1889 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1890 l
&= ~MSR_IA32_APICBASE_BASE
;
1891 l
|= MSR_IA32_APICBASE_ENABLE
| mp_lapic_addr
;
1892 wrmsr(MSR_IA32_APICBASE
, l
, h
);
1895 apic_write(APIC_LVTERR
, ERROR_APIC_VECTOR
| APIC_LVT_MASKED
);
1896 apic_write(APIC_ID
, apic_pm_state
.apic_id
);
1897 apic_write(APIC_DFR
, apic_pm_state
.apic_dfr
);
1898 apic_write(APIC_LDR
, apic_pm_state
.apic_ldr
);
1899 apic_write(APIC_TASKPRI
, apic_pm_state
.apic_taskpri
);
1900 apic_write(APIC_SPIV
, apic_pm_state
.apic_spiv
);
1901 apic_write(APIC_LVT0
, apic_pm_state
.apic_lvt0
);
1902 apic_write(APIC_LVT1
, apic_pm_state
.apic_lvt1
);
1903 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
1905 apic_write(APIC_LVTTHMR
, apic_pm_state
.apic_thmr
);
1908 apic_write(APIC_LVTPC
, apic_pm_state
.apic_lvtpc
);
1909 apic_write(APIC_LVTT
, apic_pm_state
.apic_lvtt
);
1910 apic_write(APIC_TDCR
, apic_pm_state
.apic_tdcr
);
1911 apic_write(APIC_TMICT
, apic_pm_state
.apic_tmict
);
1912 apic_write(APIC_ESR
, 0);
1913 apic_read(APIC_ESR
);
1914 apic_write(APIC_LVTERR
, apic_pm_state
.apic_lvterr
);
1915 apic_write(APIC_ESR
, 0);
1916 apic_read(APIC_ESR
);
1918 local_irq_restore(flags
);
1924 * This device has no shutdown method - fully functioning local APICs
1925 * are needed on every CPU up until machine_halt/restart/poweroff.
1928 static struct sysdev_class lapic_sysclass
= {
1930 .resume
= lapic_resume
,
1931 .suspend
= lapic_suspend
,
1934 static struct sys_device device_lapic
= {
1936 .cls
= &lapic_sysclass
,
1939 static void __cpuinit
apic_pm_activate(void)
1941 apic_pm_state
.active
= 1;
1944 static int __init
init_lapic_sysfs(void)
1950 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
1952 error
= sysdev_class_register(&lapic_sysclass
);
1954 error
= sysdev_register(&device_lapic
);
1957 device_initcall(init_lapic_sysfs
);
1959 #else /* CONFIG_PM */
1961 static void apic_pm_activate(void) { }
1963 #endif /* CONFIG_PM */
1965 #ifdef CONFIG_X86_64
1967 * apic_is_clustered_box() -- Check if we can expect good TSC
1969 * Thus far, the major user of this is IBM's Summit2 series:
1971 * Clustered boxes may have unsynced TSC problems if they are
1972 * multi-chassis. Use available data to take a good guess.
1973 * If in doubt, go HPET.
1975 __cpuinit
int apic_is_clustered_box(void)
1977 int i
, clusters
, zeros
;
1979 u16
*bios_cpu_apicid
;
1980 DECLARE_BITMAP(clustermap
, NUM_APIC_CLUSTERS
);
1983 * there is not this kind of box with AMD CPU yet.
1984 * Some AMD box with quadcore cpu and 8 sockets apicid
1985 * will be [4, 0x23] or [8, 0x27] could be thought to
1986 * vsmp box still need checking...
1988 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
) && !is_vsmp_box())
1991 bios_cpu_apicid
= early_per_cpu_ptr(x86_bios_cpu_apicid
);
1992 bitmap_zero(clustermap
, NUM_APIC_CLUSTERS
);
1994 for (i
= 0; i
< NR_CPUS
; i
++) {
1995 /* are we being called early in kernel startup? */
1996 if (bios_cpu_apicid
) {
1997 id
= bios_cpu_apicid
[i
];
1999 else if (i
< nr_cpu_ids
) {
2001 id
= per_cpu(x86_bios_cpu_apicid
, i
);
2008 if (id
!= BAD_APICID
)
2009 __set_bit(APIC_CLUSTERID(id
), clustermap
);
2012 /* Problem: Partially populated chassis may not have CPUs in some of
2013 * the APIC clusters they have been allocated. Only present CPUs have
2014 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap.
2015 * Since clusters are allocated sequentially, count zeros only if
2016 * they are bounded by ones.
2020 for (i
= 0; i
< NUM_APIC_CLUSTERS
; i
++) {
2021 if (test_bit(i
, clustermap
)) {
2022 clusters
+= 1 + zeros
;
2028 /* ScaleMP vSMPowered boxes have one cluster per board and TSCs are
2029 * not guaranteed to be synced between boards
2031 if (is_vsmp_box() && clusters
> 1)
2035 * If clusters > 2, then should be multi-chassis.
2036 * May have to revisit this when multi-core + hyperthreaded CPUs come
2037 * out, but AFAIK this will work even for them.
2039 return (clusters
> 2);
2044 * APIC command line parameters
2046 static int __init
setup_disableapic(char *arg
)
2049 setup_clear_cpu_cap(X86_FEATURE_APIC
);
2052 early_param("disableapic", setup_disableapic
);
2054 /* same as disableapic, for compatibility */
2055 static int __init
setup_nolapic(char *arg
)
2057 return setup_disableapic(arg
);
2059 early_param("nolapic", setup_nolapic
);
2061 static int __init
parse_lapic_timer_c2_ok(char *arg
)
2063 local_apic_timer_c2_ok
= 1;
2066 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok
);
2068 static int __init
parse_disable_apic_timer(char *arg
)
2070 disable_apic_timer
= 1;
2073 early_param("noapictimer", parse_disable_apic_timer
);
2075 static int __init
parse_nolapic_timer(char *arg
)
2077 disable_apic_timer
= 1;
2080 early_param("nolapic_timer", parse_nolapic_timer
);
2082 static int __init
apic_set_verbosity(char *arg
)
2085 #ifdef CONFIG_X86_64
2086 skip_ioapic_setup
= 0;
2093 if (strcmp("debug", arg
) == 0)
2094 apic_verbosity
= APIC_DEBUG
;
2095 else if (strcmp("verbose", arg
) == 0)
2096 apic_verbosity
= APIC_VERBOSE
;
2098 printk(KERN_WARNING
"APIC Verbosity level %s not recognised"
2099 " use apic=verbose or apic=debug\n", arg
);
2105 early_param("apic", apic_set_verbosity
);
2107 static int __init
lapic_insert_resource(void)
2112 /* Put local APIC into the resource map. */
2113 lapic_resource
.start
= apic_phys
;
2114 lapic_resource
.end
= lapic_resource
.start
+ PAGE_SIZE
- 1;
2115 insert_resource(&iomem_resource
, &lapic_resource
);
2121 * need call insert after e820_reserve_resources()
2122 * that is using request_resource
2124 late_initcall(lapic_insert_resource
);