2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/bootmem.h>
22 #include <linux/interrupt.h>
23 #include <linux/mc146818rtc.h>
24 #include <linux/kernel_stat.h>
25 #include <linux/sysdev.h>
26 #include <linux/cpu.h>
27 #include <linux/clockchips.h>
28 #include <linux/acpi_pmtmr.h>
29 #include <linux/module.h>
30 #include <linux/dmi.h>
32 #include <asm/atomic.h>
35 #include <asm/mpspec.h>
37 #include <asm/arch_hooks.h>
39 #include <asm/i8253.h>
42 #include <mach_apic.h>
43 #include <mach_apicdef.h>
49 #if ((SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F)
50 # error SPURIOUS_APIC_VECTOR definition error
55 * Knob to control our willingness to enable the local APIC.
59 static int force_enable_local_apic
;
61 * APIC command line parameters
63 static int __init
parse_lapic(char *arg
)
65 force_enable_local_apic
= 1;
68 early_param("lapic", parse_lapic
);
72 static int apic_calibrate_pmtmr __initdata
;
73 static __init
int setup_apicpmtimer(char *s
)
75 apic_calibrate_pmtmr
= 1;
79 __setup("apicpmtimer", setup_apicpmtimer
);
82 unsigned long mp_lapic_addr
;
84 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
85 static int disable_apic_timer __cpuinitdata
;
86 /* Local APIC timer works in C2 */
87 int local_apic_timer_c2_ok
;
88 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok
);
90 int first_system_vector
= 0xfe;
92 char system_vectors
[NR_VECTORS
] = { [0 ... NR_VECTORS
-1] = SYS_VECTOR_FREE
};
95 * Debug level, exported for io_apic.c
97 unsigned int apic_verbosity
;
101 /* Have we found an MP table */
102 int smp_found_config
;
104 static struct resource lapic_resource
= {
105 .name
= "Local APIC",
106 .flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
,
109 static unsigned int calibration_result
;
111 static int lapic_next_event(unsigned long delta
,
112 struct clock_event_device
*evt
);
113 static void lapic_timer_setup(enum clock_event_mode mode
,
114 struct clock_event_device
*evt
);
115 static void lapic_timer_broadcast(cpumask_t mask
);
116 static void apic_pm_activate(void);
119 * The local apic timer can be used for any function which is CPU local.
121 static struct clock_event_device lapic_clockevent
= {
123 .features
= CLOCK_EVT_FEAT_PERIODIC
| CLOCK_EVT_FEAT_ONESHOT
124 | CLOCK_EVT_FEAT_C3STOP
| CLOCK_EVT_FEAT_DUMMY
,
126 .set_mode
= lapic_timer_setup
,
127 .set_next_event
= lapic_next_event
,
128 .broadcast
= lapic_timer_broadcast
,
132 static DEFINE_PER_CPU(struct clock_event_device
, lapic_events
);
134 /* Local APIC was disabled by the BIOS and enabled by the kernel */
135 static int enabled_via_apicbase
;
137 static unsigned long apic_phys
;
140 * Get the LAPIC version
142 static inline int lapic_get_version(void)
144 return GET_APIC_VERSION(apic_read(APIC_LVR
));
148 * Check, if the APIC is integrated or a separate chip
150 static inline int lapic_is_integrated(void)
155 return APIC_INTEGRATED(lapic_get_version());
160 * Check, whether this is a modern or a first generation APIC
162 static int modern_apic(void)
164 /* AMD systems use old APIC versions, so check the CPU */
165 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
&&
166 boot_cpu_data
.x86
>= 0xf)
168 return lapic_get_version() >= 0x14;
172 * Paravirt kernels also might be using these below ops. So we still
173 * use generic apic_read()/apic_write(), which might be pointing to different
174 * ops in PARAVIRT case.
176 void xapic_wait_icr_idle(void)
178 while (apic_read(APIC_ICR
) & APIC_ICR_BUSY
)
182 u32
safe_xapic_wait_icr_idle(void)
189 send_status
= apic_read(APIC_ICR
) & APIC_ICR_BUSY
;
193 } while (timeout
++ < 1000);
198 void xapic_icr_write(u32 low
, u32 id
)
200 apic_write(APIC_ICR2
, SET_APIC_DEST_FIELD(id
));
201 apic_write(APIC_ICR
, low
);
204 u64
xapic_icr_read(void)
208 icr2
= apic_read(APIC_ICR2
);
209 icr1
= apic_read(APIC_ICR
);
211 return icr1
| ((u64
)icr2
<< 32);
214 static struct apic_ops xapic_ops
= {
215 .read
= native_apic_mem_read
,
216 .write
= native_apic_mem_write
,
217 .icr_read
= xapic_icr_read
,
218 .icr_write
= xapic_icr_write
,
219 .wait_icr_idle
= xapic_wait_icr_idle
,
220 .safe_wait_icr_idle
= safe_xapic_wait_icr_idle
,
223 struct apic_ops __read_mostly
*apic_ops
= &xapic_ops
;
224 EXPORT_SYMBOL_GPL(apic_ops
);
227 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
229 void __cpuinit
enable_NMI_through_LVT0(void)
233 /* unmask and set to NMI */
236 /* Level triggered for 82489DX (32bit mode) */
237 if (!lapic_is_integrated())
238 v
|= APIC_LVT_LEVEL_TRIGGER
;
240 apic_write(APIC_LVT0
, v
);
244 * get_physical_broadcast - Get number of physical broadcast IDs
246 int get_physical_broadcast(void)
248 return modern_apic() ? 0xff : 0xf;
252 * lapic_get_maxlvt - get the maximum number of local vector table entries
254 int lapic_get_maxlvt(void)
258 v
= apic_read(APIC_LVR
);
260 * - we always have APIC integrated on 64bit mode
261 * - 82489DXs do not report # of LVT entries
263 return APIC_INTEGRATED(GET_APIC_VERSION(v
)) ? GET_APIC_MAXLVT(v
) : 2;
272 #define APIC_DIVISOR 1
274 #define APIC_DIVISOR 16
278 * This function sets up the local APIC timer, with a timeout of
279 * 'clocks' APIC bus clock. During calibration we actually call
280 * this function twice on the boot CPU, once with a bogus timeout
281 * value, second time for real. The other (noncalibrating) CPUs
282 * call this function only once, with the real, calibrated value.
284 * We do reads before writes even if unnecessary, to get around the
285 * P5 APIC double write bug.
287 static void __setup_APIC_LVTT(unsigned int clocks
, int oneshot
, int irqen
)
289 unsigned int lvtt_value
, tmp_value
;
291 lvtt_value
= LOCAL_TIMER_VECTOR
;
293 lvtt_value
|= APIC_LVT_TIMER_PERIODIC
;
294 if (!lapic_is_integrated())
295 lvtt_value
|= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV
);
298 lvtt_value
|= APIC_LVT_MASKED
;
300 apic_write(APIC_LVTT
, lvtt_value
);
305 tmp_value
= apic_read(APIC_TDCR
);
306 apic_write(APIC_TDCR
,
307 (tmp_value
& ~(APIC_TDR_DIV_1
| APIC_TDR_DIV_TMBASE
)) |
311 apic_write(APIC_TMICT
, clocks
/ APIC_DIVISOR
);
315 * Setup extended LVT, AMD specific (K8, family 10h)
317 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
318 * MCE interrupts are supported. Thus MCE offset must be set to 0.
320 * If mask=1, the LVT entry does not generate interrupts while mask=0
321 * enables the vector. See also the BKDGs.
324 #define APIC_EILVT_LVTOFF_MCE 0
325 #define APIC_EILVT_LVTOFF_IBS 1
327 static void setup_APIC_eilvt(u8 lvt_off
, u8 vector
, u8 msg_type
, u8 mask
)
329 unsigned long reg
= (lvt_off
<< 4) + APIC_EILVT0
;
330 unsigned int v
= (mask
<< 16) | (msg_type
<< 8) | vector
;
335 u8
setup_APIC_eilvt_mce(u8 vector
, u8 msg_type
, u8 mask
)
337 setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE
, vector
, msg_type
, mask
);
338 return APIC_EILVT_LVTOFF_MCE
;
341 u8
setup_APIC_eilvt_ibs(u8 vector
, u8 msg_type
, u8 mask
)
343 setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS
, vector
, msg_type
, mask
);
344 return APIC_EILVT_LVTOFF_IBS
;
346 EXPORT_SYMBOL_GPL(setup_APIC_eilvt_ibs
);
349 * Program the next event, relative to now
351 static int lapic_next_event(unsigned long delta
,
352 struct clock_event_device
*evt
)
354 apic_write(APIC_TMICT
, delta
);
359 * Setup the lapic timer in periodic or oneshot mode
361 static void lapic_timer_setup(enum clock_event_mode mode
,
362 struct clock_event_device
*evt
)
367 /* Lapic used as dummy for broadcast ? */
368 if (evt
->features
& CLOCK_EVT_FEAT_DUMMY
)
371 local_irq_save(flags
);
374 case CLOCK_EVT_MODE_PERIODIC
:
375 case CLOCK_EVT_MODE_ONESHOT
:
376 __setup_APIC_LVTT(calibration_result
,
377 mode
!= CLOCK_EVT_MODE_PERIODIC
, 1);
379 case CLOCK_EVT_MODE_UNUSED
:
380 case CLOCK_EVT_MODE_SHUTDOWN
:
381 v
= apic_read(APIC_LVTT
);
382 v
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
383 apic_write(APIC_LVTT
, v
);
385 case CLOCK_EVT_MODE_RESUME
:
386 /* Nothing to do here */
390 local_irq_restore(flags
);
394 * Local APIC timer broadcast function
396 static void lapic_timer_broadcast(cpumask_t mask
)
399 send_IPI_mask(mask
, LOCAL_TIMER_VECTOR
);
404 * Setup the local APIC timer for this CPU. Copy the initilized values
405 * of the boot CPU and register the clock event in the framework.
407 static void __cpuinit
setup_APIC_timer(void)
409 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
411 memcpy(levt
, &lapic_clockevent
, sizeof(*levt
));
412 levt
->cpumask
= cpumask_of_cpu(smp_processor_id());
414 clockevents_register_device(levt
);
418 * In this functions we calibrate APIC bus clocks to the external timer.
420 * We want to do the calibration only once since we want to have local timer
421 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
424 * This was previously done by reading the PIT/HPET and waiting for a wrap
425 * around to find out, that a tick has elapsed. I have a box, where the PIT
426 * readout is broken, so it never gets out of the wait loop again. This was
427 * also reported by others.
429 * Monitoring the jiffies value is inaccurate and the clockevents
430 * infrastructure allows us to do a simple substitution of the interrupt
433 * The calibration routine also uses the pm_timer when possible, as the PIT
434 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
435 * back to normal later in the boot process).
438 #define LAPIC_CAL_LOOPS (HZ/10)
440 static __initdata
int lapic_cal_loops
= -1;
441 static __initdata
long lapic_cal_t1
, lapic_cal_t2
;
442 static __initdata
unsigned long long lapic_cal_tsc1
, lapic_cal_tsc2
;
443 static __initdata
unsigned long lapic_cal_pm1
, lapic_cal_pm2
;
444 static __initdata
unsigned long lapic_cal_j1
, lapic_cal_j2
;
447 * Temporary interrupt handler.
449 static void __init
lapic_cal_handler(struct clock_event_device
*dev
)
451 unsigned long long tsc
= 0;
452 long tapic
= apic_read(APIC_TMCCT
);
453 unsigned long pm
= acpi_pm_read_early();
458 switch (lapic_cal_loops
++) {
460 lapic_cal_t1
= tapic
;
461 lapic_cal_tsc1
= tsc
;
463 lapic_cal_j1
= jiffies
;
466 case LAPIC_CAL_LOOPS
:
467 lapic_cal_t2
= tapic
;
468 lapic_cal_tsc2
= tsc
;
469 if (pm
< lapic_cal_pm1
)
470 pm
+= ACPI_PM_OVRRUN
;
472 lapic_cal_j2
= jiffies
;
477 static int __init
calibrate_APIC_clock(void)
479 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
480 const long pm_100ms
= PMTMR_TICKS_PER_SEC
/10;
481 const long pm_thresh
= pm_100ms
/100;
482 void (*real_handler
)(struct clock_event_device
*dev
);
483 unsigned long deltaj
;
485 int pm_referenced
= 0;
489 /* Replace the global interrupt handler */
490 real_handler
= global_clock_event
->event_handler
;
491 global_clock_event
->event_handler
= lapic_cal_handler
;
494 * Setup the APIC counter to 1e9. There is no way the lapic
495 * can underflow in the 100ms detection time frame
497 __setup_APIC_LVTT(1000000000, 0, 0);
499 /* Let the interrupts run */
502 while (lapic_cal_loops
<= LAPIC_CAL_LOOPS
)
507 /* Restore the real event handler */
508 global_clock_event
->event_handler
= real_handler
;
510 /* Build delta t1-t2 as apic timer counts down */
511 delta
= lapic_cal_t1
- lapic_cal_t2
;
512 apic_printk(APIC_VERBOSE
, "... lapic delta = %ld\n", delta
);
514 /* Check, if the PM timer is available */
515 deltapm
= lapic_cal_pm2
- lapic_cal_pm1
;
516 apic_printk(APIC_VERBOSE
, "... PM timer delta = %ld\n", deltapm
);
522 mult
= clocksource_hz2mult(PMTMR_TICKS_PER_SEC
, 22);
524 if (deltapm
> (pm_100ms
- pm_thresh
) &&
525 deltapm
< (pm_100ms
+ pm_thresh
)) {
526 apic_printk(APIC_VERBOSE
, "... PM timer result ok\n");
528 res
= (((u64
) deltapm
) * mult
) >> 22;
529 do_div(res
, 1000000);
530 printk(KERN_WARNING
"APIC calibration not consistent "
531 "with PM Timer: %ldms instead of 100ms\n",
533 /* Correct the lapic counter value */
534 res
= (((u64
) delta
) * pm_100ms
);
535 do_div(res
, deltapm
);
536 printk(KERN_INFO
"APIC delta adjusted to PM-Timer: "
537 "%lu (%ld)\n", (unsigned long) res
, delta
);
543 /* Calculate the scaled math multiplication factor */
544 lapic_clockevent
.mult
= div_sc(delta
, TICK_NSEC
* LAPIC_CAL_LOOPS
,
545 lapic_clockevent
.shift
);
546 lapic_clockevent
.max_delta_ns
=
547 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent
);
548 lapic_clockevent
.min_delta_ns
=
549 clockevent_delta2ns(0xF, &lapic_clockevent
);
551 calibration_result
= (delta
* APIC_DIVISOR
) / LAPIC_CAL_LOOPS
;
553 apic_printk(APIC_VERBOSE
, "..... delta %ld\n", delta
);
554 apic_printk(APIC_VERBOSE
, "..... mult: %ld\n", lapic_clockevent
.mult
);
555 apic_printk(APIC_VERBOSE
, "..... calibration result: %u\n",
559 delta
= (long)(lapic_cal_tsc2
- lapic_cal_tsc1
);
560 apic_printk(APIC_VERBOSE
, "..... CPU clock speed is "
562 (delta
/ LAPIC_CAL_LOOPS
) / (1000000 / HZ
),
563 (delta
/ LAPIC_CAL_LOOPS
) % (1000000 / HZ
));
566 apic_printk(APIC_VERBOSE
, "..... host bus clock speed is "
568 calibration_result
/ (1000000 / HZ
),
569 calibration_result
% (1000000 / HZ
));
572 * Do a sanity check on the APIC calibration result
574 if (calibration_result
< (1000000 / HZ
)) {
577 "APIC frequency too slow, disabling apic timer\n");
581 levt
->features
&= ~CLOCK_EVT_FEAT_DUMMY
;
583 /* We trust the pm timer based calibration */
584 if (!pm_referenced
) {
585 apic_printk(APIC_VERBOSE
, "... verify APIC timer\n");
588 * Setup the apic timer manually
590 levt
->event_handler
= lapic_cal_handler
;
591 lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC
, levt
);
592 lapic_cal_loops
= -1;
594 /* Let the interrupts run */
597 while (lapic_cal_loops
<= LAPIC_CAL_LOOPS
)
602 /* Stop the lapic timer */
603 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, levt
);
608 deltaj
= lapic_cal_j2
- lapic_cal_j1
;
609 apic_printk(APIC_VERBOSE
, "... jiffies delta = %lu\n", deltaj
);
611 /* Check, if the jiffies result is consistent */
612 if (deltaj
>= LAPIC_CAL_LOOPS
-2 && deltaj
<= LAPIC_CAL_LOOPS
+2)
613 apic_printk(APIC_VERBOSE
, "... jiffies result ok\n");
615 levt
->features
|= CLOCK_EVT_FEAT_DUMMY
;
619 if (levt
->features
& CLOCK_EVT_FEAT_DUMMY
) {
621 "APIC timer disabled due to verification failure.\n");
629 * Setup the boot APIC
631 * Calibrate and verify the result.
633 void __init
setup_boot_APIC_clock(void)
636 * The local apic timer can be disabled via the kernel
637 * commandline or from the CPU detection code. Register the lapic
638 * timer as a dummy clock event source on SMP systems, so the
639 * broadcast mechanism is used. On UP systems simply ignore it.
641 if (disable_apic_timer
) {
642 printk(KERN_INFO
"Disabling APIC timer\n");
643 /* No broadcast on UP ! */
644 if (num_possible_cpus() > 1) {
645 lapic_clockevent
.mult
= 1;
651 apic_printk(APIC_VERBOSE
, "Using local APIC timer interrupts.\n"
652 "calibrating APIC timer ...\n");
654 if (calibrate_APIC_clock()) {
655 /* No broadcast on UP ! */
656 if (num_possible_cpus() > 1)
662 * If nmi_watchdog is set to IO_APIC, we need the
663 * PIT/HPET going. Otherwise register lapic as a dummy
666 if (nmi_watchdog
!= NMI_IO_APIC
)
667 lapic_clockevent
.features
&= ~CLOCK_EVT_FEAT_DUMMY
;
669 printk(KERN_WARNING
"APIC timer registered as dummy,"
670 " due to nmi_watchdog=%d!\n", nmi_watchdog
);
672 /* Setup the lapic or request the broadcast */
676 void __cpuinit
setup_secondary_APIC_clock(void)
682 * The guts of the apic timer interrupt
684 static void local_apic_timer_interrupt(void)
686 int cpu
= smp_processor_id();
687 struct clock_event_device
*evt
= &per_cpu(lapic_events
, cpu
);
690 * Normally we should not be here till LAPIC has been initialized but
691 * in some cases like kdump, its possible that there is a pending LAPIC
692 * timer interrupt from previous kernel's context and is delivered in
693 * new kernel the moment interrupts are enabled.
695 * Interrupts are enabled early and LAPIC is setup much later, hence
696 * its possible that when we get here evt->event_handler is NULL.
697 * Check for event_handler being NULL and discard the interrupt as
700 if (!evt
->event_handler
) {
702 "Spurious LAPIC timer interrupt on cpu %d\n", cpu
);
704 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, evt
);
709 * the NMI deadlock-detector uses this.
712 add_pda(apic_timer_irqs
, 1);
714 per_cpu(irq_stat
, cpu
).apic_timer_irqs
++;
717 evt
->event_handler(evt
);
721 * Local APIC timer interrupt. This is the most natural way for doing
722 * local interrupts, but local timer interrupts can be emulated by
723 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
725 * [ if a single-CPU system runs an SMP kernel then we call the local
726 * interrupt as well. Thus we cannot inline the local irq ... ]
728 void smp_apic_timer_interrupt(struct pt_regs
*regs
)
730 struct pt_regs
*old_regs
= set_irq_regs(regs
);
733 * NOTE! We'd better ACK the irq immediately,
734 * because timer handling can be slow.
738 * update_process_times() expects us to have done irq_enter().
739 * Besides, if we don't timer interrupts ignore the global
740 * interrupt lock, which is the WrongThing (tm) to do.
746 local_apic_timer_interrupt();
749 set_irq_regs(old_regs
);
752 int setup_profiling_timer(unsigned int multiplier
)
758 * Local APIC start and shutdown
762 * clear_local_APIC - shutdown the local APIC
764 * This is called, when a CPU is disabled and before rebooting, so the state of
765 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
766 * leftovers during boot.
768 void clear_local_APIC(void)
773 /* APIC hasn't been mapped yet */
777 maxlvt
= lapic_get_maxlvt();
779 * Masking an LVT entry can trigger a local APIC error
780 * if the vector is zero. Mask LVTERR first to prevent this.
783 v
= ERROR_APIC_VECTOR
; /* any non-zero vector will do */
784 apic_write(APIC_LVTERR
, v
| APIC_LVT_MASKED
);
787 * Careful: we have to set masks only first to deassert
788 * any level-triggered sources.
790 v
= apic_read(APIC_LVTT
);
791 apic_write(APIC_LVTT
, v
| APIC_LVT_MASKED
);
792 v
= apic_read(APIC_LVT0
);
793 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
794 v
= apic_read(APIC_LVT1
);
795 apic_write(APIC_LVT1
, v
| APIC_LVT_MASKED
);
797 v
= apic_read(APIC_LVTPC
);
798 apic_write(APIC_LVTPC
, v
| APIC_LVT_MASKED
);
801 /* lets not touch this if we didn't frob it */
802 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(X86_MCE_INTEL)
804 v
= apic_read(APIC_LVTTHMR
);
805 apic_write(APIC_LVTTHMR
, v
| APIC_LVT_MASKED
);
809 * Clean APIC state for other OSs:
811 apic_write(APIC_LVTT
, APIC_LVT_MASKED
);
812 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
813 apic_write(APIC_LVT1
, APIC_LVT_MASKED
);
815 apic_write(APIC_LVTERR
, APIC_LVT_MASKED
);
817 apic_write(APIC_LVTPC
, APIC_LVT_MASKED
);
819 /* Integrated APIC (!82489DX) ? */
820 if (lapic_is_integrated()) {
822 /* Clear ESR due to Pentium errata 3AP and 11AP */
823 apic_write(APIC_ESR
, 0);
829 * disable_local_APIC - clear and disable the local APIC
831 void disable_local_APIC(void)
838 * Disable APIC (implies clearing of registers
841 value
= apic_read(APIC_SPIV
);
842 value
&= ~APIC_SPIV_APIC_ENABLED
;
843 apic_write(APIC_SPIV
, value
);
847 * When LAPIC was disabled by the BIOS and enabled by the kernel,
848 * restore the disabled state.
850 if (enabled_via_apicbase
) {
853 rdmsr(MSR_IA32_APICBASE
, l
, h
);
854 l
&= ~MSR_IA32_APICBASE_ENABLE
;
855 wrmsr(MSR_IA32_APICBASE
, l
, h
);
861 * If Linux enabled the LAPIC against the BIOS default disable it down before
862 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
863 * not power-off. Additionally clear all LVT entries before disable_local_APIC
864 * for the case where Linux didn't enable the LAPIC.
866 void lapic_shutdown(void)
873 local_irq_save(flags
);
876 if (!enabled_via_apicbase
)
880 disable_local_APIC();
883 local_irq_restore(flags
);
887 * This is to verify that we're looking at a real local APIC.
888 * Check these against your board if the CPUs aren't getting
889 * started for no apparent reason.
891 int __init
verify_local_APIC(void)
893 unsigned int reg0
, reg1
;
896 * The version register is read-only in a real APIC.
898 reg0
= apic_read(APIC_LVR
);
899 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg0
);
900 apic_write(APIC_LVR
, reg0
^ APIC_LVR_MASK
);
901 reg1
= apic_read(APIC_LVR
);
902 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg1
);
905 * The two version reads above should print the same
906 * numbers. If the second one is different, then we
907 * poke at a non-APIC.
913 * Check if the version looks reasonably.
915 reg1
= GET_APIC_VERSION(reg0
);
916 if (reg1
== 0x00 || reg1
== 0xff)
918 reg1
= lapic_get_maxlvt();
919 if (reg1
< 0x02 || reg1
== 0xff)
923 * The ID register is read/write in a real APIC.
925 reg0
= apic_read(APIC_ID
);
926 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg0
);
927 apic_write(APIC_ID
, reg0
^ APIC_ID_MASK
);
928 reg1
= apic_read(APIC_ID
);
929 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg1
);
930 apic_write(APIC_ID
, reg0
);
931 if (reg1
!= (reg0
^ APIC_ID_MASK
))
935 * The next two are just to see if we have sane values.
936 * They're only really relevant if we're in Virtual Wire
937 * compatibility mode, but most boxes are anymore.
939 reg0
= apic_read(APIC_LVT0
);
940 apic_printk(APIC_DEBUG
, "Getting LVT0: %x\n", reg0
);
941 reg1
= apic_read(APIC_LVT1
);
942 apic_printk(APIC_DEBUG
, "Getting LVT1: %x\n", reg1
);
948 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
950 void __init
sync_Arb_IDs(void)
953 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
956 if (modern_apic() || boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
)
962 apic_wait_icr_idle();
964 apic_printk(APIC_DEBUG
, "Synchronizing Arb IDs.\n");
965 apic_write(APIC_ICR
, APIC_DEST_ALLINC
|
966 APIC_INT_LEVELTRIG
| APIC_DM_INIT
);
970 * An initial setup of the virtual wire mode.
972 void __init
init_bsp_APIC(void)
977 * Don't do the setup now if we have a SMP BIOS as the
978 * through-I/O-APIC virtual wire mode might be active.
980 if (smp_found_config
|| !cpu_has_apic
)
984 * Do not trust the local APIC being empty at bootup.
991 value
= apic_read(APIC_SPIV
);
992 value
&= ~APIC_VECTOR_MASK
;
993 value
|= APIC_SPIV_APIC_ENABLED
;
996 /* This bit is reserved on P4/Xeon and should be cleared */
997 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
) &&
998 (boot_cpu_data
.x86
== 15))
999 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
1002 value
|= APIC_SPIV_FOCUS_DISABLED
;
1003 value
|= SPURIOUS_APIC_VECTOR
;
1004 apic_write(APIC_SPIV
, value
);
1007 * Set up the virtual wire mode.
1009 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
1010 value
= APIC_DM_NMI
;
1011 if (!lapic_is_integrated()) /* 82489DX */
1012 value
|= APIC_LVT_LEVEL_TRIGGER
;
1013 apic_write(APIC_LVT1
, value
);
1016 static void __cpuinit
lapic_setup_esr(void)
1018 unsigned long oldvalue
, value
, maxlvt
;
1019 if (lapic_is_integrated() && !esr_disable
) {
1022 * Something untraceable is creating bad interrupts on
1023 * secondary quads ... for the moment, just leave the
1024 * ESR disabled - we can't do anything useful with the
1025 * errors anyway - mbligh
1027 printk(KERN_INFO
"Leaving ESR disabled.\n");
1031 maxlvt
= lapic_get_maxlvt();
1032 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
1033 apic_write(APIC_ESR
, 0);
1034 oldvalue
= apic_read(APIC_ESR
);
1036 /* enables sending errors */
1037 value
= ERROR_APIC_VECTOR
;
1038 apic_write(APIC_LVTERR
, value
);
1040 * spec says clear errors after enabling vector.
1043 apic_write(APIC_ESR
, 0);
1044 value
= apic_read(APIC_ESR
);
1045 if (value
!= oldvalue
)
1046 apic_printk(APIC_VERBOSE
, "ESR value before enabling "
1047 "vector: 0x%08lx after: 0x%08lx\n",
1050 printk(KERN_INFO
"No ESR for 82489DX.\n");
1056 * setup_local_APIC - setup the local APIC
1058 void __cpuinit
setup_local_APIC(void)
1063 #ifdef CONFIG_X86_32
1064 /* Pound the ESR really hard over the head with a big hammer - mbligh */
1066 apic_write(APIC_ESR
, 0);
1067 apic_write(APIC_ESR
, 0);
1068 apic_write(APIC_ESR
, 0);
1069 apic_write(APIC_ESR
, 0);
1076 * Double-check whether this APIC is really registered.
1077 * This is meaningless in clustered apic mode, so we skip it.
1079 if (!apic_id_registered())
1083 * Intel recommends to set DFR, LDR and TPR before enabling
1084 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
1085 * document number 292116). So here it goes...
1090 * Set Task Priority to 'accept all'. We never change this
1093 value
= apic_read(APIC_TASKPRI
);
1094 value
&= ~APIC_TPRI_MASK
;
1095 apic_write(APIC_TASKPRI
, value
);
1098 * After a crash, we no longer service the interrupts and a pending
1099 * interrupt from previous kernel might still have ISR bit set.
1101 * Most probably by now CPU has serviced that pending interrupt and
1102 * it might not have done the ack_APIC_irq() because it thought,
1103 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
1104 * does not clear the ISR bit and cpu thinks it has already serivced
1105 * the interrupt. Hence a vector might get locked. It was noticed
1106 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
1108 for (i
= APIC_ISR_NR
- 1; i
>= 0; i
--) {
1109 value
= apic_read(APIC_ISR
+ i
*0x10);
1110 for (j
= 31; j
>= 0; j
--) {
1117 * Now that we are all set up, enable the APIC
1119 value
= apic_read(APIC_SPIV
);
1120 value
&= ~APIC_VECTOR_MASK
;
1124 value
|= APIC_SPIV_APIC_ENABLED
;
1126 #ifdef CONFIG_X86_32
1128 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1129 * certain networking cards. If high frequency interrupts are
1130 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1131 * entry is masked/unmasked at a high rate as well then sooner or
1132 * later IOAPIC line gets 'stuck', no more interrupts are received
1133 * from the device. If focus CPU is disabled then the hang goes
1136 * [ This bug can be reproduced easily with a level-triggered
1137 * PCI Ne2000 networking cards and PII/PIII processors, dual
1141 * Actually disabling the focus CPU check just makes the hang less
1142 * frequent as it makes the interrupt distributon model be more
1143 * like LRU than MRU (the short-term load is more even across CPUs).
1144 * See also the comment in end_level_ioapic_irq(). --macro
1148 * - enable focus processor (bit==0)
1149 * - 64bit mode always use processor focus
1150 * so no need to set it
1152 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
1156 * Set spurious IRQ vector
1158 value
|= SPURIOUS_APIC_VECTOR
;
1159 apic_write(APIC_SPIV
, value
);
1162 * Set up LVT0, LVT1:
1164 * set up through-local-APIC on the BP's LINT0. This is not
1165 * strictly necessary in pure symmetric-IO mode, but sometimes
1166 * we delegate interrupts to the 8259A.
1169 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1171 value
= apic_read(APIC_LVT0
) & APIC_LVT_MASKED
;
1172 if (!smp_processor_id() && (pic_mode
|| !value
)) {
1173 value
= APIC_DM_EXTINT
;
1174 apic_printk(APIC_VERBOSE
, "enabled ExtINT on CPU#%d\n",
1175 smp_processor_id());
1177 value
= APIC_DM_EXTINT
| APIC_LVT_MASKED
;
1178 apic_printk(APIC_VERBOSE
, "masked ExtINT on CPU#%d\n",
1179 smp_processor_id());
1181 apic_write(APIC_LVT0
, value
);
1184 * only the BP should see the LINT1 NMI signal, obviously.
1186 if (!smp_processor_id())
1187 value
= APIC_DM_NMI
;
1189 value
= APIC_DM_NMI
| APIC_LVT_MASKED
;
1190 if (!lapic_is_integrated()) /* 82489DX */
1191 value
|= APIC_LVT_LEVEL_TRIGGER
;
1192 apic_write(APIC_LVT1
, value
);
1197 void __cpuinit
end_local_APIC_setup(void)
1201 #ifdef CONFIG_X86_32
1204 /* Disable the local apic timer */
1205 value
= apic_read(APIC_LVTT
);
1206 value
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
1207 apic_write(APIC_LVTT
, value
);
1211 setup_apic_nmi_watchdog(NULL
);
1216 * Detect and initialize APIC
1218 static int __init
detect_init_APIC(void)
1222 /* Disabled by kernel option? */
1226 switch (boot_cpu_data
.x86_vendor
) {
1227 case X86_VENDOR_AMD
:
1228 if ((boot_cpu_data
.x86
== 6 && boot_cpu_data
.x86_model
> 1) ||
1229 (boot_cpu_data
.x86
== 15))
1232 case X86_VENDOR_INTEL
:
1233 if (boot_cpu_data
.x86
== 6 || boot_cpu_data
.x86
== 15 ||
1234 (boot_cpu_data
.x86
== 5 && cpu_has_apic
))
1241 if (!cpu_has_apic
) {
1243 * Over-ride BIOS and try to enable the local APIC only if
1244 * "lapic" specified.
1246 if (!force_enable_local_apic
) {
1247 printk(KERN_INFO
"Local APIC disabled by BIOS -- "
1248 "you can enable it with \"lapic\"\n");
1252 * Some BIOSes disable the local APIC in the APIC_BASE
1253 * MSR. This can only be done in software for Intel P6 or later
1254 * and AMD K7 (Model > 1) or later.
1256 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1257 if (!(l
& MSR_IA32_APICBASE_ENABLE
)) {
1259 "Local APIC disabled by BIOS -- reenabling.\n");
1260 l
&= ~MSR_IA32_APICBASE_BASE
;
1261 l
|= MSR_IA32_APICBASE_ENABLE
| APIC_DEFAULT_PHYS_BASE
;
1262 wrmsr(MSR_IA32_APICBASE
, l
, h
);
1263 enabled_via_apicbase
= 1;
1267 * The APIC feature bit should now be enabled
1270 features
= cpuid_edx(1);
1271 if (!(features
& (1 << X86_FEATURE_APIC
))) {
1272 printk(KERN_WARNING
"Could not enable APIC!\n");
1275 set_cpu_cap(&boot_cpu_data
, X86_FEATURE_APIC
);
1276 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
1278 /* The BIOS may have set up the APIC at some other address */
1279 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1280 if (l
& MSR_IA32_APICBASE_ENABLE
)
1281 mp_lapic_addr
= l
& MSR_IA32_APICBASE_BASE
;
1283 printk(KERN_INFO
"Found and enabled local APIC!\n");
1290 printk(KERN_INFO
"No local APIC present or hardware disabled\n");
1295 * init_apic_mappings - initialize APIC mappings
1297 void __init
init_apic_mappings(void)
1300 * If no local APIC can be found then set up a fake all
1301 * zeroes page to simulate the local APIC and another
1302 * one for the IO-APIC.
1304 if (!smp_found_config
&& detect_init_APIC()) {
1305 apic_phys
= (unsigned long) alloc_bootmem_pages(PAGE_SIZE
);
1306 apic_phys
= __pa(apic_phys
);
1308 apic_phys
= mp_lapic_addr
;
1310 set_fixmap_nocache(FIX_APIC_BASE
, apic_phys
);
1311 printk(KERN_DEBUG
"mapped APIC to %08lx (%08lx)\n", APIC_BASE
,
1315 * Fetch the APIC ID of the BSP in case we have a
1316 * default configuration (or the MP table is broken).
1318 if (boot_cpu_physical_apicid
== -1U)
1319 boot_cpu_physical_apicid
= read_apic_id();
1324 * This initializes the IO-APIC and APIC hardware if this is
1328 int apic_version
[MAX_APICS
];
1330 int __init
APIC_init_uniprocessor(void)
1332 if (!smp_found_config
&& !cpu_has_apic
)
1336 * Complain if the BIOS pretends there is one.
1338 if (!cpu_has_apic
&&
1339 APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
])) {
1340 printk(KERN_ERR
"BIOS bug, local APIC #%d not detected!...\n",
1341 boot_cpu_physical_apicid
);
1342 clear_cpu_cap(&boot_cpu_data
, X86_FEATURE_APIC
);
1346 verify_local_APIC();
1351 * Hack: In case of kdump, after a crash, kernel might be booting
1352 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
1353 * might be zero if read from MP tables. Get it from LAPIC.
1355 #ifdef CONFIG_CRASH_DUMP
1356 boot_cpu_physical_apicid
= read_apic_id();
1358 physid_set_mask_of_physid(boot_cpu_physical_apicid
, &phys_cpu_present_map
);
1362 #ifdef CONFIG_X86_IO_APIC
1363 if (!smp_found_config
|| skip_ioapic_setup
|| !nr_ioapics
)
1365 localise_nmi_watchdog();
1366 end_local_APIC_setup();
1367 #ifdef CONFIG_X86_IO_APIC
1368 if (smp_found_config
)
1369 if (!skip_ioapic_setup
&& nr_ioapics
)
1378 * Local APIC interrupts
1382 * This interrupt should _never_ happen with our APIC/SMP architecture
1384 void smp_spurious_interrupt(struct pt_regs
*regs
)
1390 * Check if this really is a spurious interrupt and ACK it
1391 * if it is a vectored one. Just in case...
1392 * Spurious interrupts should not be ACKed.
1394 v
= apic_read(APIC_ISR
+ ((SPURIOUS_APIC_VECTOR
& ~0x1f) >> 1));
1395 if (v
& (1 << (SPURIOUS_APIC_VECTOR
& 0x1f)))
1398 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1399 printk(KERN_INFO
"spurious APIC interrupt on CPU#%d, "
1400 "should never happen.\n", smp_processor_id());
1401 __get_cpu_var(irq_stat
).irq_spurious_count
++;
1406 * This interrupt should never happen with our APIC/SMP architecture
1408 void smp_error_interrupt(struct pt_regs
*regs
)
1410 unsigned long v
, v1
;
1413 /* First tickle the hardware, only then report what went on. -- REW */
1414 v
= apic_read(APIC_ESR
);
1415 apic_write(APIC_ESR
, 0);
1416 v1
= apic_read(APIC_ESR
);
1418 atomic_inc(&irq_err_count
);
1420 /* Here is what the APIC error bits mean:
1423 2: Send accept error
1424 3: Receive accept error
1426 5: Send illegal vector
1427 6: Received illegal vector
1428 7: Illegal register address
1430 printk(KERN_DEBUG
"APIC error on CPU%d: %02lx(%02lx)\n",
1431 smp_processor_id(), v
, v1
);
1436 * connect_bsp_APIC - attach the APIC to the interrupt system
1438 void __init
connect_bsp_APIC(void)
1440 #ifdef CONFIG_X86_32
1443 * Do not trust the local APIC being empty at bootup.
1447 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
1448 * local APIC to INT and NMI lines.
1450 apic_printk(APIC_VERBOSE
, "leaving PIC mode, "
1451 "enabling APIC mode.\n");
1460 * disconnect_bsp_APIC - detach the APIC from the interrupt system
1461 * @virt_wire_setup: indicates, whether virtual wire mode is selected
1463 * Virtual wire mode is necessary to deliver legacy interrupts even when the
1466 void disconnect_bsp_APIC(int virt_wire_setup
)
1470 #ifdef CONFIG_X86_32
1473 * Put the board back into PIC mode (has an effect only on
1474 * certain older boards). Note that APIC interrupts, including
1475 * IPIs, won't work beyond this point! The only exception are
1478 apic_printk(APIC_VERBOSE
, "disabling APIC mode, "
1479 "entering PIC mode.\n");
1486 /* Go back to Virtual Wire compatibility mode */
1488 /* For the spurious interrupt use vector F, and enable it */
1489 value
= apic_read(APIC_SPIV
);
1490 value
&= ~APIC_VECTOR_MASK
;
1491 value
|= APIC_SPIV_APIC_ENABLED
;
1493 apic_write(APIC_SPIV
, value
);
1495 if (!virt_wire_setup
) {
1497 * For LVT0 make it edge triggered, active high,
1498 * external and enabled
1500 value
= apic_read(APIC_LVT0
);
1501 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1502 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1503 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1504 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1505 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_EXTINT
);
1506 apic_write(APIC_LVT0
, value
);
1509 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
1513 * For LVT1 make it edge triggered, active high,
1516 value
= apic_read(APIC_LVT1
);
1517 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1518 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1519 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1520 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1521 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_NMI
);
1522 apic_write(APIC_LVT1
, value
);
1525 void __cpuinit
generic_processor_info(int apicid
, int version
)
1533 if (version
== 0x0) {
1534 printk(KERN_WARNING
"BIOS bug, APIC version is 0 for CPU#%d! "
1535 "fixing up to 0x10. (tell your hw vendor)\n",
1539 apic_version
[apicid
] = version
;
1541 if (num_processors
>= NR_CPUS
) {
1542 printk(KERN_WARNING
"WARNING: NR_CPUS limit of %i reached."
1543 " Processor ignored.\n", NR_CPUS
);
1548 cpus_complement(tmp_map
, cpu_present_map
);
1549 cpu
= first_cpu(tmp_map
);
1551 physid_set(apicid
, phys_cpu_present_map
);
1552 if (apicid
== boot_cpu_physical_apicid
) {
1554 * x86_bios_cpu_apicid is required to have processors listed
1555 * in same order as logical cpu numbers. Hence the first
1556 * entry is BSP, and so on.
1560 if (apicid
> max_physical_apicid
)
1561 max_physical_apicid
= apicid
;
1563 #ifdef CONFIG_X86_32
1565 * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y
1566 * but we need to work other dependencies like SMP_SUSPEND etc
1567 * before this can be done without some confusion.
1568 * if (CPU_HOTPLUG_ENABLED || num_processors > 8)
1569 * - Ashok Raj <ashok.raj@intel.com>
1571 if (max_physical_apicid
>= 8) {
1572 switch (boot_cpu_data
.x86_vendor
) {
1573 case X86_VENDOR_INTEL
:
1574 if (!APIC_XAPIC(version
)) {
1578 /* If P4 and above fall through */
1579 case X86_VENDOR_AMD
:
1585 #if defined(CONFIG_X86_SMP) || defined(CONFIG_X86_64)
1586 /* are we being called early in kernel startup? */
1587 if (early_per_cpu_ptr(x86_cpu_to_apicid
)) {
1588 u16
*cpu_to_apicid
= early_per_cpu_ptr(x86_cpu_to_apicid
);
1589 u16
*bios_cpu_apicid
= early_per_cpu_ptr(x86_bios_cpu_apicid
);
1591 cpu_to_apicid
[cpu
] = apicid
;
1592 bios_cpu_apicid
[cpu
] = apicid
;
1594 per_cpu(x86_cpu_to_apicid
, cpu
) = apicid
;
1595 per_cpu(x86_bios_cpu_apicid
, cpu
) = apicid
;
1599 cpu_set(cpu
, cpu_possible_map
);
1600 cpu_set(cpu
, cpu_present_map
);
1603 #ifdef CONFIG_X86_64
1604 int hard_smp_processor_id(void)
1606 return read_apic_id();
1617 * 'active' is true if the local APIC was enabled by us and
1618 * not the BIOS; this signifies that we are also responsible
1619 * for disabling it before entering apm/acpi suspend
1622 /* r/w apic fields */
1623 unsigned int apic_id
;
1624 unsigned int apic_taskpri
;
1625 unsigned int apic_ldr
;
1626 unsigned int apic_dfr
;
1627 unsigned int apic_spiv
;
1628 unsigned int apic_lvtt
;
1629 unsigned int apic_lvtpc
;
1630 unsigned int apic_lvt0
;
1631 unsigned int apic_lvt1
;
1632 unsigned int apic_lvterr
;
1633 unsigned int apic_tmict
;
1634 unsigned int apic_tdcr
;
1635 unsigned int apic_thmr
;
1638 static int lapic_suspend(struct sys_device
*dev
, pm_message_t state
)
1640 unsigned long flags
;
1643 if (!apic_pm_state
.active
)
1646 maxlvt
= lapic_get_maxlvt();
1648 apic_pm_state
.apic_id
= apic_read(APIC_ID
);
1649 apic_pm_state
.apic_taskpri
= apic_read(APIC_TASKPRI
);
1650 apic_pm_state
.apic_ldr
= apic_read(APIC_LDR
);
1651 apic_pm_state
.apic_dfr
= apic_read(APIC_DFR
);
1652 apic_pm_state
.apic_spiv
= apic_read(APIC_SPIV
);
1653 apic_pm_state
.apic_lvtt
= apic_read(APIC_LVTT
);
1655 apic_pm_state
.apic_lvtpc
= apic_read(APIC_LVTPC
);
1656 apic_pm_state
.apic_lvt0
= apic_read(APIC_LVT0
);
1657 apic_pm_state
.apic_lvt1
= apic_read(APIC_LVT1
);
1658 apic_pm_state
.apic_lvterr
= apic_read(APIC_LVTERR
);
1659 apic_pm_state
.apic_tmict
= apic_read(APIC_TMICT
);
1660 apic_pm_state
.apic_tdcr
= apic_read(APIC_TDCR
);
1661 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
1663 apic_pm_state
.apic_thmr
= apic_read(APIC_LVTTHMR
);
1666 local_irq_save(flags
);
1667 disable_local_APIC();
1668 local_irq_restore(flags
);
1672 static int lapic_resume(struct sys_device
*dev
)
1675 unsigned long flags
;
1678 if (!apic_pm_state
.active
)
1681 maxlvt
= lapic_get_maxlvt();
1683 local_irq_save(flags
);
1685 #ifdef CONFIG_X86_64
1692 * Make sure the APICBASE points to the right address
1694 * FIXME! This will be wrong if we ever support suspend on
1695 * SMP! We'll need to do this as part of the CPU restore!
1697 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1698 l
&= ~MSR_IA32_APICBASE_BASE
;
1699 l
|= MSR_IA32_APICBASE_ENABLE
| mp_lapic_addr
;
1700 wrmsr(MSR_IA32_APICBASE
, l
, h
);
1703 apic_write(APIC_LVTERR
, ERROR_APIC_VECTOR
| APIC_LVT_MASKED
);
1704 apic_write(APIC_ID
, apic_pm_state
.apic_id
);
1705 apic_write(APIC_DFR
, apic_pm_state
.apic_dfr
);
1706 apic_write(APIC_LDR
, apic_pm_state
.apic_ldr
);
1707 apic_write(APIC_TASKPRI
, apic_pm_state
.apic_taskpri
);
1708 apic_write(APIC_SPIV
, apic_pm_state
.apic_spiv
);
1709 apic_write(APIC_LVT0
, apic_pm_state
.apic_lvt0
);
1710 apic_write(APIC_LVT1
, apic_pm_state
.apic_lvt1
);
1711 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
1713 apic_write(APIC_LVTTHMR
, apic_pm_state
.apic_thmr
);
1716 apic_write(APIC_LVTPC
, apic_pm_state
.apic_lvtpc
);
1717 apic_write(APIC_LVTT
, apic_pm_state
.apic_lvtt
);
1718 apic_write(APIC_TDCR
, apic_pm_state
.apic_tdcr
);
1719 apic_write(APIC_TMICT
, apic_pm_state
.apic_tmict
);
1720 apic_write(APIC_ESR
, 0);
1721 apic_read(APIC_ESR
);
1722 apic_write(APIC_LVTERR
, apic_pm_state
.apic_lvterr
);
1723 apic_write(APIC_ESR
, 0);
1724 apic_read(APIC_ESR
);
1726 local_irq_restore(flags
);
1732 * This device has no shutdown method - fully functioning local APICs
1733 * are needed on every CPU up until machine_halt/restart/poweroff.
1736 static struct sysdev_class lapic_sysclass
= {
1738 .resume
= lapic_resume
,
1739 .suspend
= lapic_suspend
,
1742 static struct sys_device device_lapic
= {
1744 .cls
= &lapic_sysclass
,
1747 static void __cpuinit
apic_pm_activate(void)
1749 apic_pm_state
.active
= 1;
1752 static int __init
init_lapic_sysfs(void)
1758 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
1760 error
= sysdev_class_register(&lapic_sysclass
);
1762 error
= sysdev_register(&device_lapic
);
1765 device_initcall(init_lapic_sysfs
);
1767 #else /* CONFIG_PM */
1769 static void apic_pm_activate(void) { }
1771 #endif /* CONFIG_PM */
1774 static int __init
setup_disableapic(char *arg
)
1777 setup_clear_cpu_cap(X86_FEATURE_APIC
);
1780 early_param("disableapic", setup_disableapic
);
1782 /* same as disableapic, for compatibility */
1783 static int __init
setup_nolapic(char *arg
)
1785 return setup_disableapic(arg
);
1787 early_param("nolapic", setup_nolapic
);
1789 static int __init
parse_lapic_timer_c2_ok(char *arg
)
1791 local_apic_timer_c2_ok
= 1;
1794 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok
);
1796 static int __init
parse_disable_apic_timer(char *arg
)
1798 disable_apic_timer
= 1;
1801 early_param("noapictimer", parse_disable_apic_timer
);
1803 static int __init
parse_nolapic_timer(char *arg
)
1805 disable_apic_timer
= 1;
1808 early_param("nolapic_timer", parse_nolapic_timer
);
1810 static int __init
apic_set_verbosity(char *arg
)
1813 #ifdef CONFIG_X86_64
1814 skip_ioapic_setup
= 0;
1821 if (strcmp("debug", arg
) == 0)
1822 apic_verbosity
= APIC_DEBUG
;
1823 else if (strcmp("verbose", arg
) == 0)
1824 apic_verbosity
= APIC_VERBOSE
;
1826 printk(KERN_WARNING
"APIC Verbosity level %s not recognised"
1827 " use apic=verbose or apic=debug\n", arg
);
1833 early_param("apic", apic_set_verbosity
);
1835 static int __init
lapic_insert_resource(void)
1840 /* Put local APIC into the resource map. */
1841 lapic_resource
.start
= apic_phys
;
1842 lapic_resource
.end
= lapic_resource
.start
+ PAGE_SIZE
- 1;
1843 insert_resource(&iomem_resource
, &lapic_resource
);
1849 * need call insert after e820_reserve_resources()
1850 * that is using request_resource
1852 late_initcall(lapic_insert_resource
);