2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/bootmem.h>
22 #include <linux/interrupt.h>
23 #include <linux/mc146818rtc.h>
24 #include <linux/kernel_stat.h>
25 #include <linux/sysdev.h>
26 #include <linux/cpu.h>
27 #include <linux/clockchips.h>
28 #include <linux/acpi_pmtmr.h>
29 #include <linux/module.h>
30 #include <linux/dmi.h>
32 #include <asm/atomic.h>
35 #include <asm/mpspec.h>
37 #include <asm/arch_hooks.h>
39 #include <asm/i8253.h>
42 #include <mach_apic.h>
43 #include <mach_apicdef.h>
49 #if ((SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F)
50 # error SPURIOUS_APIC_VECTOR definition error
53 unsigned long mp_lapic_addr
;
56 * Knob to control our willingness to enable the local APIC.
60 static int force_enable_local_apic
;
63 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
64 static int disable_apic_timer __cpuinitdata
;
65 /* Local APIC timer works in C2 */
66 int local_apic_timer_c2_ok
;
67 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok
);
69 int first_system_vector
= 0xfe;
71 char system_vectors
[NR_VECTORS
] = { [0 ... NR_VECTORS
-1] = SYS_VECTOR_FREE
};
74 * Debug level, exported for io_apic.c
76 unsigned int apic_verbosity
;
80 /* Have we found an MP table */
83 static struct resource lapic_resource
= {
85 .flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
,
88 static unsigned int calibration_result
;
90 static int lapic_next_event(unsigned long delta
,
91 struct clock_event_device
*evt
);
92 static void lapic_timer_setup(enum clock_event_mode mode
,
93 struct clock_event_device
*evt
);
94 static void lapic_timer_broadcast(cpumask_t mask
);
95 static void apic_pm_activate(void);
98 * The local apic timer can be used for any function which is CPU local.
100 static struct clock_event_device lapic_clockevent
= {
102 .features
= CLOCK_EVT_FEAT_PERIODIC
| CLOCK_EVT_FEAT_ONESHOT
103 | CLOCK_EVT_FEAT_C3STOP
| CLOCK_EVT_FEAT_DUMMY
,
105 .set_mode
= lapic_timer_setup
,
106 .set_next_event
= lapic_next_event
,
107 .broadcast
= lapic_timer_broadcast
,
111 static DEFINE_PER_CPU(struct clock_event_device
, lapic_events
);
113 /* Local APIC was disabled by the BIOS and enabled by the kernel */
114 static int enabled_via_apicbase
;
116 static unsigned long apic_phys
;
119 * Get the LAPIC version
121 static inline int lapic_get_version(void)
123 return GET_APIC_VERSION(apic_read(APIC_LVR
));
127 * Check, if the APIC is integrated or a separate chip
129 static inline int lapic_is_integrated(void)
131 return APIC_INTEGRATED(lapic_get_version());
135 * Check, whether this is a modern or a first generation APIC
137 static int modern_apic(void)
139 /* AMD systems use old APIC versions, so check the CPU */
140 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
&&
141 boot_cpu_data
.x86
>= 0xf)
143 return lapic_get_version() >= 0x14;
147 * Paravirt kernels also might be using these below ops. So we still
148 * use generic apic_read()/apic_write(), which might be pointing to different
149 * ops in PARAVIRT case.
151 void xapic_wait_icr_idle(void)
153 while (apic_read(APIC_ICR
) & APIC_ICR_BUSY
)
157 u32
safe_xapic_wait_icr_idle(void)
164 send_status
= apic_read(APIC_ICR
) & APIC_ICR_BUSY
;
168 } while (timeout
++ < 1000);
173 void xapic_icr_write(u32 low
, u32 id
)
175 apic_write(APIC_ICR2
, SET_APIC_DEST_FIELD(id
));
176 apic_write(APIC_ICR
, low
);
179 u64
xapic_icr_read(void)
183 icr2
= apic_read(APIC_ICR2
);
184 icr1
= apic_read(APIC_ICR
);
186 return icr1
| ((u64
)icr2
<< 32);
189 static struct apic_ops xapic_ops
= {
190 .read
= native_apic_mem_read
,
191 .write
= native_apic_mem_write
,
192 .icr_read
= xapic_icr_read
,
193 .icr_write
= xapic_icr_write
,
194 .wait_icr_idle
= xapic_wait_icr_idle
,
195 .safe_wait_icr_idle
= safe_xapic_wait_icr_idle
,
198 struct apic_ops __read_mostly
*apic_ops
= &xapic_ops
;
199 EXPORT_SYMBOL_GPL(apic_ops
);
202 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
204 void __cpuinit
enable_NMI_through_LVT0(void)
208 /* unmask and set to NMI */
211 /* Level triggered for 82489DX (32bit mode) */
212 if (!lapic_is_integrated())
213 v
|= APIC_LVT_LEVEL_TRIGGER
;
215 apic_write(APIC_LVT0
, v
);
219 * get_physical_broadcast - Get number of physical broadcast IDs
221 int get_physical_broadcast(void)
223 return modern_apic() ? 0xff : 0xf;
227 * lapic_get_maxlvt - get the maximum number of local vector table entries
229 int lapic_get_maxlvt(void)
233 v
= apic_read(APIC_LVR
);
235 * - we always have APIC integrated on 64bit mode
236 * - 82489DXs do not report # of LVT entries
238 return APIC_INTEGRATED(GET_APIC_VERSION(v
)) ? GET_APIC_MAXLVT(v
) : 2;
245 /* Clock divisor is set to 16 */
246 #define APIC_DIVISOR 16
249 * This function sets up the local APIC timer, with a timeout of
250 * 'clocks' APIC bus clock. During calibration we actually call
251 * this function twice on the boot CPU, once with a bogus timeout
252 * value, second time for real. The other (noncalibrating) CPUs
253 * call this function only once, with the real, calibrated value.
255 * We do reads before writes even if unnecessary, to get around the
256 * P5 APIC double write bug.
258 static void __setup_APIC_LVTT(unsigned int clocks
, int oneshot
, int irqen
)
260 unsigned int lvtt_value
, tmp_value
;
262 lvtt_value
= LOCAL_TIMER_VECTOR
;
264 lvtt_value
|= APIC_LVT_TIMER_PERIODIC
;
265 if (!lapic_is_integrated())
266 lvtt_value
|= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV
);
269 lvtt_value
|= APIC_LVT_MASKED
;
271 apic_write(APIC_LVTT
, lvtt_value
);
276 tmp_value
= apic_read(APIC_TDCR
);
277 apic_write(APIC_TDCR
,
278 (tmp_value
& ~(APIC_TDR_DIV_1
| APIC_TDR_DIV_TMBASE
)) |
282 apic_write(APIC_TMICT
, clocks
/ APIC_DIVISOR
);
286 * Setup extended LVT, AMD specific (K8, family 10h)
288 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
289 * MCE interrupts are supported. Thus MCE offset must be set to 0.
292 #define APIC_EILVT_LVTOFF_MCE 0
293 #define APIC_EILVT_LVTOFF_IBS 1
295 static void setup_APIC_eilvt(u8 lvt_off
, u8 vector
, u8 msg_type
, u8 mask
)
297 unsigned long reg
= (lvt_off
<< 4) + APIC_EILVT0
;
298 unsigned int v
= (mask
<< 16) | (msg_type
<< 8) | vector
;
303 u8
setup_APIC_eilvt_mce(u8 vector
, u8 msg_type
, u8 mask
)
305 setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE
, vector
, msg_type
, mask
);
306 return APIC_EILVT_LVTOFF_MCE
;
309 u8
setup_APIC_eilvt_ibs(u8 vector
, u8 msg_type
, u8 mask
)
311 setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS
, vector
, msg_type
, mask
);
312 return APIC_EILVT_LVTOFF_IBS
;
316 * Program the next event, relative to now
318 static int lapic_next_event(unsigned long delta
,
319 struct clock_event_device
*evt
)
321 apic_write(APIC_TMICT
, delta
);
326 * Setup the lapic timer in periodic or oneshot mode
328 static void lapic_timer_setup(enum clock_event_mode mode
,
329 struct clock_event_device
*evt
)
334 /* Lapic used as dummy for broadcast ? */
335 if (evt
->features
& CLOCK_EVT_FEAT_DUMMY
)
338 local_irq_save(flags
);
341 case CLOCK_EVT_MODE_PERIODIC
:
342 case CLOCK_EVT_MODE_ONESHOT
:
343 __setup_APIC_LVTT(calibration_result
,
344 mode
!= CLOCK_EVT_MODE_PERIODIC
, 1);
346 case CLOCK_EVT_MODE_UNUSED
:
347 case CLOCK_EVT_MODE_SHUTDOWN
:
348 v
= apic_read(APIC_LVTT
);
349 v
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
350 apic_write(APIC_LVTT
, v
);
352 case CLOCK_EVT_MODE_RESUME
:
353 /* Nothing to do here */
357 local_irq_restore(flags
);
361 * Local APIC timer broadcast function
363 static void lapic_timer_broadcast(cpumask_t mask
)
366 send_IPI_mask(mask
, LOCAL_TIMER_VECTOR
);
371 * Setup the local APIC timer for this CPU. Copy the initilized values
372 * of the boot CPU and register the clock event in the framework.
374 static void __devinit
setup_APIC_timer(void)
376 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
378 memcpy(levt
, &lapic_clockevent
, sizeof(*levt
));
379 levt
->cpumask
= cpumask_of_cpu(smp_processor_id());
381 clockevents_register_device(levt
);
385 * In this functions we calibrate APIC bus clocks to the external timer.
387 * We want to do the calibration only once since we want to have local timer
388 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
391 * This was previously done by reading the PIT/HPET and waiting for a wrap
392 * around to find out, that a tick has elapsed. I have a box, where the PIT
393 * readout is broken, so it never gets out of the wait loop again. This was
394 * also reported by others.
396 * Monitoring the jiffies value is inaccurate and the clockevents
397 * infrastructure allows us to do a simple substitution of the interrupt
400 * The calibration routine also uses the pm_timer when possible, as the PIT
401 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
402 * back to normal later in the boot process).
405 #define LAPIC_CAL_LOOPS (HZ/10)
407 static __initdata
int lapic_cal_loops
= -1;
408 static __initdata
long lapic_cal_t1
, lapic_cal_t2
;
409 static __initdata
unsigned long long lapic_cal_tsc1
, lapic_cal_tsc2
;
410 static __initdata
unsigned long lapic_cal_pm1
, lapic_cal_pm2
;
411 static __initdata
unsigned long lapic_cal_j1
, lapic_cal_j2
;
414 * Temporary interrupt handler.
416 static void __init
lapic_cal_handler(struct clock_event_device
*dev
)
418 unsigned long long tsc
= 0;
419 long tapic
= apic_read(APIC_TMCCT
);
420 unsigned long pm
= acpi_pm_read_early();
425 switch (lapic_cal_loops
++) {
427 lapic_cal_t1
= tapic
;
428 lapic_cal_tsc1
= tsc
;
430 lapic_cal_j1
= jiffies
;
433 case LAPIC_CAL_LOOPS
:
434 lapic_cal_t2
= tapic
;
435 lapic_cal_tsc2
= tsc
;
436 if (pm
< lapic_cal_pm1
)
437 pm
+= ACPI_PM_OVRRUN
;
439 lapic_cal_j2
= jiffies
;
444 static int __init
calibrate_APIC_clock(void)
446 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
447 const long pm_100ms
= PMTMR_TICKS_PER_SEC
/10;
448 const long pm_thresh
= pm_100ms
/100;
449 void (*real_handler
)(struct clock_event_device
*dev
);
450 unsigned long deltaj
;
452 int pm_referenced
= 0;
456 /* Replace the global interrupt handler */
457 real_handler
= global_clock_event
->event_handler
;
458 global_clock_event
->event_handler
= lapic_cal_handler
;
461 * Setup the APIC counter to 1e9. There is no way the lapic
462 * can underflow in the 100ms detection time frame
464 __setup_APIC_LVTT(1000000000, 0, 0);
466 /* Let the interrupts run */
469 while (lapic_cal_loops
<= LAPIC_CAL_LOOPS
)
474 /* Restore the real event handler */
475 global_clock_event
->event_handler
= real_handler
;
477 /* Build delta t1-t2 as apic timer counts down */
478 delta
= lapic_cal_t1
- lapic_cal_t2
;
479 apic_printk(APIC_VERBOSE
, "... lapic delta = %ld\n", delta
);
481 /* Check, if the PM timer is available */
482 deltapm
= lapic_cal_pm2
- lapic_cal_pm1
;
483 apic_printk(APIC_VERBOSE
, "... PM timer delta = %ld\n", deltapm
);
489 mult
= clocksource_hz2mult(PMTMR_TICKS_PER_SEC
, 22);
491 if (deltapm
> (pm_100ms
- pm_thresh
) &&
492 deltapm
< (pm_100ms
+ pm_thresh
)) {
493 apic_printk(APIC_VERBOSE
, "... PM timer result ok\n");
495 res
= (((u64
) deltapm
) * mult
) >> 22;
496 do_div(res
, 1000000);
497 printk(KERN_WARNING
"APIC calibration not consistent "
498 "with PM Timer: %ldms instead of 100ms\n",
500 /* Correct the lapic counter value */
501 res
= (((u64
) delta
) * pm_100ms
);
502 do_div(res
, deltapm
);
503 printk(KERN_INFO
"APIC delta adjusted to PM-Timer: "
504 "%lu (%ld)\n", (unsigned long) res
, delta
);
510 /* Calculate the scaled math multiplication factor */
511 lapic_clockevent
.mult
= div_sc(delta
, TICK_NSEC
* LAPIC_CAL_LOOPS
,
512 lapic_clockevent
.shift
);
513 lapic_clockevent
.max_delta_ns
=
514 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent
);
515 lapic_clockevent
.min_delta_ns
=
516 clockevent_delta2ns(0xF, &lapic_clockevent
);
518 calibration_result
= (delta
* APIC_DIVISOR
) / LAPIC_CAL_LOOPS
;
520 apic_printk(APIC_VERBOSE
, "..... delta %ld\n", delta
);
521 apic_printk(APIC_VERBOSE
, "..... mult: %ld\n", lapic_clockevent
.mult
);
522 apic_printk(APIC_VERBOSE
, "..... calibration result: %u\n",
526 delta
= (long)(lapic_cal_tsc2
- lapic_cal_tsc1
);
527 apic_printk(APIC_VERBOSE
, "..... CPU clock speed is "
529 (delta
/ LAPIC_CAL_LOOPS
) / (1000000 / HZ
),
530 (delta
/ LAPIC_CAL_LOOPS
) % (1000000 / HZ
));
533 apic_printk(APIC_VERBOSE
, "..... host bus clock speed is "
535 calibration_result
/ (1000000 / HZ
),
536 calibration_result
% (1000000 / HZ
));
539 * Do a sanity check on the APIC calibration result
541 if (calibration_result
< (1000000 / HZ
)) {
544 "APIC frequency too slow, disabling apic timer\n");
548 levt
->features
&= ~CLOCK_EVT_FEAT_DUMMY
;
550 /* We trust the pm timer based calibration */
551 if (!pm_referenced
) {
552 apic_printk(APIC_VERBOSE
, "... verify APIC timer\n");
555 * Setup the apic timer manually
557 levt
->event_handler
= lapic_cal_handler
;
558 lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC
, levt
);
559 lapic_cal_loops
= -1;
561 /* Let the interrupts run */
564 while (lapic_cal_loops
<= LAPIC_CAL_LOOPS
)
569 /* Stop the lapic timer */
570 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, levt
);
575 deltaj
= lapic_cal_j2
- lapic_cal_j1
;
576 apic_printk(APIC_VERBOSE
, "... jiffies delta = %lu\n", deltaj
);
578 /* Check, if the jiffies result is consistent */
579 if (deltaj
>= LAPIC_CAL_LOOPS
-2 && deltaj
<= LAPIC_CAL_LOOPS
+2)
580 apic_printk(APIC_VERBOSE
, "... jiffies result ok\n");
582 levt
->features
|= CLOCK_EVT_FEAT_DUMMY
;
586 if (levt
->features
& CLOCK_EVT_FEAT_DUMMY
) {
588 "APIC timer disabled due to verification failure.\n");
596 * Setup the boot APIC
598 * Calibrate and verify the result.
600 void __init
setup_boot_APIC_clock(void)
603 * The local apic timer can be disabled via the kernel
604 * commandline or from the CPU detection code. Register the lapic
605 * timer as a dummy clock event source on SMP systems, so the
606 * broadcast mechanism is used. On UP systems simply ignore it.
608 if (disable_apic_timer
) {
609 /* No broadcast on UP ! */
610 if (num_possible_cpus() > 1) {
611 lapic_clockevent
.mult
= 1;
617 apic_printk(APIC_VERBOSE
, "Using local APIC timer interrupts.\n"
618 "calibrating APIC timer ...\n");
620 if (calibrate_APIC_clock()) {
621 /* No broadcast on UP ! */
622 if (num_possible_cpus() > 1)
628 * If nmi_watchdog is set to IO_APIC, we need the
629 * PIT/HPET going. Otherwise register lapic as a dummy
632 if (nmi_watchdog
!= NMI_IO_APIC
)
633 lapic_clockevent
.features
&= ~CLOCK_EVT_FEAT_DUMMY
;
635 printk(KERN_WARNING
"APIC timer registered as dummy,"
636 " due to nmi_watchdog=%d!\n", nmi_watchdog
);
638 /* Setup the lapic or request the broadcast */
642 void __devinit
setup_secondary_APIC_clock(void)
648 * The guts of the apic timer interrupt
650 static void local_apic_timer_interrupt(void)
652 int cpu
= smp_processor_id();
653 struct clock_event_device
*evt
= &per_cpu(lapic_events
, cpu
);
656 * Normally we should not be here till LAPIC has been initialized but
657 * in some cases like kdump, its possible that there is a pending LAPIC
658 * timer interrupt from previous kernel's context and is delivered in
659 * new kernel the moment interrupts are enabled.
661 * Interrupts are enabled early and LAPIC is setup much later, hence
662 * its possible that when we get here evt->event_handler is NULL.
663 * Check for event_handler being NULL and discard the interrupt as
666 if (!evt
->event_handler
) {
668 "Spurious LAPIC timer interrupt on cpu %d\n", cpu
);
670 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, evt
);
675 * the NMI deadlock-detector uses this.
677 per_cpu(irq_stat
, cpu
).apic_timer_irqs
++;
679 evt
->event_handler(evt
);
683 * Local APIC timer interrupt. This is the most natural way for doing
684 * local interrupts, but local timer interrupts can be emulated by
685 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
687 * [ if a single-CPU system runs an SMP kernel then we call the local
688 * interrupt as well. Thus we cannot inline the local irq ... ]
690 void smp_apic_timer_interrupt(struct pt_regs
*regs
)
692 struct pt_regs
*old_regs
= set_irq_regs(regs
);
695 * NOTE! We'd better ACK the irq immediately,
696 * because timer handling can be slow.
700 * update_process_times() expects us to have done irq_enter().
701 * Besides, if we don't timer interrupts ignore the global
702 * interrupt lock, which is the WrongThing (tm) to do.
705 local_apic_timer_interrupt();
708 set_irq_regs(old_regs
);
711 int setup_profiling_timer(unsigned int multiplier
)
717 * Local APIC start and shutdown
721 * clear_local_APIC - shutdown the local APIC
723 * This is called, when a CPU is disabled and before rebooting, so the state of
724 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
725 * leftovers during boot.
727 void clear_local_APIC(void)
732 /* APIC hasn't been mapped yet */
736 maxlvt
= lapic_get_maxlvt();
738 * Masking an LVT entry can trigger a local APIC error
739 * if the vector is zero. Mask LVTERR first to prevent this.
742 v
= ERROR_APIC_VECTOR
; /* any non-zero vector will do */
743 apic_write(APIC_LVTERR
, v
| APIC_LVT_MASKED
);
746 * Careful: we have to set masks only first to deassert
747 * any level-triggered sources.
749 v
= apic_read(APIC_LVTT
);
750 apic_write(APIC_LVTT
, v
| APIC_LVT_MASKED
);
751 v
= apic_read(APIC_LVT0
);
752 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
753 v
= apic_read(APIC_LVT1
);
754 apic_write(APIC_LVT1
, v
| APIC_LVT_MASKED
);
756 v
= apic_read(APIC_LVTPC
);
757 apic_write(APIC_LVTPC
, v
| APIC_LVT_MASKED
);
760 /* lets not touch this if we didn't frob it */
761 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(X86_MCE_INTEL)
763 v
= apic_read(APIC_LVTTHMR
);
764 apic_write(APIC_LVTTHMR
, v
| APIC_LVT_MASKED
);
768 * Clean APIC state for other OSs:
770 apic_write(APIC_LVTT
, APIC_LVT_MASKED
);
771 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
772 apic_write(APIC_LVT1
, APIC_LVT_MASKED
);
774 apic_write(APIC_LVTERR
, APIC_LVT_MASKED
);
776 apic_write(APIC_LVTPC
, APIC_LVT_MASKED
);
778 /* Integrated APIC (!82489DX) ? */
779 if (lapic_is_integrated()) {
781 /* Clear ESR due to Pentium errata 3AP and 11AP */
782 apic_write(APIC_ESR
, 0);
788 * disable_local_APIC - clear and disable the local APIC
790 void disable_local_APIC(void)
797 * Disable APIC (implies clearing of registers
800 value
= apic_read(APIC_SPIV
);
801 value
&= ~APIC_SPIV_APIC_ENABLED
;
802 apic_write(APIC_SPIV
, value
);
805 * When LAPIC was disabled by the BIOS and enabled by the kernel,
806 * restore the disabled state.
808 if (enabled_via_apicbase
) {
811 rdmsr(MSR_IA32_APICBASE
, l
, h
);
812 l
&= ~MSR_IA32_APICBASE_ENABLE
;
813 wrmsr(MSR_IA32_APICBASE
, l
, h
);
818 * If Linux enabled the LAPIC against the BIOS default disable it down before
819 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
820 * not power-off. Additionally clear all LVT entries before disable_local_APIC
821 * for the case where Linux didn't enable the LAPIC.
823 void lapic_shutdown(void)
830 local_irq_save(flags
);
832 if (enabled_via_apicbase
)
833 disable_local_APIC();
837 local_irq_restore(flags
);
841 * This is to verify that we're looking at a real local APIC.
842 * Check these against your board if the CPUs aren't getting
843 * started for no apparent reason.
845 int __init
verify_local_APIC(void)
847 unsigned int reg0
, reg1
;
850 * The version register is read-only in a real APIC.
852 reg0
= apic_read(APIC_LVR
);
853 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg0
);
854 apic_write(APIC_LVR
, reg0
^ APIC_LVR_MASK
);
855 reg1
= apic_read(APIC_LVR
);
856 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg1
);
859 * The two version reads above should print the same
860 * numbers. If the second one is different, then we
861 * poke at a non-APIC.
867 * Check if the version looks reasonably.
869 reg1
= GET_APIC_VERSION(reg0
);
870 if (reg1
== 0x00 || reg1
== 0xff)
872 reg1
= lapic_get_maxlvt();
873 if (reg1
< 0x02 || reg1
== 0xff)
877 * The ID register is read/write in a real APIC.
879 reg0
= apic_read(APIC_ID
);
880 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg0
);
881 apic_write(APIC_ID
, reg0
^ APIC_ID_MASK
);
882 reg1
= apic_read(APIC_ID
);
883 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg1
);
884 apic_write(APIC_ID
, reg0
);
885 if (reg1
!= (reg0
^ APIC_ID_MASK
))
889 * The next two are just to see if we have sane values.
890 * They're only really relevant if we're in Virtual Wire
891 * compatibility mode, but most boxes are anymore.
893 reg0
= apic_read(APIC_LVT0
);
894 apic_printk(APIC_DEBUG
, "Getting LVT0: %x\n", reg0
);
895 reg1
= apic_read(APIC_LVT1
);
896 apic_printk(APIC_DEBUG
, "Getting LVT1: %x\n", reg1
);
902 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
904 void __init
sync_Arb_IDs(void)
907 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
910 if (modern_apic() || boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
)
916 apic_wait_icr_idle();
918 apic_printk(APIC_DEBUG
, "Synchronizing Arb IDs.\n");
919 apic_write(APIC_ICR
, APIC_DEST_ALLINC
|
920 APIC_INT_LEVELTRIG
| APIC_DM_INIT
);
924 * An initial setup of the virtual wire mode.
926 void __init
init_bsp_APIC(void)
931 * Don't do the setup now if we have a SMP BIOS as the
932 * through-I/O-APIC virtual wire mode might be active.
934 if (smp_found_config
|| !cpu_has_apic
)
938 * Do not trust the local APIC being empty at bootup.
945 value
= apic_read(APIC_SPIV
);
946 value
&= ~APIC_VECTOR_MASK
;
947 value
|= APIC_SPIV_APIC_ENABLED
;
950 /* This bit is reserved on P4/Xeon and should be cleared */
951 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
) &&
952 (boot_cpu_data
.x86
== 15))
953 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
956 value
|= APIC_SPIV_FOCUS_DISABLED
;
957 value
|= SPURIOUS_APIC_VECTOR
;
958 apic_write(APIC_SPIV
, value
);
961 * Set up the virtual wire mode.
963 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
965 if (!lapic_is_integrated()) /* 82489DX */
966 value
|= APIC_LVT_LEVEL_TRIGGER
;
967 apic_write(APIC_LVT1
, value
);
970 static void __cpuinit
lapic_setup_esr(void)
972 unsigned long oldvalue
, value
, maxlvt
;
973 if (lapic_is_integrated() && !esr_disable
) {
975 maxlvt
= lapic_get_maxlvt();
976 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
977 apic_write(APIC_ESR
, 0);
978 oldvalue
= apic_read(APIC_ESR
);
980 /* enables sending errors */
981 value
= ERROR_APIC_VECTOR
;
982 apic_write(APIC_LVTERR
, value
);
984 * spec says clear errors after enabling vector.
987 apic_write(APIC_ESR
, 0);
988 value
= apic_read(APIC_ESR
);
989 if (value
!= oldvalue
)
990 apic_printk(APIC_VERBOSE
, "ESR value before enabling "
991 "vector: 0x%08lx after: 0x%08lx\n",
996 * Something untraceable is creating bad interrupts on
997 * secondary quads ... for the moment, just leave the
998 * ESR disabled - we can't do anything useful with the
999 * errors anyway - mbligh
1001 printk(KERN_INFO
"Leaving ESR disabled.\n");
1003 printk(KERN_INFO
"No ESR for 82489DX.\n");
1009 * setup_local_APIC - setup the local APIC
1011 void __cpuinit
setup_local_APIC(void)
1013 unsigned long value
, integrated
;
1016 /* Pound the ESR really hard over the head with a big hammer - mbligh */
1018 apic_write(APIC_ESR
, 0);
1019 apic_write(APIC_ESR
, 0);
1020 apic_write(APIC_ESR
, 0);
1021 apic_write(APIC_ESR
, 0);
1024 integrated
= lapic_is_integrated();
1027 * Double-check whether this APIC is really registered.
1029 if (!apic_id_registered())
1033 * Intel recommends to set DFR, LDR and TPR before enabling
1034 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
1035 * document number 292116). So here it goes...
1040 * Set Task Priority to 'accept all'. We never change this
1043 value
= apic_read(APIC_TASKPRI
);
1044 value
&= ~APIC_TPRI_MASK
;
1045 apic_write(APIC_TASKPRI
, value
);
1048 * After a crash, we no longer service the interrupts and a pending
1049 * interrupt from previous kernel might still have ISR bit set.
1051 * Most probably by now CPU has serviced that pending interrupt and
1052 * it might not have done the ack_APIC_irq() because it thought,
1053 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
1054 * does not clear the ISR bit and cpu thinks it has already serivced
1055 * the interrupt. Hence a vector might get locked. It was noticed
1056 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
1058 for (i
= APIC_ISR_NR
- 1; i
>= 0; i
--) {
1059 value
= apic_read(APIC_ISR
+ i
*0x10);
1060 for (j
= 31; j
>= 0; j
--) {
1067 * Now that we are all set up, enable the APIC
1069 value
= apic_read(APIC_SPIV
);
1070 value
&= ~APIC_VECTOR_MASK
;
1074 value
|= APIC_SPIV_APIC_ENABLED
;
1077 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1078 * certain networking cards. If high frequency interrupts are
1079 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1080 * entry is masked/unmasked at a high rate as well then sooner or
1081 * later IOAPIC line gets 'stuck', no more interrupts are received
1082 * from the device. If focus CPU is disabled then the hang goes
1085 * [ This bug can be reproduced easily with a level-triggered
1086 * PCI Ne2000 networking cards and PII/PIII processors, dual
1090 * Actually disabling the focus CPU check just makes the hang less
1091 * frequent as it makes the interrupt distributon model be more
1092 * like LRU than MRU (the short-term load is more even across CPUs).
1093 * See also the comment in end_level_ioapic_irq(). --macro
1096 /* Enable focus processor (bit==0) */
1097 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
1100 * Set spurious IRQ vector
1102 value
|= SPURIOUS_APIC_VECTOR
;
1103 apic_write(APIC_SPIV
, value
);
1106 * Set up LVT0, LVT1:
1108 * set up through-local-APIC on the BP's LINT0. This is not
1109 * strictly necessary in pure symmetric-IO mode, but sometimes
1110 * we delegate interrupts to the 8259A.
1113 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1115 value
= apic_read(APIC_LVT0
) & APIC_LVT_MASKED
;
1116 if (!smp_processor_id() && (pic_mode
|| !value
)) {
1117 value
= APIC_DM_EXTINT
;
1118 apic_printk(APIC_VERBOSE
, "enabled ExtINT on CPU#%d\n",
1119 smp_processor_id());
1121 value
= APIC_DM_EXTINT
| APIC_LVT_MASKED
;
1122 apic_printk(APIC_VERBOSE
, "masked ExtINT on CPU#%d\n",
1123 smp_processor_id());
1125 apic_write(APIC_LVT0
, value
);
1128 * only the BP should see the LINT1 NMI signal, obviously.
1130 if (!smp_processor_id())
1131 value
= APIC_DM_NMI
;
1133 value
= APIC_DM_NMI
| APIC_LVT_MASKED
;
1134 if (!integrated
) /* 82489DX */
1135 value
|= APIC_LVT_LEVEL_TRIGGER
;
1136 apic_write(APIC_LVT1
, value
);
1139 void __cpuinit
end_local_APIC_setup(void)
1141 unsigned long value
;
1144 /* Disable the local apic timer */
1145 value
= apic_read(APIC_LVTT
);
1146 value
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
1147 apic_write(APIC_LVTT
, value
);
1149 setup_apic_nmi_watchdog(NULL
);
1154 * Detect and initialize APIC
1156 static int __init
detect_init_APIC(void)
1160 /* Disabled by kernel option? */
1164 switch (boot_cpu_data
.x86_vendor
) {
1165 case X86_VENDOR_AMD
:
1166 if ((boot_cpu_data
.x86
== 6 && boot_cpu_data
.x86_model
> 1) ||
1167 (boot_cpu_data
.x86
== 15))
1170 case X86_VENDOR_INTEL
:
1171 if (boot_cpu_data
.x86
== 6 || boot_cpu_data
.x86
== 15 ||
1172 (boot_cpu_data
.x86
== 5 && cpu_has_apic
))
1179 if (!cpu_has_apic
) {
1181 * Over-ride BIOS and try to enable the local APIC only if
1182 * "lapic" specified.
1184 if (!force_enable_local_apic
) {
1185 printk(KERN_INFO
"Local APIC disabled by BIOS -- "
1186 "you can enable it with \"lapic\"\n");
1190 * Some BIOSes disable the local APIC in the APIC_BASE
1191 * MSR. This can only be done in software for Intel P6 or later
1192 * and AMD K7 (Model > 1) or later.
1194 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1195 if (!(l
& MSR_IA32_APICBASE_ENABLE
)) {
1197 "Local APIC disabled by BIOS -- reenabling.\n");
1198 l
&= ~MSR_IA32_APICBASE_BASE
;
1199 l
|= MSR_IA32_APICBASE_ENABLE
| APIC_DEFAULT_PHYS_BASE
;
1200 wrmsr(MSR_IA32_APICBASE
, l
, h
);
1201 enabled_via_apicbase
= 1;
1205 * The APIC feature bit should now be enabled
1208 features
= cpuid_edx(1);
1209 if (!(features
& (1 << X86_FEATURE_APIC
))) {
1210 printk(KERN_WARNING
"Could not enable APIC!\n");
1213 set_cpu_cap(&boot_cpu_data
, X86_FEATURE_APIC
);
1214 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
1216 /* The BIOS may have set up the APIC at some other address */
1217 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1218 if (l
& MSR_IA32_APICBASE_ENABLE
)
1219 mp_lapic_addr
= l
& MSR_IA32_APICBASE_BASE
;
1221 printk(KERN_INFO
"Found and enabled local APIC!\n");
1228 printk(KERN_INFO
"No local APIC present or hardware disabled\n");
1233 * init_apic_mappings - initialize APIC mappings
1235 void __init
init_apic_mappings(void)
1238 * If no local APIC can be found then set up a fake all
1239 * zeroes page to simulate the local APIC and another
1240 * one for the IO-APIC.
1242 if (!smp_found_config
&& detect_init_APIC()) {
1243 apic_phys
= (unsigned long) alloc_bootmem_pages(PAGE_SIZE
);
1244 apic_phys
= __pa(apic_phys
);
1246 apic_phys
= mp_lapic_addr
;
1248 set_fixmap_nocache(FIX_APIC_BASE
, apic_phys
);
1249 printk(KERN_DEBUG
"mapped APIC to %08lx (%08lx)\n", APIC_BASE
,
1253 * Fetch the APIC ID of the BSP in case we have a
1254 * default configuration (or the MP table is broken).
1256 if (boot_cpu_physical_apicid
== -1U)
1257 boot_cpu_physical_apicid
= read_apic_id();
1262 * This initializes the IO-APIC and APIC hardware if this is
1266 int apic_version
[MAX_APICS
];
1268 int __init
APIC_init_uniprocessor(void)
1270 if (!smp_found_config
&& !cpu_has_apic
)
1274 * Complain if the BIOS pretends there is one.
1276 if (!cpu_has_apic
&&
1277 APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
])) {
1278 printk(KERN_ERR
"BIOS bug, local APIC #%d not detected!...\n",
1279 boot_cpu_physical_apicid
);
1280 clear_cpu_cap(&boot_cpu_data
, X86_FEATURE_APIC
);
1284 verify_local_APIC();
1289 * Hack: In case of kdump, after a crash, kernel might be booting
1290 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
1291 * might be zero if read from MP tables. Get it from LAPIC.
1293 #ifdef CONFIG_CRASH_DUMP
1294 boot_cpu_physical_apicid
= read_apic_id();
1296 physid_set_mask_of_physid(boot_cpu_physical_apicid
, &phys_cpu_present_map
);
1300 #ifdef CONFIG_X86_IO_APIC
1301 if (!smp_found_config
|| skip_ioapic_setup
|| !nr_ioapics
)
1303 localise_nmi_watchdog();
1304 end_local_APIC_setup();
1305 #ifdef CONFIG_X86_IO_APIC
1306 if (smp_found_config
)
1307 if (!skip_ioapic_setup
&& nr_ioapics
)
1316 * Local APIC interrupts
1320 * This interrupt should _never_ happen with our APIC/SMP architecture
1322 void smp_spurious_interrupt(struct pt_regs
*regs
)
1328 * Check if this really is a spurious interrupt and ACK it
1329 * if it is a vectored one. Just in case...
1330 * Spurious interrupts should not be ACKed.
1332 v
= apic_read(APIC_ISR
+ ((SPURIOUS_APIC_VECTOR
& ~0x1f) >> 1));
1333 if (v
& (1 << (SPURIOUS_APIC_VECTOR
& 0x1f)))
1336 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1337 printk(KERN_INFO
"spurious APIC interrupt on CPU#%d, "
1338 "should never happen.\n", smp_processor_id());
1339 __get_cpu_var(irq_stat
).irq_spurious_count
++;
1344 * This interrupt should never happen with our APIC/SMP architecture
1346 void smp_error_interrupt(struct pt_regs
*regs
)
1348 unsigned long v
, v1
;
1351 /* First tickle the hardware, only then report what went on. -- REW */
1352 v
= apic_read(APIC_ESR
);
1353 apic_write(APIC_ESR
, 0);
1354 v1
= apic_read(APIC_ESR
);
1356 atomic_inc(&irq_err_count
);
1358 /* Here is what the APIC error bits mean:
1361 2: Send accept error
1362 3: Receive accept error
1364 5: Send illegal vector
1365 6: Received illegal vector
1366 7: Illegal register address
1368 printk(KERN_DEBUG
"APIC error on CPU%d: %02lx(%02lx)\n",
1369 smp_processor_id(), v
, v1
);
1374 * connect_bsp_APIC - attach the APIC to the interrupt system
1376 void __init
connect_bsp_APIC(void)
1380 * Do not trust the local APIC being empty at bootup.
1384 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
1385 * local APIC to INT and NMI lines.
1387 apic_printk(APIC_VERBOSE
, "leaving PIC mode, "
1388 "enabling APIC mode.\n");
1396 * disconnect_bsp_APIC - detach the APIC from the interrupt system
1397 * @virt_wire_setup: indicates, whether virtual wire mode is selected
1399 * Virtual wire mode is necessary to deliver legacy interrupts even when the
1402 void disconnect_bsp_APIC(int virt_wire_setup
)
1406 * Put the board back into PIC mode (has an effect only on
1407 * certain older boards). Note that APIC interrupts, including
1408 * IPIs, won't work beyond this point! The only exception are
1411 apic_printk(APIC_VERBOSE
, "disabling APIC mode, "
1412 "entering PIC mode.\n");
1416 /* Go back to Virtual Wire compatibility mode */
1417 unsigned long value
;
1419 /* For the spurious interrupt use vector F, and enable it */
1420 value
= apic_read(APIC_SPIV
);
1421 value
&= ~APIC_VECTOR_MASK
;
1422 value
|= APIC_SPIV_APIC_ENABLED
;
1424 apic_write(APIC_SPIV
, value
);
1426 if (!virt_wire_setup
) {
1428 * For LVT0 make it edge triggered, active high,
1429 * external and enabled
1431 value
= apic_read(APIC_LVT0
);
1432 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1433 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1434 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1435 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1436 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_EXTINT
);
1437 apic_write(APIC_LVT0
, value
);
1440 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
1444 * For LVT1 make it edge triggered, active high, nmi and
1447 value
= apic_read(APIC_LVT1
);
1449 APIC_MODE_MASK
| APIC_SEND_PENDING
|
1450 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1451 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1452 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1453 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_NMI
);
1454 apic_write(APIC_LVT1
, value
);
1458 unsigned int __cpuinitdata maxcpus
= NR_CPUS
;
1460 void __cpuinit
generic_processor_info(int apicid
, int version
)
1464 physid_mask_t phys_cpu
;
1469 if (version
== 0x0) {
1470 printk(KERN_WARNING
"BIOS bug, APIC version is 0 for CPU#%d! "
1471 "fixing up to 0x10. (tell your hw vendor)\n",
1475 apic_version
[apicid
] = version
;
1477 phys_cpu
= apicid_to_cpu_present(apicid
);
1478 physids_or(phys_cpu_present_map
, phys_cpu_present_map
, phys_cpu
);
1480 if (num_processors
>= NR_CPUS
) {
1481 printk(KERN_WARNING
"WARNING: NR_CPUS limit of %i reached."
1482 " Processor ignored.\n", NR_CPUS
);
1486 if (num_processors
>= maxcpus
) {
1487 printk(KERN_WARNING
"WARNING: maxcpus limit of %i reached."
1488 " Processor ignored.\n", maxcpus
);
1493 cpus_complement(tmp_map
, cpu_present_map
);
1494 cpu
= first_cpu(tmp_map
);
1496 if (apicid
== boot_cpu_physical_apicid
)
1498 * x86_bios_cpu_apicid is required to have processors listed
1499 * in same order as logical cpu numbers. Hence the first
1500 * entry is BSP, and so on.
1504 if (apicid
> max_physical_apicid
)
1505 max_physical_apicid
= apicid
;
1508 * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y
1509 * but we need to work other dependencies like SMP_SUSPEND etc
1510 * before this can be done without some confusion.
1511 * if (CPU_HOTPLUG_ENABLED || num_processors > 8)
1512 * - Ashok Raj <ashok.raj@intel.com>
1514 if (max_physical_apicid
>= 8) {
1515 switch (boot_cpu_data
.x86_vendor
) {
1516 case X86_VENDOR_INTEL
:
1517 if (!APIC_XAPIC(version
)) {
1521 /* If P4 and above fall through */
1522 case X86_VENDOR_AMD
:
1527 /* are we being called early in kernel startup? */
1528 if (early_per_cpu_ptr(x86_cpu_to_apicid
)) {
1529 u16
*cpu_to_apicid
= early_per_cpu_ptr(x86_cpu_to_apicid
);
1530 u16
*bios_cpu_apicid
= early_per_cpu_ptr(x86_bios_cpu_apicid
);
1532 cpu_to_apicid
[cpu
] = apicid
;
1533 bios_cpu_apicid
[cpu
] = apicid
;
1535 per_cpu(x86_cpu_to_apicid
, cpu
) = apicid
;
1536 per_cpu(x86_bios_cpu_apicid
, cpu
) = apicid
;
1539 cpu_set(cpu
, cpu_possible_map
);
1540 cpu_set(cpu
, cpu_present_map
);
1550 * 'active' is true if the local APIC was enabled by us and
1551 * not the BIOS; this signifies that we are also responsible
1552 * for disabling it before entering apm/acpi suspend
1555 /* r/w apic fields */
1556 unsigned int apic_id
;
1557 unsigned int apic_taskpri
;
1558 unsigned int apic_ldr
;
1559 unsigned int apic_dfr
;
1560 unsigned int apic_spiv
;
1561 unsigned int apic_lvtt
;
1562 unsigned int apic_lvtpc
;
1563 unsigned int apic_lvt0
;
1564 unsigned int apic_lvt1
;
1565 unsigned int apic_lvterr
;
1566 unsigned int apic_tmict
;
1567 unsigned int apic_tdcr
;
1568 unsigned int apic_thmr
;
1571 static int lapic_suspend(struct sys_device
*dev
, pm_message_t state
)
1573 unsigned long flags
;
1576 if (!apic_pm_state
.active
)
1579 maxlvt
= lapic_get_maxlvt();
1581 apic_pm_state
.apic_id
= apic_read(APIC_ID
);
1582 apic_pm_state
.apic_taskpri
= apic_read(APIC_TASKPRI
);
1583 apic_pm_state
.apic_ldr
= apic_read(APIC_LDR
);
1584 apic_pm_state
.apic_dfr
= apic_read(APIC_DFR
);
1585 apic_pm_state
.apic_spiv
= apic_read(APIC_SPIV
);
1586 apic_pm_state
.apic_lvtt
= apic_read(APIC_LVTT
);
1588 apic_pm_state
.apic_lvtpc
= apic_read(APIC_LVTPC
);
1589 apic_pm_state
.apic_lvt0
= apic_read(APIC_LVT0
);
1590 apic_pm_state
.apic_lvt1
= apic_read(APIC_LVT1
);
1591 apic_pm_state
.apic_lvterr
= apic_read(APIC_LVTERR
);
1592 apic_pm_state
.apic_tmict
= apic_read(APIC_TMICT
);
1593 apic_pm_state
.apic_tdcr
= apic_read(APIC_TDCR
);
1594 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
1596 apic_pm_state
.apic_thmr
= apic_read(APIC_LVTTHMR
);
1599 local_irq_save(flags
);
1600 disable_local_APIC();
1601 local_irq_restore(flags
);
1605 static int lapic_resume(struct sys_device
*dev
)
1608 unsigned long flags
;
1611 if (!apic_pm_state
.active
)
1614 maxlvt
= lapic_get_maxlvt();
1616 local_irq_save(flags
);
1618 #ifdef CONFIG_X86_64
1624 * Make sure the APICBASE points to the right address
1626 * FIXME! This will be wrong if we ever support suspend on
1627 * SMP! We'll need to do this as part of the CPU restore!
1629 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1630 l
&= ~MSR_IA32_APICBASE_BASE
;
1631 l
|= MSR_IA32_APICBASE_ENABLE
| mp_lapic_addr
;
1632 wrmsr(MSR_IA32_APICBASE
, l
, h
);
1634 apic_write(APIC_LVTERR
, ERROR_APIC_VECTOR
| APIC_LVT_MASKED
);
1635 apic_write(APIC_ID
, apic_pm_state
.apic_id
);
1636 apic_write(APIC_DFR
, apic_pm_state
.apic_dfr
);
1637 apic_write(APIC_LDR
, apic_pm_state
.apic_ldr
);
1638 apic_write(APIC_TASKPRI
, apic_pm_state
.apic_taskpri
);
1639 apic_write(APIC_SPIV
, apic_pm_state
.apic_spiv
);
1640 apic_write(APIC_LVT0
, apic_pm_state
.apic_lvt0
);
1641 apic_write(APIC_LVT1
, apic_pm_state
.apic_lvt1
);
1642 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
1644 apic_write(APIC_LVTTHMR
, apic_pm_state
.apic_thmr
);
1647 apic_write(APIC_LVTPC
, apic_pm_state
.apic_lvtpc
);
1648 apic_write(APIC_LVTT
, apic_pm_state
.apic_lvtt
);
1649 apic_write(APIC_TDCR
, apic_pm_state
.apic_tdcr
);
1650 apic_write(APIC_TMICT
, apic_pm_state
.apic_tmict
);
1651 apic_write(APIC_ESR
, 0);
1652 apic_read(APIC_ESR
);
1653 apic_write(APIC_LVTERR
, apic_pm_state
.apic_lvterr
);
1654 apic_write(APIC_ESR
, 0);
1655 apic_read(APIC_ESR
);
1657 local_irq_restore(flags
);
1663 * This device has no shutdown method - fully functioning local APICs
1664 * are needed on every CPU up until machine_halt/restart/poweroff.
1667 static struct sysdev_class lapic_sysclass
= {
1669 .resume
= lapic_resume
,
1670 .suspend
= lapic_suspend
,
1673 static struct sys_device device_lapic
= {
1675 .cls
= &lapic_sysclass
,
1678 static void __devinit
apic_pm_activate(void)
1680 apic_pm_state
.active
= 1;
1683 static int __init
init_lapic_sysfs(void)
1689 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
1691 error
= sysdev_class_register(&lapic_sysclass
);
1693 error
= sysdev_register(&device_lapic
);
1696 device_initcall(init_lapic_sysfs
);
1698 #else /* CONFIG_PM */
1700 static void apic_pm_activate(void) { }
1702 #endif /* CONFIG_PM */
1705 * APIC command line parameters
1707 static int __init
parse_lapic(char *arg
)
1709 force_enable_local_apic
= 1;
1712 early_param("lapic", parse_lapic
);
1714 static int __init
parse_nolapic(char *arg
)
1717 setup_clear_cpu_cap(X86_FEATURE_APIC
);
1720 early_param("nolapic", parse_nolapic
);
1722 static int __init
parse_disable_apic_timer(char *arg
)
1724 disable_apic_timer
= 1;
1727 early_param("noapictimer", parse_disable_apic_timer
);
1729 static int __init
parse_nolapic_timer(char *arg
)
1731 disable_apic_timer
= 1;
1734 early_param("nolapic_timer", parse_nolapic_timer
);
1736 static int __init
parse_lapic_timer_c2_ok(char *arg
)
1738 local_apic_timer_c2_ok
= 1;
1741 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok
);
1743 static int __init
apic_set_verbosity(char *arg
)
1748 if (strcmp(arg
, "debug") == 0)
1749 apic_verbosity
= APIC_DEBUG
;
1750 else if (strcmp(arg
, "verbose") == 0)
1751 apic_verbosity
= APIC_VERBOSE
;
1755 early_param("apic", apic_set_verbosity
);
1757 static int __init
lapic_insert_resource(void)
1762 /* Put local APIC into the resource map. */
1763 lapic_resource
.start
= apic_phys
;
1764 lapic_resource
.end
= lapic_resource
.start
+ PAGE_SIZE
- 1;
1765 insert_resource(&iomem_resource
, &lapic_resource
);
1771 * need call insert after e820_reserve_resources()
1772 * that is using request_resource
1774 late_initcall(lapic_insert_resource
);