2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/bootmem.h>
22 #include <linux/interrupt.h>
23 #include <linux/mc146818rtc.h>
24 #include <linux/kernel_stat.h>
25 #include <linux/sysdev.h>
26 #include <linux/cpu.h>
27 #include <linux/clockchips.h>
28 #include <linux/acpi_pmtmr.h>
29 #include <linux/module.h>
30 #include <linux/dmi.h>
32 #include <asm/atomic.h>
35 #include <asm/mpspec.h>
37 #include <asm/arch_hooks.h>
39 #include <asm/i8253.h>
42 #include <mach_apic.h>
43 #include <mach_apicdef.h>
49 #if ((SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F)
50 # error SPURIOUS_APIC_VECTOR definition error
53 unsigned long mp_lapic_addr
;
56 * Knob to control our willingness to enable the local APIC.
60 static int force_enable_local_apic
;
63 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
64 static int disable_apic_timer __cpuinitdata
;
65 /* Local APIC timer works in C2 */
66 int local_apic_timer_c2_ok
;
67 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok
);
69 int first_system_vector
= 0xfe;
71 char system_vectors
[NR_VECTORS
] = { [0 ... NR_VECTORS
-1] = SYS_VECTOR_FREE
};
74 * Debug level, exported for io_apic.c
76 unsigned int apic_verbosity
;
80 /* Have we found an MP table */
83 static struct resource lapic_resource
= {
85 .flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
,
88 static unsigned int calibration_result
;
90 static int lapic_next_event(unsigned long delta
,
91 struct clock_event_device
*evt
);
92 static void lapic_timer_setup(enum clock_event_mode mode
,
93 struct clock_event_device
*evt
);
94 static void lapic_timer_broadcast(cpumask_t mask
);
95 static void apic_pm_activate(void);
98 * The local apic timer can be used for any function which is CPU local.
100 static struct clock_event_device lapic_clockevent
= {
102 .features
= CLOCK_EVT_FEAT_PERIODIC
| CLOCK_EVT_FEAT_ONESHOT
103 | CLOCK_EVT_FEAT_C3STOP
| CLOCK_EVT_FEAT_DUMMY
,
105 .set_mode
= lapic_timer_setup
,
106 .set_next_event
= lapic_next_event
,
107 .broadcast
= lapic_timer_broadcast
,
111 static DEFINE_PER_CPU(struct clock_event_device
, lapic_events
);
113 /* Local APIC was disabled by the BIOS and enabled by the kernel */
114 static int enabled_via_apicbase
;
116 static unsigned long apic_phys
;
119 * Get the LAPIC version
121 static inline int lapic_get_version(void)
123 return GET_APIC_VERSION(apic_read(APIC_LVR
));
127 * Check, if the APIC is integrated or a separate chip
129 static inline int lapic_is_integrated(void)
134 return APIC_INTEGRATED(lapic_get_version());
139 * Check, whether this is a modern or a first generation APIC
141 static int modern_apic(void)
143 /* AMD systems use old APIC versions, so check the CPU */
144 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
&&
145 boot_cpu_data
.x86
>= 0xf)
147 return lapic_get_version() >= 0x14;
151 * Paravirt kernels also might be using these below ops. So we still
152 * use generic apic_read()/apic_write(), which might be pointing to different
153 * ops in PARAVIRT case.
155 void xapic_wait_icr_idle(void)
157 while (apic_read(APIC_ICR
) & APIC_ICR_BUSY
)
161 u32
safe_xapic_wait_icr_idle(void)
168 send_status
= apic_read(APIC_ICR
) & APIC_ICR_BUSY
;
172 } while (timeout
++ < 1000);
177 void xapic_icr_write(u32 low
, u32 id
)
179 apic_write(APIC_ICR2
, SET_APIC_DEST_FIELD(id
));
180 apic_write(APIC_ICR
, low
);
183 u64
xapic_icr_read(void)
187 icr2
= apic_read(APIC_ICR2
);
188 icr1
= apic_read(APIC_ICR
);
190 return icr1
| ((u64
)icr2
<< 32);
193 static struct apic_ops xapic_ops
= {
194 .read
= native_apic_mem_read
,
195 .write
= native_apic_mem_write
,
196 .icr_read
= xapic_icr_read
,
197 .icr_write
= xapic_icr_write
,
198 .wait_icr_idle
= xapic_wait_icr_idle
,
199 .safe_wait_icr_idle
= safe_xapic_wait_icr_idle
,
202 struct apic_ops __read_mostly
*apic_ops
= &xapic_ops
;
203 EXPORT_SYMBOL_GPL(apic_ops
);
206 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
208 void __cpuinit
enable_NMI_through_LVT0(void)
212 /* unmask and set to NMI */
215 /* Level triggered for 82489DX (32bit mode) */
216 if (!lapic_is_integrated())
217 v
|= APIC_LVT_LEVEL_TRIGGER
;
219 apic_write(APIC_LVT0
, v
);
223 * get_physical_broadcast - Get number of physical broadcast IDs
225 int get_physical_broadcast(void)
227 return modern_apic() ? 0xff : 0xf;
231 * lapic_get_maxlvt - get the maximum number of local vector table entries
233 int lapic_get_maxlvt(void)
237 v
= apic_read(APIC_LVR
);
239 * - we always have APIC integrated on 64bit mode
240 * - 82489DXs do not report # of LVT entries
242 return APIC_INTEGRATED(GET_APIC_VERSION(v
)) ? GET_APIC_MAXLVT(v
) : 2;
251 #define APIC_DIVISOR 1
253 #define APIC_DIVISOR 16
257 * This function sets up the local APIC timer, with a timeout of
258 * 'clocks' APIC bus clock. During calibration we actually call
259 * this function twice on the boot CPU, once with a bogus timeout
260 * value, second time for real. The other (noncalibrating) CPUs
261 * call this function only once, with the real, calibrated value.
263 * We do reads before writes even if unnecessary, to get around the
264 * P5 APIC double write bug.
266 static void __setup_APIC_LVTT(unsigned int clocks
, int oneshot
, int irqen
)
268 unsigned int lvtt_value
, tmp_value
;
270 lvtt_value
= LOCAL_TIMER_VECTOR
;
272 lvtt_value
|= APIC_LVT_TIMER_PERIODIC
;
273 if (!lapic_is_integrated())
274 lvtt_value
|= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV
);
277 lvtt_value
|= APIC_LVT_MASKED
;
279 apic_write(APIC_LVTT
, lvtt_value
);
284 tmp_value
= apic_read(APIC_TDCR
);
285 apic_write(APIC_TDCR
,
286 (tmp_value
& ~(APIC_TDR_DIV_1
| APIC_TDR_DIV_TMBASE
)) |
290 apic_write(APIC_TMICT
, clocks
/ APIC_DIVISOR
);
294 * Setup extended LVT, AMD specific (K8, family 10h)
296 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
297 * MCE interrupts are supported. Thus MCE offset must be set to 0.
300 #define APIC_EILVT_LVTOFF_MCE 0
301 #define APIC_EILVT_LVTOFF_IBS 1
303 static void setup_APIC_eilvt(u8 lvt_off
, u8 vector
, u8 msg_type
, u8 mask
)
305 unsigned long reg
= (lvt_off
<< 4) + APIC_EILVT0
;
306 unsigned int v
= (mask
<< 16) | (msg_type
<< 8) | vector
;
311 u8
setup_APIC_eilvt_mce(u8 vector
, u8 msg_type
, u8 mask
)
313 setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE
, vector
, msg_type
, mask
);
314 return APIC_EILVT_LVTOFF_MCE
;
317 u8
setup_APIC_eilvt_ibs(u8 vector
, u8 msg_type
, u8 mask
)
319 setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS
, vector
, msg_type
, mask
);
320 return APIC_EILVT_LVTOFF_IBS
;
324 * Program the next event, relative to now
326 static int lapic_next_event(unsigned long delta
,
327 struct clock_event_device
*evt
)
329 apic_write(APIC_TMICT
, delta
);
334 * Setup the lapic timer in periodic or oneshot mode
336 static void lapic_timer_setup(enum clock_event_mode mode
,
337 struct clock_event_device
*evt
)
342 /* Lapic used as dummy for broadcast ? */
343 if (evt
->features
& CLOCK_EVT_FEAT_DUMMY
)
346 local_irq_save(flags
);
349 case CLOCK_EVT_MODE_PERIODIC
:
350 case CLOCK_EVT_MODE_ONESHOT
:
351 __setup_APIC_LVTT(calibration_result
,
352 mode
!= CLOCK_EVT_MODE_PERIODIC
, 1);
354 case CLOCK_EVT_MODE_UNUSED
:
355 case CLOCK_EVT_MODE_SHUTDOWN
:
356 v
= apic_read(APIC_LVTT
);
357 v
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
358 apic_write(APIC_LVTT
, v
);
360 case CLOCK_EVT_MODE_RESUME
:
361 /* Nothing to do here */
365 local_irq_restore(flags
);
369 * Local APIC timer broadcast function
371 static void lapic_timer_broadcast(cpumask_t mask
)
374 send_IPI_mask(mask
, LOCAL_TIMER_VECTOR
);
379 * Setup the local APIC timer for this CPU. Copy the initilized values
380 * of the boot CPU and register the clock event in the framework.
382 static void __devinit
setup_APIC_timer(void)
384 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
386 memcpy(levt
, &lapic_clockevent
, sizeof(*levt
));
387 levt
->cpumask
= cpumask_of_cpu(smp_processor_id());
389 clockevents_register_device(levt
);
393 * In this functions we calibrate APIC bus clocks to the external timer.
395 * We want to do the calibration only once since we want to have local timer
396 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
399 * This was previously done by reading the PIT/HPET and waiting for a wrap
400 * around to find out, that a tick has elapsed. I have a box, where the PIT
401 * readout is broken, so it never gets out of the wait loop again. This was
402 * also reported by others.
404 * Monitoring the jiffies value is inaccurate and the clockevents
405 * infrastructure allows us to do a simple substitution of the interrupt
408 * The calibration routine also uses the pm_timer when possible, as the PIT
409 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
410 * back to normal later in the boot process).
413 #define LAPIC_CAL_LOOPS (HZ/10)
415 static __initdata
int lapic_cal_loops
= -1;
416 static __initdata
long lapic_cal_t1
, lapic_cal_t2
;
417 static __initdata
unsigned long long lapic_cal_tsc1
, lapic_cal_tsc2
;
418 static __initdata
unsigned long lapic_cal_pm1
, lapic_cal_pm2
;
419 static __initdata
unsigned long lapic_cal_j1
, lapic_cal_j2
;
422 * Temporary interrupt handler.
424 static void __init
lapic_cal_handler(struct clock_event_device
*dev
)
426 unsigned long long tsc
= 0;
427 long tapic
= apic_read(APIC_TMCCT
);
428 unsigned long pm
= acpi_pm_read_early();
433 switch (lapic_cal_loops
++) {
435 lapic_cal_t1
= tapic
;
436 lapic_cal_tsc1
= tsc
;
438 lapic_cal_j1
= jiffies
;
441 case LAPIC_CAL_LOOPS
:
442 lapic_cal_t2
= tapic
;
443 lapic_cal_tsc2
= tsc
;
444 if (pm
< lapic_cal_pm1
)
445 pm
+= ACPI_PM_OVRRUN
;
447 lapic_cal_j2
= jiffies
;
452 static int __init
calibrate_APIC_clock(void)
454 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
455 const long pm_100ms
= PMTMR_TICKS_PER_SEC
/10;
456 const long pm_thresh
= pm_100ms
/100;
457 void (*real_handler
)(struct clock_event_device
*dev
);
458 unsigned long deltaj
;
460 int pm_referenced
= 0;
464 /* Replace the global interrupt handler */
465 real_handler
= global_clock_event
->event_handler
;
466 global_clock_event
->event_handler
= lapic_cal_handler
;
469 * Setup the APIC counter to 1e9. There is no way the lapic
470 * can underflow in the 100ms detection time frame
472 __setup_APIC_LVTT(1000000000, 0, 0);
474 /* Let the interrupts run */
477 while (lapic_cal_loops
<= LAPIC_CAL_LOOPS
)
482 /* Restore the real event handler */
483 global_clock_event
->event_handler
= real_handler
;
485 /* Build delta t1-t2 as apic timer counts down */
486 delta
= lapic_cal_t1
- lapic_cal_t2
;
487 apic_printk(APIC_VERBOSE
, "... lapic delta = %ld\n", delta
);
489 /* Check, if the PM timer is available */
490 deltapm
= lapic_cal_pm2
- lapic_cal_pm1
;
491 apic_printk(APIC_VERBOSE
, "... PM timer delta = %ld\n", deltapm
);
497 mult
= clocksource_hz2mult(PMTMR_TICKS_PER_SEC
, 22);
499 if (deltapm
> (pm_100ms
- pm_thresh
) &&
500 deltapm
< (pm_100ms
+ pm_thresh
)) {
501 apic_printk(APIC_VERBOSE
, "... PM timer result ok\n");
503 res
= (((u64
) deltapm
) * mult
) >> 22;
504 do_div(res
, 1000000);
505 printk(KERN_WARNING
"APIC calibration not consistent "
506 "with PM Timer: %ldms instead of 100ms\n",
508 /* Correct the lapic counter value */
509 res
= (((u64
) delta
) * pm_100ms
);
510 do_div(res
, deltapm
);
511 printk(KERN_INFO
"APIC delta adjusted to PM-Timer: "
512 "%lu (%ld)\n", (unsigned long) res
, delta
);
518 /* Calculate the scaled math multiplication factor */
519 lapic_clockevent
.mult
= div_sc(delta
, TICK_NSEC
* LAPIC_CAL_LOOPS
,
520 lapic_clockevent
.shift
);
521 lapic_clockevent
.max_delta_ns
=
522 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent
);
523 lapic_clockevent
.min_delta_ns
=
524 clockevent_delta2ns(0xF, &lapic_clockevent
);
526 calibration_result
= (delta
* APIC_DIVISOR
) / LAPIC_CAL_LOOPS
;
528 apic_printk(APIC_VERBOSE
, "..... delta %ld\n", delta
);
529 apic_printk(APIC_VERBOSE
, "..... mult: %ld\n", lapic_clockevent
.mult
);
530 apic_printk(APIC_VERBOSE
, "..... calibration result: %u\n",
534 delta
= (long)(lapic_cal_tsc2
- lapic_cal_tsc1
);
535 apic_printk(APIC_VERBOSE
, "..... CPU clock speed is "
537 (delta
/ LAPIC_CAL_LOOPS
) / (1000000 / HZ
),
538 (delta
/ LAPIC_CAL_LOOPS
) % (1000000 / HZ
));
541 apic_printk(APIC_VERBOSE
, "..... host bus clock speed is "
543 calibration_result
/ (1000000 / HZ
),
544 calibration_result
% (1000000 / HZ
));
547 * Do a sanity check on the APIC calibration result
549 if (calibration_result
< (1000000 / HZ
)) {
552 "APIC frequency too slow, disabling apic timer\n");
556 levt
->features
&= ~CLOCK_EVT_FEAT_DUMMY
;
558 /* We trust the pm timer based calibration */
559 if (!pm_referenced
) {
560 apic_printk(APIC_VERBOSE
, "... verify APIC timer\n");
563 * Setup the apic timer manually
565 levt
->event_handler
= lapic_cal_handler
;
566 lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC
, levt
);
567 lapic_cal_loops
= -1;
569 /* Let the interrupts run */
572 while (lapic_cal_loops
<= LAPIC_CAL_LOOPS
)
577 /* Stop the lapic timer */
578 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, levt
);
583 deltaj
= lapic_cal_j2
- lapic_cal_j1
;
584 apic_printk(APIC_VERBOSE
, "... jiffies delta = %lu\n", deltaj
);
586 /* Check, if the jiffies result is consistent */
587 if (deltaj
>= LAPIC_CAL_LOOPS
-2 && deltaj
<= LAPIC_CAL_LOOPS
+2)
588 apic_printk(APIC_VERBOSE
, "... jiffies result ok\n");
590 levt
->features
|= CLOCK_EVT_FEAT_DUMMY
;
594 if (levt
->features
& CLOCK_EVT_FEAT_DUMMY
) {
596 "APIC timer disabled due to verification failure.\n");
604 * Setup the boot APIC
606 * Calibrate and verify the result.
608 void __init
setup_boot_APIC_clock(void)
611 * The local apic timer can be disabled via the kernel
612 * commandline or from the CPU detection code. Register the lapic
613 * timer as a dummy clock event source on SMP systems, so the
614 * broadcast mechanism is used. On UP systems simply ignore it.
616 if (disable_apic_timer
) {
617 printk(KERN_INFO
"Disabling APIC timer\n");
618 /* No broadcast on UP ! */
619 if (num_possible_cpus() > 1) {
620 lapic_clockevent
.mult
= 1;
626 apic_printk(APIC_VERBOSE
, "Using local APIC timer interrupts.\n"
627 "calibrating APIC timer ...\n");
629 if (calibrate_APIC_clock()) {
630 /* No broadcast on UP ! */
631 if (num_possible_cpus() > 1)
637 * If nmi_watchdog is set to IO_APIC, we need the
638 * PIT/HPET going. Otherwise register lapic as a dummy
641 if (nmi_watchdog
!= NMI_IO_APIC
)
642 lapic_clockevent
.features
&= ~CLOCK_EVT_FEAT_DUMMY
;
644 printk(KERN_WARNING
"APIC timer registered as dummy,"
645 " due to nmi_watchdog=%d!\n", nmi_watchdog
);
647 /* Setup the lapic or request the broadcast */
651 void __devinit
setup_secondary_APIC_clock(void)
657 * The guts of the apic timer interrupt
659 static void local_apic_timer_interrupt(void)
661 int cpu
= smp_processor_id();
662 struct clock_event_device
*evt
= &per_cpu(lapic_events
, cpu
);
665 * Normally we should not be here till LAPIC has been initialized but
666 * in some cases like kdump, its possible that there is a pending LAPIC
667 * timer interrupt from previous kernel's context and is delivered in
668 * new kernel the moment interrupts are enabled.
670 * Interrupts are enabled early and LAPIC is setup much later, hence
671 * its possible that when we get here evt->event_handler is NULL.
672 * Check for event_handler being NULL and discard the interrupt as
675 if (!evt
->event_handler
) {
677 "Spurious LAPIC timer interrupt on cpu %d\n", cpu
);
679 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, evt
);
684 * the NMI deadlock-detector uses this.
687 add_pda(apic_timer_irqs
, 1);
689 per_cpu(irq_stat
, cpu
).apic_timer_irqs
++;
692 evt
->event_handler(evt
);
696 * Local APIC timer interrupt. This is the most natural way for doing
697 * local interrupts, but local timer interrupts can be emulated by
698 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
700 * [ if a single-CPU system runs an SMP kernel then we call the local
701 * interrupt as well. Thus we cannot inline the local irq ... ]
703 void smp_apic_timer_interrupt(struct pt_regs
*regs
)
705 struct pt_regs
*old_regs
= set_irq_regs(regs
);
708 * NOTE! We'd better ACK the irq immediately,
709 * because timer handling can be slow.
713 * update_process_times() expects us to have done irq_enter().
714 * Besides, if we don't timer interrupts ignore the global
715 * interrupt lock, which is the WrongThing (tm) to do.
718 local_apic_timer_interrupt();
721 set_irq_regs(old_regs
);
724 int setup_profiling_timer(unsigned int multiplier
)
730 * Local APIC start and shutdown
734 * clear_local_APIC - shutdown the local APIC
736 * This is called, when a CPU is disabled and before rebooting, so the state of
737 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
738 * leftovers during boot.
740 void clear_local_APIC(void)
745 /* APIC hasn't been mapped yet */
749 maxlvt
= lapic_get_maxlvt();
751 * Masking an LVT entry can trigger a local APIC error
752 * if the vector is zero. Mask LVTERR first to prevent this.
755 v
= ERROR_APIC_VECTOR
; /* any non-zero vector will do */
756 apic_write(APIC_LVTERR
, v
| APIC_LVT_MASKED
);
759 * Careful: we have to set masks only first to deassert
760 * any level-triggered sources.
762 v
= apic_read(APIC_LVTT
);
763 apic_write(APIC_LVTT
, v
| APIC_LVT_MASKED
);
764 v
= apic_read(APIC_LVT0
);
765 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
766 v
= apic_read(APIC_LVT1
);
767 apic_write(APIC_LVT1
, v
| APIC_LVT_MASKED
);
769 v
= apic_read(APIC_LVTPC
);
770 apic_write(APIC_LVTPC
, v
| APIC_LVT_MASKED
);
773 /* lets not touch this if we didn't frob it */
774 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(X86_MCE_INTEL)
776 v
= apic_read(APIC_LVTTHMR
);
777 apic_write(APIC_LVTTHMR
, v
| APIC_LVT_MASKED
);
781 * Clean APIC state for other OSs:
783 apic_write(APIC_LVTT
, APIC_LVT_MASKED
);
784 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
785 apic_write(APIC_LVT1
, APIC_LVT_MASKED
);
787 apic_write(APIC_LVTERR
, APIC_LVT_MASKED
);
789 apic_write(APIC_LVTPC
, APIC_LVT_MASKED
);
791 /* Integrated APIC (!82489DX) ? */
792 if (lapic_is_integrated()) {
794 /* Clear ESR due to Pentium errata 3AP and 11AP */
795 apic_write(APIC_ESR
, 0);
801 * disable_local_APIC - clear and disable the local APIC
803 void disable_local_APIC(void)
810 * Disable APIC (implies clearing of registers
813 value
= apic_read(APIC_SPIV
);
814 value
&= ~APIC_SPIV_APIC_ENABLED
;
815 apic_write(APIC_SPIV
, value
);
819 * When LAPIC was disabled by the BIOS and enabled by the kernel,
820 * restore the disabled state.
822 if (enabled_via_apicbase
) {
825 rdmsr(MSR_IA32_APICBASE
, l
, h
);
826 l
&= ~MSR_IA32_APICBASE_ENABLE
;
827 wrmsr(MSR_IA32_APICBASE
, l
, h
);
833 * If Linux enabled the LAPIC against the BIOS default disable it down before
834 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
835 * not power-off. Additionally clear all LVT entries before disable_local_APIC
836 * for the case where Linux didn't enable the LAPIC.
838 void lapic_shutdown(void)
845 local_irq_save(flags
);
848 if (!enabled_via_apicbase
)
852 disable_local_APIC();
855 local_irq_restore(flags
);
859 * This is to verify that we're looking at a real local APIC.
860 * Check these against your board if the CPUs aren't getting
861 * started for no apparent reason.
863 int __init
verify_local_APIC(void)
865 unsigned int reg0
, reg1
;
868 * The version register is read-only in a real APIC.
870 reg0
= apic_read(APIC_LVR
);
871 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg0
);
872 apic_write(APIC_LVR
, reg0
^ APIC_LVR_MASK
);
873 reg1
= apic_read(APIC_LVR
);
874 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg1
);
877 * The two version reads above should print the same
878 * numbers. If the second one is different, then we
879 * poke at a non-APIC.
885 * Check if the version looks reasonably.
887 reg1
= GET_APIC_VERSION(reg0
);
888 if (reg1
== 0x00 || reg1
== 0xff)
890 reg1
= lapic_get_maxlvt();
891 if (reg1
< 0x02 || reg1
== 0xff)
895 * The ID register is read/write in a real APIC.
897 reg0
= apic_read(APIC_ID
);
898 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg0
);
899 apic_write(APIC_ID
, reg0
^ APIC_ID_MASK
);
900 reg1
= apic_read(APIC_ID
);
901 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg1
);
902 apic_write(APIC_ID
, reg0
);
903 if (reg1
!= (reg0
^ APIC_ID_MASK
))
907 * The next two are just to see if we have sane values.
908 * They're only really relevant if we're in Virtual Wire
909 * compatibility mode, but most boxes are anymore.
911 reg0
= apic_read(APIC_LVT0
);
912 apic_printk(APIC_DEBUG
, "Getting LVT0: %x\n", reg0
);
913 reg1
= apic_read(APIC_LVT1
);
914 apic_printk(APIC_DEBUG
, "Getting LVT1: %x\n", reg1
);
920 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
922 void __init
sync_Arb_IDs(void)
925 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
928 if (modern_apic() || boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
)
934 apic_wait_icr_idle();
936 apic_printk(APIC_DEBUG
, "Synchronizing Arb IDs.\n");
937 apic_write(APIC_ICR
, APIC_DEST_ALLINC
|
938 APIC_INT_LEVELTRIG
| APIC_DM_INIT
);
942 * An initial setup of the virtual wire mode.
944 void __init
init_bsp_APIC(void)
949 * Don't do the setup now if we have a SMP BIOS as the
950 * through-I/O-APIC virtual wire mode might be active.
952 if (smp_found_config
|| !cpu_has_apic
)
956 * Do not trust the local APIC being empty at bootup.
963 value
= apic_read(APIC_SPIV
);
964 value
&= ~APIC_VECTOR_MASK
;
965 value
|= APIC_SPIV_APIC_ENABLED
;
968 /* This bit is reserved on P4/Xeon and should be cleared */
969 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
) &&
970 (boot_cpu_data
.x86
== 15))
971 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
974 value
|= APIC_SPIV_FOCUS_DISABLED
;
975 value
|= SPURIOUS_APIC_VECTOR
;
976 apic_write(APIC_SPIV
, value
);
979 * Set up the virtual wire mode.
981 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
983 if (!lapic_is_integrated()) /* 82489DX */
984 value
|= APIC_LVT_LEVEL_TRIGGER
;
985 apic_write(APIC_LVT1
, value
);
988 static void __cpuinit
lapic_setup_esr(void)
990 unsigned long oldvalue
, value
, maxlvt
;
991 if (lapic_is_integrated() && !esr_disable
) {
994 * Something untraceable is creating bad interrupts on
995 * secondary quads ... for the moment, just leave the
996 * ESR disabled - we can't do anything useful with the
997 * errors anyway - mbligh
999 printk(KERN_INFO
"Leaving ESR disabled.\n");
1003 maxlvt
= lapic_get_maxlvt();
1004 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
1005 apic_write(APIC_ESR
, 0);
1006 oldvalue
= apic_read(APIC_ESR
);
1008 /* enables sending errors */
1009 value
= ERROR_APIC_VECTOR
;
1010 apic_write(APIC_LVTERR
, value
);
1012 * spec says clear errors after enabling vector.
1015 apic_write(APIC_ESR
, 0);
1016 value
= apic_read(APIC_ESR
);
1017 if (value
!= oldvalue
)
1018 apic_printk(APIC_VERBOSE
, "ESR value before enabling "
1019 "vector: 0x%08lx after: 0x%08lx\n",
1022 printk(KERN_INFO
"No ESR for 82489DX.\n");
1028 * setup_local_APIC - setup the local APIC
1030 void __cpuinit
setup_local_APIC(void)
1032 unsigned long value
, integrated
;
1035 /* Pound the ESR really hard over the head with a big hammer - mbligh */
1037 apic_write(APIC_ESR
, 0);
1038 apic_write(APIC_ESR
, 0);
1039 apic_write(APIC_ESR
, 0);
1040 apic_write(APIC_ESR
, 0);
1043 integrated
= lapic_is_integrated();
1046 * Double-check whether this APIC is really registered.
1048 if (!apic_id_registered())
1052 * Intel recommends to set DFR, LDR and TPR before enabling
1053 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
1054 * document number 292116). So here it goes...
1059 * Set Task Priority to 'accept all'. We never change this
1062 value
= apic_read(APIC_TASKPRI
);
1063 value
&= ~APIC_TPRI_MASK
;
1064 apic_write(APIC_TASKPRI
, value
);
1067 * After a crash, we no longer service the interrupts and a pending
1068 * interrupt from previous kernel might still have ISR bit set.
1070 * Most probably by now CPU has serviced that pending interrupt and
1071 * it might not have done the ack_APIC_irq() because it thought,
1072 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
1073 * does not clear the ISR bit and cpu thinks it has already serivced
1074 * the interrupt. Hence a vector might get locked. It was noticed
1075 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
1077 for (i
= APIC_ISR_NR
- 1; i
>= 0; i
--) {
1078 value
= apic_read(APIC_ISR
+ i
*0x10);
1079 for (j
= 31; j
>= 0; j
--) {
1086 * Now that we are all set up, enable the APIC
1088 value
= apic_read(APIC_SPIV
);
1089 value
&= ~APIC_VECTOR_MASK
;
1093 value
|= APIC_SPIV_APIC_ENABLED
;
1096 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1097 * certain networking cards. If high frequency interrupts are
1098 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1099 * entry is masked/unmasked at a high rate as well then sooner or
1100 * later IOAPIC line gets 'stuck', no more interrupts are received
1101 * from the device. If focus CPU is disabled then the hang goes
1104 * [ This bug can be reproduced easily with a level-triggered
1105 * PCI Ne2000 networking cards and PII/PIII processors, dual
1109 * Actually disabling the focus CPU check just makes the hang less
1110 * frequent as it makes the interrupt distributon model be more
1111 * like LRU than MRU (the short-term load is more even across CPUs).
1112 * See also the comment in end_level_ioapic_irq(). --macro
1115 /* Enable focus processor (bit==0) */
1116 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
1119 * Set spurious IRQ vector
1121 value
|= SPURIOUS_APIC_VECTOR
;
1122 apic_write(APIC_SPIV
, value
);
1125 * Set up LVT0, LVT1:
1127 * set up through-local-APIC on the BP's LINT0. This is not
1128 * strictly necessary in pure symmetric-IO mode, but sometimes
1129 * we delegate interrupts to the 8259A.
1132 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1134 value
= apic_read(APIC_LVT0
) & APIC_LVT_MASKED
;
1135 if (!smp_processor_id() && (pic_mode
|| !value
)) {
1136 value
= APIC_DM_EXTINT
;
1137 apic_printk(APIC_VERBOSE
, "enabled ExtINT on CPU#%d\n",
1138 smp_processor_id());
1140 value
= APIC_DM_EXTINT
| APIC_LVT_MASKED
;
1141 apic_printk(APIC_VERBOSE
, "masked ExtINT on CPU#%d\n",
1142 smp_processor_id());
1144 apic_write(APIC_LVT0
, value
);
1147 * only the BP should see the LINT1 NMI signal, obviously.
1149 if (!smp_processor_id())
1150 value
= APIC_DM_NMI
;
1152 value
= APIC_DM_NMI
| APIC_LVT_MASKED
;
1153 if (!integrated
) /* 82489DX */
1154 value
|= APIC_LVT_LEVEL_TRIGGER
;
1155 apic_write(APIC_LVT1
, value
);
1158 void __cpuinit
end_local_APIC_setup(void)
1162 #ifdef CONFIG_X86_32
1165 /* Disable the local apic timer */
1166 value
= apic_read(APIC_LVTT
);
1167 value
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
1168 apic_write(APIC_LVTT
, value
);
1172 setup_apic_nmi_watchdog(NULL
);
1177 * Detect and initialize APIC
1179 static int __init
detect_init_APIC(void)
1183 /* Disabled by kernel option? */
1187 switch (boot_cpu_data
.x86_vendor
) {
1188 case X86_VENDOR_AMD
:
1189 if ((boot_cpu_data
.x86
== 6 && boot_cpu_data
.x86_model
> 1) ||
1190 (boot_cpu_data
.x86
== 15))
1193 case X86_VENDOR_INTEL
:
1194 if (boot_cpu_data
.x86
== 6 || boot_cpu_data
.x86
== 15 ||
1195 (boot_cpu_data
.x86
== 5 && cpu_has_apic
))
1202 if (!cpu_has_apic
) {
1204 * Over-ride BIOS and try to enable the local APIC only if
1205 * "lapic" specified.
1207 if (!force_enable_local_apic
) {
1208 printk(KERN_INFO
"Local APIC disabled by BIOS -- "
1209 "you can enable it with \"lapic\"\n");
1213 * Some BIOSes disable the local APIC in the APIC_BASE
1214 * MSR. This can only be done in software for Intel P6 or later
1215 * and AMD K7 (Model > 1) or later.
1217 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1218 if (!(l
& MSR_IA32_APICBASE_ENABLE
)) {
1220 "Local APIC disabled by BIOS -- reenabling.\n");
1221 l
&= ~MSR_IA32_APICBASE_BASE
;
1222 l
|= MSR_IA32_APICBASE_ENABLE
| APIC_DEFAULT_PHYS_BASE
;
1223 wrmsr(MSR_IA32_APICBASE
, l
, h
);
1224 enabled_via_apicbase
= 1;
1228 * The APIC feature bit should now be enabled
1231 features
= cpuid_edx(1);
1232 if (!(features
& (1 << X86_FEATURE_APIC
))) {
1233 printk(KERN_WARNING
"Could not enable APIC!\n");
1236 set_cpu_cap(&boot_cpu_data
, X86_FEATURE_APIC
);
1237 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
1239 /* The BIOS may have set up the APIC at some other address */
1240 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1241 if (l
& MSR_IA32_APICBASE_ENABLE
)
1242 mp_lapic_addr
= l
& MSR_IA32_APICBASE_BASE
;
1244 printk(KERN_INFO
"Found and enabled local APIC!\n");
1251 printk(KERN_INFO
"No local APIC present or hardware disabled\n");
1256 * init_apic_mappings - initialize APIC mappings
1258 void __init
init_apic_mappings(void)
1261 * If no local APIC can be found then set up a fake all
1262 * zeroes page to simulate the local APIC and another
1263 * one for the IO-APIC.
1265 if (!smp_found_config
&& detect_init_APIC()) {
1266 apic_phys
= (unsigned long) alloc_bootmem_pages(PAGE_SIZE
);
1267 apic_phys
= __pa(apic_phys
);
1269 apic_phys
= mp_lapic_addr
;
1271 set_fixmap_nocache(FIX_APIC_BASE
, apic_phys
);
1272 printk(KERN_DEBUG
"mapped APIC to %08lx (%08lx)\n", APIC_BASE
,
1276 * Fetch the APIC ID of the BSP in case we have a
1277 * default configuration (or the MP table is broken).
1279 if (boot_cpu_physical_apicid
== -1U)
1280 boot_cpu_physical_apicid
= read_apic_id();
1285 * This initializes the IO-APIC and APIC hardware if this is
1289 int apic_version
[MAX_APICS
];
1291 int __init
APIC_init_uniprocessor(void)
1293 if (!smp_found_config
&& !cpu_has_apic
)
1297 * Complain if the BIOS pretends there is one.
1299 if (!cpu_has_apic
&&
1300 APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
])) {
1301 printk(KERN_ERR
"BIOS bug, local APIC #%d not detected!...\n",
1302 boot_cpu_physical_apicid
);
1303 clear_cpu_cap(&boot_cpu_data
, X86_FEATURE_APIC
);
1307 verify_local_APIC();
1312 * Hack: In case of kdump, after a crash, kernel might be booting
1313 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
1314 * might be zero if read from MP tables. Get it from LAPIC.
1316 #ifdef CONFIG_CRASH_DUMP
1317 boot_cpu_physical_apicid
= read_apic_id();
1319 physid_set_mask_of_physid(boot_cpu_physical_apicid
, &phys_cpu_present_map
);
1323 #ifdef CONFIG_X86_IO_APIC
1324 if (!smp_found_config
|| skip_ioapic_setup
|| !nr_ioapics
)
1326 localise_nmi_watchdog();
1327 end_local_APIC_setup();
1328 #ifdef CONFIG_X86_IO_APIC
1329 if (smp_found_config
)
1330 if (!skip_ioapic_setup
&& nr_ioapics
)
1339 * Local APIC interrupts
1343 * This interrupt should _never_ happen with our APIC/SMP architecture
1345 void smp_spurious_interrupt(struct pt_regs
*regs
)
1351 * Check if this really is a spurious interrupt and ACK it
1352 * if it is a vectored one. Just in case...
1353 * Spurious interrupts should not be ACKed.
1355 v
= apic_read(APIC_ISR
+ ((SPURIOUS_APIC_VECTOR
& ~0x1f) >> 1));
1356 if (v
& (1 << (SPURIOUS_APIC_VECTOR
& 0x1f)))
1359 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1360 printk(KERN_INFO
"spurious APIC interrupt on CPU#%d, "
1361 "should never happen.\n", smp_processor_id());
1362 __get_cpu_var(irq_stat
).irq_spurious_count
++;
1367 * This interrupt should never happen with our APIC/SMP architecture
1369 void smp_error_interrupt(struct pt_regs
*regs
)
1371 unsigned long v
, v1
;
1374 /* First tickle the hardware, only then report what went on. -- REW */
1375 v
= apic_read(APIC_ESR
);
1376 apic_write(APIC_ESR
, 0);
1377 v1
= apic_read(APIC_ESR
);
1379 atomic_inc(&irq_err_count
);
1381 /* Here is what the APIC error bits mean:
1384 2: Send accept error
1385 3: Receive accept error
1387 5: Send illegal vector
1388 6: Received illegal vector
1389 7: Illegal register address
1391 printk(KERN_DEBUG
"APIC error on CPU%d: %02lx(%02lx)\n",
1392 smp_processor_id(), v
, v1
);
1397 * connect_bsp_APIC - attach the APIC to the interrupt system
1399 void __init
connect_bsp_APIC(void)
1401 #ifdef CONFIG_X86_32
1404 * Do not trust the local APIC being empty at bootup.
1408 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
1409 * local APIC to INT and NMI lines.
1411 apic_printk(APIC_VERBOSE
, "leaving PIC mode, "
1412 "enabling APIC mode.\n");
1421 * disconnect_bsp_APIC - detach the APIC from the interrupt system
1422 * @virt_wire_setup: indicates, whether virtual wire mode is selected
1424 * Virtual wire mode is necessary to deliver legacy interrupts even when the
1427 void disconnect_bsp_APIC(int virt_wire_setup
)
1431 #ifdef CONFIG_X86_32
1434 * Put the board back into PIC mode (has an effect only on
1435 * certain older boards). Note that APIC interrupts, including
1436 * IPIs, won't work beyond this point! The only exception are
1439 apic_printk(APIC_VERBOSE
, "disabling APIC mode, "
1440 "entering PIC mode.\n");
1447 /* Go back to Virtual Wire compatibility mode */
1449 /* For the spurious interrupt use vector F, and enable it */
1450 value
= apic_read(APIC_SPIV
);
1451 value
&= ~APIC_VECTOR_MASK
;
1452 value
|= APIC_SPIV_APIC_ENABLED
;
1454 apic_write(APIC_SPIV
, value
);
1456 if (!virt_wire_setup
) {
1458 * For LVT0 make it edge triggered, active high,
1459 * external and enabled
1461 value
= apic_read(APIC_LVT0
);
1462 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1463 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1464 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1465 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1466 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_EXTINT
);
1467 apic_write(APIC_LVT0
, value
);
1470 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
1474 * For LVT1 make it edge triggered, active high,
1477 value
= apic_read(APIC_LVT1
);
1478 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1479 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1480 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1481 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1482 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_NMI
);
1483 apic_write(APIC_LVT1
, value
);
1486 void __cpuinit
generic_processor_info(int apicid
, int version
)
1494 if (version
== 0x0) {
1495 printk(KERN_WARNING
"BIOS bug, APIC version is 0 for CPU#%d! "
1496 "fixing up to 0x10. (tell your hw vendor)\n",
1500 apic_version
[apicid
] = version
;
1502 if (num_processors
>= NR_CPUS
) {
1503 printk(KERN_WARNING
"WARNING: NR_CPUS limit of %i reached."
1504 " Processor ignored.\n", NR_CPUS
);
1509 cpus_complement(tmp_map
, cpu_present_map
);
1510 cpu
= first_cpu(tmp_map
);
1512 physid_set(apicid
, phys_cpu_present_map
);
1513 if (apicid
== boot_cpu_physical_apicid
) {
1515 * x86_bios_cpu_apicid is required to have processors listed
1516 * in same order as logical cpu numbers. Hence the first
1517 * entry is BSP, and so on.
1521 if (apicid
> max_physical_apicid
)
1522 max_physical_apicid
= apicid
;
1524 #ifdef CONFIG_X86_32
1526 * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y
1527 * but we need to work other dependencies like SMP_SUSPEND etc
1528 * before this can be done without some confusion.
1529 * if (CPU_HOTPLUG_ENABLED || num_processors > 8)
1530 * - Ashok Raj <ashok.raj@intel.com>
1532 if (max_physical_apicid
>= 8) {
1533 switch (boot_cpu_data
.x86_vendor
) {
1534 case X86_VENDOR_INTEL
:
1535 if (!APIC_XAPIC(version
)) {
1539 /* If P4 and above fall through */
1540 case X86_VENDOR_AMD
:
1546 #if defined(CONFIG_X86_SMP) || defined(CONFIG_X86_64)
1547 /* are we being called early in kernel startup? */
1548 if (early_per_cpu_ptr(x86_cpu_to_apicid
)) {
1549 u16
*cpu_to_apicid
= early_per_cpu_ptr(x86_cpu_to_apicid
);
1550 u16
*bios_cpu_apicid
= early_per_cpu_ptr(x86_bios_cpu_apicid
);
1552 cpu_to_apicid
[cpu
] = apicid
;
1553 bios_cpu_apicid
[cpu
] = apicid
;
1555 per_cpu(x86_cpu_to_apicid
, cpu
) = apicid
;
1556 per_cpu(x86_bios_cpu_apicid
, cpu
) = apicid
;
1560 cpu_set(cpu
, cpu_possible_map
);
1561 cpu_set(cpu
, cpu_present_map
);
1571 * 'active' is true if the local APIC was enabled by us and
1572 * not the BIOS; this signifies that we are also responsible
1573 * for disabling it before entering apm/acpi suspend
1576 /* r/w apic fields */
1577 unsigned int apic_id
;
1578 unsigned int apic_taskpri
;
1579 unsigned int apic_ldr
;
1580 unsigned int apic_dfr
;
1581 unsigned int apic_spiv
;
1582 unsigned int apic_lvtt
;
1583 unsigned int apic_lvtpc
;
1584 unsigned int apic_lvt0
;
1585 unsigned int apic_lvt1
;
1586 unsigned int apic_lvterr
;
1587 unsigned int apic_tmict
;
1588 unsigned int apic_tdcr
;
1589 unsigned int apic_thmr
;
1592 static int lapic_suspend(struct sys_device
*dev
, pm_message_t state
)
1594 unsigned long flags
;
1597 if (!apic_pm_state
.active
)
1600 maxlvt
= lapic_get_maxlvt();
1602 apic_pm_state
.apic_id
= apic_read(APIC_ID
);
1603 apic_pm_state
.apic_taskpri
= apic_read(APIC_TASKPRI
);
1604 apic_pm_state
.apic_ldr
= apic_read(APIC_LDR
);
1605 apic_pm_state
.apic_dfr
= apic_read(APIC_DFR
);
1606 apic_pm_state
.apic_spiv
= apic_read(APIC_SPIV
);
1607 apic_pm_state
.apic_lvtt
= apic_read(APIC_LVTT
);
1609 apic_pm_state
.apic_lvtpc
= apic_read(APIC_LVTPC
);
1610 apic_pm_state
.apic_lvt0
= apic_read(APIC_LVT0
);
1611 apic_pm_state
.apic_lvt1
= apic_read(APIC_LVT1
);
1612 apic_pm_state
.apic_lvterr
= apic_read(APIC_LVTERR
);
1613 apic_pm_state
.apic_tmict
= apic_read(APIC_TMICT
);
1614 apic_pm_state
.apic_tdcr
= apic_read(APIC_TDCR
);
1615 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
1617 apic_pm_state
.apic_thmr
= apic_read(APIC_LVTTHMR
);
1620 local_irq_save(flags
);
1621 disable_local_APIC();
1622 local_irq_restore(flags
);
1626 static int lapic_resume(struct sys_device
*dev
)
1629 unsigned long flags
;
1632 if (!apic_pm_state
.active
)
1635 maxlvt
= lapic_get_maxlvt();
1637 local_irq_save(flags
);
1639 #ifdef CONFIG_X86_64
1646 * Make sure the APICBASE points to the right address
1648 * FIXME! This will be wrong if we ever support suspend on
1649 * SMP! We'll need to do this as part of the CPU restore!
1651 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1652 l
&= ~MSR_IA32_APICBASE_BASE
;
1653 l
|= MSR_IA32_APICBASE_ENABLE
| mp_lapic_addr
;
1654 wrmsr(MSR_IA32_APICBASE
, l
, h
);
1657 apic_write(APIC_LVTERR
, ERROR_APIC_VECTOR
| APIC_LVT_MASKED
);
1658 apic_write(APIC_ID
, apic_pm_state
.apic_id
);
1659 apic_write(APIC_DFR
, apic_pm_state
.apic_dfr
);
1660 apic_write(APIC_LDR
, apic_pm_state
.apic_ldr
);
1661 apic_write(APIC_TASKPRI
, apic_pm_state
.apic_taskpri
);
1662 apic_write(APIC_SPIV
, apic_pm_state
.apic_spiv
);
1663 apic_write(APIC_LVT0
, apic_pm_state
.apic_lvt0
);
1664 apic_write(APIC_LVT1
, apic_pm_state
.apic_lvt1
);
1665 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
1667 apic_write(APIC_LVTTHMR
, apic_pm_state
.apic_thmr
);
1670 apic_write(APIC_LVTPC
, apic_pm_state
.apic_lvtpc
);
1671 apic_write(APIC_LVTT
, apic_pm_state
.apic_lvtt
);
1672 apic_write(APIC_TDCR
, apic_pm_state
.apic_tdcr
);
1673 apic_write(APIC_TMICT
, apic_pm_state
.apic_tmict
);
1674 apic_write(APIC_ESR
, 0);
1675 apic_read(APIC_ESR
);
1676 apic_write(APIC_LVTERR
, apic_pm_state
.apic_lvterr
);
1677 apic_write(APIC_ESR
, 0);
1678 apic_read(APIC_ESR
);
1680 local_irq_restore(flags
);
1686 * This device has no shutdown method - fully functioning local APICs
1687 * are needed on every CPU up until machine_halt/restart/poweroff.
1690 static struct sysdev_class lapic_sysclass
= {
1692 .resume
= lapic_resume
,
1693 .suspend
= lapic_suspend
,
1696 static struct sys_device device_lapic
= {
1698 .cls
= &lapic_sysclass
,
1701 static void __devinit
apic_pm_activate(void)
1703 apic_pm_state
.active
= 1;
1706 static int __init
init_lapic_sysfs(void)
1712 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
1714 error
= sysdev_class_register(&lapic_sysclass
);
1716 error
= sysdev_register(&device_lapic
);
1719 device_initcall(init_lapic_sysfs
);
1721 #else /* CONFIG_PM */
1723 static void apic_pm_activate(void) { }
1725 #endif /* CONFIG_PM */
1728 * APIC command line parameters
1730 static int __init
parse_lapic(char *arg
)
1732 force_enable_local_apic
= 1;
1735 early_param("lapic", parse_lapic
);
1737 static int __init
setup_disableapic(char *arg
)
1740 setup_clear_cpu_cap(X86_FEATURE_APIC
);
1743 early_param("disableapic", setup_disableapic
);
1745 /* same as disableapic, for compatibility */
1746 static int __init
setup_nolapic(char *arg
)
1748 return setup_disableapic(arg
);
1750 early_param("nolapic", setup_nolapic
);
1752 static int __init
parse_lapic_timer_c2_ok(char *arg
)
1754 local_apic_timer_c2_ok
= 1;
1757 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok
);
1759 static int __init
parse_disable_apic_timer(char *arg
)
1761 disable_apic_timer
= 1;
1764 early_param("noapictimer", parse_disable_apic_timer
);
1766 static int __init
parse_nolapic_timer(char *arg
)
1768 disable_apic_timer
= 1;
1771 early_param("nolapic_timer", parse_nolapic_timer
);
1773 static int __init
apic_set_verbosity(char *arg
)
1776 #ifdef CONFIG_X86_64
1777 skip_ioapic_setup
= 0;
1784 if (strcmp("debug", arg
) == 0)
1785 apic_verbosity
= APIC_DEBUG
;
1786 else if (strcmp("verbose", arg
) == 0)
1787 apic_verbosity
= APIC_VERBOSE
;
1789 printk(KERN_WARNING
"APIC Verbosity level %s not recognised"
1790 " use apic=verbose or apic=debug\n", arg
);
1796 early_param("apic", apic_set_verbosity
);
1798 static int __init
lapic_insert_resource(void)
1803 /* Put local APIC into the resource map. */
1804 lapic_resource
.start
= apic_phys
;
1805 lapic_resource
.end
= lapic_resource
.start
+ PAGE_SIZE
- 1;
1806 insert_resource(&iomem_resource
, &lapic_resource
);
1812 * need call insert after e820_reserve_resources()
1813 * that is using request_resource
1815 late_initcall(lapic_insert_resource
);