2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/bootmem.h>
22 #include <linux/interrupt.h>
23 #include <linux/mc146818rtc.h>
24 #include <linux/kernel_stat.h>
25 #include <linux/sysdev.h>
26 #include <linux/cpu.h>
27 #include <linux/clockchips.h>
28 #include <linux/acpi_pmtmr.h>
29 #include <linux/module.h>
30 #include <linux/dmi.h>
32 #include <asm/atomic.h>
35 #include <asm/mpspec.h>
37 #include <asm/arch_hooks.h>
39 #include <asm/i8253.h>
42 #include <mach_apic.h>
43 #include <mach_apicdef.h>
49 #if ((SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F)
50 # error SPURIOUS_APIC_VECTOR definition error
53 unsigned long mp_lapic_addr
;
56 * Knob to control our willingness to enable the local APIC.
60 static int force_enable_local_apic
;
63 /* Local APIC timer verification ok */
64 static int local_apic_timer_verify_ok
;
65 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
66 static int local_apic_timer_disabled
;
67 /* Local APIC timer works in C2 */
68 int local_apic_timer_c2_ok
;
69 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok
);
71 int first_system_vector
= 0xfe;
73 char system_vectors
[NR_VECTORS
] = { [0 ... NR_VECTORS
-1] = SYS_VECTOR_FREE
};
76 * Debug level, exported for io_apic.c
78 unsigned int apic_verbosity
;
82 /* Have we found an MP table */
85 static struct resource lapic_resource
= {
87 .flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
,
90 static unsigned int calibration_result
;
92 static int lapic_next_event(unsigned long delta
,
93 struct clock_event_device
*evt
);
94 static void lapic_timer_setup(enum clock_event_mode mode
,
95 struct clock_event_device
*evt
);
96 static void lapic_timer_broadcast(cpumask_t mask
);
97 static void apic_pm_activate(void);
100 * The local apic timer can be used for any function which is CPU local.
102 static struct clock_event_device lapic_clockevent
= {
104 .features
= CLOCK_EVT_FEAT_PERIODIC
| CLOCK_EVT_FEAT_ONESHOT
105 | CLOCK_EVT_FEAT_C3STOP
| CLOCK_EVT_FEAT_DUMMY
,
107 .set_mode
= lapic_timer_setup
,
108 .set_next_event
= lapic_next_event
,
109 .broadcast
= lapic_timer_broadcast
,
113 static DEFINE_PER_CPU(struct clock_event_device
, lapic_events
);
115 /* Local APIC was disabled by the BIOS and enabled by the kernel */
116 static int enabled_via_apicbase
;
118 static unsigned long apic_phys
;
121 * Get the LAPIC version
123 static inline int lapic_get_version(void)
125 return GET_APIC_VERSION(apic_read(APIC_LVR
));
129 * Check, if the APIC is integrated or a separate chip
131 static inline int lapic_is_integrated(void)
133 return APIC_INTEGRATED(lapic_get_version());
137 * Check, whether this is a modern or a first generation APIC
139 static int modern_apic(void)
141 /* AMD systems use old APIC versions, so check the CPU */
142 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
&&
143 boot_cpu_data
.x86
>= 0xf)
145 return lapic_get_version() >= 0x14;
149 * Paravirt kernels also might be using these below ops. So we still
150 * use generic apic_read()/apic_write(), which might be pointing to different
151 * ops in PARAVIRT case.
153 void xapic_wait_icr_idle(void)
155 while (apic_read(APIC_ICR
) & APIC_ICR_BUSY
)
159 u32
safe_xapic_wait_icr_idle(void)
166 send_status
= apic_read(APIC_ICR
) & APIC_ICR_BUSY
;
170 } while (timeout
++ < 1000);
175 void xapic_icr_write(u32 low
, u32 id
)
177 apic_write(APIC_ICR2
, SET_APIC_DEST_FIELD(id
));
178 apic_write(APIC_ICR
, low
);
181 u64
xapic_icr_read(void)
185 icr2
= apic_read(APIC_ICR2
);
186 icr1
= apic_read(APIC_ICR
);
188 return icr1
| ((u64
)icr2
<< 32);
191 static struct apic_ops xapic_ops
= {
192 .read
= native_apic_mem_read
,
193 .write
= native_apic_mem_write
,
194 .icr_read
= xapic_icr_read
,
195 .icr_write
= xapic_icr_write
,
196 .wait_icr_idle
= xapic_wait_icr_idle
,
197 .safe_wait_icr_idle
= safe_xapic_wait_icr_idle
,
200 struct apic_ops __read_mostly
*apic_ops
= &xapic_ops
;
201 EXPORT_SYMBOL_GPL(apic_ops
);
204 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
206 void __cpuinit
enable_NMI_through_LVT0(void)
210 /* unmask and set to NMI */
213 /* Level triggered for 82489DX (32bit mode) */
214 if (!lapic_is_integrated())
215 v
|= APIC_LVT_LEVEL_TRIGGER
;
217 apic_write(APIC_LVT0
, v
);
221 * get_physical_broadcast - Get number of physical broadcast IDs
223 int get_physical_broadcast(void)
225 return modern_apic() ? 0xff : 0xf;
229 * lapic_get_maxlvt - get the maximum number of local vector table entries
231 int lapic_get_maxlvt(void)
235 v
= apic_read(APIC_LVR
);
237 * - we always have APIC integrated on 64bit mode
238 * - 82489DXs do not report # of LVT entries
240 return APIC_INTEGRATED(GET_APIC_VERSION(v
)) ? GET_APIC_MAXLVT(v
) : 2;
247 /* Clock divisor is set to 16 */
248 #define APIC_DIVISOR 16
251 * This function sets up the local APIC timer, with a timeout of
252 * 'clocks' APIC bus clock. During calibration we actually call
253 * this function twice on the boot CPU, once with a bogus timeout
254 * value, second time for real. The other (noncalibrating) CPUs
255 * call this function only once, with the real, calibrated value.
257 static void __setup_APIC_LVTT(unsigned int clocks
, int oneshot
, int irqen
)
259 unsigned int lvtt_value
, tmp_value
;
261 lvtt_value
= LOCAL_TIMER_VECTOR
;
263 lvtt_value
|= APIC_LVT_TIMER_PERIODIC
;
264 if (!lapic_is_integrated())
265 lvtt_value
|= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV
);
268 lvtt_value
|= APIC_LVT_MASKED
;
270 apic_write(APIC_LVTT
, lvtt_value
);
275 tmp_value
= apic_read(APIC_TDCR
);
276 apic_write(APIC_TDCR
,
277 (tmp_value
& ~(APIC_TDR_DIV_1
| APIC_TDR_DIV_TMBASE
)) |
281 apic_write(APIC_TMICT
, clocks
/ APIC_DIVISOR
);
285 * Program the next event, relative to now
287 static int lapic_next_event(unsigned long delta
,
288 struct clock_event_device
*evt
)
290 apic_write(APIC_TMICT
, delta
);
295 * Setup the lapic timer in periodic or oneshot mode
297 static void lapic_timer_setup(enum clock_event_mode mode
,
298 struct clock_event_device
*evt
)
303 /* Lapic used for broadcast ? */
304 if (!local_apic_timer_verify_ok
)
307 local_irq_save(flags
);
310 case CLOCK_EVT_MODE_PERIODIC
:
311 case CLOCK_EVT_MODE_ONESHOT
:
312 __setup_APIC_LVTT(calibration_result
,
313 mode
!= CLOCK_EVT_MODE_PERIODIC
, 1);
315 case CLOCK_EVT_MODE_UNUSED
:
316 case CLOCK_EVT_MODE_SHUTDOWN
:
317 v
= apic_read(APIC_LVTT
);
318 v
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
319 apic_write(APIC_LVTT
, v
);
321 case CLOCK_EVT_MODE_RESUME
:
322 /* Nothing to do here */
326 local_irq_restore(flags
);
330 * Local APIC timer broadcast function
332 static void lapic_timer_broadcast(cpumask_t mask
)
335 send_IPI_mask(mask
, LOCAL_TIMER_VECTOR
);
340 * Setup the local APIC timer for this CPU. Copy the initilized values
341 * of the boot CPU and register the clock event in the framework.
343 static void __devinit
setup_APIC_timer(void)
345 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
347 memcpy(levt
, &lapic_clockevent
, sizeof(*levt
));
348 levt
->cpumask
= cpumask_of_cpu(smp_processor_id());
350 clockevents_register_device(levt
);
354 * In this functions we calibrate APIC bus clocks to the external timer.
356 * We want to do the calibration only once since we want to have local timer
357 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
360 * This was previously done by reading the PIT/HPET and waiting for a wrap
361 * around to find out, that a tick has elapsed. I have a box, where the PIT
362 * readout is broken, so it never gets out of the wait loop again. This was
363 * also reported by others.
365 * Monitoring the jiffies value is inaccurate and the clockevents
366 * infrastructure allows us to do a simple substitution of the interrupt
369 * The calibration routine also uses the pm_timer when possible, as the PIT
370 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
371 * back to normal later in the boot process).
374 #define LAPIC_CAL_LOOPS (HZ/10)
376 static __initdata
int lapic_cal_loops
= -1;
377 static __initdata
long lapic_cal_t1
, lapic_cal_t2
;
378 static __initdata
unsigned long long lapic_cal_tsc1
, lapic_cal_tsc2
;
379 static __initdata
unsigned long lapic_cal_pm1
, lapic_cal_pm2
;
380 static __initdata
unsigned long lapic_cal_j1
, lapic_cal_j2
;
383 * Temporary interrupt handler.
385 static void __init
lapic_cal_handler(struct clock_event_device
*dev
)
387 unsigned long long tsc
= 0;
388 long tapic
= apic_read(APIC_TMCCT
);
389 unsigned long pm
= acpi_pm_read_early();
394 switch (lapic_cal_loops
++) {
396 lapic_cal_t1
= tapic
;
397 lapic_cal_tsc1
= tsc
;
399 lapic_cal_j1
= jiffies
;
402 case LAPIC_CAL_LOOPS
:
403 lapic_cal_t2
= tapic
;
404 lapic_cal_tsc2
= tsc
;
405 if (pm
< lapic_cal_pm1
)
406 pm
+= ACPI_PM_OVRRUN
;
408 lapic_cal_j2
= jiffies
;
413 static int __init
calibrate_APIC_clock(void)
415 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
416 const long pm_100ms
= PMTMR_TICKS_PER_SEC
/10;
417 const long pm_thresh
= pm_100ms
/100;
418 void (*real_handler
)(struct clock_event_device
*dev
);
419 unsigned long deltaj
;
421 int pm_referenced
= 0;
425 /* Replace the global interrupt handler */
426 real_handler
= global_clock_event
->event_handler
;
427 global_clock_event
->event_handler
= lapic_cal_handler
;
430 * Setup the APIC counter to 1e9. There is no way the lapic
431 * can underflow in the 100ms detection time frame
433 __setup_APIC_LVTT(1000000000, 0, 0);
435 /* Let the interrupts run */
438 while (lapic_cal_loops
<= LAPIC_CAL_LOOPS
)
443 /* Restore the real event handler */
444 global_clock_event
->event_handler
= real_handler
;
446 /* Build delta t1-t2 as apic timer counts down */
447 delta
= lapic_cal_t1
- lapic_cal_t2
;
448 apic_printk(APIC_VERBOSE
, "... lapic delta = %ld\n", delta
);
450 /* Check, if the PM timer is available */
451 deltapm
= lapic_cal_pm2
- lapic_cal_pm1
;
452 apic_printk(APIC_VERBOSE
, "... PM timer delta = %ld\n", deltapm
);
458 mult
= clocksource_hz2mult(PMTMR_TICKS_PER_SEC
, 22);
460 if (deltapm
> (pm_100ms
- pm_thresh
) &&
461 deltapm
< (pm_100ms
+ pm_thresh
)) {
462 apic_printk(APIC_VERBOSE
, "... PM timer result ok\n");
464 res
= (((u64
) deltapm
) * mult
) >> 22;
465 do_div(res
, 1000000);
466 printk(KERN_WARNING
"APIC calibration not consistent "
467 "with PM Timer: %ldms instead of 100ms\n",
469 /* Correct the lapic counter value */
470 res
= (((u64
) delta
) * pm_100ms
);
471 do_div(res
, deltapm
);
472 printk(KERN_INFO
"APIC delta adjusted to PM-Timer: "
473 "%lu (%ld)\n", (unsigned long) res
, delta
);
479 /* Calculate the scaled math multiplication factor */
480 lapic_clockevent
.mult
= div_sc(delta
, TICK_NSEC
* LAPIC_CAL_LOOPS
,
481 lapic_clockevent
.shift
);
482 lapic_clockevent
.max_delta_ns
=
483 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent
);
484 lapic_clockevent
.min_delta_ns
=
485 clockevent_delta2ns(0xF, &lapic_clockevent
);
487 calibration_result
= (delta
* APIC_DIVISOR
) / LAPIC_CAL_LOOPS
;
489 apic_printk(APIC_VERBOSE
, "..... delta %ld\n", delta
);
490 apic_printk(APIC_VERBOSE
, "..... mult: %ld\n", lapic_clockevent
.mult
);
491 apic_printk(APIC_VERBOSE
, "..... calibration result: %u\n",
495 delta
= (long)(lapic_cal_tsc2
- lapic_cal_tsc1
);
496 apic_printk(APIC_VERBOSE
, "..... CPU clock speed is "
498 (delta
/ LAPIC_CAL_LOOPS
) / (1000000 / HZ
),
499 (delta
/ LAPIC_CAL_LOOPS
) % (1000000 / HZ
));
502 apic_printk(APIC_VERBOSE
, "..... host bus clock speed is "
504 calibration_result
/ (1000000 / HZ
),
505 calibration_result
% (1000000 / HZ
));
508 * Do a sanity check on the APIC calibration result
510 if (calibration_result
< (1000000 / HZ
)) {
513 "APIC frequency too slow, disabling apic timer\n");
517 local_apic_timer_verify_ok
= 1;
519 /* We trust the pm timer based calibration */
520 if (!pm_referenced
) {
521 apic_printk(APIC_VERBOSE
, "... verify APIC timer\n");
524 * Setup the apic timer manually
526 levt
->event_handler
= lapic_cal_handler
;
527 lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC
, levt
);
528 lapic_cal_loops
= -1;
530 /* Let the interrupts run */
533 while (lapic_cal_loops
<= LAPIC_CAL_LOOPS
)
538 /* Stop the lapic timer */
539 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, levt
);
544 deltaj
= lapic_cal_j2
- lapic_cal_j1
;
545 apic_printk(APIC_VERBOSE
, "... jiffies delta = %lu\n", deltaj
);
547 /* Check, if the jiffies result is consistent */
548 if (deltaj
>= LAPIC_CAL_LOOPS
-2 && deltaj
<= LAPIC_CAL_LOOPS
+2)
549 apic_printk(APIC_VERBOSE
, "... jiffies result ok\n");
551 local_apic_timer_verify_ok
= 0;
555 if (!local_apic_timer_verify_ok
) {
557 "APIC timer disabled due to verification failure.\n");
565 * Setup the boot APIC
567 * Calibrate and verify the result.
569 void __init
setup_boot_APIC_clock(void)
572 * The local apic timer can be disabled via the kernel
573 * commandline or from the CPU detection code. Register the lapic
574 * timer as a dummy clock event source on SMP systems, so the
575 * broadcast mechanism is used. On UP systems simply ignore it.
577 if (local_apic_timer_disabled
) {
578 /* No broadcast on UP ! */
579 if (num_possible_cpus() > 1) {
580 lapic_clockevent
.mult
= 1;
586 apic_printk(APIC_VERBOSE
, "Using local APIC timer interrupts.\n"
587 "calibrating APIC timer ...\n");
589 if (calibrate_APIC_clock()) {
590 /* No broadcast on UP ! */
591 if (num_possible_cpus() > 1)
597 * If nmi_watchdog is set to IO_APIC, we need the
598 * PIT/HPET going. Otherwise register lapic as a dummy
601 if (nmi_watchdog
!= NMI_IO_APIC
)
602 lapic_clockevent
.features
&= ~CLOCK_EVT_FEAT_DUMMY
;
604 printk(KERN_WARNING
"APIC timer registered as dummy,"
605 " due to nmi_watchdog=%d!\n", nmi_watchdog
);
607 /* Setup the lapic or request the broadcast */
611 void __devinit
setup_secondary_APIC_clock(void)
617 * The guts of the apic timer interrupt
619 static void local_apic_timer_interrupt(void)
621 int cpu
= smp_processor_id();
622 struct clock_event_device
*evt
= &per_cpu(lapic_events
, cpu
);
625 * Normally we should not be here till LAPIC has been initialized but
626 * in some cases like kdump, its possible that there is a pending LAPIC
627 * timer interrupt from previous kernel's context and is delivered in
628 * new kernel the moment interrupts are enabled.
630 * Interrupts are enabled early and LAPIC is setup much later, hence
631 * its possible that when we get here evt->event_handler is NULL.
632 * Check for event_handler being NULL and discard the interrupt as
635 if (!evt
->event_handler
) {
637 "Spurious LAPIC timer interrupt on cpu %d\n", cpu
);
639 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, evt
);
644 * the NMI deadlock-detector uses this.
646 per_cpu(irq_stat
, cpu
).apic_timer_irqs
++;
648 evt
->event_handler(evt
);
652 * Local APIC timer interrupt. This is the most natural way for doing
653 * local interrupts, but local timer interrupts can be emulated by
654 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
656 * [ if a single-CPU system runs an SMP kernel then we call the local
657 * interrupt as well. Thus we cannot inline the local irq ... ]
659 void smp_apic_timer_interrupt(struct pt_regs
*regs
)
661 struct pt_regs
*old_regs
= set_irq_regs(regs
);
664 * NOTE! We'd better ACK the irq immediately,
665 * because timer handling can be slow.
669 * update_process_times() expects us to have done irq_enter().
670 * Besides, if we don't timer interrupts ignore the global
671 * interrupt lock, which is the WrongThing (tm) to do.
674 local_apic_timer_interrupt();
677 set_irq_regs(old_regs
);
680 int setup_profiling_timer(unsigned int multiplier
)
686 * Setup extended LVT, AMD specific (K8, family 10h)
688 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
689 * MCE interrupts are supported. Thus MCE offset must be set to 0.
692 #define APIC_EILVT_LVTOFF_MCE 0
693 #define APIC_EILVT_LVTOFF_IBS 1
695 static void setup_APIC_eilvt(u8 lvt_off
, u8 vector
, u8 msg_type
, u8 mask
)
697 unsigned long reg
= (lvt_off
<< 4) + APIC_EILVT0
;
698 unsigned int v
= (mask
<< 16) | (msg_type
<< 8) | vector
;
702 u8
setup_APIC_eilvt_mce(u8 vector
, u8 msg_type
, u8 mask
)
704 setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE
, vector
, msg_type
, mask
);
705 return APIC_EILVT_LVTOFF_MCE
;
708 u8
setup_APIC_eilvt_ibs(u8 vector
, u8 msg_type
, u8 mask
)
710 setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS
, vector
, msg_type
, mask
);
711 return APIC_EILVT_LVTOFF_IBS
;
715 * Local APIC start and shutdown
719 * clear_local_APIC - shutdown the local APIC
721 * This is called, when a CPU is disabled and before rebooting, so the state of
722 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
723 * leftovers during boot.
725 void clear_local_APIC(void)
730 /* APIC hasn't been mapped yet */
734 maxlvt
= lapic_get_maxlvt();
736 * Masking an LVT entry can trigger a local APIC error
737 * if the vector is zero. Mask LVTERR first to prevent this.
740 v
= ERROR_APIC_VECTOR
; /* any non-zero vector will do */
741 apic_write(APIC_LVTERR
, v
| APIC_LVT_MASKED
);
744 * Careful: we have to set masks only first to deassert
745 * any level-triggered sources.
747 v
= apic_read(APIC_LVTT
);
748 apic_write(APIC_LVTT
, v
| APIC_LVT_MASKED
);
749 v
= apic_read(APIC_LVT0
);
750 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
751 v
= apic_read(APIC_LVT1
);
752 apic_write(APIC_LVT1
, v
| APIC_LVT_MASKED
);
754 v
= apic_read(APIC_LVTPC
);
755 apic_write(APIC_LVTPC
, v
| APIC_LVT_MASKED
);
758 /* lets not touch this if we didn't frob it */
759 #ifdef CONFIG_X86_MCE_P4THERMAL
761 v
= apic_read(APIC_LVTTHMR
);
762 apic_write(APIC_LVTTHMR
, v
| APIC_LVT_MASKED
);
766 * Clean APIC state for other OSs:
768 apic_write(APIC_LVTT
, APIC_LVT_MASKED
);
769 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
770 apic_write(APIC_LVT1
, APIC_LVT_MASKED
);
772 apic_write(APIC_LVTERR
, APIC_LVT_MASKED
);
774 apic_write(APIC_LVTPC
, APIC_LVT_MASKED
);
776 #ifdef CONFIG_X86_MCE_P4THERMAL
778 apic_write(APIC_LVTTHMR
, APIC_LVT_MASKED
);
780 /* Integrated APIC (!82489DX) ? */
781 if (lapic_is_integrated()) {
783 /* Clear ESR due to Pentium errata 3AP and 11AP */
784 apic_write(APIC_ESR
, 0);
790 * disable_local_APIC - clear and disable the local APIC
792 void disable_local_APIC(void)
799 * Disable APIC (implies clearing of registers
802 value
= apic_read(APIC_SPIV
);
803 value
&= ~APIC_SPIV_APIC_ENABLED
;
804 apic_write(APIC_SPIV
, value
);
807 * When LAPIC was disabled by the BIOS and enabled by the kernel,
808 * restore the disabled state.
810 if (enabled_via_apicbase
) {
813 rdmsr(MSR_IA32_APICBASE
, l
, h
);
814 l
&= ~MSR_IA32_APICBASE_ENABLE
;
815 wrmsr(MSR_IA32_APICBASE
, l
, h
);
820 * If Linux enabled the LAPIC against the BIOS default disable it down before
821 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
822 * not power-off. Additionally clear all LVT entries before disable_local_APIC
823 * for the case where Linux didn't enable the LAPIC.
825 void lapic_shutdown(void)
832 local_irq_save(flags
);
835 if (enabled_via_apicbase
)
836 disable_local_APIC();
838 local_irq_restore(flags
);
842 * This is to verify that we're looking at a real local APIC.
843 * Check these against your board if the CPUs aren't getting
844 * started for no apparent reason.
846 int __init
verify_local_APIC(void)
848 unsigned int reg0
, reg1
;
851 * The version register is read-only in a real APIC.
853 reg0
= apic_read(APIC_LVR
);
854 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg0
);
855 apic_write(APIC_LVR
, reg0
^ APIC_LVR_MASK
);
856 reg1
= apic_read(APIC_LVR
);
857 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg1
);
860 * The two version reads above should print the same
861 * numbers. If the second one is different, then we
862 * poke at a non-APIC.
868 * Check if the version looks reasonably.
870 reg1
= GET_APIC_VERSION(reg0
);
871 if (reg1
== 0x00 || reg1
== 0xff)
873 reg1
= lapic_get_maxlvt();
874 if (reg1
< 0x02 || reg1
== 0xff)
878 * The ID register is read/write in a real APIC.
880 reg0
= apic_read(APIC_ID
);
881 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg0
);
884 * The next two are just to see if we have sane values.
885 * They're only really relevant if we're in Virtual Wire
886 * compatibility mode, but most boxes are anymore.
888 reg0
= apic_read(APIC_LVT0
);
889 apic_printk(APIC_DEBUG
, "Getting LVT0: %x\n", reg0
);
890 reg1
= apic_read(APIC_LVT1
);
891 apic_printk(APIC_DEBUG
, "Getting LVT1: %x\n", reg1
);
897 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
899 void __init
sync_Arb_IDs(void)
902 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
905 if (modern_apic() || boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
)
910 apic_wait_icr_idle();
912 apic_printk(APIC_DEBUG
, "Synchronizing Arb IDs.\n");
914 APIC_DEST_ALLINC
| APIC_INT_LEVELTRIG
| APIC_DM_INIT
);
918 * An initial setup of the virtual wire mode.
920 void __init
init_bsp_APIC(void)
925 * Don't do the setup now if we have a SMP BIOS as the
926 * through-I/O-APIC virtual wire mode might be active.
928 if (smp_found_config
|| !cpu_has_apic
)
932 * Do not trust the local APIC being empty at bootup.
939 value
= apic_read(APIC_SPIV
);
940 value
&= ~APIC_VECTOR_MASK
;
941 value
|= APIC_SPIV_APIC_ENABLED
;
943 /* This bit is reserved on P4/Xeon and should be cleared */
944 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
) &&
945 (boot_cpu_data
.x86
== 15))
946 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
948 value
|= APIC_SPIV_FOCUS_DISABLED
;
949 value
|= SPURIOUS_APIC_VECTOR
;
950 apic_write(APIC_SPIV
, value
);
953 * Set up the virtual wire mode.
955 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
957 if (!lapic_is_integrated()) /* 82489DX */
958 value
|= APIC_LVT_LEVEL_TRIGGER
;
959 apic_write(APIC_LVT1
, value
);
962 static void __cpuinit
lapic_setup_esr(void)
964 unsigned long oldvalue
, value
, maxlvt
;
965 if (lapic_is_integrated() && !esr_disable
) {
967 maxlvt
= lapic_get_maxlvt();
968 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
969 apic_write(APIC_ESR
, 0);
970 oldvalue
= apic_read(APIC_ESR
);
972 /* enables sending errors */
973 value
= ERROR_APIC_VECTOR
;
974 apic_write(APIC_LVTERR
, value
);
976 * spec says clear errors after enabling vector.
979 apic_write(APIC_ESR
, 0);
980 value
= apic_read(APIC_ESR
);
981 if (value
!= oldvalue
)
982 apic_printk(APIC_VERBOSE
, "ESR value before enabling "
983 "vector: 0x%08lx after: 0x%08lx\n",
988 * Something untraceable is creating bad interrupts on
989 * secondary quads ... for the moment, just leave the
990 * ESR disabled - we can't do anything useful with the
991 * errors anyway - mbligh
993 printk(KERN_INFO
"Leaving ESR disabled.\n");
995 printk(KERN_INFO
"No ESR for 82489DX.\n");
1001 * setup_local_APIC - setup the local APIC
1003 void __cpuinit
setup_local_APIC(void)
1005 unsigned long value
, integrated
;
1008 /* Pound the ESR really hard over the head with a big hammer - mbligh */
1010 apic_write(APIC_ESR
, 0);
1011 apic_write(APIC_ESR
, 0);
1012 apic_write(APIC_ESR
, 0);
1013 apic_write(APIC_ESR
, 0);
1016 integrated
= lapic_is_integrated();
1019 * Double-check whether this APIC is really registered.
1021 if (!apic_id_registered())
1025 * Intel recommends to set DFR, LDR and TPR before enabling
1026 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
1027 * document number 292116). So here it goes...
1032 * Set Task Priority to 'accept all'. We never change this
1035 value
= apic_read(APIC_TASKPRI
);
1036 value
&= ~APIC_TPRI_MASK
;
1037 apic_write(APIC_TASKPRI
, value
);
1040 * After a crash, we no longer service the interrupts and a pending
1041 * interrupt from previous kernel might still have ISR bit set.
1043 * Most probably by now CPU has serviced that pending interrupt and
1044 * it might not have done the ack_APIC_irq() because it thought,
1045 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
1046 * does not clear the ISR bit and cpu thinks it has already serivced
1047 * the interrupt. Hence a vector might get locked. It was noticed
1048 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
1050 for (i
= APIC_ISR_NR
- 1; i
>= 0; i
--) {
1051 value
= apic_read(APIC_ISR
+ i
*0x10);
1052 for (j
= 31; j
>= 0; j
--) {
1059 * Now that we are all set up, enable the APIC
1061 value
= apic_read(APIC_SPIV
);
1062 value
&= ~APIC_VECTOR_MASK
;
1066 value
|= APIC_SPIV_APIC_ENABLED
;
1069 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1070 * certain networking cards. If high frequency interrupts are
1071 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1072 * entry is masked/unmasked at a high rate as well then sooner or
1073 * later IOAPIC line gets 'stuck', no more interrupts are received
1074 * from the device. If focus CPU is disabled then the hang goes
1077 * [ This bug can be reproduced easily with a level-triggered
1078 * PCI Ne2000 networking cards and PII/PIII processors, dual
1082 * Actually disabling the focus CPU check just makes the hang less
1083 * frequent as it makes the interrupt distributon model be more
1084 * like LRU than MRU (the short-term load is more even across CPUs).
1085 * See also the comment in end_level_ioapic_irq(). --macro
1088 /* Enable focus processor (bit==0) */
1089 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
1092 * Set spurious IRQ vector
1094 value
|= SPURIOUS_APIC_VECTOR
;
1095 apic_write(APIC_SPIV
, value
);
1098 * Set up LVT0, LVT1:
1100 * set up through-local-APIC on the BP's LINT0. This is not
1101 * strictly necessary in pure symmetric-IO mode, but sometimes
1102 * we delegate interrupts to the 8259A.
1105 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1107 value
= apic_read(APIC_LVT0
) & APIC_LVT_MASKED
;
1108 if (!smp_processor_id() && (pic_mode
|| !value
)) {
1109 value
= APIC_DM_EXTINT
;
1110 apic_printk(APIC_VERBOSE
, "enabled ExtINT on CPU#%d\n",
1111 smp_processor_id());
1113 value
= APIC_DM_EXTINT
| APIC_LVT_MASKED
;
1114 apic_printk(APIC_VERBOSE
, "masked ExtINT on CPU#%d\n",
1115 smp_processor_id());
1117 apic_write(APIC_LVT0
, value
);
1120 * only the BP should see the LINT1 NMI signal, obviously.
1122 if (!smp_processor_id())
1123 value
= APIC_DM_NMI
;
1125 value
= APIC_DM_NMI
| APIC_LVT_MASKED
;
1126 if (!integrated
) /* 82489DX */
1127 value
|= APIC_LVT_LEVEL_TRIGGER
;
1128 apic_write(APIC_LVT1
, value
);
1131 void __cpuinit
end_local_APIC_setup(void)
1133 unsigned long value
;
1136 /* Disable the local apic timer */
1137 value
= apic_read(APIC_LVTT
);
1138 value
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
1139 apic_write(APIC_LVTT
, value
);
1141 setup_apic_nmi_watchdog(NULL
);
1146 * Detect and initialize APIC
1148 static int __init
detect_init_APIC(void)
1152 /* Disabled by kernel option? */
1156 switch (boot_cpu_data
.x86_vendor
) {
1157 case X86_VENDOR_AMD
:
1158 if ((boot_cpu_data
.x86
== 6 && boot_cpu_data
.x86_model
> 1) ||
1159 (boot_cpu_data
.x86
== 15))
1162 case X86_VENDOR_INTEL
:
1163 if (boot_cpu_data
.x86
== 6 || boot_cpu_data
.x86
== 15 ||
1164 (boot_cpu_data
.x86
== 5 && cpu_has_apic
))
1171 if (!cpu_has_apic
) {
1173 * Over-ride BIOS and try to enable the local APIC only if
1174 * "lapic" specified.
1176 if (!force_enable_local_apic
) {
1177 printk(KERN_INFO
"Local APIC disabled by BIOS -- "
1178 "you can enable it with \"lapic\"\n");
1182 * Some BIOSes disable the local APIC in the APIC_BASE
1183 * MSR. This can only be done in software for Intel P6 or later
1184 * and AMD K7 (Model > 1) or later.
1186 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1187 if (!(l
& MSR_IA32_APICBASE_ENABLE
)) {
1189 "Local APIC disabled by BIOS -- reenabling.\n");
1190 l
&= ~MSR_IA32_APICBASE_BASE
;
1191 l
|= MSR_IA32_APICBASE_ENABLE
| APIC_DEFAULT_PHYS_BASE
;
1192 wrmsr(MSR_IA32_APICBASE
, l
, h
);
1193 enabled_via_apicbase
= 1;
1197 * The APIC feature bit should now be enabled
1200 features
= cpuid_edx(1);
1201 if (!(features
& (1 << X86_FEATURE_APIC
))) {
1202 printk(KERN_WARNING
"Could not enable APIC!\n");
1205 set_cpu_cap(&boot_cpu_data
, X86_FEATURE_APIC
);
1206 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
1208 /* The BIOS may have set up the APIC at some other address */
1209 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1210 if (l
& MSR_IA32_APICBASE_ENABLE
)
1211 mp_lapic_addr
= l
& MSR_IA32_APICBASE_BASE
;
1213 printk(KERN_INFO
"Found and enabled local APIC!\n");
1220 printk(KERN_INFO
"No local APIC present or hardware disabled\n");
1225 * init_apic_mappings - initialize APIC mappings
1227 void __init
init_apic_mappings(void)
1230 * If no local APIC can be found then set up a fake all
1231 * zeroes page to simulate the local APIC and another
1232 * one for the IO-APIC.
1234 if (!smp_found_config
&& detect_init_APIC()) {
1235 apic_phys
= (unsigned long) alloc_bootmem_pages(PAGE_SIZE
);
1236 apic_phys
= __pa(apic_phys
);
1238 apic_phys
= mp_lapic_addr
;
1240 set_fixmap_nocache(FIX_APIC_BASE
, apic_phys
);
1241 printk(KERN_DEBUG
"mapped APIC to %08lx (%08lx)\n", APIC_BASE
,
1245 * Fetch the APIC ID of the BSP in case we have a
1246 * default configuration (or the MP table is broken).
1248 if (boot_cpu_physical_apicid
== -1U)
1249 boot_cpu_physical_apicid
= read_apic_id();
1254 * This initializes the IO-APIC and APIC hardware if this is
1258 int apic_version
[MAX_APICS
];
1260 int __init
APIC_init_uniprocessor(void)
1262 if (!smp_found_config
&& !cpu_has_apic
)
1266 * Complain if the BIOS pretends there is one.
1268 if (!cpu_has_apic
&&
1269 APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
])) {
1270 printk(KERN_ERR
"BIOS bug, local APIC #%d not detected!...\n",
1271 boot_cpu_physical_apicid
);
1272 clear_cpu_cap(&boot_cpu_data
, X86_FEATURE_APIC
);
1276 verify_local_APIC();
1281 * Hack: In case of kdump, after a crash, kernel might be booting
1282 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
1283 * might be zero if read from MP tables. Get it from LAPIC.
1285 #ifdef CONFIG_CRASH_DUMP
1286 boot_cpu_physical_apicid
= read_apic_id();
1288 physid_set_mask_of_physid(boot_cpu_physical_apicid
, &phys_cpu_present_map
);
1292 #ifdef CONFIG_X86_IO_APIC
1293 if (!smp_found_config
|| skip_ioapic_setup
|| !nr_ioapics
)
1295 localise_nmi_watchdog();
1296 end_local_APIC_setup();
1297 #ifdef CONFIG_X86_IO_APIC
1298 if (smp_found_config
)
1299 if (!skip_ioapic_setup
&& nr_ioapics
)
1308 * Local APIC interrupts
1312 * This interrupt should _never_ happen with our APIC/SMP architecture
1314 void smp_spurious_interrupt(struct pt_regs
*regs
)
1320 * Check if this really is a spurious interrupt and ACK it
1321 * if it is a vectored one. Just in case...
1322 * Spurious interrupts should not be ACKed.
1324 v
= apic_read(APIC_ISR
+ ((SPURIOUS_APIC_VECTOR
& ~0x1f) >> 1));
1325 if (v
& (1 << (SPURIOUS_APIC_VECTOR
& 0x1f)))
1328 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1329 printk(KERN_INFO
"spurious APIC interrupt on CPU#%d, "
1330 "should never happen.\n", smp_processor_id());
1331 __get_cpu_var(irq_stat
).irq_spurious_count
++;
1336 * This interrupt should never happen with our APIC/SMP architecture
1338 void smp_error_interrupt(struct pt_regs
*regs
)
1340 unsigned long v
, v1
;
1343 /* First tickle the hardware, only then report what went on. -- REW */
1344 v
= apic_read(APIC_ESR
);
1345 apic_write(APIC_ESR
, 0);
1346 v1
= apic_read(APIC_ESR
);
1348 atomic_inc(&irq_err_count
);
1350 /* Here is what the APIC error bits mean:
1353 2: Send accept error
1354 3: Receive accept error
1356 5: Send illegal vector
1357 6: Received illegal vector
1358 7: Illegal register address
1360 printk(KERN_DEBUG
"APIC error on CPU%d: %02lx(%02lx)\n",
1361 smp_processor_id(), v
, v1
);
1366 * connect_bsp_APIC - attach the APIC to the interrupt system
1368 void __init
connect_bsp_APIC(void)
1372 * Do not trust the local APIC being empty at bootup.
1376 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
1377 * local APIC to INT and NMI lines.
1379 apic_printk(APIC_VERBOSE
, "leaving PIC mode, "
1380 "enabling APIC mode.\n");
1388 * disconnect_bsp_APIC - detach the APIC from the interrupt system
1389 * @virt_wire_setup: indicates, whether virtual wire mode is selected
1391 * Virtual wire mode is necessary to deliver legacy interrupts even when the
1394 void disconnect_bsp_APIC(int virt_wire_setup
)
1398 * Put the board back into PIC mode (has an effect only on
1399 * certain older boards). Note that APIC interrupts, including
1400 * IPIs, won't work beyond this point! The only exception are
1403 apic_printk(APIC_VERBOSE
, "disabling APIC mode, "
1404 "entering PIC mode.\n");
1408 /* Go back to Virtual Wire compatibility mode */
1409 unsigned long value
;
1411 /* For the spurious interrupt use vector F, and enable it */
1412 value
= apic_read(APIC_SPIV
);
1413 value
&= ~APIC_VECTOR_MASK
;
1414 value
|= APIC_SPIV_APIC_ENABLED
;
1416 apic_write(APIC_SPIV
, value
);
1418 if (!virt_wire_setup
) {
1420 * For LVT0 make it edge triggered, active high,
1421 * external and enabled
1423 value
= apic_read(APIC_LVT0
);
1424 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1425 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1426 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1427 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1428 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_EXTINT
);
1429 apic_write(APIC_LVT0
, value
);
1432 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
1436 * For LVT1 make it edge triggered, active high, nmi and
1439 value
= apic_read(APIC_LVT1
);
1441 APIC_MODE_MASK
| APIC_SEND_PENDING
|
1442 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1443 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1444 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1445 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_NMI
);
1446 apic_write(APIC_LVT1
, value
);
1450 void __cpuinit
generic_processor_info(int apicid
, int version
)
1454 physid_mask_t phys_cpu
;
1459 if (version
== 0x0) {
1460 printk(KERN_WARNING
"BIOS bug, APIC version is 0 for CPU#%d! "
1461 "fixing up to 0x10. (tell your hw vendor)\n",
1465 apic_version
[apicid
] = version
;
1467 phys_cpu
= apicid_to_cpu_present(apicid
);
1468 physids_or(phys_cpu_present_map
, phys_cpu_present_map
, phys_cpu
);
1470 if (num_processors
>= NR_CPUS
) {
1471 printk(KERN_WARNING
"WARNING: NR_CPUS limit of %i reached."
1472 " Processor ignored.\n", NR_CPUS
);
1477 cpus_complement(tmp_map
, cpu_present_map
);
1478 cpu
= first_cpu(tmp_map
);
1480 if (apicid
== boot_cpu_physical_apicid
)
1482 * x86_bios_cpu_apicid is required to have processors listed
1483 * in same order as logical cpu numbers. Hence the first
1484 * entry is BSP, and so on.
1488 if (apicid
> max_physical_apicid
)
1489 max_physical_apicid
= apicid
;
1492 * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y
1493 * but we need to work other dependencies like SMP_SUSPEND etc
1494 * before this can be done without some confusion.
1495 * if (CPU_HOTPLUG_ENABLED || num_processors > 8)
1496 * - Ashok Raj <ashok.raj@intel.com>
1498 if (max_physical_apicid
>= 8) {
1499 switch (boot_cpu_data
.x86_vendor
) {
1500 case X86_VENDOR_INTEL
:
1501 if (!APIC_XAPIC(version
)) {
1505 /* If P4 and above fall through */
1506 case X86_VENDOR_AMD
:
1511 /* are we being called early in kernel startup? */
1512 if (early_per_cpu_ptr(x86_cpu_to_apicid
)) {
1513 u16
*cpu_to_apicid
= early_per_cpu_ptr(x86_cpu_to_apicid
);
1514 u16
*bios_cpu_apicid
= early_per_cpu_ptr(x86_bios_cpu_apicid
);
1516 cpu_to_apicid
[cpu
] = apicid
;
1517 bios_cpu_apicid
[cpu
] = apicid
;
1519 per_cpu(x86_cpu_to_apicid
, cpu
) = apicid
;
1520 per_cpu(x86_bios_cpu_apicid
, cpu
) = apicid
;
1523 cpu_set(cpu
, cpu_possible_map
);
1524 cpu_set(cpu
, cpu_present_map
);
1534 /* r/w apic fields */
1535 unsigned int apic_id
;
1536 unsigned int apic_taskpri
;
1537 unsigned int apic_ldr
;
1538 unsigned int apic_dfr
;
1539 unsigned int apic_spiv
;
1540 unsigned int apic_lvtt
;
1541 unsigned int apic_lvtpc
;
1542 unsigned int apic_lvt0
;
1543 unsigned int apic_lvt1
;
1544 unsigned int apic_lvterr
;
1545 unsigned int apic_tmict
;
1546 unsigned int apic_tdcr
;
1547 unsigned int apic_thmr
;
1550 static int lapic_suspend(struct sys_device
*dev
, pm_message_t state
)
1552 unsigned long flags
;
1555 if (!apic_pm_state
.active
)
1558 maxlvt
= lapic_get_maxlvt();
1560 apic_pm_state
.apic_id
= apic_read(APIC_ID
);
1561 apic_pm_state
.apic_taskpri
= apic_read(APIC_TASKPRI
);
1562 apic_pm_state
.apic_ldr
= apic_read(APIC_LDR
);
1563 apic_pm_state
.apic_dfr
= apic_read(APIC_DFR
);
1564 apic_pm_state
.apic_spiv
= apic_read(APIC_SPIV
);
1565 apic_pm_state
.apic_lvtt
= apic_read(APIC_LVTT
);
1567 apic_pm_state
.apic_lvtpc
= apic_read(APIC_LVTPC
);
1568 apic_pm_state
.apic_lvt0
= apic_read(APIC_LVT0
);
1569 apic_pm_state
.apic_lvt1
= apic_read(APIC_LVT1
);
1570 apic_pm_state
.apic_lvterr
= apic_read(APIC_LVTERR
);
1571 apic_pm_state
.apic_tmict
= apic_read(APIC_TMICT
);
1572 apic_pm_state
.apic_tdcr
= apic_read(APIC_TDCR
);
1573 #ifdef CONFIG_X86_MCE_P4THERMAL
1575 apic_pm_state
.apic_thmr
= apic_read(APIC_LVTTHMR
);
1578 local_irq_save(flags
);
1579 disable_local_APIC();
1580 local_irq_restore(flags
);
1584 static int lapic_resume(struct sys_device
*dev
)
1587 unsigned long flags
;
1590 if (!apic_pm_state
.active
)
1593 maxlvt
= lapic_get_maxlvt();
1595 local_irq_save(flags
);
1598 * Make sure the APICBASE points to the right address
1600 * FIXME! This will be wrong if we ever support suspend on
1601 * SMP! We'll need to do this as part of the CPU restore!
1603 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1604 l
&= ~MSR_IA32_APICBASE_BASE
;
1605 l
|= MSR_IA32_APICBASE_ENABLE
| mp_lapic_addr
;
1606 wrmsr(MSR_IA32_APICBASE
, l
, h
);
1608 apic_write(APIC_LVTERR
, ERROR_APIC_VECTOR
| APIC_LVT_MASKED
);
1609 apic_write(APIC_ID
, apic_pm_state
.apic_id
);
1610 apic_write(APIC_DFR
, apic_pm_state
.apic_dfr
);
1611 apic_write(APIC_LDR
, apic_pm_state
.apic_ldr
);
1612 apic_write(APIC_TASKPRI
, apic_pm_state
.apic_taskpri
);
1613 apic_write(APIC_SPIV
, apic_pm_state
.apic_spiv
);
1614 apic_write(APIC_LVT0
, apic_pm_state
.apic_lvt0
);
1615 apic_write(APIC_LVT1
, apic_pm_state
.apic_lvt1
);
1616 #ifdef CONFIG_X86_MCE_P4THERMAL
1618 apic_write(APIC_LVTTHMR
, apic_pm_state
.apic_thmr
);
1621 apic_write(APIC_LVTPC
, apic_pm_state
.apic_lvtpc
);
1622 apic_write(APIC_LVTT
, apic_pm_state
.apic_lvtt
);
1623 apic_write(APIC_TDCR
, apic_pm_state
.apic_tdcr
);
1624 apic_write(APIC_TMICT
, apic_pm_state
.apic_tmict
);
1625 apic_write(APIC_ESR
, 0);
1626 apic_read(APIC_ESR
);
1627 apic_write(APIC_LVTERR
, apic_pm_state
.apic_lvterr
);
1628 apic_write(APIC_ESR
, 0);
1629 apic_read(APIC_ESR
);
1630 local_irq_restore(flags
);
1635 * This device has no shutdown method - fully functioning local APICs
1636 * are needed on every CPU up until machine_halt/restart/poweroff.
1639 static struct sysdev_class lapic_sysclass
= {
1641 .resume
= lapic_resume
,
1642 .suspend
= lapic_suspend
,
1645 static struct sys_device device_lapic
= {
1647 .cls
= &lapic_sysclass
,
1650 static void __devinit
apic_pm_activate(void)
1652 apic_pm_state
.active
= 1;
1655 static int __init
init_lapic_sysfs(void)
1661 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
1663 error
= sysdev_class_register(&lapic_sysclass
);
1665 error
= sysdev_register(&device_lapic
);
1668 device_initcall(init_lapic_sysfs
);
1670 #else /* CONFIG_PM */
1672 static void apic_pm_activate(void) { }
1674 #endif /* CONFIG_PM */
1677 * APIC command line parameters
1679 static int __init
parse_lapic(char *arg
)
1681 force_enable_local_apic
= 1;
1684 early_param("lapic", parse_lapic
);
1686 static int __init
parse_nolapic(char *arg
)
1689 setup_clear_cpu_cap(X86_FEATURE_APIC
);
1692 early_param("nolapic", parse_nolapic
);
1694 static int __init
parse_disable_lapic_timer(char *arg
)
1696 local_apic_timer_disabled
= 1;
1699 early_param("nolapic_timer", parse_disable_lapic_timer
);
1701 static int __init
parse_lapic_timer_c2_ok(char *arg
)
1703 local_apic_timer_c2_ok
= 1;
1706 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok
);
1708 static int __init
apic_set_verbosity(char *arg
)
1713 if (strcmp(arg
, "debug") == 0)
1714 apic_verbosity
= APIC_DEBUG
;
1715 else if (strcmp(arg
, "verbose") == 0)
1716 apic_verbosity
= APIC_VERBOSE
;
1720 early_param("apic", apic_set_verbosity
);
1722 static int __init
lapic_insert_resource(void)
1727 /* Put local APIC into the resource map. */
1728 lapic_resource
.start
= apic_phys
;
1729 lapic_resource
.end
= lapic_resource
.start
+ PAGE_SIZE
- 1;
1730 insert_resource(&iomem_resource
, &lapic_resource
);
1736 * need call insert after e820_reserve_resources()
1737 * that is using request_resource
1739 late_initcall(lapic_insert_resource
);