2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/bootmem.h>
22 #include <linux/interrupt.h>
23 #include <linux/mc146818rtc.h>
24 #include <linux/kernel_stat.h>
25 #include <linux/sysdev.h>
26 #include <linux/cpu.h>
27 #include <linux/clockchips.h>
28 #include <linux/acpi_pmtmr.h>
29 #include <linux/module.h>
30 #include <linux/dmi.h>
32 #include <asm/atomic.h>
35 #include <asm/mpspec.h>
37 #include <asm/arch_hooks.h>
39 #include <asm/i8253.h>
42 #include <mach_apic.h>
43 #include <mach_apicdef.h>
49 #if ((SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F)
50 # error SPURIOUS_APIC_VECTOR definition error
53 unsigned long mp_lapic_addr
;
56 * Knob to control our willingness to enable the local APIC.
60 static int force_enable_local_apic
;
63 /* Local APIC timer verification ok */
64 static int local_apic_timer_verify_ok
;
65 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
66 static int local_apic_timer_disabled
;
67 /* Local APIC timer works in C2 */
68 int local_apic_timer_c2_ok
;
69 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok
);
71 int first_system_vector
= 0xfe;
73 char system_vectors
[NR_VECTORS
] = { [0 ... NR_VECTORS
-1] = SYS_VECTOR_FREE
};
76 * Debug level, exported for io_apic.c
82 /* Have we found an MP table */
85 static struct resource lapic_resource
= {
87 .flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
,
90 static unsigned int calibration_result
;
92 static int lapic_next_event(unsigned long delta
,
93 struct clock_event_device
*evt
);
94 static void lapic_timer_setup(enum clock_event_mode mode
,
95 struct clock_event_device
*evt
);
96 static void lapic_timer_broadcast(cpumask_t mask
);
97 static void apic_pm_activate(void);
100 * The local apic timer can be used for any function which is CPU local.
102 static struct clock_event_device lapic_clockevent
= {
104 .features
= CLOCK_EVT_FEAT_PERIODIC
| CLOCK_EVT_FEAT_ONESHOT
105 | CLOCK_EVT_FEAT_C3STOP
| CLOCK_EVT_FEAT_DUMMY
,
107 .set_mode
= lapic_timer_setup
,
108 .set_next_event
= lapic_next_event
,
109 .broadcast
= lapic_timer_broadcast
,
113 static DEFINE_PER_CPU(struct clock_event_device
, lapic_events
);
115 /* Local APIC was disabled by the BIOS and enabled by the kernel */
116 static int enabled_via_apicbase
;
118 static unsigned long apic_phys
;
121 * Get the LAPIC version
123 static inline int lapic_get_version(void)
125 return GET_APIC_VERSION(apic_read(APIC_LVR
));
129 * Check, if the APIC is integrated or a separate chip
131 static inline int lapic_is_integrated(void)
133 return APIC_INTEGRATED(lapic_get_version());
137 * Check, whether this is a modern or a first generation APIC
139 static int modern_apic(void)
141 /* AMD systems use old APIC versions, so check the CPU */
142 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
&&
143 boot_cpu_data
.x86
>= 0xf)
145 return lapic_get_version() >= 0x14;
149 * Paravirt kernels also might be using these below ops. So we still
150 * use generic apic_read()/apic_write(), which might be pointing to different
151 * ops in PARAVIRT case.
153 void xapic_wait_icr_idle(void)
155 while (apic_read(APIC_ICR
) & APIC_ICR_BUSY
)
159 u32
safe_xapic_wait_icr_idle(void)
166 send_status
= apic_read(APIC_ICR
) & APIC_ICR_BUSY
;
170 } while (timeout
++ < 1000);
175 void xapic_icr_write(u32 low
, u32 id
)
177 apic_write_around(APIC_ICR2
, SET_APIC_DEST_FIELD(id
));
178 apic_write_around(APIC_ICR
, low
);
181 u64
xapic_icr_read(void)
185 icr2
= apic_read(APIC_ICR2
);
186 icr1
= apic_read(APIC_ICR
);
188 return icr1
| ((u64
)icr2
<< 32);
191 static struct apic_ops xapic_ops
= {
192 .read
= native_apic_mem_read
,
193 .write
= native_apic_mem_write
,
194 .write_atomic
= native_apic_mem_write_atomic
,
195 .icr_read
= xapic_icr_read
,
196 .icr_write
= xapic_icr_write
,
197 .wait_icr_idle
= xapic_wait_icr_idle
,
198 .safe_wait_icr_idle
= safe_xapic_wait_icr_idle
,
201 struct apic_ops __read_mostly
*apic_ops
= &xapic_ops
;
202 EXPORT_SYMBOL_GPL(apic_ops
);
205 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
207 void __cpuinit
enable_NMI_through_LVT0(void)
209 unsigned int v
= APIC_DM_NMI
;
211 /* Level triggered for 82489DX */
212 if (!lapic_is_integrated())
213 v
|= APIC_LVT_LEVEL_TRIGGER
;
214 apic_write_around(APIC_LVT0
, v
);
218 * get_physical_broadcast - Get number of physical broadcast IDs
220 int get_physical_broadcast(void)
222 return modern_apic() ? 0xff : 0xf;
226 * lapic_get_maxlvt - get the maximum number of local vector table entries
228 int lapic_get_maxlvt(void)
230 unsigned int v
= apic_read(APIC_LVR
);
232 /* 82489DXs do not report # of LVT entries. */
233 return APIC_INTEGRATED(GET_APIC_VERSION(v
)) ? GET_APIC_MAXLVT(v
) : 2;
240 /* Clock divisor is set to 16 */
241 #define APIC_DIVISOR 16
244 * This function sets up the local APIC timer, with a timeout of
245 * 'clocks' APIC bus clock. During calibration we actually call
246 * this function twice on the boot CPU, once with a bogus timeout
247 * value, second time for real. The other (noncalibrating) CPUs
248 * call this function only once, with the real, calibrated value.
250 * We do reads before writes even if unnecessary, to get around the
251 * P5 APIC double write bug.
253 static void __setup_APIC_LVTT(unsigned int clocks
, int oneshot
, int irqen
)
255 unsigned int lvtt_value
, tmp_value
;
257 lvtt_value
= LOCAL_TIMER_VECTOR
;
259 lvtt_value
|= APIC_LVT_TIMER_PERIODIC
;
260 if (!lapic_is_integrated())
261 lvtt_value
|= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV
);
264 lvtt_value
|= APIC_LVT_MASKED
;
266 apic_write_around(APIC_LVTT
, lvtt_value
);
271 tmp_value
= apic_read(APIC_TDCR
);
272 apic_write_around(APIC_TDCR
, (tmp_value
273 & ~(APIC_TDR_DIV_1
| APIC_TDR_DIV_TMBASE
))
277 apic_write_around(APIC_TMICT
, clocks
/APIC_DIVISOR
);
281 * Program the next event, relative to now
283 static int lapic_next_event(unsigned long delta
,
284 struct clock_event_device
*evt
)
286 apic_write_around(APIC_TMICT
, delta
);
291 * Setup the lapic timer in periodic or oneshot mode
293 static void lapic_timer_setup(enum clock_event_mode mode
,
294 struct clock_event_device
*evt
)
299 /* Lapic used for broadcast ? */
300 if (!local_apic_timer_verify_ok
)
303 local_irq_save(flags
);
306 case CLOCK_EVT_MODE_PERIODIC
:
307 case CLOCK_EVT_MODE_ONESHOT
:
308 __setup_APIC_LVTT(calibration_result
,
309 mode
!= CLOCK_EVT_MODE_PERIODIC
, 1);
311 case CLOCK_EVT_MODE_UNUSED
:
312 case CLOCK_EVT_MODE_SHUTDOWN
:
313 v
= apic_read(APIC_LVTT
);
314 v
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
315 apic_write_around(APIC_LVTT
, v
);
317 case CLOCK_EVT_MODE_RESUME
:
318 /* Nothing to do here */
322 local_irq_restore(flags
);
326 * Local APIC timer broadcast function
328 static void lapic_timer_broadcast(cpumask_t mask
)
331 send_IPI_mask(mask
, LOCAL_TIMER_VECTOR
);
336 * Setup the local APIC timer for this CPU. Copy the initilized values
337 * of the boot CPU and register the clock event in the framework.
339 static void __devinit
setup_APIC_timer(void)
341 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
343 memcpy(levt
, &lapic_clockevent
, sizeof(*levt
));
344 levt
->cpumask
= cpumask_of_cpu(smp_processor_id());
346 clockevents_register_device(levt
);
350 * In this functions we calibrate APIC bus clocks to the external timer.
352 * We want to do the calibration only once since we want to have local timer
353 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
356 * This was previously done by reading the PIT/HPET and waiting for a wrap
357 * around to find out, that a tick has elapsed. I have a box, where the PIT
358 * readout is broken, so it never gets out of the wait loop again. This was
359 * also reported by others.
361 * Monitoring the jiffies value is inaccurate and the clockevents
362 * infrastructure allows us to do a simple substitution of the interrupt
365 * The calibration routine also uses the pm_timer when possible, as the PIT
366 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
367 * back to normal later in the boot process).
370 #define LAPIC_CAL_LOOPS (HZ/10)
372 static __initdata
int lapic_cal_loops
= -1;
373 static __initdata
long lapic_cal_t1
, lapic_cal_t2
;
374 static __initdata
unsigned long long lapic_cal_tsc1
, lapic_cal_tsc2
;
375 static __initdata
unsigned long lapic_cal_pm1
, lapic_cal_pm2
;
376 static __initdata
unsigned long lapic_cal_j1
, lapic_cal_j2
;
379 * Temporary interrupt handler.
381 static void __init
lapic_cal_handler(struct clock_event_device
*dev
)
383 unsigned long long tsc
= 0;
384 long tapic
= apic_read(APIC_TMCCT
);
385 unsigned long pm
= acpi_pm_read_early();
390 switch (lapic_cal_loops
++) {
392 lapic_cal_t1
= tapic
;
393 lapic_cal_tsc1
= tsc
;
395 lapic_cal_j1
= jiffies
;
398 case LAPIC_CAL_LOOPS
:
399 lapic_cal_t2
= tapic
;
400 lapic_cal_tsc2
= tsc
;
401 if (pm
< lapic_cal_pm1
)
402 pm
+= ACPI_PM_OVRRUN
;
404 lapic_cal_j2
= jiffies
;
410 * Setup the boot APIC
412 * Calibrate and verify the result.
414 void __init
setup_boot_APIC_clock(void)
416 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
417 const long pm_100ms
= PMTMR_TICKS_PER_SEC
/10;
418 const long pm_thresh
= pm_100ms
/100;
419 void (*real_handler
)(struct clock_event_device
*dev
);
420 unsigned long deltaj
;
422 int pm_referenced
= 0;
425 * The local apic timer can be disabled via the kernel
426 * commandline or from the CPU detection code. Register the lapic
427 * timer as a dummy clock event source on SMP systems, so the
428 * broadcast mechanism is used. On UP systems simply ignore it.
430 if (local_apic_timer_disabled
) {
431 /* No broadcast on UP ! */
432 if (num_possible_cpus() > 1) {
433 lapic_clockevent
.mult
= 1;
439 apic_printk(APIC_VERBOSE
, "Using local APIC timer interrupts.\n"
440 "calibrating APIC timer ...\n");
444 /* Replace the global interrupt handler */
445 real_handler
= global_clock_event
->event_handler
;
446 global_clock_event
->event_handler
= lapic_cal_handler
;
449 * Setup the APIC counter to 1e9. There is no way the lapic
450 * can underflow in the 100ms detection time frame
452 __setup_APIC_LVTT(1000000000, 0, 0);
454 /* Let the interrupts run */
457 while (lapic_cal_loops
<= LAPIC_CAL_LOOPS
)
462 /* Restore the real event handler */
463 global_clock_event
->event_handler
= real_handler
;
465 /* Build delta t1-t2 as apic timer counts down */
466 delta
= lapic_cal_t1
- lapic_cal_t2
;
467 apic_printk(APIC_VERBOSE
, "... lapic delta = %ld\n", delta
);
469 /* Check, if the PM timer is available */
470 deltapm
= lapic_cal_pm2
- lapic_cal_pm1
;
471 apic_printk(APIC_VERBOSE
, "... PM timer delta = %ld\n", deltapm
);
477 mult
= clocksource_hz2mult(PMTMR_TICKS_PER_SEC
, 22);
479 if (deltapm
> (pm_100ms
- pm_thresh
) &&
480 deltapm
< (pm_100ms
+ pm_thresh
)) {
481 apic_printk(APIC_VERBOSE
, "... PM timer result ok\n");
483 res
= (((u64
) deltapm
) * mult
) >> 22;
484 do_div(res
, 1000000);
485 printk(KERN_WARNING
"APIC calibration not consistent "
486 "with PM Timer: %ldms instead of 100ms\n",
488 /* Correct the lapic counter value */
489 res
= (((u64
) delta
) * pm_100ms
);
490 do_div(res
, deltapm
);
491 printk(KERN_INFO
"APIC delta adjusted to PM-Timer: "
492 "%lu (%ld)\n", (unsigned long) res
, delta
);
498 /* Calculate the scaled math multiplication factor */
499 lapic_clockevent
.mult
= div_sc(delta
, TICK_NSEC
* LAPIC_CAL_LOOPS
,
500 lapic_clockevent
.shift
);
501 lapic_clockevent
.max_delta_ns
=
502 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent
);
503 lapic_clockevent
.min_delta_ns
=
504 clockevent_delta2ns(0xF, &lapic_clockevent
);
506 calibration_result
= (delta
* APIC_DIVISOR
) / LAPIC_CAL_LOOPS
;
508 apic_printk(APIC_VERBOSE
, "..... delta %ld\n", delta
);
509 apic_printk(APIC_VERBOSE
, "..... mult: %ld\n", lapic_clockevent
.mult
);
510 apic_printk(APIC_VERBOSE
, "..... calibration result: %u\n",
514 delta
= (long)(lapic_cal_tsc2
- lapic_cal_tsc1
);
515 apic_printk(APIC_VERBOSE
, "..... CPU clock speed is "
517 (delta
/ LAPIC_CAL_LOOPS
) / (1000000 / HZ
),
518 (delta
/ LAPIC_CAL_LOOPS
) % (1000000 / HZ
));
521 apic_printk(APIC_VERBOSE
, "..... host bus clock speed is "
523 calibration_result
/ (1000000 / HZ
),
524 calibration_result
% (1000000 / HZ
));
526 local_apic_timer_verify_ok
= 1;
529 * Do a sanity check on the APIC calibration result
531 if (calibration_result
< (1000000 / HZ
)) {
534 "APIC frequency too slow, disabling apic timer\n");
535 /* No broadcast on UP ! */
536 if (num_possible_cpus() > 1)
541 /* We trust the pm timer based calibration */
542 if (!pm_referenced
) {
543 apic_printk(APIC_VERBOSE
, "... verify APIC timer\n");
546 * Setup the apic timer manually
548 levt
->event_handler
= lapic_cal_handler
;
549 lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC
, levt
);
550 lapic_cal_loops
= -1;
552 /* Let the interrupts run */
555 while (lapic_cal_loops
<= LAPIC_CAL_LOOPS
)
560 /* Stop the lapic timer */
561 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, levt
);
566 deltaj
= lapic_cal_j2
- lapic_cal_j1
;
567 apic_printk(APIC_VERBOSE
, "... jiffies delta = %lu\n", deltaj
);
569 /* Check, if the jiffies result is consistent */
570 if (deltaj
>= LAPIC_CAL_LOOPS
-2 && deltaj
<= LAPIC_CAL_LOOPS
+2)
571 apic_printk(APIC_VERBOSE
, "... jiffies result ok\n");
573 local_apic_timer_verify_ok
= 0;
577 if (!local_apic_timer_verify_ok
) {
579 "APIC timer disabled due to verification failure.\n");
580 /* No broadcast on UP ! */
581 if (num_possible_cpus() == 1)
585 * If nmi_watchdog is set to IO_APIC, we need the
586 * PIT/HPET going. Otherwise register lapic as a dummy
589 if (nmi_watchdog
!= NMI_IO_APIC
)
590 lapic_clockevent
.features
&= ~CLOCK_EVT_FEAT_DUMMY
;
592 printk(KERN_WARNING
"APIC timer registered as dummy,"
593 " due to nmi_watchdog=%d!\n", nmi_watchdog
);
596 /* Setup the lapic or request the broadcast */
600 void __devinit
setup_secondary_APIC_clock(void)
606 * The guts of the apic timer interrupt
608 static void local_apic_timer_interrupt(void)
610 int cpu
= smp_processor_id();
611 struct clock_event_device
*evt
= &per_cpu(lapic_events
, cpu
);
614 * Normally we should not be here till LAPIC has been initialized but
615 * in some cases like kdump, its possible that there is a pending LAPIC
616 * timer interrupt from previous kernel's context and is delivered in
617 * new kernel the moment interrupts are enabled.
619 * Interrupts are enabled early and LAPIC is setup much later, hence
620 * its possible that when we get here evt->event_handler is NULL.
621 * Check for event_handler being NULL and discard the interrupt as
624 if (!evt
->event_handler
) {
626 "Spurious LAPIC timer interrupt on cpu %d\n", cpu
);
628 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, evt
);
633 * the NMI deadlock-detector uses this.
635 per_cpu(irq_stat
, cpu
).apic_timer_irqs
++;
637 evt
->event_handler(evt
);
641 * Local APIC timer interrupt. This is the most natural way for doing
642 * local interrupts, but local timer interrupts can be emulated by
643 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
645 * [ if a single-CPU system runs an SMP kernel then we call the local
646 * interrupt as well. Thus we cannot inline the local irq ... ]
648 void smp_apic_timer_interrupt(struct pt_regs
*regs
)
650 struct pt_regs
*old_regs
= set_irq_regs(regs
);
653 * NOTE! We'd better ACK the irq immediately,
654 * because timer handling can be slow.
658 * update_process_times() expects us to have done irq_enter().
659 * Besides, if we don't timer interrupts ignore the global
660 * interrupt lock, which is the WrongThing (tm) to do.
663 local_apic_timer_interrupt();
666 set_irq_regs(old_regs
);
669 int setup_profiling_timer(unsigned int multiplier
)
675 * Setup extended LVT, AMD specific (K8, family 10h)
677 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
678 * MCE interrupts are supported. Thus MCE offset must be set to 0.
681 #define APIC_EILVT_LVTOFF_MCE 0
682 #define APIC_EILVT_LVTOFF_IBS 1
684 static void setup_APIC_eilvt(u8 lvt_off
, u8 vector
, u8 msg_type
, u8 mask
)
686 unsigned long reg
= (lvt_off
<< 4) + APIC_EILVT0
;
687 unsigned int v
= (mask
<< 16) | (msg_type
<< 8) | vector
;
691 u8
setup_APIC_eilvt_mce(u8 vector
, u8 msg_type
, u8 mask
)
693 setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE
, vector
, msg_type
, mask
);
694 return APIC_EILVT_LVTOFF_MCE
;
697 u8
setup_APIC_eilvt_ibs(u8 vector
, u8 msg_type
, u8 mask
)
699 setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS
, vector
, msg_type
, mask
);
700 return APIC_EILVT_LVTOFF_IBS
;
704 * Local APIC start and shutdown
708 * clear_local_APIC - shutdown the local APIC
710 * This is called, when a CPU is disabled and before rebooting, so the state of
711 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
712 * leftovers during boot.
714 void clear_local_APIC(void)
719 /* APIC hasn't been mapped yet */
723 maxlvt
= lapic_get_maxlvt();
725 * Masking an LVT entry can trigger a local APIC error
726 * if the vector is zero. Mask LVTERR first to prevent this.
729 v
= ERROR_APIC_VECTOR
; /* any non-zero vector will do */
730 apic_write_around(APIC_LVTERR
, v
| APIC_LVT_MASKED
);
733 * Careful: we have to set masks only first to deassert
734 * any level-triggered sources.
736 v
= apic_read(APIC_LVTT
);
737 apic_write_around(APIC_LVTT
, v
| APIC_LVT_MASKED
);
738 v
= apic_read(APIC_LVT0
);
739 apic_write_around(APIC_LVT0
, v
| APIC_LVT_MASKED
);
740 v
= apic_read(APIC_LVT1
);
741 apic_write_around(APIC_LVT1
, v
| APIC_LVT_MASKED
);
743 v
= apic_read(APIC_LVTPC
);
744 apic_write_around(APIC_LVTPC
, v
| APIC_LVT_MASKED
);
747 /* lets not touch this if we didn't frob it */
748 #ifdef CONFIG_X86_MCE_P4THERMAL
750 v
= apic_read(APIC_LVTTHMR
);
751 apic_write_around(APIC_LVTTHMR
, v
| APIC_LVT_MASKED
);
755 * Clean APIC state for other OSs:
757 apic_write_around(APIC_LVTT
, APIC_LVT_MASKED
);
758 apic_write_around(APIC_LVT0
, APIC_LVT_MASKED
);
759 apic_write_around(APIC_LVT1
, APIC_LVT_MASKED
);
761 apic_write_around(APIC_LVTERR
, APIC_LVT_MASKED
);
763 apic_write_around(APIC_LVTPC
, APIC_LVT_MASKED
);
765 #ifdef CONFIG_X86_MCE_P4THERMAL
767 apic_write_around(APIC_LVTTHMR
, APIC_LVT_MASKED
);
769 /* Integrated APIC (!82489DX) ? */
770 if (lapic_is_integrated()) {
772 /* Clear ESR due to Pentium errata 3AP and 11AP */
773 apic_write(APIC_ESR
, 0);
779 * disable_local_APIC - clear and disable the local APIC
781 void disable_local_APIC(void)
788 * Disable APIC (implies clearing of registers
791 value
= apic_read(APIC_SPIV
);
792 value
&= ~APIC_SPIV_APIC_ENABLED
;
793 apic_write_around(APIC_SPIV
, value
);
796 * When LAPIC was disabled by the BIOS and enabled by the kernel,
797 * restore the disabled state.
799 if (enabled_via_apicbase
) {
802 rdmsr(MSR_IA32_APICBASE
, l
, h
);
803 l
&= ~MSR_IA32_APICBASE_ENABLE
;
804 wrmsr(MSR_IA32_APICBASE
, l
, h
);
809 * If Linux enabled the LAPIC against the BIOS default disable it down before
810 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
811 * not power-off. Additionally clear all LVT entries before disable_local_APIC
812 * for the case where Linux didn't enable the LAPIC.
814 void lapic_shutdown(void)
821 local_irq_save(flags
);
824 if (enabled_via_apicbase
)
825 disable_local_APIC();
827 local_irq_restore(flags
);
831 * This is to verify that we're looking at a real local APIC.
832 * Check these against your board if the CPUs aren't getting
833 * started for no apparent reason.
835 int __init
verify_local_APIC(void)
837 unsigned int reg0
, reg1
;
840 * The version register is read-only in a real APIC.
842 reg0
= apic_read(APIC_LVR
);
843 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg0
);
844 apic_write(APIC_LVR
, reg0
^ APIC_LVR_MASK
);
845 reg1
= apic_read(APIC_LVR
);
846 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg1
);
849 * The two version reads above should print the same
850 * numbers. If the second one is different, then we
851 * poke at a non-APIC.
857 * Check if the version looks reasonably.
859 reg1
= GET_APIC_VERSION(reg0
);
860 if (reg1
== 0x00 || reg1
== 0xff)
862 reg1
= lapic_get_maxlvt();
863 if (reg1
< 0x02 || reg1
== 0xff)
867 * The ID register is read/write in a real APIC.
869 reg0
= apic_read(APIC_ID
);
870 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg0
);
873 * The next two are just to see if we have sane values.
874 * They're only really relevant if we're in Virtual Wire
875 * compatibility mode, but most boxes are anymore.
877 reg0
= apic_read(APIC_LVT0
);
878 apic_printk(APIC_DEBUG
, "Getting LVT0: %x\n", reg0
);
879 reg1
= apic_read(APIC_LVT1
);
880 apic_printk(APIC_DEBUG
, "Getting LVT1: %x\n", reg1
);
886 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
888 void __init
sync_Arb_IDs(void)
891 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
894 if (modern_apic() || boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
)
899 apic_wait_icr_idle();
901 apic_printk(APIC_DEBUG
, "Synchronizing Arb IDs.\n");
902 apic_write_around(APIC_ICR
, APIC_DEST_ALLINC
| APIC_INT_LEVELTRIG
907 * An initial setup of the virtual wire mode.
909 void __init
init_bsp_APIC(void)
914 * Don't do the setup now if we have a SMP BIOS as the
915 * through-I/O-APIC virtual wire mode might be active.
917 if (smp_found_config
|| !cpu_has_apic
)
921 * Do not trust the local APIC being empty at bootup.
928 value
= apic_read(APIC_SPIV
);
929 value
&= ~APIC_VECTOR_MASK
;
930 value
|= APIC_SPIV_APIC_ENABLED
;
932 /* This bit is reserved on P4/Xeon and should be cleared */
933 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
) &&
934 (boot_cpu_data
.x86
== 15))
935 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
937 value
|= APIC_SPIV_FOCUS_DISABLED
;
938 value
|= SPURIOUS_APIC_VECTOR
;
939 apic_write_around(APIC_SPIV
, value
);
942 * Set up the virtual wire mode.
944 apic_write_around(APIC_LVT0
, APIC_DM_EXTINT
);
946 if (!lapic_is_integrated()) /* 82489DX */
947 value
|= APIC_LVT_LEVEL_TRIGGER
;
948 apic_write_around(APIC_LVT1
, value
);
951 static void __cpuinit
lapic_setup_esr(void)
953 unsigned long oldvalue
, value
, maxlvt
;
954 if (lapic_is_integrated() && !esr_disable
) {
956 maxlvt
= lapic_get_maxlvt();
957 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
958 apic_write(APIC_ESR
, 0);
959 oldvalue
= apic_read(APIC_ESR
);
961 /* enables sending errors */
962 value
= ERROR_APIC_VECTOR
;
963 apic_write_around(APIC_LVTERR
, value
);
965 * spec says clear errors after enabling vector.
968 apic_write(APIC_ESR
, 0);
969 value
= apic_read(APIC_ESR
);
970 if (value
!= oldvalue
)
971 apic_printk(APIC_VERBOSE
, "ESR value before enabling "
972 "vector: 0x%08lx after: 0x%08lx\n",
977 * Something untraceable is creating bad interrupts on
978 * secondary quads ... for the moment, just leave the
979 * ESR disabled - we can't do anything useful with the
980 * errors anyway - mbligh
982 printk(KERN_INFO
"Leaving ESR disabled.\n");
984 printk(KERN_INFO
"No ESR for 82489DX.\n");
990 * setup_local_APIC - setup the local APIC
992 void __cpuinit
setup_local_APIC(void)
994 unsigned long value
, integrated
;
997 /* Pound the ESR really hard over the head with a big hammer - mbligh */
999 apic_write(APIC_ESR
, 0);
1000 apic_write(APIC_ESR
, 0);
1001 apic_write(APIC_ESR
, 0);
1002 apic_write(APIC_ESR
, 0);
1005 integrated
= lapic_is_integrated();
1008 * Double-check whether this APIC is really registered.
1010 if (!apic_id_registered())
1014 * Intel recommends to set DFR, LDR and TPR before enabling
1015 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
1016 * document number 292116). So here it goes...
1021 * Set Task Priority to 'accept all'. We never change this
1024 value
= apic_read(APIC_TASKPRI
);
1025 value
&= ~APIC_TPRI_MASK
;
1026 apic_write_around(APIC_TASKPRI
, value
);
1029 * After a crash, we no longer service the interrupts and a pending
1030 * interrupt from previous kernel might still have ISR bit set.
1032 * Most probably by now CPU has serviced that pending interrupt and
1033 * it might not have done the ack_APIC_irq() because it thought,
1034 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
1035 * does not clear the ISR bit and cpu thinks it has already serivced
1036 * the interrupt. Hence a vector might get locked. It was noticed
1037 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
1039 for (i
= APIC_ISR_NR
- 1; i
>= 0; i
--) {
1040 value
= apic_read(APIC_ISR
+ i
*0x10);
1041 for (j
= 31; j
>= 0; j
--) {
1048 * Now that we are all set up, enable the APIC
1050 value
= apic_read(APIC_SPIV
);
1051 value
&= ~APIC_VECTOR_MASK
;
1055 value
|= APIC_SPIV_APIC_ENABLED
;
1058 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1059 * certain networking cards. If high frequency interrupts are
1060 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1061 * entry is masked/unmasked at a high rate as well then sooner or
1062 * later IOAPIC line gets 'stuck', no more interrupts are received
1063 * from the device. If focus CPU is disabled then the hang goes
1066 * [ This bug can be reproduced easily with a level-triggered
1067 * PCI Ne2000 networking cards and PII/PIII processors, dual
1071 * Actually disabling the focus CPU check just makes the hang less
1072 * frequent as it makes the interrupt distributon model be more
1073 * like LRU than MRU (the short-term load is more even across CPUs).
1074 * See also the comment in end_level_ioapic_irq(). --macro
1077 /* Enable focus processor (bit==0) */
1078 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
1081 * Set spurious IRQ vector
1083 value
|= SPURIOUS_APIC_VECTOR
;
1084 apic_write_around(APIC_SPIV
, value
);
1087 * Set up LVT0, LVT1:
1089 * set up through-local-APIC on the BP's LINT0. This is not
1090 * strictly necessary in pure symmetric-IO mode, but sometimes
1091 * we delegate interrupts to the 8259A.
1094 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1096 value
= apic_read(APIC_LVT0
) & APIC_LVT_MASKED
;
1097 if (!smp_processor_id() && (pic_mode
|| !value
)) {
1098 value
= APIC_DM_EXTINT
;
1099 apic_printk(APIC_VERBOSE
, "enabled ExtINT on CPU#%d\n",
1100 smp_processor_id());
1102 value
= APIC_DM_EXTINT
| APIC_LVT_MASKED
;
1103 apic_printk(APIC_VERBOSE
, "masked ExtINT on CPU#%d\n",
1104 smp_processor_id());
1106 apic_write_around(APIC_LVT0
, value
);
1109 * only the BP should see the LINT1 NMI signal, obviously.
1111 if (!smp_processor_id())
1112 value
= APIC_DM_NMI
;
1114 value
= APIC_DM_NMI
| APIC_LVT_MASKED
;
1115 if (!integrated
) /* 82489DX */
1116 value
|= APIC_LVT_LEVEL_TRIGGER
;
1117 apic_write_around(APIC_LVT1
, value
);
1120 void __cpuinit
end_local_APIC_setup(void)
1122 unsigned long value
;
1125 /* Disable the local apic timer */
1126 value
= apic_read(APIC_LVTT
);
1127 value
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
1128 apic_write_around(APIC_LVTT
, value
);
1130 setup_apic_nmi_watchdog(NULL
);
1135 * Detect and initialize APIC
1137 static int __init
detect_init_APIC(void)
1141 /* Disabled by kernel option? */
1145 switch (boot_cpu_data
.x86_vendor
) {
1146 case X86_VENDOR_AMD
:
1147 if ((boot_cpu_data
.x86
== 6 && boot_cpu_data
.x86_model
> 1) ||
1148 (boot_cpu_data
.x86
== 15))
1151 case X86_VENDOR_INTEL
:
1152 if (boot_cpu_data
.x86
== 6 || boot_cpu_data
.x86
== 15 ||
1153 (boot_cpu_data
.x86
== 5 && cpu_has_apic
))
1160 if (!cpu_has_apic
) {
1162 * Over-ride BIOS and try to enable the local APIC only if
1163 * "lapic" specified.
1165 if (!force_enable_local_apic
) {
1166 printk(KERN_INFO
"Local APIC disabled by BIOS -- "
1167 "you can enable it with \"lapic\"\n");
1171 * Some BIOSes disable the local APIC in the APIC_BASE
1172 * MSR. This can only be done in software for Intel P6 or later
1173 * and AMD K7 (Model > 1) or later.
1175 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1176 if (!(l
& MSR_IA32_APICBASE_ENABLE
)) {
1178 "Local APIC disabled by BIOS -- reenabling.\n");
1179 l
&= ~MSR_IA32_APICBASE_BASE
;
1180 l
|= MSR_IA32_APICBASE_ENABLE
| APIC_DEFAULT_PHYS_BASE
;
1181 wrmsr(MSR_IA32_APICBASE
, l
, h
);
1182 enabled_via_apicbase
= 1;
1186 * The APIC feature bit should now be enabled
1189 features
= cpuid_edx(1);
1190 if (!(features
& (1 << X86_FEATURE_APIC
))) {
1191 printk(KERN_WARNING
"Could not enable APIC!\n");
1194 set_cpu_cap(&boot_cpu_data
, X86_FEATURE_APIC
);
1195 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
1197 /* The BIOS may have set up the APIC at some other address */
1198 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1199 if (l
& MSR_IA32_APICBASE_ENABLE
)
1200 mp_lapic_addr
= l
& MSR_IA32_APICBASE_BASE
;
1202 printk(KERN_INFO
"Found and enabled local APIC!\n");
1209 printk(KERN_INFO
"No local APIC present or hardware disabled\n");
1214 * init_apic_mappings - initialize APIC mappings
1216 void __init
init_apic_mappings(void)
1219 * If no local APIC can be found then set up a fake all
1220 * zeroes page to simulate the local APIC and another
1221 * one for the IO-APIC.
1223 if (!smp_found_config
&& detect_init_APIC()) {
1224 apic_phys
= (unsigned long) alloc_bootmem_pages(PAGE_SIZE
);
1225 apic_phys
= __pa(apic_phys
);
1227 apic_phys
= mp_lapic_addr
;
1229 set_fixmap_nocache(FIX_APIC_BASE
, apic_phys
);
1230 printk(KERN_DEBUG
"mapped APIC to %08lx (%08lx)\n", APIC_BASE
,
1234 * Fetch the APIC ID of the BSP in case we have a
1235 * default configuration (or the MP table is broken).
1237 if (boot_cpu_physical_apicid
== -1U)
1238 boot_cpu_physical_apicid
= read_apic_id();
1243 * This initializes the IO-APIC and APIC hardware if this is
1247 int apic_version
[MAX_APICS
];
1249 int __init
APIC_init_uniprocessor(void)
1252 clear_cpu_cap(&boot_cpu_data
, X86_FEATURE_APIC
);
1254 if (!smp_found_config
&& !cpu_has_apic
)
1258 * Complain if the BIOS pretends there is one.
1260 if (!cpu_has_apic
&&
1261 APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
])) {
1262 printk(KERN_ERR
"BIOS bug, local APIC #%d not detected!...\n",
1263 boot_cpu_physical_apicid
);
1264 clear_cpu_cap(&boot_cpu_data
, X86_FEATURE_APIC
);
1268 verify_local_APIC();
1273 * Hack: In case of kdump, after a crash, kernel might be booting
1274 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
1275 * might be zero if read from MP tables. Get it from LAPIC.
1277 #ifdef CONFIG_CRASH_DUMP
1278 boot_cpu_physical_apicid
= read_apic_id();
1280 physid_set_mask_of_physid(boot_cpu_physical_apicid
, &phys_cpu_present_map
);
1284 #ifdef CONFIG_X86_IO_APIC
1285 if (!smp_found_config
|| skip_ioapic_setup
|| !nr_ioapics
)
1287 localise_nmi_watchdog();
1288 end_local_APIC_setup();
1289 #ifdef CONFIG_X86_IO_APIC
1290 if (smp_found_config
)
1291 if (!skip_ioapic_setup
&& nr_ioapics
)
1300 * Local APIC interrupts
1304 * This interrupt should _never_ happen with our APIC/SMP architecture
1306 void smp_spurious_interrupt(struct pt_regs
*regs
)
1312 * Check if this really is a spurious interrupt and ACK it
1313 * if it is a vectored one. Just in case...
1314 * Spurious interrupts should not be ACKed.
1316 v
= apic_read(APIC_ISR
+ ((SPURIOUS_APIC_VECTOR
& ~0x1f) >> 1));
1317 if (v
& (1 << (SPURIOUS_APIC_VECTOR
& 0x1f)))
1320 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1321 printk(KERN_INFO
"spurious APIC interrupt on CPU#%d, "
1322 "should never happen.\n", smp_processor_id());
1323 __get_cpu_var(irq_stat
).irq_spurious_count
++;
1328 * This interrupt should never happen with our APIC/SMP architecture
1330 void smp_error_interrupt(struct pt_regs
*regs
)
1332 unsigned long v
, v1
;
1335 /* First tickle the hardware, only then report what went on. -- REW */
1336 v
= apic_read(APIC_ESR
);
1337 apic_write(APIC_ESR
, 0);
1338 v1
= apic_read(APIC_ESR
);
1340 atomic_inc(&irq_err_count
);
1342 /* Here is what the APIC error bits mean:
1345 2: Send accept error
1346 3: Receive accept error
1348 5: Send illegal vector
1349 6: Received illegal vector
1350 7: Illegal register address
1352 printk(KERN_DEBUG
"APIC error on CPU%d: %02lx(%02lx)\n",
1353 smp_processor_id(), v
, v1
);
1358 void __init
smp_intr_init(void)
1361 * IRQ0 must be given a fixed assignment and initialized,
1362 * because it's used before the IO-APIC is set up.
1364 set_intr_gate(FIRST_DEVICE_VECTOR
, interrupt
[0]);
1367 * The reschedule interrupt is a CPU-to-CPU reschedule-helper
1368 * IPI, driven by wakeup.
1370 alloc_intr_gate(RESCHEDULE_VECTOR
, reschedule_interrupt
);
1372 /* IPI for invalidation */
1373 alloc_intr_gate(INVALIDATE_TLB_VECTOR
, invalidate_interrupt
);
1375 /* IPI for generic function call */
1376 alloc_intr_gate(CALL_FUNCTION_VECTOR
, call_function_interrupt
);
1381 * Initialize APIC interrupts
1383 void __init
apic_intr_init(void)
1388 /* self generated IPI for local APIC timer */
1389 alloc_intr_gate(LOCAL_TIMER_VECTOR
, apic_timer_interrupt
);
1391 /* IPI vectors for APIC spurious and error interrupts */
1392 alloc_intr_gate(SPURIOUS_APIC_VECTOR
, spurious_interrupt
);
1393 alloc_intr_gate(ERROR_APIC_VECTOR
, error_interrupt
);
1395 /* thermal monitor LVT interrupt */
1396 #ifdef CONFIG_X86_MCE_P4THERMAL
1397 alloc_intr_gate(THERMAL_APIC_VECTOR
, thermal_interrupt
);
1402 * connect_bsp_APIC - attach the APIC to the interrupt system
1404 void __init
connect_bsp_APIC(void)
1408 * Do not trust the local APIC being empty at bootup.
1412 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
1413 * local APIC to INT and NMI lines.
1415 apic_printk(APIC_VERBOSE
, "leaving PIC mode, "
1416 "enabling APIC mode.\n");
1424 * disconnect_bsp_APIC - detach the APIC from the interrupt system
1425 * @virt_wire_setup: indicates, whether virtual wire mode is selected
1427 * Virtual wire mode is necessary to deliver legacy interrupts even when the
1430 void disconnect_bsp_APIC(int virt_wire_setup
)
1434 * Put the board back into PIC mode (has an effect only on
1435 * certain older boards). Note that APIC interrupts, including
1436 * IPIs, won't work beyond this point! The only exception are
1439 apic_printk(APIC_VERBOSE
, "disabling APIC mode, "
1440 "entering PIC mode.\n");
1444 /* Go back to Virtual Wire compatibility mode */
1445 unsigned long value
;
1447 /* For the spurious interrupt use vector F, and enable it */
1448 value
= apic_read(APIC_SPIV
);
1449 value
&= ~APIC_VECTOR_MASK
;
1450 value
|= APIC_SPIV_APIC_ENABLED
;
1452 apic_write_around(APIC_SPIV
, value
);
1454 if (!virt_wire_setup
) {
1456 * For LVT0 make it edge triggered, active high,
1457 * external and enabled
1459 value
= apic_read(APIC_LVT0
);
1460 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1461 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1462 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1463 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1464 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_EXTINT
);
1465 apic_write_around(APIC_LVT0
, value
);
1468 apic_write_around(APIC_LVT0
, APIC_LVT_MASKED
);
1472 * For LVT1 make it edge triggered, active high, nmi and
1475 value
= apic_read(APIC_LVT1
);
1477 APIC_MODE_MASK
| APIC_SEND_PENDING
|
1478 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1479 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1480 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1481 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_NMI
);
1482 apic_write_around(APIC_LVT1
, value
);
1486 unsigned int __cpuinitdata maxcpus
= NR_CPUS
;
1488 void __cpuinit
generic_processor_info(int apicid
, int version
)
1492 physid_mask_t phys_cpu
;
1497 if (version
== 0x0) {
1498 printk(KERN_WARNING
"BIOS bug, APIC version is 0 for CPU#%d! "
1499 "fixing up to 0x10. (tell your hw vendor)\n",
1503 apic_version
[apicid
] = version
;
1505 phys_cpu
= apicid_to_cpu_present(apicid
);
1506 physids_or(phys_cpu_present_map
, phys_cpu_present_map
, phys_cpu
);
1508 if (num_processors
>= NR_CPUS
) {
1509 printk(KERN_WARNING
"WARNING: NR_CPUS limit of %i reached."
1510 " Processor ignored.\n", NR_CPUS
);
1514 if (num_processors
>= maxcpus
) {
1515 printk(KERN_WARNING
"WARNING: maxcpus limit of %i reached."
1516 " Processor ignored.\n", maxcpus
);
1521 cpus_complement(tmp_map
, cpu_present_map
);
1522 cpu
= first_cpu(tmp_map
);
1524 if (apicid
== boot_cpu_physical_apicid
)
1526 * x86_bios_cpu_apicid is required to have processors listed
1527 * in same order as logical cpu numbers. Hence the first
1528 * entry is BSP, and so on.
1532 if (apicid
> max_physical_apicid
)
1533 max_physical_apicid
= apicid
;
1536 * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y
1537 * but we need to work other dependencies like SMP_SUSPEND etc
1538 * before this can be done without some confusion.
1539 * if (CPU_HOTPLUG_ENABLED || num_processors > 8)
1540 * - Ashok Raj <ashok.raj@intel.com>
1542 if (max_physical_apicid
>= 8) {
1543 switch (boot_cpu_data
.x86_vendor
) {
1544 case X86_VENDOR_INTEL
:
1545 if (!APIC_XAPIC(version
)) {
1549 /* If P4 and above fall through */
1550 case X86_VENDOR_AMD
:
1555 /* are we being called early in kernel startup? */
1556 if (early_per_cpu_ptr(x86_cpu_to_apicid
)) {
1557 u16
*cpu_to_apicid
= early_per_cpu_ptr(x86_cpu_to_apicid
);
1558 u16
*bios_cpu_apicid
= early_per_cpu_ptr(x86_bios_cpu_apicid
);
1560 cpu_to_apicid
[cpu
] = apicid
;
1561 bios_cpu_apicid
[cpu
] = apicid
;
1563 per_cpu(x86_cpu_to_apicid
, cpu
) = apicid
;
1564 per_cpu(x86_bios_cpu_apicid
, cpu
) = apicid
;
1567 cpu_set(cpu
, cpu_possible_map
);
1568 cpu_set(cpu
, cpu_present_map
);
1578 /* r/w apic fields */
1579 unsigned int apic_id
;
1580 unsigned int apic_taskpri
;
1581 unsigned int apic_ldr
;
1582 unsigned int apic_dfr
;
1583 unsigned int apic_spiv
;
1584 unsigned int apic_lvtt
;
1585 unsigned int apic_lvtpc
;
1586 unsigned int apic_lvt0
;
1587 unsigned int apic_lvt1
;
1588 unsigned int apic_lvterr
;
1589 unsigned int apic_tmict
;
1590 unsigned int apic_tdcr
;
1591 unsigned int apic_thmr
;
1594 static int lapic_suspend(struct sys_device
*dev
, pm_message_t state
)
1596 unsigned long flags
;
1599 if (!apic_pm_state
.active
)
1602 maxlvt
= lapic_get_maxlvt();
1604 apic_pm_state
.apic_id
= apic_read(APIC_ID
);
1605 apic_pm_state
.apic_taskpri
= apic_read(APIC_TASKPRI
);
1606 apic_pm_state
.apic_ldr
= apic_read(APIC_LDR
);
1607 apic_pm_state
.apic_dfr
= apic_read(APIC_DFR
);
1608 apic_pm_state
.apic_spiv
= apic_read(APIC_SPIV
);
1609 apic_pm_state
.apic_lvtt
= apic_read(APIC_LVTT
);
1611 apic_pm_state
.apic_lvtpc
= apic_read(APIC_LVTPC
);
1612 apic_pm_state
.apic_lvt0
= apic_read(APIC_LVT0
);
1613 apic_pm_state
.apic_lvt1
= apic_read(APIC_LVT1
);
1614 apic_pm_state
.apic_lvterr
= apic_read(APIC_LVTERR
);
1615 apic_pm_state
.apic_tmict
= apic_read(APIC_TMICT
);
1616 apic_pm_state
.apic_tdcr
= apic_read(APIC_TDCR
);
1617 #ifdef CONFIG_X86_MCE_P4THERMAL
1619 apic_pm_state
.apic_thmr
= apic_read(APIC_LVTTHMR
);
1622 local_irq_save(flags
);
1623 disable_local_APIC();
1624 local_irq_restore(flags
);
1628 static int lapic_resume(struct sys_device
*dev
)
1631 unsigned long flags
;
1634 if (!apic_pm_state
.active
)
1637 maxlvt
= lapic_get_maxlvt();
1639 local_irq_save(flags
);
1642 * Make sure the APICBASE points to the right address
1644 * FIXME! This will be wrong if we ever support suspend on
1645 * SMP! We'll need to do this as part of the CPU restore!
1647 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1648 l
&= ~MSR_IA32_APICBASE_BASE
;
1649 l
|= MSR_IA32_APICBASE_ENABLE
| mp_lapic_addr
;
1650 wrmsr(MSR_IA32_APICBASE
, l
, h
);
1652 apic_write(APIC_LVTERR
, ERROR_APIC_VECTOR
| APIC_LVT_MASKED
);
1653 apic_write(APIC_ID
, apic_pm_state
.apic_id
);
1654 apic_write(APIC_DFR
, apic_pm_state
.apic_dfr
);
1655 apic_write(APIC_LDR
, apic_pm_state
.apic_ldr
);
1656 apic_write(APIC_TASKPRI
, apic_pm_state
.apic_taskpri
);
1657 apic_write(APIC_SPIV
, apic_pm_state
.apic_spiv
);
1658 apic_write(APIC_LVT0
, apic_pm_state
.apic_lvt0
);
1659 apic_write(APIC_LVT1
, apic_pm_state
.apic_lvt1
);
1660 #ifdef CONFIG_X86_MCE_P4THERMAL
1662 apic_write(APIC_LVTTHMR
, apic_pm_state
.apic_thmr
);
1665 apic_write(APIC_LVTPC
, apic_pm_state
.apic_lvtpc
);
1666 apic_write(APIC_LVTT
, apic_pm_state
.apic_lvtt
);
1667 apic_write(APIC_TDCR
, apic_pm_state
.apic_tdcr
);
1668 apic_write(APIC_TMICT
, apic_pm_state
.apic_tmict
);
1669 apic_write(APIC_ESR
, 0);
1670 apic_read(APIC_ESR
);
1671 apic_write(APIC_LVTERR
, apic_pm_state
.apic_lvterr
);
1672 apic_write(APIC_ESR
, 0);
1673 apic_read(APIC_ESR
);
1674 local_irq_restore(flags
);
1679 * This device has no shutdown method - fully functioning local APICs
1680 * are needed on every CPU up until machine_halt/restart/poweroff.
1683 static struct sysdev_class lapic_sysclass
= {
1685 .resume
= lapic_resume
,
1686 .suspend
= lapic_suspend
,
1689 static struct sys_device device_lapic
= {
1691 .cls
= &lapic_sysclass
,
1694 static void __devinit
apic_pm_activate(void)
1696 apic_pm_state
.active
= 1;
1699 static int __init
init_lapic_sysfs(void)
1705 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
1707 error
= sysdev_class_register(&lapic_sysclass
);
1709 error
= sysdev_register(&device_lapic
);
1712 device_initcall(init_lapic_sysfs
);
1714 #else /* CONFIG_PM */
1716 static void apic_pm_activate(void) { }
1718 #endif /* CONFIG_PM */
1721 * APIC command line parameters
1723 static int __init
parse_lapic(char *arg
)
1725 force_enable_local_apic
= 1;
1728 early_param("lapic", parse_lapic
);
1730 static int __init
parse_nolapic(char *arg
)
1733 clear_cpu_cap(&boot_cpu_data
, X86_FEATURE_APIC
);
1736 early_param("nolapic", parse_nolapic
);
1738 static int __init
parse_disable_lapic_timer(char *arg
)
1740 local_apic_timer_disabled
= 1;
1743 early_param("nolapic_timer", parse_disable_lapic_timer
);
1745 static int __init
parse_lapic_timer_c2_ok(char *arg
)
1747 local_apic_timer_c2_ok
= 1;
1750 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok
);
1752 static int __init
apic_set_verbosity(char *str
)
1754 if (strcmp("debug", str
) == 0)
1755 apic_verbosity
= APIC_DEBUG
;
1756 else if (strcmp("verbose", str
) == 0)
1757 apic_verbosity
= APIC_VERBOSE
;
1760 __setup("apic=", apic_set_verbosity
);
1762 static int __init
lapic_insert_resource(void)
1767 /* Put local APIC into the resource map. */
1768 lapic_resource
.start
= apic_phys
;
1769 lapic_resource
.end
= lapic_resource
.start
+ PAGE_SIZE
- 1;
1770 insert_resource(&iomem_resource
, &lapic_resource
);
1776 * need call insert after e820_reserve_resources()
1777 * that is using request_resource
1779 late_initcall(lapic_insert_resource
);