2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/bootmem.h>
22 #include <linux/interrupt.h>
23 #include <linux/mc146818rtc.h>
24 #include <linux/kernel_stat.h>
25 #include <linux/sysdev.h>
26 #include <linux/ioport.h>
27 #include <linux/cpu.h>
28 #include <linux/clockchips.h>
29 #include <linux/acpi_pmtmr.h>
30 #include <linux/module.h>
31 #include <linux/dmi.h>
32 #include <linux/dmar.h>
34 #include <asm/atomic.h>
37 #include <asm/mpspec.h>
39 #include <asm/arch_hooks.h>
41 #include <asm/pgalloc.h>
42 #include <asm/i8253.h>
45 #include <asm/proto.h>
46 #include <asm/timex.h>
48 #include <asm/i8259.h>
50 #include <mach_apic.h>
51 #include <mach_apicdef.h>
57 #if ((SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F)
58 # error SPURIOUS_APIC_VECTOR definition error
63 * Knob to control our willingness to enable the local APIC.
67 static int force_enable_local_apic
;
69 * APIC command line parameters
71 static int __init
parse_lapic(char *arg
)
73 force_enable_local_apic
= 1;
76 early_param("lapic", parse_lapic
);
77 /* Local APIC was disabled by the BIOS and enabled by the kernel */
78 static int enabled_via_apicbase
;
83 static int apic_calibrate_pmtmr __initdata
;
84 static __init
int setup_apicpmtimer(char *s
)
86 apic_calibrate_pmtmr
= 1;
90 __setup("apicpmtimer", setup_apicpmtimer
);
99 /* x2apic enabled before OS handover */
100 int x2apic_preenabled
;
102 static __init
int setup_nox2apic(char *str
)
105 setup_clear_cpu_cap(X86_FEATURE_X2APIC
);
108 early_param("nox2apic", setup_nox2apic
);
111 unsigned long mp_lapic_addr
;
113 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
114 static int disable_apic_timer __cpuinitdata
;
115 /* Local APIC timer works in C2 */
116 int local_apic_timer_c2_ok
;
117 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok
);
119 int first_system_vector
= 0xfe;
121 char system_vectors
[NR_VECTORS
] = { [0 ... NR_VECTORS
-1] = SYS_VECTOR_FREE
};
124 * Debug level, exported for io_apic.c
126 unsigned int apic_verbosity
;
130 /* Have we found an MP table */
131 int smp_found_config
;
133 static struct resource lapic_resource
= {
134 .name
= "Local APIC",
135 .flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
,
138 static unsigned int calibration_result
;
140 static int lapic_next_event(unsigned long delta
,
141 struct clock_event_device
*evt
);
142 static void lapic_timer_setup(enum clock_event_mode mode
,
143 struct clock_event_device
*evt
);
144 static void lapic_timer_broadcast(cpumask_t mask
);
145 static void apic_pm_activate(void);
148 * The local apic timer can be used for any function which is CPU local.
150 static struct clock_event_device lapic_clockevent
= {
152 .features
= CLOCK_EVT_FEAT_PERIODIC
| CLOCK_EVT_FEAT_ONESHOT
153 | CLOCK_EVT_FEAT_C3STOP
| CLOCK_EVT_FEAT_DUMMY
,
155 .set_mode
= lapic_timer_setup
,
156 .set_next_event
= lapic_next_event
,
157 .broadcast
= lapic_timer_broadcast
,
161 static DEFINE_PER_CPU(struct clock_event_device
, lapic_events
);
163 static unsigned long apic_phys
;
166 * Get the LAPIC version
168 static inline int lapic_get_version(void)
170 return GET_APIC_VERSION(apic_read(APIC_LVR
));
174 * Check, if the APIC is integrated or a separate chip
176 static inline int lapic_is_integrated(void)
181 return APIC_INTEGRATED(lapic_get_version());
186 * Check, whether this is a modern or a first generation APIC
188 static int modern_apic(void)
190 /* AMD systems use old APIC versions, so check the CPU */
191 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
&&
192 boot_cpu_data
.x86
>= 0xf)
194 return lapic_get_version() >= 0x14;
198 * Paravirt kernels also might be using these below ops. So we still
199 * use generic apic_read()/apic_write(), which might be pointing to different
200 * ops in PARAVIRT case.
202 void xapic_wait_icr_idle(void)
204 while (apic_read(APIC_ICR
) & APIC_ICR_BUSY
)
208 u32
safe_xapic_wait_icr_idle(void)
215 send_status
= apic_read(APIC_ICR
) & APIC_ICR_BUSY
;
219 } while (timeout
++ < 1000);
224 void xapic_icr_write(u32 low
, u32 id
)
226 apic_write(APIC_ICR2
, SET_APIC_DEST_FIELD(id
));
227 apic_write(APIC_ICR
, low
);
230 u64
xapic_icr_read(void)
234 icr2
= apic_read(APIC_ICR2
);
235 icr1
= apic_read(APIC_ICR
);
237 return icr1
| ((u64
)icr2
<< 32);
240 static struct apic_ops xapic_ops
= {
241 .read
= native_apic_mem_read
,
242 .write
= native_apic_mem_write
,
243 .icr_read
= xapic_icr_read
,
244 .icr_write
= xapic_icr_write
,
245 .wait_icr_idle
= xapic_wait_icr_idle
,
246 .safe_wait_icr_idle
= safe_xapic_wait_icr_idle
,
249 struct apic_ops __read_mostly
*apic_ops
= &xapic_ops
;
250 EXPORT_SYMBOL_GPL(apic_ops
);
253 static void x2apic_wait_icr_idle(void)
255 /* no need to wait for icr idle in x2apic */
259 static u32
safe_x2apic_wait_icr_idle(void)
261 /* no need to wait for icr idle in x2apic */
265 void x2apic_icr_write(u32 low
, u32 id
)
267 wrmsrl(APIC_BASE_MSR
+ (APIC_ICR
>> 4), ((__u64
) id
) << 32 | low
);
270 u64
x2apic_icr_read(void)
274 rdmsrl(APIC_BASE_MSR
+ (APIC_ICR
>> 4), val
);
278 static struct apic_ops x2apic_ops
= {
279 .read
= native_apic_msr_read
,
280 .write
= native_apic_msr_write
,
281 .icr_read
= x2apic_icr_read
,
282 .icr_write
= x2apic_icr_write
,
283 .wait_icr_idle
= x2apic_wait_icr_idle
,
284 .safe_wait_icr_idle
= safe_x2apic_wait_icr_idle
,
289 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
291 void __cpuinit
enable_NMI_through_LVT0(void)
295 /* unmask and set to NMI */
298 /* Level triggered for 82489DX (32bit mode) */
299 if (!lapic_is_integrated())
300 v
|= APIC_LVT_LEVEL_TRIGGER
;
302 apic_write(APIC_LVT0
, v
);
307 * get_physical_broadcast - Get number of physical broadcast IDs
309 int get_physical_broadcast(void)
311 return modern_apic() ? 0xff : 0xf;
316 * lapic_get_maxlvt - get the maximum number of local vector table entries
318 int lapic_get_maxlvt(void)
322 v
= apic_read(APIC_LVR
);
324 * - we always have APIC integrated on 64bit mode
325 * - 82489DXs do not report # of LVT entries
327 return APIC_INTEGRATED(GET_APIC_VERSION(v
)) ? GET_APIC_MAXLVT(v
) : 2;
336 #define APIC_DIVISOR 1
338 #define APIC_DIVISOR 16
342 * This function sets up the local APIC timer, with a timeout of
343 * 'clocks' APIC bus clock. During calibration we actually call
344 * this function twice on the boot CPU, once with a bogus timeout
345 * value, second time for real. The other (noncalibrating) CPUs
346 * call this function only once, with the real, calibrated value.
348 * We do reads before writes even if unnecessary, to get around the
349 * P5 APIC double write bug.
351 static void __setup_APIC_LVTT(unsigned int clocks
, int oneshot
, int irqen
)
353 unsigned int lvtt_value
, tmp_value
;
355 lvtt_value
= LOCAL_TIMER_VECTOR
;
357 lvtt_value
|= APIC_LVT_TIMER_PERIODIC
;
358 if (!lapic_is_integrated())
359 lvtt_value
|= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV
);
362 lvtt_value
|= APIC_LVT_MASKED
;
364 apic_write(APIC_LVTT
, lvtt_value
);
369 tmp_value
= apic_read(APIC_TDCR
);
370 apic_write(APIC_TDCR
,
371 (tmp_value
& ~(APIC_TDR_DIV_1
| APIC_TDR_DIV_TMBASE
)) |
375 apic_write(APIC_TMICT
, clocks
/ APIC_DIVISOR
);
379 * Setup extended LVT, AMD specific (K8, family 10h)
381 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
382 * MCE interrupts are supported. Thus MCE offset must be set to 0.
384 * If mask=1, the LVT entry does not generate interrupts while mask=0
385 * enables the vector. See also the BKDGs.
388 #define APIC_EILVT_LVTOFF_MCE 0
389 #define APIC_EILVT_LVTOFF_IBS 1
391 static void setup_APIC_eilvt(u8 lvt_off
, u8 vector
, u8 msg_type
, u8 mask
)
393 unsigned long reg
= (lvt_off
<< 4) + APIC_EILVT0
;
394 unsigned int v
= (mask
<< 16) | (msg_type
<< 8) | vector
;
399 u8
setup_APIC_eilvt_mce(u8 vector
, u8 msg_type
, u8 mask
)
401 setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE
, vector
, msg_type
, mask
);
402 return APIC_EILVT_LVTOFF_MCE
;
405 u8
setup_APIC_eilvt_ibs(u8 vector
, u8 msg_type
, u8 mask
)
407 setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS
, vector
, msg_type
, mask
);
408 return APIC_EILVT_LVTOFF_IBS
;
410 EXPORT_SYMBOL_GPL(setup_APIC_eilvt_ibs
);
413 * Program the next event, relative to now
415 static int lapic_next_event(unsigned long delta
,
416 struct clock_event_device
*evt
)
418 apic_write(APIC_TMICT
, delta
);
423 * Setup the lapic timer in periodic or oneshot mode
425 static void lapic_timer_setup(enum clock_event_mode mode
,
426 struct clock_event_device
*evt
)
431 /* Lapic used as dummy for broadcast ? */
432 if (evt
->features
& CLOCK_EVT_FEAT_DUMMY
)
435 local_irq_save(flags
);
438 case CLOCK_EVT_MODE_PERIODIC
:
439 case CLOCK_EVT_MODE_ONESHOT
:
440 __setup_APIC_LVTT(calibration_result
,
441 mode
!= CLOCK_EVT_MODE_PERIODIC
, 1);
443 case CLOCK_EVT_MODE_UNUSED
:
444 case CLOCK_EVT_MODE_SHUTDOWN
:
445 v
= apic_read(APIC_LVTT
);
446 v
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
447 apic_write(APIC_LVTT
, v
);
449 case CLOCK_EVT_MODE_RESUME
:
450 /* Nothing to do here */
454 local_irq_restore(flags
);
458 * Local APIC timer broadcast function
460 static void lapic_timer_broadcast(cpumask_t mask
)
463 send_IPI_mask(mask
, LOCAL_TIMER_VECTOR
);
468 * Setup the local APIC timer for this CPU. Copy the initilized values
469 * of the boot CPU and register the clock event in the framework.
471 static void __cpuinit
setup_APIC_timer(void)
473 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
475 memcpy(levt
, &lapic_clockevent
, sizeof(*levt
));
476 levt
->cpumask
= cpumask_of_cpu(smp_processor_id());
478 clockevents_register_device(levt
);
483 * In this function we calibrate APIC bus clocks to the external
484 * timer. Unfortunately we cannot use jiffies and the timer irq
485 * to calibrate, since some later bootup code depends on getting
486 * the first irq? Ugh.
488 * We want to do the calibration only once since we
489 * want to have local timer irqs syncron. CPUs connected
490 * by the same APIC bus have the very same bus frequency.
491 * And we want to have irqs off anyways, no accidental
495 #define TICK_COUNT 100000000
497 static int __init
calibrate_APIC_clock(void)
499 unsigned apic
, apic_start
;
500 unsigned long tsc
, tsc_start
;
506 * Put whatever arbitrary (but long enough) timeout
507 * value into the APIC clock, we just want to get the
508 * counter running for calibration.
510 * No interrupt enable !
512 __setup_APIC_LVTT(250000000, 0, 0);
514 apic_start
= apic_read(APIC_TMCCT
);
515 #ifdef CONFIG_X86_PM_TIMER
516 if (apic_calibrate_pmtmr
&& pmtmr_ioport
) {
517 pmtimer_wait(5000); /* 5ms wait */
518 apic
= apic_read(APIC_TMCCT
);
519 result
= (apic_start
- apic
) * 1000L / 5;
526 apic
= apic_read(APIC_TMCCT
);
528 } while ((tsc
- tsc_start
) < TICK_COUNT
&&
529 (apic_start
- apic
) < TICK_COUNT
);
531 result
= (apic_start
- apic
) * 1000L * tsc_khz
/
537 printk(KERN_DEBUG
"APIC timer calibration result %d\n", result
);
539 printk(KERN_INFO
"Detected %d.%03d MHz APIC timer.\n",
540 result
/ 1000 / 1000, result
/ 1000 % 1000);
542 /* Calculate the scaled math multiplication factor */
543 lapic_clockevent
.mult
= div_sc(result
, NSEC_PER_SEC
,
544 lapic_clockevent
.shift
);
545 lapic_clockevent
.max_delta_ns
=
546 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent
);
547 lapic_clockevent
.min_delta_ns
=
548 clockevent_delta2ns(0xF, &lapic_clockevent
);
550 calibration_result
= (result
* APIC_DIVISOR
) / HZ
;
553 * Do a sanity check on the APIC calibration result
555 if (calibration_result
< (1000000 / HZ
)) {
557 "APIC frequency too slow, disabling apic timer\n");
566 * In this functions we calibrate APIC bus clocks to the external timer.
568 * We want to do the calibration only once since we want to have local timer
569 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
572 * This was previously done by reading the PIT/HPET and waiting for a wrap
573 * around to find out, that a tick has elapsed. I have a box, where the PIT
574 * readout is broken, so it never gets out of the wait loop again. This was
575 * also reported by others.
577 * Monitoring the jiffies value is inaccurate and the clockevents
578 * infrastructure allows us to do a simple substitution of the interrupt
581 * The calibration routine also uses the pm_timer when possible, as the PIT
582 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
583 * back to normal later in the boot process).
586 #define LAPIC_CAL_LOOPS (HZ/10)
588 static __initdata
int lapic_cal_loops
= -1;
589 static __initdata
long lapic_cal_t1
, lapic_cal_t2
;
590 static __initdata
unsigned long long lapic_cal_tsc1
, lapic_cal_tsc2
;
591 static __initdata
unsigned long lapic_cal_pm1
, lapic_cal_pm2
;
592 static __initdata
unsigned long lapic_cal_j1
, lapic_cal_j2
;
595 * Temporary interrupt handler.
597 static void __init
lapic_cal_handler(struct clock_event_device
*dev
)
599 unsigned long long tsc
= 0;
600 long tapic
= apic_read(APIC_TMCCT
);
601 unsigned long pm
= acpi_pm_read_early();
606 switch (lapic_cal_loops
++) {
608 lapic_cal_t1
= tapic
;
609 lapic_cal_tsc1
= tsc
;
611 lapic_cal_j1
= jiffies
;
614 case LAPIC_CAL_LOOPS
:
615 lapic_cal_t2
= tapic
;
616 lapic_cal_tsc2
= tsc
;
617 if (pm
< lapic_cal_pm1
)
618 pm
+= ACPI_PM_OVRRUN
;
620 lapic_cal_j2
= jiffies
;
625 static int __init
calibrate_APIC_clock(void)
627 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
628 const long pm_100ms
= PMTMR_TICKS_PER_SEC
/10;
629 const long pm_thresh
= pm_100ms
/100;
630 void (*real_handler
)(struct clock_event_device
*dev
);
631 unsigned long deltaj
;
633 int pm_referenced
= 0;
637 /* Replace the global interrupt handler */
638 real_handler
= global_clock_event
->event_handler
;
639 global_clock_event
->event_handler
= lapic_cal_handler
;
642 * Setup the APIC counter to 1e9. There is no way the lapic
643 * can underflow in the 100ms detection time frame
645 __setup_APIC_LVTT(1000000000, 0, 0);
647 /* Let the interrupts run */
650 while (lapic_cal_loops
<= LAPIC_CAL_LOOPS
)
655 /* Restore the real event handler */
656 global_clock_event
->event_handler
= real_handler
;
658 /* Build delta t1-t2 as apic timer counts down */
659 delta
= lapic_cal_t1
- lapic_cal_t2
;
660 apic_printk(APIC_VERBOSE
, "... lapic delta = %ld\n", delta
);
662 /* Check, if the PM timer is available */
663 deltapm
= lapic_cal_pm2
- lapic_cal_pm1
;
664 apic_printk(APIC_VERBOSE
, "... PM timer delta = %ld\n", deltapm
);
670 mult
= clocksource_hz2mult(PMTMR_TICKS_PER_SEC
, 22);
672 if (deltapm
> (pm_100ms
- pm_thresh
) &&
673 deltapm
< (pm_100ms
+ pm_thresh
)) {
674 apic_printk(APIC_VERBOSE
, "... PM timer result ok\n");
676 res
= (((u64
) deltapm
) * mult
) >> 22;
677 do_div(res
, 1000000);
678 printk(KERN_WARNING
"APIC calibration not consistent "
679 "with PM Timer: %ldms instead of 100ms\n",
681 /* Correct the lapic counter value */
682 res
= (((u64
) delta
) * pm_100ms
);
683 do_div(res
, deltapm
);
684 printk(KERN_INFO
"APIC delta adjusted to PM-Timer: "
685 "%lu (%ld)\n", (unsigned long) res
, delta
);
691 /* Calculate the scaled math multiplication factor */
692 lapic_clockevent
.mult
= div_sc(delta
, TICK_NSEC
* LAPIC_CAL_LOOPS
,
693 lapic_clockevent
.shift
);
694 lapic_clockevent
.max_delta_ns
=
695 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent
);
696 lapic_clockevent
.min_delta_ns
=
697 clockevent_delta2ns(0xF, &lapic_clockevent
);
699 calibration_result
= (delta
* APIC_DIVISOR
) / LAPIC_CAL_LOOPS
;
701 apic_printk(APIC_VERBOSE
, "..... delta %ld\n", delta
);
702 apic_printk(APIC_VERBOSE
, "..... mult: %ld\n", lapic_clockevent
.mult
);
703 apic_printk(APIC_VERBOSE
, "..... calibration result: %u\n",
707 delta
= (long)(lapic_cal_tsc2
- lapic_cal_tsc1
);
708 apic_printk(APIC_VERBOSE
, "..... CPU clock speed is "
710 (delta
/ LAPIC_CAL_LOOPS
) / (1000000 / HZ
),
711 (delta
/ LAPIC_CAL_LOOPS
) % (1000000 / HZ
));
714 apic_printk(APIC_VERBOSE
, "..... host bus clock speed is "
716 calibration_result
/ (1000000 / HZ
),
717 calibration_result
% (1000000 / HZ
));
720 * Do a sanity check on the APIC calibration result
722 if (calibration_result
< (1000000 / HZ
)) {
725 "APIC frequency too slow, disabling apic timer\n");
729 levt
->features
&= ~CLOCK_EVT_FEAT_DUMMY
;
731 /* We trust the pm timer based calibration */
732 if (!pm_referenced
) {
733 apic_printk(APIC_VERBOSE
, "... verify APIC timer\n");
736 * Setup the apic timer manually
738 levt
->event_handler
= lapic_cal_handler
;
739 lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC
, levt
);
740 lapic_cal_loops
= -1;
742 /* Let the interrupts run */
745 while (lapic_cal_loops
<= LAPIC_CAL_LOOPS
)
750 /* Stop the lapic timer */
751 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, levt
);
756 deltaj
= lapic_cal_j2
- lapic_cal_j1
;
757 apic_printk(APIC_VERBOSE
, "... jiffies delta = %lu\n", deltaj
);
759 /* Check, if the jiffies result is consistent */
760 if (deltaj
>= LAPIC_CAL_LOOPS
-2 && deltaj
<= LAPIC_CAL_LOOPS
+2)
761 apic_printk(APIC_VERBOSE
, "... jiffies result ok\n");
763 levt
->features
|= CLOCK_EVT_FEAT_DUMMY
;
767 if (levt
->features
& CLOCK_EVT_FEAT_DUMMY
) {
769 "APIC timer disabled due to verification failure.\n");
779 * Setup the boot APIC
781 * Calibrate and verify the result.
783 void __init
setup_boot_APIC_clock(void)
786 * The local apic timer can be disabled via the kernel
787 * commandline or from the CPU detection code. Register the lapic
788 * timer as a dummy clock event source on SMP systems, so the
789 * broadcast mechanism is used. On UP systems simply ignore it.
791 if (disable_apic_timer
) {
792 printk(KERN_INFO
"Disabling APIC timer\n");
793 /* No broadcast on UP ! */
794 if (num_possible_cpus() > 1) {
795 lapic_clockevent
.mult
= 1;
801 apic_printk(APIC_VERBOSE
, "Using local APIC timer interrupts.\n"
802 "calibrating APIC timer ...\n");
804 if (calibrate_APIC_clock()) {
805 /* No broadcast on UP ! */
806 if (num_possible_cpus() > 1)
812 * If nmi_watchdog is set to IO_APIC, we need the
813 * PIT/HPET going. Otherwise register lapic as a dummy
816 if (nmi_watchdog
!= NMI_IO_APIC
)
817 lapic_clockevent
.features
&= ~CLOCK_EVT_FEAT_DUMMY
;
819 printk(KERN_WARNING
"APIC timer registered as dummy,"
820 " due to nmi_watchdog=%d!\n", nmi_watchdog
);
822 /* Setup the lapic or request the broadcast */
826 void __cpuinit
setup_secondary_APIC_clock(void)
832 * The guts of the apic timer interrupt
834 static void local_apic_timer_interrupt(void)
836 int cpu
= smp_processor_id();
837 struct clock_event_device
*evt
= &per_cpu(lapic_events
, cpu
);
840 * Normally we should not be here till LAPIC has been initialized but
841 * in some cases like kdump, its possible that there is a pending LAPIC
842 * timer interrupt from previous kernel's context and is delivered in
843 * new kernel the moment interrupts are enabled.
845 * Interrupts are enabled early and LAPIC is setup much later, hence
846 * its possible that when we get here evt->event_handler is NULL.
847 * Check for event_handler being NULL and discard the interrupt as
850 if (!evt
->event_handler
) {
852 "Spurious LAPIC timer interrupt on cpu %d\n", cpu
);
854 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, evt
);
859 * the NMI deadlock-detector uses this.
862 add_pda(apic_timer_irqs
, 1);
864 per_cpu(irq_stat
, cpu
).apic_timer_irqs
++;
867 evt
->event_handler(evt
);
871 * Local APIC timer interrupt. This is the most natural way for doing
872 * local interrupts, but local timer interrupts can be emulated by
873 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
875 * [ if a single-CPU system runs an SMP kernel then we call the local
876 * interrupt as well. Thus we cannot inline the local irq ... ]
878 void smp_apic_timer_interrupt(struct pt_regs
*regs
)
880 struct pt_regs
*old_regs
= set_irq_regs(regs
);
883 * NOTE! We'd better ACK the irq immediately,
884 * because timer handling can be slow.
888 * update_process_times() expects us to have done irq_enter().
889 * Besides, if we don't timer interrupts ignore the global
890 * interrupt lock, which is the WrongThing (tm) to do.
896 local_apic_timer_interrupt();
899 set_irq_regs(old_regs
);
902 int setup_profiling_timer(unsigned int multiplier
)
908 * Local APIC start and shutdown
912 * clear_local_APIC - shutdown the local APIC
914 * This is called, when a CPU is disabled and before rebooting, so the state of
915 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
916 * leftovers during boot.
918 void clear_local_APIC(void)
923 /* APIC hasn't been mapped yet */
927 maxlvt
= lapic_get_maxlvt();
929 * Masking an LVT entry can trigger a local APIC error
930 * if the vector is zero. Mask LVTERR first to prevent this.
933 v
= ERROR_APIC_VECTOR
; /* any non-zero vector will do */
934 apic_write(APIC_LVTERR
, v
| APIC_LVT_MASKED
);
937 * Careful: we have to set masks only first to deassert
938 * any level-triggered sources.
940 v
= apic_read(APIC_LVTT
);
941 apic_write(APIC_LVTT
, v
| APIC_LVT_MASKED
);
942 v
= apic_read(APIC_LVT0
);
943 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
944 v
= apic_read(APIC_LVT1
);
945 apic_write(APIC_LVT1
, v
| APIC_LVT_MASKED
);
947 v
= apic_read(APIC_LVTPC
);
948 apic_write(APIC_LVTPC
, v
| APIC_LVT_MASKED
);
951 /* lets not touch this if we didn't frob it */
952 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(X86_MCE_INTEL)
954 v
= apic_read(APIC_LVTTHMR
);
955 apic_write(APIC_LVTTHMR
, v
| APIC_LVT_MASKED
);
959 * Clean APIC state for other OSs:
961 apic_write(APIC_LVTT
, APIC_LVT_MASKED
);
962 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
963 apic_write(APIC_LVT1
, APIC_LVT_MASKED
);
965 apic_write(APIC_LVTERR
, APIC_LVT_MASKED
);
967 apic_write(APIC_LVTPC
, APIC_LVT_MASKED
);
969 /* Integrated APIC (!82489DX) ? */
970 if (lapic_is_integrated()) {
972 /* Clear ESR due to Pentium errata 3AP and 11AP */
973 apic_write(APIC_ESR
, 0);
979 * disable_local_APIC - clear and disable the local APIC
981 void disable_local_APIC(void)
988 * Disable APIC (implies clearing of registers
991 value
= apic_read(APIC_SPIV
);
992 value
&= ~APIC_SPIV_APIC_ENABLED
;
993 apic_write(APIC_SPIV
, value
);
997 * When LAPIC was disabled by the BIOS and enabled by the kernel,
998 * restore the disabled state.
1000 if (enabled_via_apicbase
) {
1003 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1004 l
&= ~MSR_IA32_APICBASE_ENABLE
;
1005 wrmsr(MSR_IA32_APICBASE
, l
, h
);
1011 * If Linux enabled the LAPIC against the BIOS default disable it down before
1012 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
1013 * not power-off. Additionally clear all LVT entries before disable_local_APIC
1014 * for the case where Linux didn't enable the LAPIC.
1016 void lapic_shutdown(void)
1018 unsigned long flags
;
1023 local_irq_save(flags
);
1025 #ifdef CONFIG_X86_32
1026 if (!enabled_via_apicbase
)
1030 disable_local_APIC();
1033 local_irq_restore(flags
);
1037 * This is to verify that we're looking at a real local APIC.
1038 * Check these against your board if the CPUs aren't getting
1039 * started for no apparent reason.
1041 int __init
verify_local_APIC(void)
1043 unsigned int reg0
, reg1
;
1046 * The version register is read-only in a real APIC.
1048 reg0
= apic_read(APIC_LVR
);
1049 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg0
);
1050 apic_write(APIC_LVR
, reg0
^ APIC_LVR_MASK
);
1051 reg1
= apic_read(APIC_LVR
);
1052 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg1
);
1055 * The two version reads above should print the same
1056 * numbers. If the second one is different, then we
1057 * poke at a non-APIC.
1063 * Check if the version looks reasonably.
1065 reg1
= GET_APIC_VERSION(reg0
);
1066 if (reg1
== 0x00 || reg1
== 0xff)
1068 reg1
= lapic_get_maxlvt();
1069 if (reg1
< 0x02 || reg1
== 0xff)
1073 * The ID register is read/write in a real APIC.
1075 reg0
= apic_read(APIC_ID
);
1076 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg0
);
1077 apic_write(APIC_ID
, reg0
^ APIC_ID_MASK
);
1078 reg1
= apic_read(APIC_ID
);
1079 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg1
);
1080 apic_write(APIC_ID
, reg0
);
1081 if (reg1
!= (reg0
^ APIC_ID_MASK
))
1085 * The next two are just to see if we have sane values.
1086 * They're only really relevant if we're in Virtual Wire
1087 * compatibility mode, but most boxes are anymore.
1089 reg0
= apic_read(APIC_LVT0
);
1090 apic_printk(APIC_DEBUG
, "Getting LVT0: %x\n", reg0
);
1091 reg1
= apic_read(APIC_LVT1
);
1092 apic_printk(APIC_DEBUG
, "Getting LVT1: %x\n", reg1
);
1098 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
1100 void __init
sync_Arb_IDs(void)
1103 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
1106 if (modern_apic() || boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
)
1112 apic_wait_icr_idle();
1114 apic_printk(APIC_DEBUG
, "Synchronizing Arb IDs.\n");
1115 apic_write(APIC_ICR
, APIC_DEST_ALLINC
|
1116 APIC_INT_LEVELTRIG
| APIC_DM_INIT
);
1120 * An initial setup of the virtual wire mode.
1122 void __init
init_bsp_APIC(void)
1127 * Don't do the setup now if we have a SMP BIOS as the
1128 * through-I/O-APIC virtual wire mode might be active.
1130 if (smp_found_config
|| !cpu_has_apic
)
1134 * Do not trust the local APIC being empty at bootup.
1141 value
= apic_read(APIC_SPIV
);
1142 value
&= ~APIC_VECTOR_MASK
;
1143 value
|= APIC_SPIV_APIC_ENABLED
;
1145 #ifdef CONFIG_X86_32
1146 /* This bit is reserved on P4/Xeon and should be cleared */
1147 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
) &&
1148 (boot_cpu_data
.x86
== 15))
1149 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
1152 value
|= APIC_SPIV_FOCUS_DISABLED
;
1153 value
|= SPURIOUS_APIC_VECTOR
;
1154 apic_write(APIC_SPIV
, value
);
1157 * Set up the virtual wire mode.
1159 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
1160 value
= APIC_DM_NMI
;
1161 if (!lapic_is_integrated()) /* 82489DX */
1162 value
|= APIC_LVT_LEVEL_TRIGGER
;
1163 apic_write(APIC_LVT1
, value
);
1166 static void __cpuinit
lapic_setup_esr(void)
1168 unsigned long oldvalue
, value
, maxlvt
;
1169 if (lapic_is_integrated() && !esr_disable
) {
1172 * Something untraceable is creating bad interrupts on
1173 * secondary quads ... for the moment, just leave the
1174 * ESR disabled - we can't do anything useful with the
1175 * errors anyway - mbligh
1177 printk(KERN_INFO
"Leaving ESR disabled.\n");
1181 maxlvt
= lapic_get_maxlvt();
1182 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
1183 apic_write(APIC_ESR
, 0);
1184 oldvalue
= apic_read(APIC_ESR
);
1186 /* enables sending errors */
1187 value
= ERROR_APIC_VECTOR
;
1188 apic_write(APIC_LVTERR
, value
);
1190 * spec says clear errors after enabling vector.
1193 apic_write(APIC_ESR
, 0);
1194 value
= apic_read(APIC_ESR
);
1195 if (value
!= oldvalue
)
1196 apic_printk(APIC_VERBOSE
, "ESR value before enabling "
1197 "vector: 0x%08lx after: 0x%08lx\n",
1200 printk(KERN_INFO
"No ESR for 82489DX.\n");
1206 * setup_local_APIC - setup the local APIC
1208 void __cpuinit
setup_local_APIC(void)
1213 #ifdef CONFIG_X86_32
1214 /* Pound the ESR really hard over the head with a big hammer - mbligh */
1216 apic_write(APIC_ESR
, 0);
1217 apic_write(APIC_ESR
, 0);
1218 apic_write(APIC_ESR
, 0);
1219 apic_write(APIC_ESR
, 0);
1226 * Double-check whether this APIC is really registered.
1227 * This is meaningless in clustered apic mode, so we skip it.
1229 if (!apic_id_registered())
1233 * Intel recommends to set DFR, LDR and TPR before enabling
1234 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
1235 * document number 292116). So here it goes...
1240 * Set Task Priority to 'accept all'. We never change this
1243 value
= apic_read(APIC_TASKPRI
);
1244 value
&= ~APIC_TPRI_MASK
;
1245 apic_write(APIC_TASKPRI
, value
);
1248 * After a crash, we no longer service the interrupts and a pending
1249 * interrupt from previous kernel might still have ISR bit set.
1251 * Most probably by now CPU has serviced that pending interrupt and
1252 * it might not have done the ack_APIC_irq() because it thought,
1253 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
1254 * does not clear the ISR bit and cpu thinks it has already serivced
1255 * the interrupt. Hence a vector might get locked. It was noticed
1256 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
1258 for (i
= APIC_ISR_NR
- 1; i
>= 0; i
--) {
1259 value
= apic_read(APIC_ISR
+ i
*0x10);
1260 for (j
= 31; j
>= 0; j
--) {
1267 * Now that we are all set up, enable the APIC
1269 value
= apic_read(APIC_SPIV
);
1270 value
&= ~APIC_VECTOR_MASK
;
1274 value
|= APIC_SPIV_APIC_ENABLED
;
1276 #ifdef CONFIG_X86_32
1278 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1279 * certain networking cards. If high frequency interrupts are
1280 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1281 * entry is masked/unmasked at a high rate as well then sooner or
1282 * later IOAPIC line gets 'stuck', no more interrupts are received
1283 * from the device. If focus CPU is disabled then the hang goes
1286 * [ This bug can be reproduced easily with a level-triggered
1287 * PCI Ne2000 networking cards and PII/PIII processors, dual
1291 * Actually disabling the focus CPU check just makes the hang less
1292 * frequent as it makes the interrupt distributon model be more
1293 * like LRU than MRU (the short-term load is more even across CPUs).
1294 * See also the comment in end_level_ioapic_irq(). --macro
1298 * - enable focus processor (bit==0)
1299 * - 64bit mode always use processor focus
1300 * so no need to set it
1302 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
1306 * Set spurious IRQ vector
1308 value
|= SPURIOUS_APIC_VECTOR
;
1309 apic_write(APIC_SPIV
, value
);
1312 * Set up LVT0, LVT1:
1314 * set up through-local-APIC on the BP's LINT0. This is not
1315 * strictly necessary in pure symmetric-IO mode, but sometimes
1316 * we delegate interrupts to the 8259A.
1319 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1321 value
= apic_read(APIC_LVT0
) & APIC_LVT_MASKED
;
1322 if (!smp_processor_id() && (pic_mode
|| !value
)) {
1323 value
= APIC_DM_EXTINT
;
1324 apic_printk(APIC_VERBOSE
, "enabled ExtINT on CPU#%d\n",
1325 smp_processor_id());
1327 value
= APIC_DM_EXTINT
| APIC_LVT_MASKED
;
1328 apic_printk(APIC_VERBOSE
, "masked ExtINT on CPU#%d\n",
1329 smp_processor_id());
1331 apic_write(APIC_LVT0
, value
);
1334 * only the BP should see the LINT1 NMI signal, obviously.
1336 if (!smp_processor_id())
1337 value
= APIC_DM_NMI
;
1339 value
= APIC_DM_NMI
| APIC_LVT_MASKED
;
1340 if (!lapic_is_integrated()) /* 82489DX */
1341 value
|= APIC_LVT_LEVEL_TRIGGER
;
1342 apic_write(APIC_LVT1
, value
);
1347 void __cpuinit
end_local_APIC_setup(void)
1351 #ifdef CONFIG_X86_32
1354 /* Disable the local apic timer */
1355 value
= apic_read(APIC_LVTT
);
1356 value
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
1357 apic_write(APIC_LVTT
, value
);
1361 setup_apic_nmi_watchdog(NULL
);
1366 void check_x2apic(void)
1370 rdmsr(MSR_IA32_APICBASE
, msr
, msr2
);
1372 if (msr
& X2APIC_ENABLE
) {
1373 printk("x2apic enabled by BIOS, switching to x2apic ops\n");
1374 x2apic_preenabled
= x2apic
= 1;
1375 apic_ops
= &x2apic_ops
;
1379 void enable_x2apic(void)
1383 rdmsr(MSR_IA32_APICBASE
, msr
, msr2
);
1384 if (!(msr
& X2APIC_ENABLE
)) {
1385 printk("Enabling x2apic\n");
1386 wrmsr(MSR_IA32_APICBASE
, msr
| X2APIC_ENABLE
, 0);
1390 void enable_IR_x2apic(void)
1392 #ifdef CONFIG_INTR_REMAP
1394 unsigned long flags
;
1396 if (!cpu_has_x2apic
)
1399 if (!x2apic_preenabled
&& disable_x2apic
) {
1401 "Skipped enabling x2apic and Interrupt-remapping "
1402 "because of nox2apic\n");
1406 if (x2apic_preenabled
&& disable_x2apic
)
1407 panic("Bios already enabled x2apic, can't enforce nox2apic");
1409 if (!x2apic_preenabled
&& skip_ioapic_setup
) {
1411 "Skipped enabling x2apic and Interrupt-remapping "
1412 "because of skipping io-apic setup\n");
1416 ret
= dmar_table_init();
1419 "dmar_table_init() failed with %d:\n", ret
);
1421 if (x2apic_preenabled
)
1422 panic("x2apic enabled by bios. But IR enabling failed");
1425 "Not enabling x2apic,Intr-remapping\n");
1429 local_irq_save(flags
);
1431 save_mask_IO_APIC_setup();
1433 ret
= enable_intr_remapping(1);
1435 if (ret
&& x2apic_preenabled
) {
1436 local_irq_restore(flags
);
1437 panic("x2apic enabled by bios. But IR enabling failed");
1445 apic_ops
= &x2apic_ops
;
1451 * IR enabling failed
1453 restore_IO_APIC_setup();
1455 reinit_intr_remapped_IO_APIC(x2apic_preenabled
);
1458 local_irq_restore(flags
);
1461 if (!x2apic_preenabled
)
1463 "Enabled x2apic and interrupt-remapping\n");
1466 "Enabled Interrupt-remapping\n");
1469 "Failed to enable Interrupt-remapping and x2apic\n");
1471 if (!cpu_has_x2apic
)
1474 if (x2apic_preenabled
)
1475 panic("x2apic enabled prior OS handover,"
1476 " enable CONFIG_INTR_REMAP");
1478 printk(KERN_INFO
"Enable CONFIG_INTR_REMAP for enabling intr-remapping "
1484 #endif /* HAVE_X2APIC */
1486 #ifdef CONFIG_X86_64
1488 * Detect and enable local APICs on non-SMP boards.
1489 * Original code written by Keir Fraser.
1490 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1491 * not correctly set up (usually the APIC timer won't work etc.)
1493 static int __init
detect_init_APIC(void)
1495 if (!cpu_has_apic
) {
1496 printk(KERN_INFO
"No local APIC present\n");
1500 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
1501 boot_cpu_physical_apicid
= 0;
1506 * Detect and initialize APIC
1508 static int __init
detect_init_APIC(void)
1512 /* Disabled by kernel option? */
1516 switch (boot_cpu_data
.x86_vendor
) {
1517 case X86_VENDOR_AMD
:
1518 if ((boot_cpu_data
.x86
== 6 && boot_cpu_data
.x86_model
> 1) ||
1519 (boot_cpu_data
.x86
== 15))
1522 case X86_VENDOR_INTEL
:
1523 if (boot_cpu_data
.x86
== 6 || boot_cpu_data
.x86
== 15 ||
1524 (boot_cpu_data
.x86
== 5 && cpu_has_apic
))
1531 if (!cpu_has_apic
) {
1533 * Over-ride BIOS and try to enable the local APIC only if
1534 * "lapic" specified.
1536 if (!force_enable_local_apic
) {
1537 printk(KERN_INFO
"Local APIC disabled by BIOS -- "
1538 "you can enable it with \"lapic\"\n");
1542 * Some BIOSes disable the local APIC in the APIC_BASE
1543 * MSR. This can only be done in software for Intel P6 or later
1544 * and AMD K7 (Model > 1) or later.
1546 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1547 if (!(l
& MSR_IA32_APICBASE_ENABLE
)) {
1549 "Local APIC disabled by BIOS -- reenabling.\n");
1550 l
&= ~MSR_IA32_APICBASE_BASE
;
1551 l
|= MSR_IA32_APICBASE_ENABLE
| APIC_DEFAULT_PHYS_BASE
;
1552 wrmsr(MSR_IA32_APICBASE
, l
, h
);
1553 enabled_via_apicbase
= 1;
1557 * The APIC feature bit should now be enabled
1560 features
= cpuid_edx(1);
1561 if (!(features
& (1 << X86_FEATURE_APIC
))) {
1562 printk(KERN_WARNING
"Could not enable APIC!\n");
1565 set_cpu_cap(&boot_cpu_data
, X86_FEATURE_APIC
);
1566 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
1568 /* The BIOS may have set up the APIC at some other address */
1569 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1570 if (l
& MSR_IA32_APICBASE_ENABLE
)
1571 mp_lapic_addr
= l
& MSR_IA32_APICBASE_BASE
;
1573 printk(KERN_INFO
"Found and enabled local APIC!\n");
1580 printk(KERN_INFO
"No local APIC present or hardware disabled\n");
1585 #ifdef CONFIG_X86_64
1586 void __init
early_init_lapic_mapping(void)
1588 unsigned long phys_addr
;
1591 * If no local APIC can be found then go out
1592 * : it means there is no mpatable and MADT
1594 if (!smp_found_config
)
1597 phys_addr
= mp_lapic_addr
;
1599 set_fixmap_nocache(FIX_APIC_BASE
, phys_addr
);
1600 apic_printk(APIC_VERBOSE
, "mapped APIC to %16lx (%16lx)\n",
1601 APIC_BASE
, phys_addr
);
1604 * Fetch the APIC ID of the BSP in case we have a
1605 * default configuration (or the MP table is broken).
1607 boot_cpu_physical_apicid
= read_apic_id();
1612 * init_apic_mappings - initialize APIC mappings
1614 void __init
init_apic_mappings(void)
1618 boot_cpu_physical_apicid
= read_apic_id();
1624 * If no local APIC can be found then set up a fake all
1625 * zeroes page to simulate the local APIC and another
1626 * one for the IO-APIC.
1628 if (!smp_found_config
&& detect_init_APIC()) {
1629 apic_phys
= (unsigned long) alloc_bootmem_pages(PAGE_SIZE
);
1630 apic_phys
= __pa(apic_phys
);
1632 apic_phys
= mp_lapic_addr
;
1634 set_fixmap_nocache(FIX_APIC_BASE
, apic_phys
);
1635 apic_printk(APIC_VERBOSE
, "mapped APIC to %16lx (%16lx)\n",
1636 APIC_BASE
, apic_phys
);
1639 * Fetch the APIC ID of the BSP in case we have a
1640 * default configuration (or the MP table is broken).
1642 if (boot_cpu_physical_apicid
== -1U)
1643 boot_cpu_physical_apicid
= read_apic_id();
1647 * This initializes the IO-APIC and APIC hardware if this is
1650 int apic_version
[MAX_APICS
];
1652 int __init
APIC_init_uniprocessor(void)
1654 #ifdef CONFIG_X86_64
1656 printk(KERN_INFO
"Apic disabled\n");
1659 if (!cpu_has_apic
) {
1661 printk(KERN_INFO
"Apic disabled by BIOS\n");
1665 if (!smp_found_config
&& !cpu_has_apic
)
1669 * Complain if the BIOS pretends there is one.
1671 if (!cpu_has_apic
&&
1672 APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
])) {
1673 printk(KERN_ERR
"BIOS bug, local APIC #%d not detected!...\n",
1674 boot_cpu_physical_apicid
);
1675 clear_cpu_cap(&boot_cpu_data
, X86_FEATURE_APIC
);
1683 #ifdef CONFIG_X86_64
1684 setup_apic_routing();
1687 verify_local_APIC();
1690 #ifdef CONFIG_X86_64
1691 apic_write(APIC_ID
, SET_APIC_ID(boot_cpu_physical_apicid
));
1694 * Hack: In case of kdump, after a crash, kernel might be booting
1695 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
1696 * might be zero if read from MP tables. Get it from LAPIC.
1698 # ifdef CONFIG_CRASH_DUMP
1699 boot_cpu_physical_apicid
= read_apic_id();
1702 physid_set_mask_of_physid(boot_cpu_physical_apicid
, &phys_cpu_present_map
);
1705 #ifdef CONFIG_X86_64
1707 * Now enable IO-APICs, actually call clear_IO_APIC
1708 * We need clear_IO_APIC before enabling vector on BP
1710 if (!skip_ioapic_setup
&& nr_ioapics
)
1714 #ifdef CONFIG_X86_IO_APIC
1715 if (!smp_found_config
|| skip_ioapic_setup
|| !nr_ioapics
)
1717 localise_nmi_watchdog();
1718 end_local_APIC_setup();
1720 #ifdef CONFIG_X86_IO_APIC
1721 if (smp_found_config
&& !skip_ioapic_setup
&& nr_ioapics
)
1723 # ifdef CONFIG_X86_64
1729 #ifdef CONFIG_X86_64
1730 setup_boot_APIC_clock();
1731 check_nmi_watchdog();
1740 * Local APIC interrupts
1744 * This interrupt should _never_ happen with our APIC/SMP architecture
1746 #ifdef CONFIG_X86_64
1747 asmlinkage
void smp_spurious_interrupt(void)
1749 void smp_spurious_interrupt(struct pt_regs
*regs
)
1754 #ifdef CONFIG_X86_64
1759 * Check if this really is a spurious interrupt and ACK it
1760 * if it is a vectored one. Just in case...
1761 * Spurious interrupts should not be ACKed.
1763 v
= apic_read(APIC_ISR
+ ((SPURIOUS_APIC_VECTOR
& ~0x1f) >> 1));
1764 if (v
& (1 << (SPURIOUS_APIC_VECTOR
& 0x1f)))
1767 #ifdef CONFIG_X86_64
1768 add_pda(irq_spurious_count
, 1);
1770 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1771 printk(KERN_INFO
"spurious APIC interrupt on CPU#%d, "
1772 "should never happen.\n", smp_processor_id());
1773 __get_cpu_var(irq_stat
).irq_spurious_count
++;
1779 * This interrupt should never happen with our APIC/SMP architecture
1781 #ifdef CONFIG_X86_64
1782 asmlinkage
void smp_error_interrupt(void)
1784 void smp_error_interrupt(struct pt_regs
*regs
)
1789 #ifdef CONFIG_X86_64
1793 /* First tickle the hardware, only then report what went on. -- REW */
1794 v
= apic_read(APIC_ESR
);
1795 apic_write(APIC_ESR
, 0);
1796 v1
= apic_read(APIC_ESR
);
1798 atomic_inc(&irq_err_count
);
1800 /* Here is what the APIC error bits mean:
1803 2: Send accept error
1804 3: Receive accept error
1806 5: Send illegal vector
1807 6: Received illegal vector
1808 7: Illegal register address
1810 printk(KERN_DEBUG
"APIC error on CPU%d: %02x(%02x)\n",
1811 smp_processor_id(), v
, v1
);
1816 * connect_bsp_APIC - attach the APIC to the interrupt system
1818 void __init
connect_bsp_APIC(void)
1820 #ifdef CONFIG_X86_32
1823 * Do not trust the local APIC being empty at bootup.
1827 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
1828 * local APIC to INT and NMI lines.
1830 apic_printk(APIC_VERBOSE
, "leaving PIC mode, "
1831 "enabling APIC mode.\n");
1840 * disconnect_bsp_APIC - detach the APIC from the interrupt system
1841 * @virt_wire_setup: indicates, whether virtual wire mode is selected
1843 * Virtual wire mode is necessary to deliver legacy interrupts even when the
1846 void disconnect_bsp_APIC(int virt_wire_setup
)
1850 #ifdef CONFIG_X86_32
1853 * Put the board back into PIC mode (has an effect only on
1854 * certain older boards). Note that APIC interrupts, including
1855 * IPIs, won't work beyond this point! The only exception are
1858 apic_printk(APIC_VERBOSE
, "disabling APIC mode, "
1859 "entering PIC mode.\n");
1866 /* Go back to Virtual Wire compatibility mode */
1868 /* For the spurious interrupt use vector F, and enable it */
1869 value
= apic_read(APIC_SPIV
);
1870 value
&= ~APIC_VECTOR_MASK
;
1871 value
|= APIC_SPIV_APIC_ENABLED
;
1873 apic_write(APIC_SPIV
, value
);
1875 if (!virt_wire_setup
) {
1877 * For LVT0 make it edge triggered, active high,
1878 * external and enabled
1880 value
= apic_read(APIC_LVT0
);
1881 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1882 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1883 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1884 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1885 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_EXTINT
);
1886 apic_write(APIC_LVT0
, value
);
1889 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
1893 * For LVT1 make it edge triggered, active high,
1896 value
= apic_read(APIC_LVT1
);
1897 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1898 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1899 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1900 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1901 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_NMI
);
1902 apic_write(APIC_LVT1
, value
);
1905 void __cpuinit
generic_processor_info(int apicid
, int version
)
1913 if (version
== 0x0) {
1914 printk(KERN_WARNING
"BIOS bug, APIC version is 0 for CPU#%d! "
1915 "fixing up to 0x10. (tell your hw vendor)\n",
1919 apic_version
[apicid
] = version
;
1921 if (num_processors
>= NR_CPUS
) {
1922 printk(KERN_WARNING
"WARNING: NR_CPUS limit of %i reached."
1923 " Processor ignored.\n", NR_CPUS
);
1928 cpus_complement(tmp_map
, cpu_present_map
);
1929 cpu
= first_cpu(tmp_map
);
1931 physid_set(apicid
, phys_cpu_present_map
);
1932 if (apicid
== boot_cpu_physical_apicid
) {
1934 * x86_bios_cpu_apicid is required to have processors listed
1935 * in same order as logical cpu numbers. Hence the first
1936 * entry is BSP, and so on.
1940 if (apicid
> max_physical_apicid
)
1941 max_physical_apicid
= apicid
;
1943 #ifdef CONFIG_X86_32
1945 * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y
1946 * but we need to work other dependencies like SMP_SUSPEND etc
1947 * before this can be done without some confusion.
1948 * if (CPU_HOTPLUG_ENABLED || num_processors > 8)
1949 * - Ashok Raj <ashok.raj@intel.com>
1951 if (max_physical_apicid
>= 8) {
1952 switch (boot_cpu_data
.x86_vendor
) {
1953 case X86_VENDOR_INTEL
:
1954 if (!APIC_XAPIC(version
)) {
1958 /* If P4 and above fall through */
1959 case X86_VENDOR_AMD
:
1965 #if defined(CONFIG_X86_SMP) || defined(CONFIG_X86_64)
1966 /* are we being called early in kernel startup? */
1967 if (early_per_cpu_ptr(x86_cpu_to_apicid
)) {
1968 u16
*cpu_to_apicid
= early_per_cpu_ptr(x86_cpu_to_apicid
);
1969 u16
*bios_cpu_apicid
= early_per_cpu_ptr(x86_bios_cpu_apicid
);
1971 cpu_to_apicid
[cpu
] = apicid
;
1972 bios_cpu_apicid
[cpu
] = apicid
;
1974 per_cpu(x86_cpu_to_apicid
, cpu
) = apicid
;
1975 per_cpu(x86_bios_cpu_apicid
, cpu
) = apicid
;
1979 cpu_set(cpu
, cpu_possible_map
);
1980 cpu_set(cpu
, cpu_present_map
);
1983 #ifdef CONFIG_X86_64
1984 int hard_smp_processor_id(void)
1986 return read_apic_id();
1997 * 'active' is true if the local APIC was enabled by us and
1998 * not the BIOS; this signifies that we are also responsible
1999 * for disabling it before entering apm/acpi suspend
2002 /* r/w apic fields */
2003 unsigned int apic_id
;
2004 unsigned int apic_taskpri
;
2005 unsigned int apic_ldr
;
2006 unsigned int apic_dfr
;
2007 unsigned int apic_spiv
;
2008 unsigned int apic_lvtt
;
2009 unsigned int apic_lvtpc
;
2010 unsigned int apic_lvt0
;
2011 unsigned int apic_lvt1
;
2012 unsigned int apic_lvterr
;
2013 unsigned int apic_tmict
;
2014 unsigned int apic_tdcr
;
2015 unsigned int apic_thmr
;
2018 static int lapic_suspend(struct sys_device
*dev
, pm_message_t state
)
2020 unsigned long flags
;
2023 if (!apic_pm_state
.active
)
2026 maxlvt
= lapic_get_maxlvt();
2028 apic_pm_state
.apic_id
= apic_read(APIC_ID
);
2029 apic_pm_state
.apic_taskpri
= apic_read(APIC_TASKPRI
);
2030 apic_pm_state
.apic_ldr
= apic_read(APIC_LDR
);
2031 apic_pm_state
.apic_dfr
= apic_read(APIC_DFR
);
2032 apic_pm_state
.apic_spiv
= apic_read(APIC_SPIV
);
2033 apic_pm_state
.apic_lvtt
= apic_read(APIC_LVTT
);
2035 apic_pm_state
.apic_lvtpc
= apic_read(APIC_LVTPC
);
2036 apic_pm_state
.apic_lvt0
= apic_read(APIC_LVT0
);
2037 apic_pm_state
.apic_lvt1
= apic_read(APIC_LVT1
);
2038 apic_pm_state
.apic_lvterr
= apic_read(APIC_LVTERR
);
2039 apic_pm_state
.apic_tmict
= apic_read(APIC_TMICT
);
2040 apic_pm_state
.apic_tdcr
= apic_read(APIC_TDCR
);
2041 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
2043 apic_pm_state
.apic_thmr
= apic_read(APIC_LVTTHMR
);
2046 local_irq_save(flags
);
2047 disable_local_APIC();
2048 local_irq_restore(flags
);
2052 static int lapic_resume(struct sys_device
*dev
)
2055 unsigned long flags
;
2058 if (!apic_pm_state
.active
)
2061 maxlvt
= lapic_get_maxlvt();
2063 local_irq_save(flags
);
2072 * Make sure the APICBASE points to the right address
2074 * FIXME! This will be wrong if we ever support suspend on
2075 * SMP! We'll need to do this as part of the CPU restore!
2077 rdmsr(MSR_IA32_APICBASE
, l
, h
);
2078 l
&= ~MSR_IA32_APICBASE_BASE
;
2079 l
|= MSR_IA32_APICBASE_ENABLE
| mp_lapic_addr
;
2080 wrmsr(MSR_IA32_APICBASE
, l
, h
);
2083 apic_write(APIC_LVTERR
, ERROR_APIC_VECTOR
| APIC_LVT_MASKED
);
2084 apic_write(APIC_ID
, apic_pm_state
.apic_id
);
2085 apic_write(APIC_DFR
, apic_pm_state
.apic_dfr
);
2086 apic_write(APIC_LDR
, apic_pm_state
.apic_ldr
);
2087 apic_write(APIC_TASKPRI
, apic_pm_state
.apic_taskpri
);
2088 apic_write(APIC_SPIV
, apic_pm_state
.apic_spiv
);
2089 apic_write(APIC_LVT0
, apic_pm_state
.apic_lvt0
);
2090 apic_write(APIC_LVT1
, apic_pm_state
.apic_lvt1
);
2091 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
2093 apic_write(APIC_LVTTHMR
, apic_pm_state
.apic_thmr
);
2096 apic_write(APIC_LVTPC
, apic_pm_state
.apic_lvtpc
);
2097 apic_write(APIC_LVTT
, apic_pm_state
.apic_lvtt
);
2098 apic_write(APIC_TDCR
, apic_pm_state
.apic_tdcr
);
2099 apic_write(APIC_TMICT
, apic_pm_state
.apic_tmict
);
2100 apic_write(APIC_ESR
, 0);
2101 apic_read(APIC_ESR
);
2102 apic_write(APIC_LVTERR
, apic_pm_state
.apic_lvterr
);
2103 apic_write(APIC_ESR
, 0);
2104 apic_read(APIC_ESR
);
2106 local_irq_restore(flags
);
2112 * This device has no shutdown method - fully functioning local APICs
2113 * are needed on every CPU up until machine_halt/restart/poweroff.
2116 static struct sysdev_class lapic_sysclass
= {
2118 .resume
= lapic_resume
,
2119 .suspend
= lapic_suspend
,
2122 static struct sys_device device_lapic
= {
2124 .cls
= &lapic_sysclass
,
2127 static void __cpuinit
apic_pm_activate(void)
2129 apic_pm_state
.active
= 1;
2132 static int __init
init_lapic_sysfs(void)
2138 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
2140 error
= sysdev_class_register(&lapic_sysclass
);
2142 error
= sysdev_register(&device_lapic
);
2145 device_initcall(init_lapic_sysfs
);
2147 #else /* CONFIG_PM */
2149 static void apic_pm_activate(void) { }
2151 #endif /* CONFIG_PM */
2153 #ifdef CONFIG_X86_64
2155 * apic_is_clustered_box() -- Check if we can expect good TSC
2157 * Thus far, the major user of this is IBM's Summit2 series:
2159 * Clustered boxes may have unsynced TSC problems if they are
2160 * multi-chassis. Use available data to take a good guess.
2161 * If in doubt, go HPET.
2163 __cpuinit
int apic_is_clustered_box(void)
2165 int i
, clusters
, zeros
;
2167 u16
*bios_cpu_apicid
;
2168 DECLARE_BITMAP(clustermap
, NUM_APIC_CLUSTERS
);
2171 * there is not this kind of box with AMD CPU yet.
2172 * Some AMD box with quadcore cpu and 8 sockets apicid
2173 * will be [4, 0x23] or [8, 0x27] could be thought to
2174 * vsmp box still need checking...
2176 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
) && !is_vsmp_box())
2179 bios_cpu_apicid
= early_per_cpu_ptr(x86_bios_cpu_apicid
);
2180 bitmap_zero(clustermap
, NUM_APIC_CLUSTERS
);
2182 for (i
= 0; i
< NR_CPUS
; i
++) {
2183 /* are we being called early in kernel startup? */
2184 if (bios_cpu_apicid
) {
2185 id
= bios_cpu_apicid
[i
];
2187 else if (i
< nr_cpu_ids
) {
2189 id
= per_cpu(x86_bios_cpu_apicid
, i
);
2196 if (id
!= BAD_APICID
)
2197 __set_bit(APIC_CLUSTERID(id
), clustermap
);
2200 /* Problem: Partially populated chassis may not have CPUs in some of
2201 * the APIC clusters they have been allocated. Only present CPUs have
2202 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap.
2203 * Since clusters are allocated sequentially, count zeros only if
2204 * they are bounded by ones.
2208 for (i
= 0; i
< NUM_APIC_CLUSTERS
; i
++) {
2209 if (test_bit(i
, clustermap
)) {
2210 clusters
+= 1 + zeros
;
2216 /* ScaleMP vSMPowered boxes have one cluster per board and TSCs are
2217 * not guaranteed to be synced between boards
2219 if (is_vsmp_box() && clusters
> 1)
2223 * If clusters > 2, then should be multi-chassis.
2224 * May have to revisit this when multi-core + hyperthreaded CPUs come
2225 * out, but AFAIK this will work even for them.
2227 return (clusters
> 2);
2232 * APIC command line parameters
2234 static int __init
setup_disableapic(char *arg
)
2237 setup_clear_cpu_cap(X86_FEATURE_APIC
);
2240 early_param("disableapic", setup_disableapic
);
2242 /* same as disableapic, for compatibility */
2243 static int __init
setup_nolapic(char *arg
)
2245 return setup_disableapic(arg
);
2247 early_param("nolapic", setup_nolapic
);
2249 static int __init
parse_lapic_timer_c2_ok(char *arg
)
2251 local_apic_timer_c2_ok
= 1;
2254 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok
);
2256 static int __init
parse_disable_apic_timer(char *arg
)
2258 disable_apic_timer
= 1;
2261 early_param("noapictimer", parse_disable_apic_timer
);
2263 static int __init
parse_nolapic_timer(char *arg
)
2265 disable_apic_timer
= 1;
2268 early_param("nolapic_timer", parse_nolapic_timer
);
2270 static int __init
apic_set_verbosity(char *arg
)
2273 #ifdef CONFIG_X86_64
2274 skip_ioapic_setup
= 0;
2280 if (strcmp("debug", arg
) == 0)
2281 apic_verbosity
= APIC_DEBUG
;
2282 else if (strcmp("verbose", arg
) == 0)
2283 apic_verbosity
= APIC_VERBOSE
;
2285 printk(KERN_WARNING
"APIC Verbosity level %s not recognised"
2286 " use apic=verbose or apic=debug\n", arg
);
2292 early_param("apic", apic_set_verbosity
);
2294 static int __init
lapic_insert_resource(void)
2299 /* Put local APIC into the resource map. */
2300 lapic_resource
.start
= apic_phys
;
2301 lapic_resource
.end
= lapic_resource
.start
+ PAGE_SIZE
- 1;
2302 insert_resource(&iomem_resource
, &lapic_resource
);
2308 * need call insert after e820_reserve_resources()
2309 * that is using request_resource
2311 late_initcall(lapic_insert_resource
);