2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/bootmem.h>
22 #include <linux/interrupt.h>
23 #include <linux/mc146818rtc.h>
24 #include <linux/kernel_stat.h>
25 #include <linux/sysdev.h>
26 #include <linux/ioport.h>
27 #include <linux/clockchips.h>
28 #include <linux/acpi_pmtmr.h>
29 #include <linux/module.h>
30 #include <linux/dmar.h>
32 #include <asm/atomic.h>
35 #include <asm/mpspec.h>
37 #include <asm/pgalloc.h>
40 #include <asm/proto.h>
41 #include <asm/timex.h>
43 #include <asm/i8259.h>
46 #include <mach_apic.h>
48 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
49 static int disable_apic_timer __cpuinitdata
;
50 static int apic_calibrate_pmtmr __initdata
;
55 /* x2apic enabled before OS handover */
56 int x2apic_preenabled
;
58 /* Local APIC timer works in C2 */
59 int local_apic_timer_c2_ok
;
60 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok
);
63 * Debug level, exported for io_apic.c
65 unsigned int apic_verbosity
;
67 /* Have we found an MP table */
70 static struct resource lapic_resource
= {
72 .flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
,
75 static unsigned int calibration_result
;
77 static int lapic_next_event(unsigned long delta
,
78 struct clock_event_device
*evt
);
79 static void lapic_timer_setup(enum clock_event_mode mode
,
80 struct clock_event_device
*evt
);
81 static void lapic_timer_broadcast(cpumask_t mask
);
82 static void apic_pm_activate(void);
84 static struct clock_event_device lapic_clockevent
= {
86 .features
= CLOCK_EVT_FEAT_PERIODIC
| CLOCK_EVT_FEAT_ONESHOT
87 | CLOCK_EVT_FEAT_C3STOP
| CLOCK_EVT_FEAT_DUMMY
,
89 .set_mode
= lapic_timer_setup
,
90 .set_next_event
= lapic_next_event
,
91 .broadcast
= lapic_timer_broadcast
,
95 static DEFINE_PER_CPU(struct clock_event_device
, lapic_events
);
97 static unsigned long apic_phys
;
99 unsigned long mp_lapic_addr
;
101 unsigned int __cpuinitdata maxcpus
= NR_CPUS
;
103 * Get the LAPIC version
105 static inline int lapic_get_version(void)
107 return GET_APIC_VERSION(apic_read(APIC_LVR
));
111 * Check, if the APIC is integrated or a seperate chip
113 static inline int lapic_is_integrated(void)
119 * Check, whether this is a modern or a first generation APIC
121 static int modern_apic(void)
123 /* AMD systems use old APIC versions, so check the CPU */
124 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
&&
125 boot_cpu_data
.x86
>= 0xf)
127 return lapic_get_version() >= 0x14;
130 void xapic_wait_icr_idle(void)
132 while (apic_read(APIC_ICR
) & APIC_ICR_BUSY
)
136 u32
safe_xapic_wait_icr_idle(void)
143 send_status
= apic_read(APIC_ICR
) & APIC_ICR_BUSY
;
147 } while (timeout
++ < 1000);
152 void xapic_icr_write(u32 low
, u32 id
)
154 apic_write(APIC_ICR2
, SET_APIC_DEST_FIELD(id
));
155 apic_write(APIC_ICR
, low
);
158 u64
xapic_icr_read(void)
162 icr2
= apic_read(APIC_ICR2
);
163 icr1
= apic_read(APIC_ICR
);
165 return (icr1
| ((u64
)icr2
<< 32));
168 static struct apic_ops xapic_ops
= {
169 .read
= native_apic_mem_read
,
170 .write
= native_apic_mem_write
,
171 .icr_read
= xapic_icr_read
,
172 .icr_write
= xapic_icr_write
,
173 .wait_icr_idle
= xapic_wait_icr_idle
,
174 .safe_wait_icr_idle
= safe_xapic_wait_icr_idle
,
177 struct apic_ops __read_mostly
*apic_ops
= &xapic_ops
;
179 EXPORT_SYMBOL_GPL(apic_ops
);
181 static void x2apic_wait_icr_idle(void)
183 /* no need to wait for icr idle in x2apic */
187 static u32
safe_x2apic_wait_icr_idle(void)
189 /* no need to wait for icr idle in x2apic */
193 void x2apic_icr_write(u32 low
, u32 id
)
195 wrmsrl(APIC_BASE_MSR
+ (APIC_ICR
>> 4), ((__u64
) id
) << 32 | low
);
198 u64
x2apic_icr_read(void)
202 rdmsrl(APIC_BASE_MSR
+ (APIC_ICR
>> 4), val
);
206 static struct apic_ops x2apic_ops
= {
207 .read
= native_apic_msr_read
,
208 .write
= native_apic_msr_write
,
209 .icr_read
= x2apic_icr_read
,
210 .icr_write
= x2apic_icr_write
,
211 .wait_icr_idle
= x2apic_wait_icr_idle
,
212 .safe_wait_icr_idle
= safe_x2apic_wait_icr_idle
,
216 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
218 void __cpuinit
enable_NMI_through_LVT0(void)
222 /* unmask and set to NMI */
225 /* Level triggered for 82489DX (32bit mode) */
226 if (!lapic_is_integrated())
227 v
|= APIC_LVT_LEVEL_TRIGGER
;
229 apic_write(APIC_LVT0
, v
);
233 * lapic_get_maxlvt - get the maximum number of local vector table entries
235 int lapic_get_maxlvt(void)
239 v
= apic_read(APIC_LVR
);
241 * - we always have APIC integrated on 64bit mode
242 * - 82489DXs do not report # of LVT entries
244 return APIC_INTEGRATED(GET_APIC_VERSION(v
)) ? GET_APIC_MAXLVT(v
) : 2;
247 /* Clock divisor is set to 1 */
248 #define APIC_DIVISOR 1
251 * This function sets up the local APIC timer, with a timeout of
252 * 'clocks' APIC bus clock. During calibration we actually call
253 * this function twice on the boot CPU, once with a bogus timeout
254 * value, second time for real. The other (noncalibrating) CPUs
255 * call this function only once, with the real, calibrated value.
257 * We do reads before writes even if unnecessary, to get around the
258 * P5 APIC double write bug.
261 static void __setup_APIC_LVTT(unsigned int clocks
, int oneshot
, int irqen
)
263 unsigned int lvtt_value
, tmp_value
;
265 lvtt_value
= LOCAL_TIMER_VECTOR
;
267 lvtt_value
|= APIC_LVT_TIMER_PERIODIC
;
268 if (!lapic_is_integrated())
269 lvtt_value
|= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV
);
272 lvtt_value
|= APIC_LVT_MASKED
;
274 apic_write(APIC_LVTT
, lvtt_value
);
279 tmp_value
= apic_read(APIC_TDCR
);
280 apic_write(APIC_TDCR
, (tmp_value
281 & ~(APIC_TDR_DIV_1
| APIC_TDR_DIV_TMBASE
))
285 apic_write(APIC_TMICT
, clocks
/ APIC_DIVISOR
);
289 * Setup extended LVT, AMD specific (K8, family 10h)
291 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
292 * MCE interrupts are supported. Thus MCE offset must be set to 0.
295 #define APIC_EILVT_LVTOFF_MCE 0
296 #define APIC_EILVT_LVTOFF_IBS 1
298 static void setup_APIC_eilvt(u8 lvt_off
, u8 vector
, u8 msg_type
, u8 mask
)
300 unsigned long reg
= (lvt_off
<< 4) + APIC_EILVT0
;
301 unsigned int v
= (mask
<< 16) | (msg_type
<< 8) | vector
;
306 u8
setup_APIC_eilvt_mce(u8 vector
, u8 msg_type
, u8 mask
)
308 setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE
, vector
, msg_type
, mask
);
309 return APIC_EILVT_LVTOFF_MCE
;
312 u8
setup_APIC_eilvt_ibs(u8 vector
, u8 msg_type
, u8 mask
)
314 setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS
, vector
, msg_type
, mask
);
315 return APIC_EILVT_LVTOFF_IBS
;
319 * Program the next event, relative to now
321 static int lapic_next_event(unsigned long delta
,
322 struct clock_event_device
*evt
)
324 apic_write(APIC_TMICT
, delta
);
329 * Setup the lapic timer in periodic or oneshot mode
331 static void lapic_timer_setup(enum clock_event_mode mode
,
332 struct clock_event_device
*evt
)
337 /* Lapic used as dummy for broadcast ? */
338 if (evt
->features
& CLOCK_EVT_FEAT_DUMMY
)
341 local_irq_save(flags
);
344 case CLOCK_EVT_MODE_PERIODIC
:
345 case CLOCK_EVT_MODE_ONESHOT
:
346 __setup_APIC_LVTT(calibration_result
,
347 mode
!= CLOCK_EVT_MODE_PERIODIC
, 1);
349 case CLOCK_EVT_MODE_UNUSED
:
350 case CLOCK_EVT_MODE_SHUTDOWN
:
351 v
= apic_read(APIC_LVTT
);
352 v
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
353 apic_write(APIC_LVTT
, v
);
355 case CLOCK_EVT_MODE_RESUME
:
356 /* Nothing to do here */
360 local_irq_restore(flags
);
364 * Local APIC timer broadcast function
366 static void lapic_timer_broadcast(cpumask_t mask
)
369 send_IPI_mask(mask
, LOCAL_TIMER_VECTOR
);
374 * Setup the local APIC timer for this CPU. Copy the initilized values
375 * of the boot CPU and register the clock event in the framework.
377 static void setup_APIC_timer(void)
379 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
381 memcpy(levt
, &lapic_clockevent
, sizeof(*levt
));
382 levt
->cpumask
= cpumask_of_cpu(smp_processor_id());
384 clockevents_register_device(levt
);
388 * In this function we calibrate APIC bus clocks to the external
389 * timer. Unfortunately we cannot use jiffies and the timer irq
390 * to calibrate, since some later bootup code depends on getting
391 * the first irq? Ugh.
393 * We want to do the calibration only once since we
394 * want to have local timer irqs syncron. CPUs connected
395 * by the same APIC bus have the very same bus frequency.
396 * And we want to have irqs off anyways, no accidental
400 #define TICK_COUNT 100000000
402 static int __init
calibrate_APIC_clock(void)
404 unsigned apic
, apic_start
;
405 unsigned long tsc
, tsc_start
;
411 * Put whatever arbitrary (but long enough) timeout
412 * value into the APIC clock, we just want to get the
413 * counter running for calibration.
415 * No interrupt enable !
417 __setup_APIC_LVTT(250000000, 0, 0);
419 apic_start
= apic_read(APIC_TMCCT
);
420 #ifdef CONFIG_X86_PM_TIMER
421 if (apic_calibrate_pmtmr
&& pmtmr_ioport
) {
422 pmtimer_wait(5000); /* 5ms wait */
423 apic
= apic_read(APIC_TMCCT
);
424 result
= (apic_start
- apic
) * 1000L / 5;
431 apic
= apic_read(APIC_TMCCT
);
433 } while ((tsc
- tsc_start
) < TICK_COUNT
&&
434 (apic_start
- apic
) < TICK_COUNT
);
436 result
= (apic_start
- apic
) * 1000L * tsc_khz
/
442 printk(KERN_DEBUG
"APIC timer calibration result %d\n", result
);
444 printk(KERN_INFO
"Detected %d.%03d MHz APIC timer.\n",
445 result
/ 1000 / 1000, result
/ 1000 % 1000);
447 /* Calculate the scaled math multiplication factor */
448 lapic_clockevent
.mult
= div_sc(result
, NSEC_PER_SEC
,
449 lapic_clockevent
.shift
);
450 lapic_clockevent
.max_delta_ns
=
451 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent
);
452 lapic_clockevent
.min_delta_ns
=
453 clockevent_delta2ns(0xF, &lapic_clockevent
);
455 calibration_result
= (result
* APIC_DIVISOR
) / HZ
;
458 * Do a sanity check on the APIC calibration result
460 if (calibration_result
< (1000000 / HZ
)) {
462 "APIC frequency too slow, disabling apic timer\n");
470 * Setup the boot APIC
472 * Calibrate and verify the result.
474 void __init
setup_boot_APIC_clock(void)
477 * The local apic timer can be disabled via the kernel commandline.
478 * Register the lapic timer as a dummy clock event source on SMP
479 * systems, so the broadcast mechanism is used. On UP systems simply
482 if (disable_apic_timer
) {
483 printk(KERN_INFO
"Disabling APIC timer\n");
484 /* No broadcast on UP ! */
485 if (num_possible_cpus() > 1) {
486 lapic_clockevent
.mult
= 1;
492 printk(KERN_INFO
"Using local APIC timer interrupts.\n");
493 if (calibrate_APIC_clock()) {
494 /* No broadcast on UP ! */
495 if (num_possible_cpus() > 1)
501 * If nmi_watchdog is set to IO_APIC, we need the
502 * PIT/HPET going. Otherwise register lapic as a dummy
505 if (nmi_watchdog
!= NMI_IO_APIC
)
506 lapic_clockevent
.features
&= ~CLOCK_EVT_FEAT_DUMMY
;
508 printk(KERN_WARNING
"APIC timer registered as dummy,"
509 " due to nmi_watchdog=%d!\n", nmi_watchdog
);
514 void __cpuinit
setup_secondary_APIC_clock(void)
520 * The guts of the apic timer interrupt
522 static void local_apic_timer_interrupt(void)
524 int cpu
= smp_processor_id();
525 struct clock_event_device
*evt
= &per_cpu(lapic_events
, cpu
);
528 * Normally we should not be here till LAPIC has been initialized but
529 * in some cases like kdump, its possible that there is a pending LAPIC
530 * timer interrupt from previous kernel's context and is delivered in
531 * new kernel the moment interrupts are enabled.
533 * Interrupts are enabled early and LAPIC is setup much later, hence
534 * its possible that when we get here evt->event_handler is NULL.
535 * Check for event_handler being NULL and discard the interrupt as
538 if (!evt
->event_handler
) {
540 "Spurious LAPIC timer interrupt on cpu %d\n", cpu
);
542 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, evt
);
547 * the NMI deadlock-detector uses this.
549 add_pda(apic_timer_irqs
, 1);
551 evt
->event_handler(evt
);
555 * Local APIC timer interrupt. This is the most natural way for doing
556 * local interrupts, but local timer interrupts can be emulated by
557 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
559 * [ if a single-CPU system runs an SMP kernel then we call the local
560 * interrupt as well. Thus we cannot inline the local irq ... ]
562 void smp_apic_timer_interrupt(struct pt_regs
*regs
)
564 struct pt_regs
*old_regs
= set_irq_regs(regs
);
567 * NOTE! We'd better ACK the irq immediately,
568 * because timer handling can be slow.
572 * update_process_times() expects us to have done irq_enter().
573 * Besides, if we don't timer interrupts ignore the global
574 * interrupt lock, which is the WrongThing (tm) to do.
578 local_apic_timer_interrupt();
580 set_irq_regs(old_regs
);
583 int setup_profiling_timer(unsigned int multiplier
)
590 * Local APIC start and shutdown
594 * clear_local_APIC - shutdown the local APIC
596 * This is called, when a CPU is disabled and before rebooting, so the state of
597 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
598 * leftovers during boot.
600 void clear_local_APIC(void)
605 /* APIC hasn't been mapped yet */
609 maxlvt
= lapic_get_maxlvt();
611 * Masking an LVT entry can trigger a local APIC error
612 * if the vector is zero. Mask LVTERR first to prevent this.
615 v
= ERROR_APIC_VECTOR
; /* any non-zero vector will do */
616 apic_write(APIC_LVTERR
, v
| APIC_LVT_MASKED
);
619 * Careful: we have to set masks only first to deassert
620 * any level-triggered sources.
622 v
= apic_read(APIC_LVTT
);
623 apic_write(APIC_LVTT
, v
| APIC_LVT_MASKED
);
624 v
= apic_read(APIC_LVT0
);
625 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
626 v
= apic_read(APIC_LVT1
);
627 apic_write(APIC_LVT1
, v
| APIC_LVT_MASKED
);
629 v
= apic_read(APIC_LVTPC
);
630 apic_write(APIC_LVTPC
, v
| APIC_LVT_MASKED
);
634 * Clean APIC state for other OSs:
636 apic_write(APIC_LVTT
, APIC_LVT_MASKED
);
637 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
638 apic_write(APIC_LVT1
, APIC_LVT_MASKED
);
640 apic_write(APIC_LVTERR
, APIC_LVT_MASKED
);
642 apic_write(APIC_LVTPC
, APIC_LVT_MASKED
);
643 apic_write(APIC_ESR
, 0);
648 * disable_local_APIC - clear and disable the local APIC
650 void disable_local_APIC(void)
657 * Disable APIC (implies clearing of registers
660 value
= apic_read(APIC_SPIV
);
661 value
&= ~APIC_SPIV_APIC_ENABLED
;
662 apic_write(APIC_SPIV
, value
);
665 void lapic_shutdown(void)
672 local_irq_save(flags
);
674 disable_local_APIC();
676 local_irq_restore(flags
);
680 * This is to verify that we're looking at a real local APIC.
681 * Check these against your board if the CPUs aren't getting
682 * started for no apparent reason.
684 int __init
verify_local_APIC(void)
686 unsigned int reg0
, reg1
;
689 * The version register is read-only in a real APIC.
691 reg0
= apic_read(APIC_LVR
);
692 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg0
);
693 apic_write(APIC_LVR
, reg0
^ APIC_LVR_MASK
);
694 reg1
= apic_read(APIC_LVR
);
695 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg1
);
698 * The two version reads above should print the same
699 * numbers. If the second one is different, then we
700 * poke at a non-APIC.
706 * Check if the version looks reasonably.
708 reg1
= GET_APIC_VERSION(reg0
);
709 if (reg1
== 0x00 || reg1
== 0xff)
711 reg1
= lapic_get_maxlvt();
712 if (reg1
< 0x02 || reg1
== 0xff)
716 * The ID register is read/write in a real APIC.
718 reg0
= apic_read(APIC_ID
);
719 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg0
);
720 apic_write(APIC_ID
, reg0
^ APIC_ID_MASK
);
721 reg1
= apic_read(APIC_ID
);
722 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg1
);
723 apic_write(APIC_ID
, reg0
);
724 if (reg1
!= (reg0
^ APIC_ID_MASK
))
728 * The next two are just to see if we have sane values.
729 * They're only really relevant if we're in Virtual Wire
730 * compatibility mode, but most boxes are anymore.
732 reg0
= apic_read(APIC_LVT0
);
733 apic_printk(APIC_DEBUG
, "Getting LVT0: %x\n", reg0
);
734 reg1
= apic_read(APIC_LVT1
);
735 apic_printk(APIC_DEBUG
, "Getting LVT1: %x\n", reg1
);
741 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
743 void __init
sync_Arb_IDs(void)
746 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
749 if (modern_apic() || boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
)
755 apic_wait_icr_idle();
757 apic_printk(APIC_DEBUG
, "Synchronizing Arb IDs.\n");
758 apic_write(APIC_ICR
, APIC_DEST_ALLINC
|
759 APIC_INT_LEVELTRIG
| APIC_DM_INIT
);
763 * An initial setup of the virtual wire mode.
765 void __init
init_bsp_APIC(void)
770 * Don't do the setup now if we have a SMP BIOS as the
771 * through-I/O-APIC virtual wire mode might be active.
773 if (smp_found_config
|| !cpu_has_apic
)
777 * Do not trust the local APIC being empty at bootup.
784 value
= apic_read(APIC_SPIV
);
785 value
&= ~APIC_VECTOR_MASK
;
786 value
|= APIC_SPIV_APIC_ENABLED
;
789 /* This bit is reserved on P4/Xeon and should be cleared */
790 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
) &&
791 (boot_cpu_data
.x86
== 15))
792 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
795 value
|= APIC_SPIV_FOCUS_DISABLED
;
796 value
|= SPURIOUS_APIC_VECTOR
;
797 apic_write(APIC_SPIV
, value
);
800 * Set up the virtual wire mode.
802 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
804 if (!lapic_is_integrated()) /* 82489DX */
805 value
|= APIC_LVT_LEVEL_TRIGGER
;
806 apic_write(APIC_LVT1
, value
);
810 * setup_local_APIC - setup the local APIC
812 void __cpuinit
setup_local_APIC(void)
818 value
= apic_read(APIC_LVR
);
820 BUILD_BUG_ON((SPURIOUS_APIC_VECTOR
& 0x0f) != 0x0f);
823 * Double-check whether this APIC is really registered.
824 * This is meaningless in clustered apic mode, so we skip it.
826 if (!apic_id_registered())
830 * Intel recommends to set DFR, LDR and TPR before enabling
831 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
832 * document number 292116). So here it goes...
837 * Set Task Priority to 'accept all'. We never change this
840 value
= apic_read(APIC_TASKPRI
);
841 value
&= ~APIC_TPRI_MASK
;
842 apic_write(APIC_TASKPRI
, value
);
845 * After a crash, we no longer service the interrupts and a pending
846 * interrupt from previous kernel might still have ISR bit set.
848 * Most probably by now CPU has serviced that pending interrupt and
849 * it might not have done the ack_APIC_irq() because it thought,
850 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
851 * does not clear the ISR bit and cpu thinks it has already serivced
852 * the interrupt. Hence a vector might get locked. It was noticed
853 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
855 for (i
= APIC_ISR_NR
- 1; i
>= 0; i
--) {
856 value
= apic_read(APIC_ISR
+ i
*0x10);
857 for (j
= 31; j
>= 0; j
--) {
864 * Now that we are all set up, enable the APIC
866 value
= apic_read(APIC_SPIV
);
867 value
&= ~APIC_VECTOR_MASK
;
871 value
|= APIC_SPIV_APIC_ENABLED
;
873 /* We always use processor focus */
876 * Set spurious IRQ vector
878 value
|= SPURIOUS_APIC_VECTOR
;
879 apic_write(APIC_SPIV
, value
);
884 * set up through-local-APIC on the BP's LINT0. This is not
885 * strictly necessary in pure symmetric-IO mode, but sometimes
886 * we delegate interrupts to the 8259A.
889 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
891 value
= apic_read(APIC_LVT0
) & APIC_LVT_MASKED
;
892 if (!smp_processor_id() && !value
) {
893 value
= APIC_DM_EXTINT
;
894 apic_printk(APIC_VERBOSE
, "enabled ExtINT on CPU#%d\n",
897 value
= APIC_DM_EXTINT
| APIC_LVT_MASKED
;
898 apic_printk(APIC_VERBOSE
, "masked ExtINT on CPU#%d\n",
901 apic_write(APIC_LVT0
, value
);
904 * only the BP should see the LINT1 NMI signal, obviously.
906 if (!smp_processor_id())
909 value
= APIC_DM_NMI
| APIC_LVT_MASKED
;
910 apic_write(APIC_LVT1
, value
);
914 static void __cpuinit
lapic_setup_esr(void)
916 unsigned maxlvt
= lapic_get_maxlvt();
918 apic_write(APIC_LVTERR
, ERROR_APIC_VECTOR
);
920 * spec says clear errors after enabling vector.
923 apic_write(APIC_ESR
, 0);
926 void __cpuinit
end_local_APIC_setup(void)
929 setup_apic_nmi_watchdog(NULL
);
933 void check_x2apic(void)
937 rdmsr(MSR_IA32_APICBASE
, msr
, msr2
);
939 if (msr
& X2APIC_ENABLE
) {
940 printk("x2apic enabled by BIOS, switching to x2apic ops\n");
941 x2apic_preenabled
= x2apic
= 1;
942 apic_ops
= &x2apic_ops
;
946 void enable_x2apic(void)
950 rdmsr(MSR_IA32_APICBASE
, msr
, msr2
);
951 if (!(msr
& X2APIC_ENABLE
)) {
952 printk("Enabling x2apic\n");
953 wrmsr(MSR_IA32_APICBASE
, msr
| X2APIC_ENABLE
, 0);
957 void enable_IR_x2apic(void)
959 #ifdef CONFIG_INTR_REMAP
966 if (!x2apic_preenabled
&& disable_x2apic
) {
968 "Skipped enabling x2apic and Interrupt-remapping "
969 "because of nox2apic\n");
973 if (x2apic_preenabled
&& disable_x2apic
)
974 panic("Bios already enabled x2apic, can't enforce nox2apic");
976 if (!x2apic_preenabled
&& skip_ioapic_setup
) {
978 "Skipped enabling x2apic and Interrupt-remapping "
979 "because of skipping io-apic setup\n");
983 ret
= dmar_table_init();
986 "dmar_table_init() failed with %d:\n", ret
);
988 if (x2apic_preenabled
)
989 panic("x2apic enabled by bios. But IR enabling failed");
992 "Not enabling x2apic,Intr-remapping\n");
996 local_irq_save(flags
);
998 save_mask_IO_APIC_setup();
1000 ret
= enable_intr_remapping(1);
1002 if (ret
&& x2apic_preenabled
) {
1003 local_irq_restore(flags
);
1004 panic("x2apic enabled by bios. But IR enabling failed");
1012 apic_ops
= &x2apic_ops
;
1018 * IR enabling failed
1020 restore_IO_APIC_setup();
1022 reinit_intr_remapped_IO_APIC(x2apic_preenabled
);
1025 local_irq_restore(flags
);
1028 if (!x2apic_preenabled
)
1030 "Enabled x2apic and interrupt-remapping\n");
1033 "Enabled Interrupt-remapping\n");
1036 "Failed to enable Interrupt-remapping and x2apic\n");
1038 if (!cpu_has_x2apic
)
1041 if (x2apic_preenabled
)
1042 panic("x2apic enabled prior OS handover,"
1043 " enable CONFIG_INTR_REMAP");
1045 printk(KERN_INFO
"Enable CONFIG_INTR_REMAP for enabling intr-remapping "
1053 * Detect and enable local APICs on non-SMP boards.
1054 * Original code written by Keir Fraser.
1055 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1056 * not correctly set up (usually the APIC timer won't work etc.)
1058 static int __init
detect_init_APIC(void)
1060 if (!cpu_has_apic
) {
1061 printk(KERN_INFO
"No local APIC present\n");
1065 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
1066 boot_cpu_physical_apicid
= 0;
1070 void __init
early_init_lapic_mapping(void)
1072 unsigned long phys_addr
;
1075 * If no local APIC can be found then go out
1076 * : it means there is no mpatable and MADT
1078 if (!smp_found_config
)
1081 phys_addr
= mp_lapic_addr
;
1083 set_fixmap_nocache(FIX_APIC_BASE
, phys_addr
);
1084 apic_printk(APIC_VERBOSE
, "mapped APIC to %16lx (%16lx)\n",
1085 APIC_BASE
, phys_addr
);
1088 * Fetch the APIC ID of the BSP in case we have a
1089 * default configuration (or the MP table is broken).
1091 boot_cpu_physical_apicid
= read_apic_id();
1095 * init_apic_mappings - initialize APIC mappings
1097 void __init
init_apic_mappings(void)
1100 boot_cpu_physical_apicid
= read_apic_id();
1105 * If no local APIC can be found then set up a fake all
1106 * zeroes page to simulate the local APIC and another
1107 * one for the IO-APIC.
1109 if (!smp_found_config
&& detect_init_APIC()) {
1110 apic_phys
= (unsigned long) alloc_bootmem_pages(PAGE_SIZE
);
1111 apic_phys
= __pa(apic_phys
);
1113 apic_phys
= mp_lapic_addr
;
1115 set_fixmap_nocache(FIX_APIC_BASE
, apic_phys
);
1116 apic_printk(APIC_VERBOSE
, "mapped APIC to %16lx (%16lx)\n",
1117 APIC_BASE
, apic_phys
);
1120 * Fetch the APIC ID of the BSP in case we have a
1121 * default configuration (or the MP table is broken).
1123 boot_cpu_physical_apicid
= read_apic_id();
1127 * This initializes the IO-APIC and APIC hardware if this is
1130 int __init
APIC_init_uniprocessor(void)
1133 printk(KERN_INFO
"Apic disabled\n");
1136 if (!cpu_has_apic
) {
1138 printk(KERN_INFO
"Apic disabled by BIOS\n");
1143 setup_apic_routing();
1145 verify_local_APIC();
1149 physid_set_mask_of_physid(boot_cpu_physical_apicid
, &phys_cpu_present_map
);
1150 apic_write(APIC_ID
, SET_APIC_ID(boot_cpu_physical_apicid
));
1155 * Now enable IO-APICs, actually call clear_IO_APIC
1156 * We need clear_IO_APIC before enabling vector on BP
1158 if (!skip_ioapic_setup
&& nr_ioapics
)
1161 if (!smp_found_config
|| skip_ioapic_setup
|| !nr_ioapics
)
1162 localise_nmi_watchdog();
1163 end_local_APIC_setup();
1165 if (smp_found_config
&& !skip_ioapic_setup
&& nr_ioapics
)
1169 setup_boot_APIC_clock();
1170 check_nmi_watchdog();
1175 * Local APIC interrupts
1179 * This interrupt should _never_ happen with our APIC/SMP architecture
1181 asmlinkage
void smp_spurious_interrupt(void)
1187 * Check if this really is a spurious interrupt and ACK it
1188 * if it is a vectored one. Just in case...
1189 * Spurious interrupts should not be ACKed.
1191 v
= apic_read(APIC_ISR
+ ((SPURIOUS_APIC_VECTOR
& ~0x1f) >> 1));
1192 if (v
& (1 << (SPURIOUS_APIC_VECTOR
& 0x1f)))
1195 add_pda(irq_spurious_count
, 1);
1200 * This interrupt should never happen with our APIC/SMP architecture
1202 asmlinkage
void smp_error_interrupt(void)
1208 /* First tickle the hardware, only then report what went on. -- REW */
1209 v
= apic_read(APIC_ESR
);
1210 apic_write(APIC_ESR
, 0);
1211 v1
= apic_read(APIC_ESR
);
1213 atomic_inc(&irq_err_count
);
1215 /* Here is what the APIC error bits mean:
1218 2: Send accept error
1219 3: Receive accept error
1221 5: Send illegal vector
1222 6: Received illegal vector
1223 7: Illegal register address
1225 printk(KERN_DEBUG
"APIC error on CPU%d: %02x(%02x)\n",
1226 smp_processor_id(), v
, v1
);
1231 * * connect_bsp_APIC - attach the APIC to the interrupt system
1233 void __init
connect_bsp_APIC(void)
1238 void disconnect_bsp_APIC(int virt_wire_setup
)
1240 /* Go back to Virtual Wire compatibility mode */
1241 unsigned long value
;
1243 /* For the spurious interrupt use vector F, and enable it */
1244 value
= apic_read(APIC_SPIV
);
1245 value
&= ~APIC_VECTOR_MASK
;
1246 value
|= APIC_SPIV_APIC_ENABLED
;
1248 apic_write(APIC_SPIV
, value
);
1250 if (!virt_wire_setup
) {
1252 * For LVT0 make it edge triggered, active high,
1253 * external and enabled
1255 value
= apic_read(APIC_LVT0
);
1256 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1257 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1258 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1259 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1260 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_EXTINT
);
1261 apic_write(APIC_LVT0
, value
);
1264 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
1267 /* For LVT1 make it edge triggered, active high, nmi and enabled */
1268 value
= apic_read(APIC_LVT1
);
1269 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1270 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1271 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1272 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1273 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_NMI
);
1274 apic_write(APIC_LVT1
, value
);
1277 void __cpuinit
generic_processor_info(int apicid
, int version
)
1282 if (num_processors
>= NR_CPUS
) {
1283 printk(KERN_WARNING
"WARNING: NR_CPUS limit of %i reached."
1284 " Processor ignored.\n", NR_CPUS
);
1288 if (num_processors
>= maxcpus
) {
1289 printk(KERN_WARNING
"WARNING: maxcpus limit of %i reached."
1290 " Processor ignored.\n", maxcpus
);
1295 cpus_complement(tmp_map
, cpu_present_map
);
1296 cpu
= first_cpu(tmp_map
);
1298 physid_set(apicid
, phys_cpu_present_map
);
1299 if (apicid
== boot_cpu_physical_apicid
) {
1301 * x86_bios_cpu_apicid is required to have processors listed
1302 * in same order as logical cpu numbers. Hence the first
1303 * entry is BSP, and so on.
1307 if (apicid
> max_physical_apicid
)
1308 max_physical_apicid
= apicid
;
1310 /* are we being called early in kernel startup? */
1311 if (early_per_cpu_ptr(x86_cpu_to_apicid
)) {
1312 u16
*cpu_to_apicid
= early_per_cpu_ptr(x86_cpu_to_apicid
);
1313 u16
*bios_cpu_apicid
= early_per_cpu_ptr(x86_bios_cpu_apicid
);
1315 cpu_to_apicid
[cpu
] = apicid
;
1316 bios_cpu_apicid
[cpu
] = apicid
;
1318 per_cpu(x86_cpu_to_apicid
, cpu
) = apicid
;
1319 per_cpu(x86_bios_cpu_apicid
, cpu
) = apicid
;
1322 cpu_set(cpu
, cpu_possible_map
);
1323 cpu_set(cpu
, cpu_present_map
);
1326 int hard_smp_processor_id(void)
1328 return read_apic_id();
1337 /* 'active' is true if the local APIC was enabled by us and
1338 not the BIOS; this signifies that we are also responsible
1339 for disabling it before entering apm/acpi suspend */
1341 /* r/w apic fields */
1342 unsigned int apic_id
;
1343 unsigned int apic_taskpri
;
1344 unsigned int apic_ldr
;
1345 unsigned int apic_dfr
;
1346 unsigned int apic_spiv
;
1347 unsigned int apic_lvtt
;
1348 unsigned int apic_lvtpc
;
1349 unsigned int apic_lvt0
;
1350 unsigned int apic_lvt1
;
1351 unsigned int apic_lvterr
;
1352 unsigned int apic_tmict
;
1353 unsigned int apic_tdcr
;
1354 unsigned int apic_thmr
;
1357 static int lapic_suspend(struct sys_device
*dev
, pm_message_t state
)
1359 unsigned long flags
;
1362 if (!apic_pm_state
.active
)
1365 maxlvt
= lapic_get_maxlvt();
1367 apic_pm_state
.apic_id
= apic_read(APIC_ID
);
1368 apic_pm_state
.apic_taskpri
= apic_read(APIC_TASKPRI
);
1369 apic_pm_state
.apic_ldr
= apic_read(APIC_LDR
);
1370 apic_pm_state
.apic_dfr
= apic_read(APIC_DFR
);
1371 apic_pm_state
.apic_spiv
= apic_read(APIC_SPIV
);
1372 apic_pm_state
.apic_lvtt
= apic_read(APIC_LVTT
);
1374 apic_pm_state
.apic_lvtpc
= apic_read(APIC_LVTPC
);
1375 apic_pm_state
.apic_lvt0
= apic_read(APIC_LVT0
);
1376 apic_pm_state
.apic_lvt1
= apic_read(APIC_LVT1
);
1377 apic_pm_state
.apic_lvterr
= apic_read(APIC_LVTERR
);
1378 apic_pm_state
.apic_tmict
= apic_read(APIC_TMICT
);
1379 apic_pm_state
.apic_tdcr
= apic_read(APIC_TDCR
);
1380 #ifdef CONFIG_X86_MCE_INTEL
1382 apic_pm_state
.apic_thmr
= apic_read(APIC_LVTTHMR
);
1384 local_irq_save(flags
);
1385 disable_local_APIC();
1386 local_irq_restore(flags
);
1390 static int lapic_resume(struct sys_device
*dev
)
1393 unsigned long flags
;
1396 if (!apic_pm_state
.active
)
1399 maxlvt
= lapic_get_maxlvt();
1401 local_irq_save(flags
);
1403 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1404 l
&= ~MSR_IA32_APICBASE_BASE
;
1405 l
|= MSR_IA32_APICBASE_ENABLE
| mp_lapic_addr
;
1406 wrmsr(MSR_IA32_APICBASE
, l
, h
);
1410 apic_write(APIC_LVTERR
, ERROR_APIC_VECTOR
| APIC_LVT_MASKED
);
1411 apic_write(APIC_ID
, apic_pm_state
.apic_id
);
1412 apic_write(APIC_DFR
, apic_pm_state
.apic_dfr
);
1413 apic_write(APIC_LDR
, apic_pm_state
.apic_ldr
);
1414 apic_write(APIC_TASKPRI
, apic_pm_state
.apic_taskpri
);
1415 apic_write(APIC_SPIV
, apic_pm_state
.apic_spiv
);
1416 apic_write(APIC_LVT0
, apic_pm_state
.apic_lvt0
);
1417 apic_write(APIC_LVT1
, apic_pm_state
.apic_lvt1
);
1418 #ifdef CONFIG_X86_MCE_INTEL
1420 apic_write(APIC_LVTTHMR
, apic_pm_state
.apic_thmr
);
1423 apic_write(APIC_LVTPC
, apic_pm_state
.apic_lvtpc
);
1424 apic_write(APIC_LVTT
, apic_pm_state
.apic_lvtt
);
1425 apic_write(APIC_TDCR
, apic_pm_state
.apic_tdcr
);
1426 apic_write(APIC_TMICT
, apic_pm_state
.apic_tmict
);
1427 apic_write(APIC_ESR
, 0);
1428 apic_read(APIC_ESR
);
1429 apic_write(APIC_LVTERR
, apic_pm_state
.apic_lvterr
);
1430 apic_write(APIC_ESR
, 0);
1431 apic_read(APIC_ESR
);
1432 local_irq_restore(flags
);
1436 static struct sysdev_class lapic_sysclass
= {
1438 .resume
= lapic_resume
,
1439 .suspend
= lapic_suspend
,
1442 static struct sys_device device_lapic
= {
1444 .cls
= &lapic_sysclass
,
1447 static void __cpuinit
apic_pm_activate(void)
1449 apic_pm_state
.active
= 1;
1452 static int __init
init_lapic_sysfs(void)
1458 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
1460 error
= sysdev_class_register(&lapic_sysclass
);
1462 error
= sysdev_register(&device_lapic
);
1465 device_initcall(init_lapic_sysfs
);
1467 #else /* CONFIG_PM */
1469 static void apic_pm_activate(void) { }
1471 #endif /* CONFIG_PM */
1474 * apic_is_clustered_box() -- Check if we can expect good TSC
1476 * Thus far, the major user of this is IBM's Summit2 series:
1478 * Clustered boxes may have unsynced TSC problems if they are
1479 * multi-chassis. Use available data to take a good guess.
1480 * If in doubt, go HPET.
1482 __cpuinit
int apic_is_clustered_box(void)
1484 int i
, clusters
, zeros
;
1486 u16
*bios_cpu_apicid
;
1487 DECLARE_BITMAP(clustermap
, NUM_APIC_CLUSTERS
);
1490 * there is not this kind of box with AMD CPU yet.
1491 * Some AMD box with quadcore cpu and 8 sockets apicid
1492 * will be [4, 0x23] or [8, 0x27] could be thought to
1493 * vsmp box still need checking...
1495 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
) && !is_vsmp_box())
1498 bios_cpu_apicid
= early_per_cpu_ptr(x86_bios_cpu_apicid
);
1499 bitmap_zero(clustermap
, NUM_APIC_CLUSTERS
);
1501 for (i
= 0; i
< NR_CPUS
; i
++) {
1502 /* are we being called early in kernel startup? */
1503 if (bios_cpu_apicid
) {
1504 id
= bios_cpu_apicid
[i
];
1506 else if (i
< nr_cpu_ids
) {
1508 id
= per_cpu(x86_bios_cpu_apicid
, i
);
1515 if (id
!= BAD_APICID
)
1516 __set_bit(APIC_CLUSTERID(id
), clustermap
);
1519 /* Problem: Partially populated chassis may not have CPUs in some of
1520 * the APIC clusters they have been allocated. Only present CPUs have
1521 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap.
1522 * Since clusters are allocated sequentially, count zeros only if
1523 * they are bounded by ones.
1527 for (i
= 0; i
< NUM_APIC_CLUSTERS
; i
++) {
1528 if (test_bit(i
, clustermap
)) {
1529 clusters
+= 1 + zeros
;
1535 /* ScaleMP vSMPowered boxes have one cluster per board and TSCs are
1536 * not guaranteed to be synced between boards
1538 if (is_vsmp_box() && clusters
> 1)
1542 * If clusters > 2, then should be multi-chassis.
1543 * May have to revisit this when multi-core + hyperthreaded CPUs come
1544 * out, but AFAIK this will work even for them.
1546 return (clusters
> 2);
1549 static __init
int setup_nox2apic(char *str
)
1552 clear_cpu_cap(&boot_cpu_data
, X86_FEATURE_X2APIC
);
1555 early_param("nox2apic", setup_nox2apic
);
1559 * APIC command line parameters
1561 static int __init
apic_set_verbosity(char *str
)
1564 skip_ioapic_setup
= 0;
1568 if (strcmp("debug", str
) == 0)
1569 apic_verbosity
= APIC_DEBUG
;
1570 else if (strcmp("verbose", str
) == 0)
1571 apic_verbosity
= APIC_VERBOSE
;
1573 printk(KERN_WARNING
"APIC Verbosity level %s not recognised"
1574 " use apic=verbose or apic=debug\n", str
);
1580 early_param("apic", apic_set_verbosity
);
1582 static __init
int setup_disableapic(char *str
)
1585 setup_clear_cpu_cap(X86_FEATURE_APIC
);
1588 early_param("disableapic", setup_disableapic
);
1590 /* same as disableapic, for compatibility */
1591 static __init
int setup_nolapic(char *str
)
1593 return setup_disableapic(str
);
1595 early_param("nolapic", setup_nolapic
);
1597 static int __init
parse_lapic_timer_c2_ok(char *arg
)
1599 local_apic_timer_c2_ok
= 1;
1602 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok
);
1604 static int __init
parse_disable_apic_timer(char *arg
)
1606 disable_apic_timer
= 1;
1609 early_param("noapictimer", parse_disable_apic_timer
);
1611 static int __init
parse_nolapic_timer(char *arg
)
1613 disable_apic_timer
= 1;
1616 early_param("nolapic_timer", parse_nolapic_timer
);
1618 static __init
int setup_apicpmtimer(char *s
)
1620 apic_calibrate_pmtmr
= 1;
1624 __setup("apicpmtimer", setup_apicpmtimer
);
1626 static int __init
lapic_insert_resource(void)
1631 /* Put local APIC into the resource map. */
1632 lapic_resource
.start
= apic_phys
;
1633 lapic_resource
.end
= lapic_resource
.start
+ PAGE_SIZE
- 1;
1634 insert_resource(&iomem_resource
, &lapic_resource
);
1640 * need call insert after e820_reserve_resources()
1641 * that is using request_resource
1643 late_initcall(lapic_insert_resource
);