2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/bootmem.h>
22 #include <linux/interrupt.h>
23 #include <linux/mc146818rtc.h>
24 #include <linux/kernel_stat.h>
25 #include <linux/sysdev.h>
26 #include <linux/ioport.h>
27 #include <linux/clockchips.h>
28 #include <linux/acpi_pmtmr.h>
29 #include <linux/module.h>
31 #include <asm/atomic.h>
34 #include <asm/mpspec.h>
36 #include <asm/pgalloc.h>
39 #include <asm/proto.h>
40 #include <asm/timex.h>
44 #include <mach_apic.h>
46 static int disable_apic_timer __cpuinitdata
;
47 static int apic_calibrate_pmtmr __initdata
;
50 /* Local APIC timer works in C2 */
51 int local_apic_timer_c2_ok
;
52 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok
);
55 * Debug level, exported for io_apic.c
59 /* Have we found an MP table */
62 static struct resource lapic_resource
= {
64 .flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
,
67 static unsigned int calibration_result
;
69 static int lapic_next_event(unsigned long delta
,
70 struct clock_event_device
*evt
);
71 static void lapic_timer_setup(enum clock_event_mode mode
,
72 struct clock_event_device
*evt
);
73 static void lapic_timer_broadcast(cpumask_t mask
);
74 static void apic_pm_activate(void);
76 static struct clock_event_device lapic_clockevent
= {
78 .features
= CLOCK_EVT_FEAT_PERIODIC
| CLOCK_EVT_FEAT_ONESHOT
79 | CLOCK_EVT_FEAT_C3STOP
| CLOCK_EVT_FEAT_DUMMY
,
81 .set_mode
= lapic_timer_setup
,
82 .set_next_event
= lapic_next_event
,
83 .broadcast
= lapic_timer_broadcast
,
87 static DEFINE_PER_CPU(struct clock_event_device
, lapic_events
);
89 static unsigned long apic_phys
;
91 unsigned long mp_lapic_addr
;
93 unsigned int __cpuinitdata maxcpus
= NR_CPUS
;
95 * Get the LAPIC version
97 static inline int lapic_get_version(void)
99 return GET_APIC_VERSION(apic_read(APIC_LVR
));
103 * Check, if the APIC is integrated or a seperate chip
105 static inline int lapic_is_integrated(void)
111 * Check, whether this is a modern or a first generation APIC
113 static int modern_apic(void)
115 /* AMD systems use old APIC versions, so check the CPU */
116 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
&&
117 boot_cpu_data
.x86
>= 0xf)
119 return lapic_get_version() >= 0x14;
122 void xapic_wait_icr_idle(void)
124 while (apic_read(APIC_ICR
) & APIC_ICR_BUSY
)
128 u32
safe_xapic_wait_icr_idle(void)
135 send_status
= apic_read(APIC_ICR
) & APIC_ICR_BUSY
;
139 } while (timeout
++ < 1000);
144 void xapic_icr_write(u32 low
, u32 id
)
146 apic_write(APIC_ICR2
, id
<< 24);
147 apic_write(APIC_ICR
, low
);
150 u64
xapic_icr_read(void)
154 icr2
= apic_read(APIC_ICR2
);
155 icr1
= apic_read(APIC_ICR
);
157 return (icr1
| ((u64
)icr2
<< 32));
160 static struct apic_ops xapic_ops
= {
161 .read
= native_apic_mem_read
,
162 .write
= native_apic_mem_write
,
163 .write_atomic
= native_apic_mem_write_atomic
,
164 .icr_read
= xapic_icr_read
,
165 .icr_write
= xapic_icr_write
,
166 .wait_icr_idle
= xapic_wait_icr_idle
,
167 .safe_wait_icr_idle
= safe_xapic_wait_icr_idle
,
170 struct apic_ops __read_mostly
*apic_ops
= &xapic_ops
;
172 EXPORT_SYMBOL_GPL(apic_ops
);
174 static void x2apic_wait_icr_idle(void)
176 /* no need to wait for icr idle in x2apic */
180 static u32
safe_x2apic_wait_icr_idle(void)
182 /* no need to wait for icr idle in x2apic */
186 void x2apic_icr_write(u32 low
, u32 id
)
188 wrmsrl(APIC_BASE_MSR
+ (APIC_ICR
>> 4), ((__u64
) id
) << 32 | low
);
191 u64
x2apic_icr_read(void)
195 rdmsrl(APIC_BASE_MSR
+ (APIC_ICR
>> 4), val
);
199 static struct apic_ops x2apic_ops
= {
200 .read
= native_apic_msr_read
,
201 .write
= native_apic_msr_write
,
202 .write_atomic
= native_apic_msr_write
,
203 .icr_read
= x2apic_icr_read
,
204 .icr_write
= x2apic_icr_write
,
205 .wait_icr_idle
= x2apic_wait_icr_idle
,
206 .safe_wait_icr_idle
= safe_x2apic_wait_icr_idle
,
210 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
212 void __cpuinit
enable_NMI_through_LVT0(void)
216 /* unmask and set to NMI */
218 apic_write(APIC_LVT0
, v
);
222 * lapic_get_maxlvt - get the maximum number of local vector table entries
224 int lapic_get_maxlvt(void)
226 unsigned int v
, maxlvt
;
228 v
= apic_read(APIC_LVR
);
229 maxlvt
= GET_APIC_MAXLVT(v
);
234 * This function sets up the local APIC timer, with a timeout of
235 * 'clocks' APIC bus clock. During calibration we actually call
236 * this function twice on the boot CPU, once with a bogus timeout
237 * value, second time for real. The other (noncalibrating) CPUs
238 * call this function only once, with the real, calibrated value.
240 * We do reads before writes even if unnecessary, to get around the
241 * P5 APIC double write bug.
244 static void __setup_APIC_LVTT(unsigned int clocks
, int oneshot
, int irqen
)
246 unsigned int lvtt_value
, tmp_value
;
248 lvtt_value
= LOCAL_TIMER_VECTOR
;
250 lvtt_value
|= APIC_LVT_TIMER_PERIODIC
;
252 lvtt_value
|= APIC_LVT_MASKED
;
254 apic_write(APIC_LVTT
, lvtt_value
);
259 tmp_value
= apic_read(APIC_TDCR
);
260 apic_write(APIC_TDCR
, (tmp_value
261 & ~(APIC_TDR_DIV_1
| APIC_TDR_DIV_TMBASE
))
265 apic_write(APIC_TMICT
, clocks
);
269 * Setup extended LVT, AMD specific (K8, family 10h)
271 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
272 * MCE interrupts are supported. Thus MCE offset must be set to 0.
275 #define APIC_EILVT_LVTOFF_MCE 0
276 #define APIC_EILVT_LVTOFF_IBS 1
278 static void setup_APIC_eilvt(u8 lvt_off
, u8 vector
, u8 msg_type
, u8 mask
)
280 unsigned long reg
= (lvt_off
<< 4) + APIC_EILVT0
;
281 unsigned int v
= (mask
<< 16) | (msg_type
<< 8) | vector
;
286 u8
setup_APIC_eilvt_mce(u8 vector
, u8 msg_type
, u8 mask
)
288 setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE
, vector
, msg_type
, mask
);
289 return APIC_EILVT_LVTOFF_MCE
;
292 u8
setup_APIC_eilvt_ibs(u8 vector
, u8 msg_type
, u8 mask
)
294 setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS
, vector
, msg_type
, mask
);
295 return APIC_EILVT_LVTOFF_IBS
;
299 * Program the next event, relative to now
301 static int lapic_next_event(unsigned long delta
,
302 struct clock_event_device
*evt
)
304 apic_write(APIC_TMICT
, delta
);
309 * Setup the lapic timer in periodic or oneshot mode
311 static void lapic_timer_setup(enum clock_event_mode mode
,
312 struct clock_event_device
*evt
)
317 /* Lapic used as dummy for broadcast ? */
318 if (evt
->features
& CLOCK_EVT_FEAT_DUMMY
)
321 local_irq_save(flags
);
324 case CLOCK_EVT_MODE_PERIODIC
:
325 case CLOCK_EVT_MODE_ONESHOT
:
326 __setup_APIC_LVTT(calibration_result
,
327 mode
!= CLOCK_EVT_MODE_PERIODIC
, 1);
329 case CLOCK_EVT_MODE_UNUSED
:
330 case CLOCK_EVT_MODE_SHUTDOWN
:
331 v
= apic_read(APIC_LVTT
);
332 v
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
333 apic_write(APIC_LVTT
, v
);
335 case CLOCK_EVT_MODE_RESUME
:
336 /* Nothing to do here */
340 local_irq_restore(flags
);
344 * Local APIC timer broadcast function
346 static void lapic_timer_broadcast(cpumask_t mask
)
349 send_IPI_mask(mask
, LOCAL_TIMER_VECTOR
);
354 * Setup the local APIC timer for this CPU. Copy the initilized values
355 * of the boot CPU and register the clock event in the framework.
357 static void setup_APIC_timer(void)
359 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
361 memcpy(levt
, &lapic_clockevent
, sizeof(*levt
));
362 levt
->cpumask
= cpumask_of_cpu(smp_processor_id());
364 clockevents_register_device(levt
);
368 * In this function we calibrate APIC bus clocks to the external
369 * timer. Unfortunately we cannot use jiffies and the timer irq
370 * to calibrate, since some later bootup code depends on getting
371 * the first irq? Ugh.
373 * We want to do the calibration only once since we
374 * want to have local timer irqs syncron. CPUs connected
375 * by the same APIC bus have the very same bus frequency.
376 * And we want to have irqs off anyways, no accidental
380 #define TICK_COUNT 100000000
382 static void __init
calibrate_APIC_clock(void)
384 unsigned apic
, apic_start
;
385 unsigned long tsc
, tsc_start
;
391 * Put whatever arbitrary (but long enough) timeout
392 * value into the APIC clock, we just want to get the
393 * counter running for calibration.
395 * No interrupt enable !
397 __setup_APIC_LVTT(250000000, 0, 0);
399 apic_start
= apic_read(APIC_TMCCT
);
400 #ifdef CONFIG_X86_PM_TIMER
401 if (apic_calibrate_pmtmr
&& pmtmr_ioport
) {
402 pmtimer_wait(5000); /* 5ms wait */
403 apic
= apic_read(APIC_TMCCT
);
404 result
= (apic_start
- apic
) * 1000L / 5;
411 apic
= apic_read(APIC_TMCCT
);
413 } while ((tsc
- tsc_start
) < TICK_COUNT
&&
414 (apic_start
- apic
) < TICK_COUNT
);
416 result
= (apic_start
- apic
) * 1000L * tsc_khz
/
422 printk(KERN_DEBUG
"APIC timer calibration result %d\n", result
);
424 printk(KERN_INFO
"Detected %d.%03d MHz APIC timer.\n",
425 result
/ 1000 / 1000, result
/ 1000 % 1000);
427 /* Calculate the scaled math multiplication factor */
428 lapic_clockevent
.mult
= div_sc(result
, NSEC_PER_SEC
,
429 lapic_clockevent
.shift
);
430 lapic_clockevent
.max_delta_ns
=
431 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent
);
432 lapic_clockevent
.min_delta_ns
=
433 clockevent_delta2ns(0xF, &lapic_clockevent
);
435 calibration_result
= result
/ HZ
;
439 * Setup the boot APIC
441 * Calibrate and verify the result.
443 void __init
setup_boot_APIC_clock(void)
446 * The local apic timer can be disabled via the kernel commandline.
447 * Register the lapic timer as a dummy clock event source on SMP
448 * systems, so the broadcast mechanism is used. On UP systems simply
451 if (disable_apic_timer
) {
452 printk(KERN_INFO
"Disabling APIC timer\n");
453 /* No broadcast on UP ! */
454 if (num_possible_cpus() > 1) {
455 lapic_clockevent
.mult
= 1;
461 printk(KERN_INFO
"Using local APIC timer interrupts.\n");
462 calibrate_APIC_clock();
465 * Do a sanity check on the APIC calibration result
467 if (calibration_result
< (1000000 / HZ
)) {
469 "APIC frequency too slow, disabling apic timer\n");
470 /* No broadcast on UP ! */
471 if (num_possible_cpus() > 1)
477 * If nmi_watchdog is set to IO_APIC, we need the
478 * PIT/HPET going. Otherwise register lapic as a dummy
481 if (nmi_watchdog
!= NMI_IO_APIC
)
482 lapic_clockevent
.features
&= ~CLOCK_EVT_FEAT_DUMMY
;
484 printk(KERN_WARNING
"APIC timer registered as dummy,"
485 " due to nmi_watchdog=%d!\n", nmi_watchdog
);
490 void __cpuinit
setup_secondary_APIC_clock(void)
496 * The guts of the apic timer interrupt
498 static void local_apic_timer_interrupt(void)
500 int cpu
= smp_processor_id();
501 struct clock_event_device
*evt
= &per_cpu(lapic_events
, cpu
);
504 * Normally we should not be here till LAPIC has been initialized but
505 * in some cases like kdump, its possible that there is a pending LAPIC
506 * timer interrupt from previous kernel's context and is delivered in
507 * new kernel the moment interrupts are enabled.
509 * Interrupts are enabled early and LAPIC is setup much later, hence
510 * its possible that when we get here evt->event_handler is NULL.
511 * Check for event_handler being NULL and discard the interrupt as
514 if (!evt
->event_handler
) {
516 "Spurious LAPIC timer interrupt on cpu %d\n", cpu
);
518 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, evt
);
523 * the NMI deadlock-detector uses this.
525 add_pda(apic_timer_irqs
, 1);
527 evt
->event_handler(evt
);
531 * Local APIC timer interrupt. This is the most natural way for doing
532 * local interrupts, but local timer interrupts can be emulated by
533 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
535 * [ if a single-CPU system runs an SMP kernel then we call the local
536 * interrupt as well. Thus we cannot inline the local irq ... ]
538 void smp_apic_timer_interrupt(struct pt_regs
*regs
)
540 struct pt_regs
*old_regs
= set_irq_regs(regs
);
543 * NOTE! We'd better ACK the irq immediately,
544 * because timer handling can be slow.
548 * update_process_times() expects us to have done irq_enter().
549 * Besides, if we don't timer interrupts ignore the global
550 * interrupt lock, which is the WrongThing (tm) to do.
554 local_apic_timer_interrupt();
556 set_irq_regs(old_regs
);
559 int setup_profiling_timer(unsigned int multiplier
)
566 * Local APIC start and shutdown
570 * clear_local_APIC - shutdown the local APIC
572 * This is called, when a CPU is disabled and before rebooting, so the state of
573 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
574 * leftovers during boot.
576 void clear_local_APIC(void)
581 /* APIC hasn't been mapped yet */
585 maxlvt
= lapic_get_maxlvt();
587 * Masking an LVT entry can trigger a local APIC error
588 * if the vector is zero. Mask LVTERR first to prevent this.
591 v
= ERROR_APIC_VECTOR
; /* any non-zero vector will do */
592 apic_write(APIC_LVTERR
, v
| APIC_LVT_MASKED
);
595 * Careful: we have to set masks only first to deassert
596 * any level-triggered sources.
598 v
= apic_read(APIC_LVTT
);
599 apic_write(APIC_LVTT
, v
| APIC_LVT_MASKED
);
600 v
= apic_read(APIC_LVT0
);
601 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
602 v
= apic_read(APIC_LVT1
);
603 apic_write(APIC_LVT1
, v
| APIC_LVT_MASKED
);
605 v
= apic_read(APIC_LVTPC
);
606 apic_write(APIC_LVTPC
, v
| APIC_LVT_MASKED
);
610 * Clean APIC state for other OSs:
612 apic_write(APIC_LVTT
, APIC_LVT_MASKED
);
613 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
614 apic_write(APIC_LVT1
, APIC_LVT_MASKED
);
616 apic_write(APIC_LVTERR
, APIC_LVT_MASKED
);
618 apic_write(APIC_LVTPC
, APIC_LVT_MASKED
);
619 apic_write(APIC_ESR
, 0);
624 * disable_local_APIC - clear and disable the local APIC
626 void disable_local_APIC(void)
633 * Disable APIC (implies clearing of registers
636 value
= apic_read(APIC_SPIV
);
637 value
&= ~APIC_SPIV_APIC_ENABLED
;
638 apic_write(APIC_SPIV
, value
);
641 void lapic_shutdown(void)
648 local_irq_save(flags
);
650 disable_local_APIC();
652 local_irq_restore(flags
);
656 * This is to verify that we're looking at a real local APIC.
657 * Check these against your board if the CPUs aren't getting
658 * started for no apparent reason.
660 int __init
verify_local_APIC(void)
662 unsigned int reg0
, reg1
;
665 * The version register is read-only in a real APIC.
667 reg0
= apic_read(APIC_LVR
);
668 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg0
);
669 apic_write(APIC_LVR
, reg0
^ APIC_LVR_MASK
);
670 reg1
= apic_read(APIC_LVR
);
671 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg1
);
674 * The two version reads above should print the same
675 * numbers. If the second one is different, then we
676 * poke at a non-APIC.
682 * Check if the version looks reasonably.
684 reg1
= GET_APIC_VERSION(reg0
);
685 if (reg1
== 0x00 || reg1
== 0xff)
687 reg1
= lapic_get_maxlvt();
688 if (reg1
< 0x02 || reg1
== 0xff)
692 * The ID register is read/write in a real APIC.
694 reg0
= apic_read(APIC_ID
);
695 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg0
);
696 apic_write(APIC_ID
, reg0
^ APIC_ID_MASK
);
697 reg1
= apic_read(APIC_ID
);
698 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg1
);
699 apic_write(APIC_ID
, reg0
);
700 if (reg1
!= (reg0
^ APIC_ID_MASK
))
704 * The next two are just to see if we have sane values.
705 * They're only really relevant if we're in Virtual Wire
706 * compatibility mode, but most boxes are anymore.
708 reg0
= apic_read(APIC_LVT0
);
709 apic_printk(APIC_DEBUG
, "Getting LVT0: %x\n", reg0
);
710 reg1
= apic_read(APIC_LVT1
);
711 apic_printk(APIC_DEBUG
, "Getting LVT1: %x\n", reg1
);
717 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
719 void __init
sync_Arb_IDs(void)
721 /* Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 */
728 apic_wait_icr_idle();
730 apic_printk(APIC_DEBUG
, "Synchronizing Arb IDs.\n");
731 apic_write(APIC_ICR
, APIC_DEST_ALLINC
| APIC_INT_LEVELTRIG
736 * An initial setup of the virtual wire mode.
738 void __init
init_bsp_APIC(void)
743 * Don't do the setup now if we have a SMP BIOS as the
744 * through-I/O-APIC virtual wire mode might be active.
746 if (smp_found_config
|| !cpu_has_apic
)
749 value
= apic_read(APIC_LVR
);
752 * Do not trust the local APIC being empty at bootup.
759 value
= apic_read(APIC_SPIV
);
760 value
&= ~APIC_VECTOR_MASK
;
761 value
|= APIC_SPIV_APIC_ENABLED
;
762 value
|= APIC_SPIV_FOCUS_DISABLED
;
763 value
|= SPURIOUS_APIC_VECTOR
;
764 apic_write(APIC_SPIV
, value
);
767 * Set up the virtual wire mode.
769 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
771 apic_write(APIC_LVT1
, value
);
775 * setup_local_APIC - setup the local APIC
777 void __cpuinit
setup_local_APIC(void)
783 value
= apic_read(APIC_LVR
);
785 BUILD_BUG_ON((SPURIOUS_APIC_VECTOR
& 0x0f) != 0x0f);
788 * Double-check whether this APIC is really registered.
789 * This is meaningless in clustered apic mode, so we skip it.
791 if (!apic_id_registered())
795 * Intel recommends to set DFR, LDR and TPR before enabling
796 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
797 * document number 292116). So here it goes...
802 * Set Task Priority to 'accept all'. We never change this
805 value
= apic_read(APIC_TASKPRI
);
806 value
&= ~APIC_TPRI_MASK
;
807 apic_write(APIC_TASKPRI
, value
);
810 * After a crash, we no longer service the interrupts and a pending
811 * interrupt from previous kernel might still have ISR bit set.
813 * Most probably by now CPU has serviced that pending interrupt and
814 * it might not have done the ack_APIC_irq() because it thought,
815 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
816 * does not clear the ISR bit and cpu thinks it has already serivced
817 * the interrupt. Hence a vector might get locked. It was noticed
818 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
820 for (i
= APIC_ISR_NR
- 1; i
>= 0; i
--) {
821 value
= apic_read(APIC_ISR
+ i
*0x10);
822 for (j
= 31; j
>= 0; j
--) {
829 * Now that we are all set up, enable the APIC
831 value
= apic_read(APIC_SPIV
);
832 value
&= ~APIC_VECTOR_MASK
;
836 value
|= APIC_SPIV_APIC_ENABLED
;
838 /* We always use processor focus */
841 * Set spurious IRQ vector
843 value
|= SPURIOUS_APIC_VECTOR
;
844 apic_write(APIC_SPIV
, value
);
849 * set up through-local-APIC on the BP's LINT0. This is not
850 * strictly necessary in pure symmetric-IO mode, but sometimes
851 * we delegate interrupts to the 8259A.
854 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
856 value
= apic_read(APIC_LVT0
) & APIC_LVT_MASKED
;
857 if (!smp_processor_id() && !value
) {
858 value
= APIC_DM_EXTINT
;
859 apic_printk(APIC_VERBOSE
, "enabled ExtINT on CPU#%d\n",
862 value
= APIC_DM_EXTINT
| APIC_LVT_MASKED
;
863 apic_printk(APIC_VERBOSE
, "masked ExtINT on CPU#%d\n",
866 apic_write(APIC_LVT0
, value
);
869 * only the BP should see the LINT1 NMI signal, obviously.
871 if (!smp_processor_id())
874 value
= APIC_DM_NMI
| APIC_LVT_MASKED
;
875 apic_write(APIC_LVT1
, value
);
879 static void __cpuinit
lapic_setup_esr(void)
881 unsigned maxlvt
= lapic_get_maxlvt();
883 apic_write(APIC_LVTERR
, ERROR_APIC_VECTOR
);
885 * spec says clear errors after enabling vector.
888 apic_write(APIC_ESR
, 0);
891 void __cpuinit
end_local_APIC_setup(void)
894 setup_apic_nmi_watchdog(NULL
);
899 * Detect and enable local APICs on non-SMP boards.
900 * Original code written by Keir Fraser.
901 * On AMD64 we trust the BIOS - if it says no APIC it is likely
902 * not correctly set up (usually the APIC timer won't work etc.)
904 static int __init
detect_init_APIC(void)
907 printk(KERN_INFO
"No local APIC present\n");
911 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
912 boot_cpu_physical_apicid
= 0;
916 void __init
early_init_lapic_mapping(void)
918 unsigned long phys_addr
;
921 * If no local APIC can be found then go out
922 * : it means there is no mpatable and MADT
924 if (!smp_found_config
)
927 phys_addr
= mp_lapic_addr
;
929 set_fixmap_nocache(FIX_APIC_BASE
, phys_addr
);
930 apic_printk(APIC_VERBOSE
, "mapped APIC to %16lx (%16lx)\n",
931 APIC_BASE
, phys_addr
);
934 * Fetch the APIC ID of the BSP in case we have a
935 * default configuration (or the MP table is broken).
937 boot_cpu_physical_apicid
= GET_APIC_ID(read_apic_id());
941 * init_apic_mappings - initialize APIC mappings
943 void __init
init_apic_mappings(void)
946 * If no local APIC can be found then set up a fake all
947 * zeroes page to simulate the local APIC and another
948 * one for the IO-APIC.
950 if (!smp_found_config
&& detect_init_APIC()) {
951 apic_phys
= (unsigned long) alloc_bootmem_pages(PAGE_SIZE
);
952 apic_phys
= __pa(apic_phys
);
954 apic_phys
= mp_lapic_addr
;
956 set_fixmap_nocache(FIX_APIC_BASE
, apic_phys
);
957 apic_printk(APIC_VERBOSE
, "mapped APIC to %16lx (%16lx)\n",
958 APIC_BASE
, apic_phys
);
961 * Fetch the APIC ID of the BSP in case we have a
962 * default configuration (or the MP table is broken).
964 boot_cpu_physical_apicid
= GET_APIC_ID(read_apic_id());
968 * This initializes the IO-APIC and APIC hardware if this is
971 int __init
APIC_init_uniprocessor(void)
974 printk(KERN_INFO
"Apic disabled\n");
979 printk(KERN_INFO
"Apic disabled by BIOS\n");
987 physid_set_mask_of_physid(boot_cpu_physical_apicid
, &phys_cpu_present_map
);
988 apic_write(APIC_ID
, SET_APIC_ID(boot_cpu_physical_apicid
));
993 * Now enable IO-APICs, actually call clear_IO_APIC
994 * We need clear_IO_APIC before enabling vector on BP
996 if (!skip_ioapic_setup
&& nr_ioapics
)
999 if (!smp_found_config
|| skip_ioapic_setup
|| !nr_ioapics
)
1000 localise_nmi_watchdog();
1001 end_local_APIC_setup();
1003 if (smp_found_config
&& !skip_ioapic_setup
&& nr_ioapics
)
1007 setup_boot_APIC_clock();
1008 check_nmi_watchdog();
1013 * Local APIC interrupts
1017 * This interrupt should _never_ happen with our APIC/SMP architecture
1019 asmlinkage
void smp_spurious_interrupt(void)
1025 * Check if this really is a spurious interrupt and ACK it
1026 * if it is a vectored one. Just in case...
1027 * Spurious interrupts should not be ACKed.
1029 v
= apic_read(APIC_ISR
+ ((SPURIOUS_APIC_VECTOR
& ~0x1f) >> 1));
1030 if (v
& (1 << (SPURIOUS_APIC_VECTOR
& 0x1f)))
1033 add_pda(irq_spurious_count
, 1);
1038 * This interrupt should never happen with our APIC/SMP architecture
1040 asmlinkage
void smp_error_interrupt(void)
1046 /* First tickle the hardware, only then report what went on. -- REW */
1047 v
= apic_read(APIC_ESR
);
1048 apic_write(APIC_ESR
, 0);
1049 v1
= apic_read(APIC_ESR
);
1051 atomic_inc(&irq_err_count
);
1053 /* Here is what the APIC error bits mean:
1056 2: Send accept error
1057 3: Receive accept error
1059 5: Send illegal vector
1060 6: Received illegal vector
1061 7: Illegal register address
1063 printk(KERN_DEBUG
"APIC error on CPU%d: %02x(%02x)\n",
1064 smp_processor_id(), v
, v1
);
1069 * * connect_bsp_APIC - attach the APIC to the interrupt system
1071 void __init
connect_bsp_APIC(void)
1076 void disconnect_bsp_APIC(int virt_wire_setup
)
1078 /* Go back to Virtual Wire compatibility mode */
1079 unsigned long value
;
1081 /* For the spurious interrupt use vector F, and enable it */
1082 value
= apic_read(APIC_SPIV
);
1083 value
&= ~APIC_VECTOR_MASK
;
1084 value
|= APIC_SPIV_APIC_ENABLED
;
1086 apic_write(APIC_SPIV
, value
);
1088 if (!virt_wire_setup
) {
1090 * For LVT0 make it edge triggered, active high,
1091 * external and enabled
1093 value
= apic_read(APIC_LVT0
);
1094 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1095 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1096 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1097 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1098 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_EXTINT
);
1099 apic_write(APIC_LVT0
, value
);
1102 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
1105 /* For LVT1 make it edge triggered, active high, nmi and enabled */
1106 value
= apic_read(APIC_LVT1
);
1107 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1108 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1109 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1110 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1111 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_NMI
);
1112 apic_write(APIC_LVT1
, value
);
1115 void __cpuinit
generic_processor_info(int apicid
, int version
)
1120 if (num_processors
>= NR_CPUS
) {
1121 printk(KERN_WARNING
"WARNING: NR_CPUS limit of %i reached."
1122 " Processor ignored.\n", NR_CPUS
);
1126 if (num_processors
>= maxcpus
) {
1127 printk(KERN_WARNING
"WARNING: maxcpus limit of %i reached."
1128 " Processor ignored.\n", maxcpus
);
1133 cpus_complement(tmp_map
, cpu_present_map
);
1134 cpu
= first_cpu(tmp_map
);
1136 physid_set(apicid
, phys_cpu_present_map
);
1137 if (apicid
== boot_cpu_physical_apicid
) {
1139 * x86_bios_cpu_apicid is required to have processors listed
1140 * in same order as logical cpu numbers. Hence the first
1141 * entry is BSP, and so on.
1145 if (apicid
> max_physical_apicid
)
1146 max_physical_apicid
= apicid
;
1148 /* are we being called early in kernel startup? */
1149 if (early_per_cpu_ptr(x86_cpu_to_apicid
)) {
1150 u16
*cpu_to_apicid
= early_per_cpu_ptr(x86_cpu_to_apicid
);
1151 u16
*bios_cpu_apicid
= early_per_cpu_ptr(x86_bios_cpu_apicid
);
1153 cpu_to_apicid
[cpu
] = apicid
;
1154 bios_cpu_apicid
[cpu
] = apicid
;
1156 per_cpu(x86_cpu_to_apicid
, cpu
) = apicid
;
1157 per_cpu(x86_bios_cpu_apicid
, cpu
) = apicid
;
1160 cpu_set(cpu
, cpu_possible_map
);
1161 cpu_set(cpu
, cpu_present_map
);
1164 int hard_smp_processor_id(void)
1166 return read_apic_id();
1175 /* 'active' is true if the local APIC was enabled by us and
1176 not the BIOS; this signifies that we are also responsible
1177 for disabling it before entering apm/acpi suspend */
1179 /* r/w apic fields */
1180 unsigned int apic_id
;
1181 unsigned int apic_taskpri
;
1182 unsigned int apic_ldr
;
1183 unsigned int apic_dfr
;
1184 unsigned int apic_spiv
;
1185 unsigned int apic_lvtt
;
1186 unsigned int apic_lvtpc
;
1187 unsigned int apic_lvt0
;
1188 unsigned int apic_lvt1
;
1189 unsigned int apic_lvterr
;
1190 unsigned int apic_tmict
;
1191 unsigned int apic_tdcr
;
1192 unsigned int apic_thmr
;
1195 static int lapic_suspend(struct sys_device
*dev
, pm_message_t state
)
1197 unsigned long flags
;
1200 if (!apic_pm_state
.active
)
1203 maxlvt
= lapic_get_maxlvt();
1205 apic_pm_state
.apic_id
= apic_read(APIC_ID
);
1206 apic_pm_state
.apic_taskpri
= apic_read(APIC_TASKPRI
);
1207 apic_pm_state
.apic_ldr
= apic_read(APIC_LDR
);
1208 apic_pm_state
.apic_dfr
= apic_read(APIC_DFR
);
1209 apic_pm_state
.apic_spiv
= apic_read(APIC_SPIV
);
1210 apic_pm_state
.apic_lvtt
= apic_read(APIC_LVTT
);
1212 apic_pm_state
.apic_lvtpc
= apic_read(APIC_LVTPC
);
1213 apic_pm_state
.apic_lvt0
= apic_read(APIC_LVT0
);
1214 apic_pm_state
.apic_lvt1
= apic_read(APIC_LVT1
);
1215 apic_pm_state
.apic_lvterr
= apic_read(APIC_LVTERR
);
1216 apic_pm_state
.apic_tmict
= apic_read(APIC_TMICT
);
1217 apic_pm_state
.apic_tdcr
= apic_read(APIC_TDCR
);
1218 #ifdef CONFIG_X86_MCE_INTEL
1220 apic_pm_state
.apic_thmr
= apic_read(APIC_LVTTHMR
);
1222 local_irq_save(flags
);
1223 disable_local_APIC();
1224 local_irq_restore(flags
);
1228 static int lapic_resume(struct sys_device
*dev
)
1231 unsigned long flags
;
1234 if (!apic_pm_state
.active
)
1237 maxlvt
= lapic_get_maxlvt();
1239 local_irq_save(flags
);
1240 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1241 l
&= ~MSR_IA32_APICBASE_BASE
;
1242 l
|= MSR_IA32_APICBASE_ENABLE
| mp_lapic_addr
;
1243 wrmsr(MSR_IA32_APICBASE
, l
, h
);
1244 apic_write(APIC_LVTERR
, ERROR_APIC_VECTOR
| APIC_LVT_MASKED
);
1245 apic_write(APIC_ID
, apic_pm_state
.apic_id
);
1246 apic_write(APIC_DFR
, apic_pm_state
.apic_dfr
);
1247 apic_write(APIC_LDR
, apic_pm_state
.apic_ldr
);
1248 apic_write(APIC_TASKPRI
, apic_pm_state
.apic_taskpri
);
1249 apic_write(APIC_SPIV
, apic_pm_state
.apic_spiv
);
1250 apic_write(APIC_LVT0
, apic_pm_state
.apic_lvt0
);
1251 apic_write(APIC_LVT1
, apic_pm_state
.apic_lvt1
);
1252 #ifdef CONFIG_X86_MCE_INTEL
1254 apic_write(APIC_LVTTHMR
, apic_pm_state
.apic_thmr
);
1257 apic_write(APIC_LVTPC
, apic_pm_state
.apic_lvtpc
);
1258 apic_write(APIC_LVTT
, apic_pm_state
.apic_lvtt
);
1259 apic_write(APIC_TDCR
, apic_pm_state
.apic_tdcr
);
1260 apic_write(APIC_TMICT
, apic_pm_state
.apic_tmict
);
1261 apic_write(APIC_ESR
, 0);
1262 apic_read(APIC_ESR
);
1263 apic_write(APIC_LVTERR
, apic_pm_state
.apic_lvterr
);
1264 apic_write(APIC_ESR
, 0);
1265 apic_read(APIC_ESR
);
1266 local_irq_restore(flags
);
1270 static struct sysdev_class lapic_sysclass
= {
1272 .resume
= lapic_resume
,
1273 .suspend
= lapic_suspend
,
1276 static struct sys_device device_lapic
= {
1278 .cls
= &lapic_sysclass
,
1281 static void __cpuinit
apic_pm_activate(void)
1283 apic_pm_state
.active
= 1;
1286 static int __init
init_lapic_sysfs(void)
1292 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
1294 error
= sysdev_class_register(&lapic_sysclass
);
1296 error
= sysdev_register(&device_lapic
);
1299 device_initcall(init_lapic_sysfs
);
1301 #else /* CONFIG_PM */
1303 static void apic_pm_activate(void) { }
1305 #endif /* CONFIG_PM */
1308 * apic_is_clustered_box() -- Check if we can expect good TSC
1310 * Thus far, the major user of this is IBM's Summit2 series:
1312 * Clustered boxes may have unsynced TSC problems if they are
1313 * multi-chassis. Use available data to take a good guess.
1314 * If in doubt, go HPET.
1316 __cpuinit
int apic_is_clustered_box(void)
1318 int i
, clusters
, zeros
;
1320 u16
*bios_cpu_apicid
;
1321 DECLARE_BITMAP(clustermap
, NUM_APIC_CLUSTERS
);
1324 * there is not this kind of box with AMD CPU yet.
1325 * Some AMD box with quadcore cpu and 8 sockets apicid
1326 * will be [4, 0x23] or [8, 0x27] could be thought to
1327 * vsmp box still need checking...
1329 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
) && !is_vsmp_box())
1332 bios_cpu_apicid
= early_per_cpu_ptr(x86_bios_cpu_apicid
);
1333 bitmap_zero(clustermap
, NUM_APIC_CLUSTERS
);
1335 for (i
= 0; i
< NR_CPUS
; i
++) {
1336 /* are we being called early in kernel startup? */
1337 if (bios_cpu_apicid
) {
1338 id
= bios_cpu_apicid
[i
];
1340 else if (i
< nr_cpu_ids
) {
1342 id
= per_cpu(x86_bios_cpu_apicid
, i
);
1349 if (id
!= BAD_APICID
)
1350 __set_bit(APIC_CLUSTERID(id
), clustermap
);
1353 /* Problem: Partially populated chassis may not have CPUs in some of
1354 * the APIC clusters they have been allocated. Only present CPUs have
1355 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap.
1356 * Since clusters are allocated sequentially, count zeros only if
1357 * they are bounded by ones.
1361 for (i
= 0; i
< NUM_APIC_CLUSTERS
; i
++) {
1362 if (test_bit(i
, clustermap
)) {
1363 clusters
+= 1 + zeros
;
1369 /* ScaleMP vSMPowered boxes have one cluster per board and TSCs are
1370 * not guaranteed to be synced between boards
1372 if (is_vsmp_box() && clusters
> 1)
1376 * If clusters > 2, then should be multi-chassis.
1377 * May have to revisit this when multi-core + hyperthreaded CPUs come
1378 * out, but AFAIK this will work even for them.
1380 return (clusters
> 2);
1384 * APIC command line parameters
1386 static int __init
apic_set_verbosity(char *str
)
1389 skip_ioapic_setup
= 0;
1393 if (strcmp("debug", str
) == 0)
1394 apic_verbosity
= APIC_DEBUG
;
1395 else if (strcmp("verbose", str
) == 0)
1396 apic_verbosity
= APIC_VERBOSE
;
1398 printk(KERN_WARNING
"APIC Verbosity level %s not recognised"
1399 " use apic=verbose or apic=debug\n", str
);
1405 early_param("apic", apic_set_verbosity
);
1407 static __init
int setup_disableapic(char *str
)
1410 clear_cpu_cap(&boot_cpu_data
, X86_FEATURE_APIC
);
1413 early_param("disableapic", setup_disableapic
);
1415 /* same as disableapic, for compatibility */
1416 static __init
int setup_nolapic(char *str
)
1418 return setup_disableapic(str
);
1420 early_param("nolapic", setup_nolapic
);
1422 static int __init
parse_lapic_timer_c2_ok(char *arg
)
1424 local_apic_timer_c2_ok
= 1;
1427 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok
);
1429 static __init
int setup_noapictimer(char *str
)
1431 if (str
[0] != ' ' && str
[0] != 0)
1433 disable_apic_timer
= 1;
1436 __setup("noapictimer", setup_noapictimer
);
1438 static __init
int setup_apicpmtimer(char *s
)
1440 apic_calibrate_pmtmr
= 1;
1444 __setup("apicpmtimer", setup_apicpmtimer
);
1446 static int __init
lapic_insert_resource(void)
1451 /* Put local APIC into the resource map. */
1452 lapic_resource
.start
= apic_phys
;
1453 lapic_resource
.end
= lapic_resource
.start
+ PAGE_SIZE
- 1;
1454 insert_resource(&iomem_resource
, &lapic_resource
);
1460 * need call insert after e820_reserve_resources()
1461 * that is using request_resource
1463 late_initcall(lapic_insert_resource
);