2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/bootmem.h>
22 #include <linux/interrupt.h>
23 #include <linux/mc146818rtc.h>
24 #include <linux/kernel_stat.h>
25 #include <linux/sysdev.h>
26 #include <linux/module.h>
27 #include <linux/ioport.h>
28 #include <linux/clockchips.h>
29 #include <linux/acpi_pmtmr.h>
31 #include <asm/atomic.h>
34 #include <asm/mpspec.h>
35 #include <asm/pgalloc.h>
36 #include <asm/mach_apic.h>
39 #include <asm/proto.h>
40 #include <asm/timex.h>
45 int disable_apic_timer __cpuinitdata
;
46 static int apic_calibrate_pmtmr __initdata
;
49 /* Local APIC timer works in C2? */
50 int local_apic_timer_c2_ok
;
51 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok
);
53 static struct resource lapic_resource
= {
55 .flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
,
58 static unsigned int calibration_result
;
60 static int lapic_next_event(unsigned long delta
,
61 struct clock_event_device
*evt
);
62 static void lapic_timer_setup(enum clock_event_mode mode
,
63 struct clock_event_device
*evt
);
64 static void lapic_timer_broadcast(cpumask_t mask
);
65 static void apic_pm_activate(void);
67 static struct clock_event_device lapic_clockevent
= {
69 .features
= CLOCK_EVT_FEAT_PERIODIC
| CLOCK_EVT_FEAT_ONESHOT
70 | CLOCK_EVT_FEAT_C3STOP
| CLOCK_EVT_FEAT_DUMMY
,
72 .set_mode
= lapic_timer_setup
,
73 .set_next_event
= lapic_next_event
,
74 .broadcast
= lapic_timer_broadcast
,
78 static DEFINE_PER_CPU(struct clock_event_device
, lapic_events
);
81 * Get the LAPIC version
83 static inline int lapic_get_version(void)
85 return GET_APIC_VERSION(apic_read(APIC_LVR
));
89 * Check, if the APIC is integrated or a seperate chip
91 static inline int lapic_is_integrated(void)
97 * Check, whether this is a modern or a first generation APIC
99 static int modern_apic(void)
101 /* AMD systems use old APIC versions, so check the CPU */
102 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
&&
103 boot_cpu_data
.x86
>= 0xf)
105 return lapic_get_version() >= 0x14;
108 void apic_wait_icr_idle(void)
110 while (apic_read(APIC_ICR
) & APIC_ICR_BUSY
)
114 u32
safe_apic_wait_icr_idle(void)
121 send_status
= apic_read(APIC_ICR
) & APIC_ICR_BUSY
;
125 } while (timeout
++ < 1000);
131 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
133 void enable_NMI_through_LVT0(void *dummy
)
137 /* unmask and set to NMI */
139 apic_write(APIC_LVT0
, v
);
143 * lapic_get_maxlvt - get the maximum number of local vector table entries
145 int lapic_get_maxlvt(void)
147 unsigned int v
, maxlvt
;
149 v
= apic_read(APIC_LVR
);
150 maxlvt
= GET_APIC_MAXLVT(v
);
155 * This function sets up the local APIC timer, with a timeout of
156 * 'clocks' APIC bus clock. During calibration we actually call
157 * this function twice on the boot CPU, once with a bogus timeout
158 * value, second time for real. The other (noncalibrating) CPUs
159 * call this function only once, with the real, calibrated value.
161 * We do reads before writes even if unnecessary, to get around the
162 * P5 APIC double write bug.
165 static void __setup_APIC_LVTT(unsigned int clocks
, int oneshot
, int irqen
)
167 unsigned int lvtt_value
, tmp_value
;
169 lvtt_value
= LOCAL_TIMER_VECTOR
;
171 lvtt_value
|= APIC_LVT_TIMER_PERIODIC
;
173 lvtt_value
|= APIC_LVT_MASKED
;
175 apic_write(APIC_LVTT
, lvtt_value
);
180 tmp_value
= apic_read(APIC_TDCR
);
181 apic_write(APIC_TDCR
, (tmp_value
182 & ~(APIC_TDR_DIV_1
| APIC_TDR_DIV_TMBASE
))
186 apic_write(APIC_TMICT
, clocks
);
190 * Setup extended LVT, AMD specific (K8, family 10h)
192 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
193 * MCE interrupts are supported. Thus MCE offset must be set to 0.
196 #define APIC_EILVT_LVTOFF_MCE 0
197 #define APIC_EILVT_LVTOFF_IBS 1
199 static void setup_APIC_eilvt(u8 lvt_off
, u8 vector
, u8 msg_type
, u8 mask
)
201 unsigned long reg
= (lvt_off
<< 4) + APIC_EILVT0
;
202 unsigned int v
= (mask
<< 16) | (msg_type
<< 8) | vector
;
207 u8
setup_APIC_eilvt_mce(u8 vector
, u8 msg_type
, u8 mask
)
209 setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE
, vector
, msg_type
, mask
);
210 return APIC_EILVT_LVTOFF_MCE
;
213 u8
setup_APIC_eilvt_ibs(u8 vector
, u8 msg_type
, u8 mask
)
215 setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS
, vector
, msg_type
, mask
);
216 return APIC_EILVT_LVTOFF_IBS
;
220 * Program the next event, relative to now
222 static int lapic_next_event(unsigned long delta
,
223 struct clock_event_device
*evt
)
225 apic_write(APIC_TMICT
, delta
);
230 * Setup the lapic timer in periodic or oneshot mode
232 static void lapic_timer_setup(enum clock_event_mode mode
,
233 struct clock_event_device
*evt
)
238 /* Lapic used as dummy for broadcast ? */
239 if (evt
->features
& CLOCK_EVT_FEAT_DUMMY
)
242 local_irq_save(flags
);
245 case CLOCK_EVT_MODE_PERIODIC
:
246 case CLOCK_EVT_MODE_ONESHOT
:
247 __setup_APIC_LVTT(calibration_result
,
248 mode
!= CLOCK_EVT_MODE_PERIODIC
, 1);
250 case CLOCK_EVT_MODE_UNUSED
:
251 case CLOCK_EVT_MODE_SHUTDOWN
:
252 v
= apic_read(APIC_LVTT
);
253 v
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
254 apic_write(APIC_LVTT
, v
);
256 case CLOCK_EVT_MODE_RESUME
:
257 /* Nothing to do here */
261 local_irq_restore(flags
);
265 * Local APIC timer broadcast function
267 static void lapic_timer_broadcast(cpumask_t mask
)
270 send_IPI_mask(mask
, LOCAL_TIMER_VECTOR
);
275 * Setup the local APIC timer for this CPU. Copy the initilized values
276 * of the boot CPU and register the clock event in the framework.
278 static void setup_APIC_timer(void)
280 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
282 memcpy(levt
, &lapic_clockevent
, sizeof(*levt
));
283 levt
->cpumask
= cpumask_of_cpu(smp_processor_id());
285 clockevents_register_device(levt
);
289 * In this function we calibrate APIC bus clocks to the external
290 * timer. Unfortunately we cannot use jiffies and the timer irq
291 * to calibrate, since some later bootup code depends on getting
292 * the first irq? Ugh.
294 * We want to do the calibration only once since we
295 * want to have local timer irqs syncron. CPUs connected
296 * by the same APIC bus have the very same bus frequency.
297 * And we want to have irqs off anyways, no accidental
301 #define TICK_COUNT 100000000
303 static void __init
calibrate_APIC_clock(void)
305 unsigned apic
, apic_start
;
306 unsigned long tsc
, tsc_start
;
312 * Put whatever arbitrary (but long enough) timeout
313 * value into the APIC clock, we just want to get the
314 * counter running for calibration.
316 * No interrupt enable !
318 __setup_APIC_LVTT(250000000, 0, 0);
320 apic_start
= apic_read(APIC_TMCCT
);
321 #ifdef CONFIG_X86_PM_TIMER
322 if (apic_calibrate_pmtmr
&& pmtmr_ioport
) {
323 pmtimer_wait(5000); /* 5ms wait */
324 apic
= apic_read(APIC_TMCCT
);
325 result
= (apic_start
- apic
) * 1000L / 5;
332 apic
= apic_read(APIC_TMCCT
);
334 } while ((tsc
- tsc_start
) < TICK_COUNT
&&
335 (apic_start
- apic
) < TICK_COUNT
);
337 result
= (apic_start
- apic
) * 1000L * tsc_khz
/
343 printk(KERN_DEBUG
"APIC timer calibration result %d\n", result
);
345 printk(KERN_INFO
"Detected %d.%03d MHz APIC timer.\n",
346 result
/ 1000 / 1000, result
/ 1000 % 1000);
348 /* Calculate the scaled math multiplication factor */
349 lapic_clockevent
.mult
= div_sc(result
, NSEC_PER_SEC
, 32);
350 lapic_clockevent
.max_delta_ns
=
351 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent
);
352 lapic_clockevent
.min_delta_ns
=
353 clockevent_delta2ns(0xF, &lapic_clockevent
);
355 calibration_result
= result
/ HZ
;
358 void __init
setup_boot_APIC_clock(void)
361 * The local apic timer can be disabled via the kernel commandline.
362 * Register the lapic timer as a dummy clock event source on SMP
363 * systems, so the broadcast mechanism is used. On UP systems simply
366 if (disable_apic_timer
) {
367 printk(KERN_INFO
"Disabling APIC timer\n");
368 /* No broadcast on UP ! */
369 if (num_possible_cpus() > 1)
374 printk(KERN_INFO
"Using local APIC timer interrupts.\n");
375 calibrate_APIC_clock();
378 * If nmi_watchdog is set to IO_APIC, we need the
379 * PIT/HPET going. Otherwise register lapic as a dummy
382 if (nmi_watchdog
!= NMI_IO_APIC
)
383 lapic_clockevent
.features
&= ~CLOCK_EVT_FEAT_DUMMY
;
385 printk(KERN_WARNING
"APIC timer registered as dummy,"
386 " due to nmi_watchdog=1!\n");
392 * AMD C1E enabled CPUs have a real nasty problem: Some BIOSes set the
393 * C1E flag only in the secondary CPU, so when we detect the wreckage
394 * we already have enabled the boot CPU local apic timer. Check, if
395 * disable_apic_timer is set and the DUMMY flag is cleared. If yes,
396 * set the DUMMY flag again and force the broadcast mode in the
399 void __cpuinit
check_boot_apic_timer_broadcast(void)
401 if (!disable_apic_timer
||
402 (lapic_clockevent
.features
& CLOCK_EVT_FEAT_DUMMY
))
405 printk(KERN_INFO
"AMD C1E detected late. Force timer broadcast.\n");
406 lapic_clockevent
.features
|= CLOCK_EVT_FEAT_DUMMY
;
409 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE
, &boot_cpu_id
);
413 void __cpuinit
setup_secondary_APIC_clock(void)
415 check_boot_apic_timer_broadcast();
420 * The guts of the apic timer interrupt
422 static void local_apic_timer_interrupt(void)
424 int cpu
= smp_processor_id();
425 struct clock_event_device
*evt
= &per_cpu(lapic_events
, cpu
);
428 * Normally we should not be here till LAPIC has been initialized but
429 * in some cases like kdump, its possible that there is a pending LAPIC
430 * timer interrupt from previous kernel's context and is delivered in
431 * new kernel the moment interrupts are enabled.
433 * Interrupts are enabled early and LAPIC is setup much later, hence
434 * its possible that when we get here evt->event_handler is NULL.
435 * Check for event_handler being NULL and discard the interrupt as
438 if (!evt
->event_handler
) {
440 "Spurious LAPIC timer interrupt on cpu %d\n", cpu
);
442 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, evt
);
447 * the NMI deadlock-detector uses this.
449 add_pda(apic_timer_irqs
, 1);
451 evt
->event_handler(evt
);
455 * Local APIC timer interrupt. This is the most natural way for doing
456 * local interrupts, but local timer interrupts can be emulated by
457 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
459 * [ if a single-CPU system runs an SMP kernel then we call the local
460 * interrupt as well. Thus we cannot inline the local irq ... ]
462 void smp_apic_timer_interrupt(struct pt_regs
*regs
)
464 struct pt_regs
*old_regs
= set_irq_regs(regs
);
467 * NOTE! We'd better ACK the irq immediately,
468 * because timer handling can be slow.
472 * update_process_times() expects us to have done irq_enter().
473 * Besides, if we don't timer interrupts ignore the global
474 * interrupt lock, which is the WrongThing (tm) to do.
478 local_apic_timer_interrupt();
480 set_irq_regs(old_regs
);
483 int setup_profiling_timer(unsigned int multiplier
)
490 * Local APIC start and shutdown
494 * clear_local_APIC - shutdown the local APIC
496 * This is called, when a CPU is disabled and before rebooting, so the state of
497 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
498 * leftovers during boot.
500 void clear_local_APIC(void)
502 int maxlvt
= lapic_get_maxlvt();
506 * Masking an LVT entry can trigger a local APIC error
507 * if the vector is zero. Mask LVTERR first to prevent this.
510 v
= ERROR_APIC_VECTOR
; /* any non-zero vector will do */
511 apic_write(APIC_LVTERR
, v
| APIC_LVT_MASKED
);
514 * Careful: we have to set masks only first to deassert
515 * any level-triggered sources.
517 v
= apic_read(APIC_LVTT
);
518 apic_write(APIC_LVTT
, v
| APIC_LVT_MASKED
);
519 v
= apic_read(APIC_LVT0
);
520 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
521 v
= apic_read(APIC_LVT1
);
522 apic_write(APIC_LVT1
, v
| APIC_LVT_MASKED
);
524 v
= apic_read(APIC_LVTPC
);
525 apic_write(APIC_LVTPC
, v
| APIC_LVT_MASKED
);
529 * Clean APIC state for other OSs:
531 apic_write(APIC_LVTT
, APIC_LVT_MASKED
);
532 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
533 apic_write(APIC_LVT1
, APIC_LVT_MASKED
);
535 apic_write(APIC_LVTERR
, APIC_LVT_MASKED
);
537 apic_write(APIC_LVTPC
, APIC_LVT_MASKED
);
538 apic_write(APIC_ESR
, 0);
543 * disable_local_APIC - clear and disable the local APIC
545 void disable_local_APIC(void)
552 * Disable APIC (implies clearing of registers
555 value
= apic_read(APIC_SPIV
);
556 value
&= ~APIC_SPIV_APIC_ENABLED
;
557 apic_write(APIC_SPIV
, value
);
560 void lapic_shutdown(void)
567 local_irq_save(flags
);
569 disable_local_APIC();
571 local_irq_restore(flags
);
575 * This is to verify that we're looking at a real local APIC.
576 * Check these against your board if the CPUs aren't getting
577 * started for no apparent reason.
579 int __init
verify_local_APIC(void)
581 unsigned int reg0
, reg1
;
584 * The version register is read-only in a real APIC.
586 reg0
= apic_read(APIC_LVR
);
587 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg0
);
588 apic_write(APIC_LVR
, reg0
^ APIC_LVR_MASK
);
589 reg1
= apic_read(APIC_LVR
);
590 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg1
);
593 * The two version reads above should print the same
594 * numbers. If the second one is different, then we
595 * poke at a non-APIC.
601 * Check if the version looks reasonably.
603 reg1
= GET_APIC_VERSION(reg0
);
604 if (reg1
== 0x00 || reg1
== 0xff)
606 reg1
= lapic_get_maxlvt();
607 if (reg1
< 0x02 || reg1
== 0xff)
611 * The ID register is read/write in a real APIC.
613 reg0
= apic_read(APIC_ID
);
614 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg0
);
615 apic_write(APIC_ID
, reg0
^ APIC_ID_MASK
);
616 reg1
= apic_read(APIC_ID
);
617 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg1
);
618 apic_write(APIC_ID
, reg0
);
619 if (reg1
!= (reg0
^ APIC_ID_MASK
))
623 * The next two are just to see if we have sane values.
624 * They're only really relevant if we're in Virtual Wire
625 * compatibility mode, but most boxes are anymore.
627 reg0
= apic_read(APIC_LVT0
);
628 apic_printk(APIC_DEBUG
, "Getting LVT0: %x\n", reg0
);
629 reg1
= apic_read(APIC_LVT1
);
630 apic_printk(APIC_DEBUG
, "Getting LVT1: %x\n", reg1
);
636 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
638 void __init
sync_Arb_IDs(void)
640 /* Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 */
647 apic_wait_icr_idle();
649 apic_printk(APIC_DEBUG
, "Synchronizing Arb IDs.\n");
650 apic_write(APIC_ICR
, APIC_DEST_ALLINC
| APIC_INT_LEVELTRIG
655 * An initial setup of the virtual wire mode.
657 void __init
init_bsp_APIC(void)
662 * Don't do the setup now if we have a SMP BIOS as the
663 * through-I/O-APIC virtual wire mode might be active.
665 if (smp_found_config
|| !cpu_has_apic
)
668 value
= apic_read(APIC_LVR
);
671 * Do not trust the local APIC being empty at bootup.
678 value
= apic_read(APIC_SPIV
);
679 value
&= ~APIC_VECTOR_MASK
;
680 value
|= APIC_SPIV_APIC_ENABLED
;
681 value
|= APIC_SPIV_FOCUS_DISABLED
;
682 value
|= SPURIOUS_APIC_VECTOR
;
683 apic_write(APIC_SPIV
, value
);
686 * Set up the virtual wire mode.
688 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
690 apic_write(APIC_LVT1
, value
);
694 * setup_local_APIC - setup the local APIC
696 void __cpuinit
setup_local_APIC(void)
701 value
= apic_read(APIC_LVR
);
703 BUILD_BUG_ON((SPURIOUS_APIC_VECTOR
& 0x0f) != 0x0f);
706 * Double-check whether this APIC is really registered.
707 * This is meaningless in clustered apic mode, so we skip it.
709 if (!apic_id_registered())
713 * Intel recommends to set DFR, LDR and TPR before enabling
714 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
715 * document number 292116). So here it goes...
720 * Set Task Priority to 'accept all'. We never change this
723 value
= apic_read(APIC_TASKPRI
);
724 value
&= ~APIC_TPRI_MASK
;
725 apic_write(APIC_TASKPRI
, value
);
728 * After a crash, we no longer service the interrupts and a pending
729 * interrupt from previous kernel might still have ISR bit set.
731 * Most probably by now CPU has serviced that pending interrupt and
732 * it might not have done the ack_APIC_irq() because it thought,
733 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
734 * does not clear the ISR bit and cpu thinks it has already serivced
735 * the interrupt. Hence a vector might get locked. It was noticed
736 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
738 for (i
= APIC_ISR_NR
- 1; i
>= 0; i
--) {
739 value
= apic_read(APIC_ISR
+ i
*0x10);
740 for (j
= 31; j
>= 0; j
--) {
747 * Now that we are all set up, enable the APIC
749 value
= apic_read(APIC_SPIV
);
750 value
&= ~APIC_VECTOR_MASK
;
754 value
|= APIC_SPIV_APIC_ENABLED
;
756 /* We always use processor focus */
759 * Set spurious IRQ vector
761 value
|= SPURIOUS_APIC_VECTOR
;
762 apic_write(APIC_SPIV
, value
);
767 * set up through-local-APIC on the BP's LINT0. This is not
768 * strictly necessary in pure symmetric-IO mode, but sometimes
769 * we delegate interrupts to the 8259A.
772 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
774 value
= apic_read(APIC_LVT0
) & APIC_LVT_MASKED
;
775 if (!smp_processor_id() && !value
) {
776 value
= APIC_DM_EXTINT
;
777 apic_printk(APIC_VERBOSE
, "enabled ExtINT on CPU#%d\n",
780 value
= APIC_DM_EXTINT
| APIC_LVT_MASKED
;
781 apic_printk(APIC_VERBOSE
, "masked ExtINT on CPU#%d\n",
784 apic_write(APIC_LVT0
, value
);
787 * only the BP should see the LINT1 NMI signal, obviously.
789 if (!smp_processor_id())
792 value
= APIC_DM_NMI
| APIC_LVT_MASKED
;
793 apic_write(APIC_LVT1
, value
);
796 void __cpuinit
lapic_setup_esr(void)
798 unsigned maxlvt
= lapic_get_maxlvt();
800 apic_write(APIC_LVTERR
, ERROR_APIC_VECTOR
);
802 * spec says clear errors after enabling vector.
805 apic_write(APIC_ESR
, 0);
808 void __cpuinit
end_local_APIC_setup(void)
811 nmi_watchdog_default();
812 setup_apic_nmi_watchdog(NULL
);
817 * Detect and enable local APICs on non-SMP boards.
818 * Original code written by Keir Fraser.
819 * On AMD64 we trust the BIOS - if it says no APIC it is likely
820 * not correctly set up (usually the APIC timer won't work etc.)
822 static int __init
detect_init_APIC(void)
825 printk(KERN_INFO
"No local APIC present\n");
829 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
835 * init_apic_mappings - initialize APIC mappings
837 void __init
init_apic_mappings(void)
839 unsigned long apic_phys
;
842 * If no local APIC can be found then set up a fake all
843 * zeroes page to simulate the local APIC and another
844 * one for the IO-APIC.
846 if (!smp_found_config
&& detect_init_APIC()) {
847 apic_phys
= (unsigned long) alloc_bootmem_pages(PAGE_SIZE
);
848 apic_phys
= __pa(apic_phys
);
850 apic_phys
= mp_lapic_addr
;
852 set_fixmap_nocache(FIX_APIC_BASE
, apic_phys
);
853 apic_printk(APIC_VERBOSE
, "mapped APIC to %16lx (%16lx)\n",
854 APIC_BASE
, apic_phys
);
856 /* Put local APIC into the resource map. */
857 lapic_resource
.start
= apic_phys
;
858 lapic_resource
.end
= lapic_resource
.start
+ PAGE_SIZE
- 1;
859 insert_resource(&iomem_resource
, &lapic_resource
);
862 * Fetch the APIC ID of the BSP in case we have a
863 * default configuration (or the MP table is broken).
865 boot_cpu_id
= GET_APIC_ID(apic_read(APIC_ID
));
869 * This initializes the IO-APIC and APIC hardware if this is
872 int __init
APIC_init_uniprocessor(void)
875 printk(KERN_INFO
"Apic disabled\n");
880 printk(KERN_INFO
"Apic disabled by BIOS\n");
886 phys_cpu_present_map
= physid_mask_of_physid(boot_cpu_id
);
887 apic_write(APIC_ID
, SET_APIC_ID(boot_cpu_id
));
892 * Now enable IO-APICs, actually call clear_IO_APIC
893 * We need clear_IO_APIC before enabling vector on BP
895 if (!skip_ioapic_setup
&& nr_ioapics
)
898 end_local_APIC_setup();
900 if (smp_found_config
&& !skip_ioapic_setup
&& nr_ioapics
)
904 setup_boot_APIC_clock();
905 check_nmi_watchdog();
910 * Local APIC interrupts
914 * This interrupt should _never_ happen with our APIC/SMP architecture
916 asmlinkage
void smp_spurious_interrupt(void)
922 * Check if this really is a spurious interrupt and ACK it
923 * if it is a vectored one. Just in case...
924 * Spurious interrupts should not be ACKed.
926 v
= apic_read(APIC_ISR
+ ((SPURIOUS_APIC_VECTOR
& ~0x1f) >> 1));
927 if (v
& (1 << (SPURIOUS_APIC_VECTOR
& 0x1f)))
930 add_pda(irq_spurious_count
, 1);
935 * This interrupt should never happen with our APIC/SMP architecture
937 asmlinkage
void smp_error_interrupt(void)
943 /* First tickle the hardware, only then report what went on. -- REW */
944 v
= apic_read(APIC_ESR
);
945 apic_write(APIC_ESR
, 0);
946 v1
= apic_read(APIC_ESR
);
948 atomic_inc(&irq_err_count
);
950 /* Here is what the APIC error bits mean:
954 3: Receive accept error
956 5: Send illegal vector
957 6: Received illegal vector
958 7: Illegal register address
960 printk(KERN_DEBUG
"APIC error on CPU%d: %02x(%02x)\n",
961 smp_processor_id(), v
, v1
);
965 void disconnect_bsp_APIC(int virt_wire_setup
)
967 /* Go back to Virtual Wire compatibility mode */
970 /* For the spurious interrupt use vector F, and enable it */
971 value
= apic_read(APIC_SPIV
);
972 value
&= ~APIC_VECTOR_MASK
;
973 value
|= APIC_SPIV_APIC_ENABLED
;
975 apic_write(APIC_SPIV
, value
);
977 if (!virt_wire_setup
) {
979 * For LVT0 make it edge triggered, active high,
980 * external and enabled
982 value
= apic_read(APIC_LVT0
);
983 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
984 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
985 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
986 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
987 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_EXTINT
);
988 apic_write(APIC_LVT0
, value
);
991 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
994 /* For LVT1 make it edge triggered, active high, nmi and enabled */
995 value
= apic_read(APIC_LVT1
);
996 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
997 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
998 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
999 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1000 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_NMI
);
1001 apic_write(APIC_LVT1
, value
);
1010 /* 'active' is true if the local APIC was enabled by us and
1011 not the BIOS; this signifies that we are also responsible
1012 for disabling it before entering apm/acpi suspend */
1014 /* r/w apic fields */
1015 unsigned int apic_id
;
1016 unsigned int apic_taskpri
;
1017 unsigned int apic_ldr
;
1018 unsigned int apic_dfr
;
1019 unsigned int apic_spiv
;
1020 unsigned int apic_lvtt
;
1021 unsigned int apic_lvtpc
;
1022 unsigned int apic_lvt0
;
1023 unsigned int apic_lvt1
;
1024 unsigned int apic_lvterr
;
1025 unsigned int apic_tmict
;
1026 unsigned int apic_tdcr
;
1027 unsigned int apic_thmr
;
1030 static int lapic_suspend(struct sys_device
*dev
, pm_message_t state
)
1032 unsigned long flags
;
1035 if (!apic_pm_state
.active
)
1038 maxlvt
= lapic_get_maxlvt();
1040 apic_pm_state
.apic_id
= apic_read(APIC_ID
);
1041 apic_pm_state
.apic_taskpri
= apic_read(APIC_TASKPRI
);
1042 apic_pm_state
.apic_ldr
= apic_read(APIC_LDR
);
1043 apic_pm_state
.apic_dfr
= apic_read(APIC_DFR
);
1044 apic_pm_state
.apic_spiv
= apic_read(APIC_SPIV
);
1045 apic_pm_state
.apic_lvtt
= apic_read(APIC_LVTT
);
1047 apic_pm_state
.apic_lvtpc
= apic_read(APIC_LVTPC
);
1048 apic_pm_state
.apic_lvt0
= apic_read(APIC_LVT0
);
1049 apic_pm_state
.apic_lvt1
= apic_read(APIC_LVT1
);
1050 apic_pm_state
.apic_lvterr
= apic_read(APIC_LVTERR
);
1051 apic_pm_state
.apic_tmict
= apic_read(APIC_TMICT
);
1052 apic_pm_state
.apic_tdcr
= apic_read(APIC_TDCR
);
1053 #ifdef CONFIG_X86_MCE_INTEL
1055 apic_pm_state
.apic_thmr
= apic_read(APIC_LVTTHMR
);
1057 local_irq_save(flags
);
1058 disable_local_APIC();
1059 local_irq_restore(flags
);
1063 static int lapic_resume(struct sys_device
*dev
)
1066 unsigned long flags
;
1069 if (!apic_pm_state
.active
)
1072 maxlvt
= lapic_get_maxlvt();
1074 local_irq_save(flags
);
1075 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1076 l
&= ~MSR_IA32_APICBASE_BASE
;
1077 l
|= MSR_IA32_APICBASE_ENABLE
| mp_lapic_addr
;
1078 wrmsr(MSR_IA32_APICBASE
, l
, h
);
1079 apic_write(APIC_LVTERR
, ERROR_APIC_VECTOR
| APIC_LVT_MASKED
);
1080 apic_write(APIC_ID
, apic_pm_state
.apic_id
);
1081 apic_write(APIC_DFR
, apic_pm_state
.apic_dfr
);
1082 apic_write(APIC_LDR
, apic_pm_state
.apic_ldr
);
1083 apic_write(APIC_TASKPRI
, apic_pm_state
.apic_taskpri
);
1084 apic_write(APIC_SPIV
, apic_pm_state
.apic_spiv
);
1085 apic_write(APIC_LVT0
, apic_pm_state
.apic_lvt0
);
1086 apic_write(APIC_LVT1
, apic_pm_state
.apic_lvt1
);
1087 #ifdef CONFIG_X86_MCE_INTEL
1089 apic_write(APIC_LVTTHMR
, apic_pm_state
.apic_thmr
);
1092 apic_write(APIC_LVTPC
, apic_pm_state
.apic_lvtpc
);
1093 apic_write(APIC_LVTT
, apic_pm_state
.apic_lvtt
);
1094 apic_write(APIC_TDCR
, apic_pm_state
.apic_tdcr
);
1095 apic_write(APIC_TMICT
, apic_pm_state
.apic_tmict
);
1096 apic_write(APIC_ESR
, 0);
1097 apic_read(APIC_ESR
);
1098 apic_write(APIC_LVTERR
, apic_pm_state
.apic_lvterr
);
1099 apic_write(APIC_ESR
, 0);
1100 apic_read(APIC_ESR
);
1101 local_irq_restore(flags
);
1105 static struct sysdev_class lapic_sysclass
= {
1107 .resume
= lapic_resume
,
1108 .suspend
= lapic_suspend
,
1111 static struct sys_device device_lapic
= {
1113 .cls
= &lapic_sysclass
,
1116 static void __cpuinit
apic_pm_activate(void)
1118 apic_pm_state
.active
= 1;
1121 static int __init
init_lapic_sysfs(void)
1126 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
1127 error
= sysdev_class_register(&lapic_sysclass
);
1129 error
= sysdev_register(&device_lapic
);
1132 device_initcall(init_lapic_sysfs
);
1134 #else /* CONFIG_PM */
1136 static void apic_pm_activate(void) { }
1138 #endif /* CONFIG_PM */
1141 * apic_is_clustered_box() -- Check if we can expect good TSC
1143 * Thus far, the major user of this is IBM's Summit2 series:
1145 * Clustered boxes may have unsynced TSC problems if they are
1146 * multi-chassis. Use available data to take a good guess.
1147 * If in doubt, go HPET.
1149 __cpuinit
int apic_is_clustered_box(void)
1151 int i
, clusters
, zeros
;
1153 DECLARE_BITMAP(clustermap
, NUM_APIC_CLUSTERS
);
1155 bitmap_zero(clustermap
, NUM_APIC_CLUSTERS
);
1157 for (i
= 0; i
< NR_CPUS
; i
++) {
1158 id
= bios_cpu_apicid
[i
];
1159 if (id
!= BAD_APICID
)
1160 __set_bit(APIC_CLUSTERID(id
), clustermap
);
1163 /* Problem: Partially populated chassis may not have CPUs in some of
1164 * the APIC clusters they have been allocated. Only present CPUs have
1165 * bios_cpu_apicid entries, thus causing zeroes in the bitmap. Since
1166 * clusters are allocated sequentially, count zeros only if they are
1171 for (i
= 0; i
< NUM_APIC_CLUSTERS
; i
++) {
1172 if (test_bit(i
, clustermap
)) {
1173 clusters
+= 1 + zeros
;
1180 * If clusters > 2, then should be multi-chassis.
1181 * May have to revisit this when multi-core + hyperthreaded CPUs come
1182 * out, but AFAIK this will work even for them.
1184 return (clusters
> 2);
1188 * APIC command line parameters
1190 static int __init
apic_set_verbosity(char *str
)
1193 skip_ioapic_setup
= 0;
1197 if (strcmp("debug", str
) == 0)
1198 apic_verbosity
= APIC_DEBUG
;
1199 else if (strcmp("verbose", str
) == 0)
1200 apic_verbosity
= APIC_VERBOSE
;
1202 printk(KERN_WARNING
"APIC Verbosity level %s not recognised"
1203 " use apic=verbose or apic=debug\n", str
);
1209 early_param("apic", apic_set_verbosity
);
1211 static __init
int setup_disableapic(char *str
)
1214 clear_cpu_cap(&boot_cpu_data
, X86_FEATURE_APIC
);
1217 early_param("disableapic", setup_disableapic
);
1219 /* same as disableapic, for compatibility */
1220 static __init
int setup_nolapic(char *str
)
1222 return setup_disableapic(str
);
1224 early_param("nolapic", setup_nolapic
);
1226 static int __init
parse_lapic_timer_c2_ok(char *arg
)
1228 local_apic_timer_c2_ok
= 1;
1231 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok
);
1233 static __init
int setup_noapictimer(char *str
)
1235 if (str
[0] != ' ' && str
[0] != 0)
1237 disable_apic_timer
= 1;
1240 __setup("noapictimer", setup_noapictimer
);
1242 static __init
int setup_apicpmtimer(char *s
)
1244 apic_calibrate_pmtmr
= 1;
1248 __setup("apicpmtimer", setup_apicpmtimer
);