2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/bootmem.h>
22 #include <linux/interrupt.h>
23 #include <linux/mc146818rtc.h>
24 #include <linux/kernel_stat.h>
25 #include <linux/sysdev.h>
26 #include <linux/ioport.h>
27 #include <linux/clockchips.h>
28 #include <linux/acpi_pmtmr.h>
29 #include <linux/module.h>
30 #include <linux/dmar.h>
32 #include <asm/atomic.h>
35 #include <asm/mpspec.h>
38 #include <asm/pgalloc.h>
41 #include <asm/proto.h>
42 #include <asm/timex.h>
44 #include <asm/i8259.h>
47 #include <mach_apic.h>
52 #if ((SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F)
53 # error SPURIOUS_APIC_VECTOR definition error
58 * Knob to control our willingness to enable the local APIC.
62 static int force_enable_local_apic
;
64 * APIC command line parameters
66 static int __init
parse_lapic(char *arg
)
68 force_enable_local_apic
= 1;
71 early_param("lapic", parse_lapic
);
72 /* Local APIC was disabled by the BIOS and enabled by the kernel */
73 static int enabled_via_apicbase
;
78 static int apic_calibrate_pmtmr __initdata
;
79 static __init
int setup_apicpmtimer(char *s
)
81 apic_calibrate_pmtmr
= 1;
85 __setup("apicpmtimer", setup_apicpmtimer
);
94 /* x2apic enabled before OS handover */
95 int x2apic_preenabled
;
97 static __init
int setup_nox2apic(char *str
)
100 setup_clear_cpu_cap(X86_FEATURE_X2APIC
);
103 early_param("nox2apic", setup_nox2apic
);
106 unsigned long mp_lapic_addr
;
108 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
109 static int disable_apic_timer __cpuinitdata
;
110 /* Local APIC timer works in C2 */
111 int local_apic_timer_c2_ok
;
112 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok
);
114 int first_system_vector
= 0xfe;
116 char system_vectors
[NR_VECTORS
] = { [0 ... NR_VECTORS
-1] = SYS_VECTOR_FREE
};
119 * Debug level, exported for io_apic.c
121 unsigned int apic_verbosity
;
125 /* Have we found an MP table */
126 int smp_found_config
;
128 static struct resource lapic_resource
= {
129 .name
= "Local APIC",
130 .flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
,
133 static unsigned int calibration_result
;
135 static int lapic_next_event(unsigned long delta
,
136 struct clock_event_device
*evt
);
137 static void lapic_timer_setup(enum clock_event_mode mode
,
138 struct clock_event_device
*evt
);
139 static void lapic_timer_broadcast(cpumask_t mask
);
140 static void apic_pm_activate(void);
143 * The local apic timer can be used for any function which is CPU local.
145 static struct clock_event_device lapic_clockevent
= {
147 .features
= CLOCK_EVT_FEAT_PERIODIC
| CLOCK_EVT_FEAT_ONESHOT
148 | CLOCK_EVT_FEAT_C3STOP
| CLOCK_EVT_FEAT_DUMMY
,
150 .set_mode
= lapic_timer_setup
,
151 .set_next_event
= lapic_next_event
,
152 .broadcast
= lapic_timer_broadcast
,
156 static DEFINE_PER_CPU(struct clock_event_device
, lapic_events
);
158 static unsigned long apic_phys
;
161 * Get the LAPIC version
163 static inline int lapic_get_version(void)
165 return GET_APIC_VERSION(apic_read(APIC_LVR
));
169 * Check, if the APIC is integrated or a separate chip
171 static inline int lapic_is_integrated(void)
176 return APIC_INTEGRATED(lapic_get_version());
181 * Check, whether this is a modern or a first generation APIC
183 static int modern_apic(void)
185 /* AMD systems use old APIC versions, so check the CPU */
186 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
&&
187 boot_cpu_data
.x86
>= 0xf)
189 return lapic_get_version() >= 0x14;
193 * Paravirt kernels also might be using these below ops. So we still
194 * use generic apic_read()/apic_write(), which might be pointing to different
195 * ops in PARAVIRT case.
197 void xapic_wait_icr_idle(void)
199 while (apic_read(APIC_ICR
) & APIC_ICR_BUSY
)
203 u32
safe_xapic_wait_icr_idle(void)
210 send_status
= apic_read(APIC_ICR
) & APIC_ICR_BUSY
;
214 } while (timeout
++ < 1000);
219 void xapic_icr_write(u32 low
, u32 id
)
221 apic_write(APIC_ICR2
, SET_APIC_DEST_FIELD(id
));
222 apic_write(APIC_ICR
, low
);
225 u64
xapic_icr_read(void)
229 icr2
= apic_read(APIC_ICR2
);
230 icr1
= apic_read(APIC_ICR
);
232 return icr1
| ((u64
)icr2
<< 32);
235 static struct apic_ops xapic_ops
= {
236 .read
= native_apic_mem_read
,
237 .write
= native_apic_mem_write
,
238 .icr_read
= xapic_icr_read
,
239 .icr_write
= xapic_icr_write
,
240 .wait_icr_idle
= xapic_wait_icr_idle
,
241 .safe_wait_icr_idle
= safe_xapic_wait_icr_idle
,
244 struct apic_ops __read_mostly
*apic_ops
= &xapic_ops
;
245 EXPORT_SYMBOL_GPL(apic_ops
);
248 static void x2apic_wait_icr_idle(void)
250 /* no need to wait for icr idle in x2apic */
254 static u32
safe_x2apic_wait_icr_idle(void)
256 /* no need to wait for icr idle in x2apic */
260 void x2apic_icr_write(u32 low
, u32 id
)
262 wrmsrl(APIC_BASE_MSR
+ (APIC_ICR
>> 4), ((__u64
) id
) << 32 | low
);
265 u64
x2apic_icr_read(void)
269 rdmsrl(APIC_BASE_MSR
+ (APIC_ICR
>> 4), val
);
273 static struct apic_ops x2apic_ops
= {
274 .read
= native_apic_msr_read
,
275 .write
= native_apic_msr_write
,
276 .icr_read
= x2apic_icr_read
,
277 .icr_write
= x2apic_icr_write
,
278 .wait_icr_idle
= x2apic_wait_icr_idle
,
279 .safe_wait_icr_idle
= safe_x2apic_wait_icr_idle
,
284 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
286 void __cpuinit
enable_NMI_through_LVT0(void)
290 /* unmask and set to NMI */
293 /* Level triggered for 82489DX (32bit mode) */
294 if (!lapic_is_integrated())
295 v
|= APIC_LVT_LEVEL_TRIGGER
;
297 apic_write(APIC_LVT0
, v
);
302 * get_physical_broadcast - Get number of physical broadcast IDs
304 int get_physical_broadcast(void)
306 return modern_apic() ? 0xff : 0xf;
311 * lapic_get_maxlvt - get the maximum number of local vector table entries
313 int lapic_get_maxlvt(void)
317 v
= apic_read(APIC_LVR
);
319 * - we always have APIC integrated on 64bit mode
320 * - 82489DXs do not report # of LVT entries
322 return APIC_INTEGRATED(GET_APIC_VERSION(v
)) ? GET_APIC_MAXLVT(v
) : 2;
331 #define APIC_DIVISOR 1
333 #define APIC_DIVISOR 16
337 * This function sets up the local APIC timer, with a timeout of
338 * 'clocks' APIC bus clock. During calibration we actually call
339 * this function twice on the boot CPU, once with a bogus timeout
340 * value, second time for real. The other (noncalibrating) CPUs
341 * call this function only once, with the real, calibrated value.
343 * We do reads before writes even if unnecessary, to get around the
344 * P5 APIC double write bug.
346 static void __setup_APIC_LVTT(unsigned int clocks
, int oneshot
, int irqen
)
348 unsigned int lvtt_value
, tmp_value
;
350 lvtt_value
= LOCAL_TIMER_VECTOR
;
352 lvtt_value
|= APIC_LVT_TIMER_PERIODIC
;
353 if (!lapic_is_integrated())
354 lvtt_value
|= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV
);
357 lvtt_value
|= APIC_LVT_MASKED
;
359 apic_write(APIC_LVTT
, lvtt_value
);
364 tmp_value
= apic_read(APIC_TDCR
);
365 apic_write(APIC_TDCR
,
366 (tmp_value
& ~(APIC_TDR_DIV_1
| APIC_TDR_DIV_TMBASE
)) |
370 apic_write(APIC_TMICT
, clocks
/ APIC_DIVISOR
);
374 * Setup extended LVT, AMD specific (K8, family 10h)
376 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
377 * MCE interrupts are supported. Thus MCE offset must be set to 0.
379 * If mask=1, the LVT entry does not generate interrupts while mask=0
380 * enables the vector. See also the BKDGs.
383 #define APIC_EILVT_LVTOFF_MCE 0
384 #define APIC_EILVT_LVTOFF_IBS 1
386 static void setup_APIC_eilvt(u8 lvt_off
, u8 vector
, u8 msg_type
, u8 mask
)
388 unsigned long reg
= (lvt_off
<< 4) + APIC_EILVT0
;
389 unsigned int v
= (mask
<< 16) | (msg_type
<< 8) | vector
;
394 u8
setup_APIC_eilvt_mce(u8 vector
, u8 msg_type
, u8 mask
)
396 setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE
, vector
, msg_type
, mask
);
397 return APIC_EILVT_LVTOFF_MCE
;
400 u8
setup_APIC_eilvt_ibs(u8 vector
, u8 msg_type
, u8 mask
)
402 setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS
, vector
, msg_type
, mask
);
403 return APIC_EILVT_LVTOFF_IBS
;
405 EXPORT_SYMBOL_GPL(setup_APIC_eilvt_ibs
);
408 * Program the next event, relative to now
410 static int lapic_next_event(unsigned long delta
,
411 struct clock_event_device
*evt
)
413 apic_write(APIC_TMICT
, delta
);
418 * Setup the lapic timer in periodic or oneshot mode
420 static void lapic_timer_setup(enum clock_event_mode mode
,
421 struct clock_event_device
*evt
)
426 /* Lapic used as dummy for broadcast ? */
427 if (evt
->features
& CLOCK_EVT_FEAT_DUMMY
)
430 local_irq_save(flags
);
433 case CLOCK_EVT_MODE_PERIODIC
:
434 case CLOCK_EVT_MODE_ONESHOT
:
435 __setup_APIC_LVTT(calibration_result
,
436 mode
!= CLOCK_EVT_MODE_PERIODIC
, 1);
438 case CLOCK_EVT_MODE_UNUSED
:
439 case CLOCK_EVT_MODE_SHUTDOWN
:
440 v
= apic_read(APIC_LVTT
);
441 v
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
442 apic_write(APIC_LVTT
, v
);
444 case CLOCK_EVT_MODE_RESUME
:
445 /* Nothing to do here */
449 local_irq_restore(flags
);
453 * Local APIC timer broadcast function
455 static void lapic_timer_broadcast(cpumask_t mask
)
458 send_IPI_mask(mask
, LOCAL_TIMER_VECTOR
);
463 * Setup the local APIC timer for this CPU. Copy the initilized values
464 * of the boot CPU and register the clock event in the framework.
466 static void __cpuinit
setup_APIC_timer(void)
468 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
470 memcpy(levt
, &lapic_clockevent
, sizeof(*levt
));
471 levt
->cpumask
= cpumask_of_cpu(smp_processor_id());
473 clockevents_register_device(levt
);
477 * In this function we calibrate APIC bus clocks to the external
478 * timer. Unfortunately we cannot use jiffies and the timer irq
479 * to calibrate, since some later bootup code depends on getting
480 * the first irq? Ugh.
482 * We want to do the calibration only once since we
483 * want to have local timer irqs syncron. CPUs connected
484 * by the same APIC bus have the very same bus frequency.
485 * And we want to have irqs off anyways, no accidental
489 #define TICK_COUNT 100000000
491 static int __init
calibrate_APIC_clock(void)
493 unsigned apic
, apic_start
;
494 unsigned long tsc
, tsc_start
;
500 * Put whatever arbitrary (but long enough) timeout
501 * value into the APIC clock, we just want to get the
502 * counter running for calibration.
504 * No interrupt enable !
506 __setup_APIC_LVTT(250000000, 0, 0);
508 apic_start
= apic_read(APIC_TMCCT
);
509 #ifdef CONFIG_X86_PM_TIMER
510 if (apic_calibrate_pmtmr
&& pmtmr_ioport
) {
511 pmtimer_wait(5000); /* 5ms wait */
512 apic
= apic_read(APIC_TMCCT
);
513 result
= (apic_start
- apic
) * 1000L / 5;
520 apic
= apic_read(APIC_TMCCT
);
522 } while ((tsc
- tsc_start
) < TICK_COUNT
&&
523 (apic_start
- apic
) < TICK_COUNT
);
525 result
= (apic_start
- apic
) * 1000L * tsc_khz
/
531 printk(KERN_DEBUG
"APIC timer calibration result %d\n", result
);
533 printk(KERN_INFO
"Detected %d.%03d MHz APIC timer.\n",
534 result
/ 1000 / 1000, result
/ 1000 % 1000);
536 /* Calculate the scaled math multiplication factor */
537 lapic_clockevent
.mult
= div_sc(result
, NSEC_PER_SEC
,
538 lapic_clockevent
.shift
);
539 lapic_clockevent
.max_delta_ns
=
540 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent
);
541 lapic_clockevent
.min_delta_ns
=
542 clockevent_delta2ns(0xF, &lapic_clockevent
);
544 calibration_result
= (result
* APIC_DIVISOR
) / HZ
;
547 * Do a sanity check on the APIC calibration result
549 if (calibration_result
< (1000000 / HZ
)) {
551 "APIC frequency too slow, disabling apic timer\n");
559 * Setup the boot APIC
561 * Calibrate and verify the result.
563 void __init
setup_boot_APIC_clock(void)
566 * The local apic timer can be disabled via the kernel
567 * commandline or from the CPU detection code. Register the lapic
568 * timer as a dummy clock event source on SMP systems, so the
569 * broadcast mechanism is used. On UP systems simply ignore it.
571 if (disable_apic_timer
) {
572 printk(KERN_INFO
"Disabling APIC timer\n");
573 /* No broadcast on UP ! */
574 if (num_possible_cpus() > 1) {
575 lapic_clockevent
.mult
= 1;
581 apic_printk(APIC_VERBOSE
, "Using local APIC timer interrupts.\n"
582 "calibrating APIC timer ...\n");
584 if (calibrate_APIC_clock()) {
585 /* No broadcast on UP ! */
586 if (num_possible_cpus() > 1)
592 * If nmi_watchdog is set to IO_APIC, we need the
593 * PIT/HPET going. Otherwise register lapic as a dummy
596 if (nmi_watchdog
!= NMI_IO_APIC
)
597 lapic_clockevent
.features
&= ~CLOCK_EVT_FEAT_DUMMY
;
599 printk(KERN_WARNING
"APIC timer registered as dummy,"
600 " due to nmi_watchdog=%d!\n", nmi_watchdog
);
602 /* Setup the lapic or request the broadcast */
606 void __cpuinit
setup_secondary_APIC_clock(void)
612 * The guts of the apic timer interrupt
614 static void local_apic_timer_interrupt(void)
616 int cpu
= smp_processor_id();
617 struct clock_event_device
*evt
= &per_cpu(lapic_events
, cpu
);
620 * Normally we should not be here till LAPIC has been initialized but
621 * in some cases like kdump, its possible that there is a pending LAPIC
622 * timer interrupt from previous kernel's context and is delivered in
623 * new kernel the moment interrupts are enabled.
625 * Interrupts are enabled early and LAPIC is setup much later, hence
626 * its possible that when we get here evt->event_handler is NULL.
627 * Check for event_handler being NULL and discard the interrupt as
630 if (!evt
->event_handler
) {
632 "Spurious LAPIC timer interrupt on cpu %d\n", cpu
);
634 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, evt
);
639 * the NMI deadlock-detector uses this.
642 add_pda(apic_timer_irqs
, 1);
644 per_cpu(irq_stat
, cpu
).apic_timer_irqs
++;
647 evt
->event_handler(evt
);
651 * Local APIC timer interrupt. This is the most natural way for doing
652 * local interrupts, but local timer interrupts can be emulated by
653 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
655 * [ if a single-CPU system runs an SMP kernel then we call the local
656 * interrupt as well. Thus we cannot inline the local irq ... ]
658 void smp_apic_timer_interrupt(struct pt_regs
*regs
)
660 struct pt_regs
*old_regs
= set_irq_regs(regs
);
663 * NOTE! We'd better ACK the irq immediately,
664 * because timer handling can be slow.
668 * update_process_times() expects us to have done irq_enter().
669 * Besides, if we don't timer interrupts ignore the global
670 * interrupt lock, which is the WrongThing (tm) to do.
676 local_apic_timer_interrupt();
679 set_irq_regs(old_regs
);
682 int setup_profiling_timer(unsigned int multiplier
)
688 * Local APIC start and shutdown
692 * clear_local_APIC - shutdown the local APIC
694 * This is called, when a CPU is disabled and before rebooting, so the state of
695 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
696 * leftovers during boot.
698 void clear_local_APIC(void)
703 /* APIC hasn't been mapped yet */
707 maxlvt
= lapic_get_maxlvt();
709 * Masking an LVT entry can trigger a local APIC error
710 * if the vector is zero. Mask LVTERR first to prevent this.
713 v
= ERROR_APIC_VECTOR
; /* any non-zero vector will do */
714 apic_write(APIC_LVTERR
, v
| APIC_LVT_MASKED
);
717 * Careful: we have to set masks only first to deassert
718 * any level-triggered sources.
720 v
= apic_read(APIC_LVTT
);
721 apic_write(APIC_LVTT
, v
| APIC_LVT_MASKED
);
722 v
= apic_read(APIC_LVT0
);
723 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
724 v
= apic_read(APIC_LVT1
);
725 apic_write(APIC_LVT1
, v
| APIC_LVT_MASKED
);
727 v
= apic_read(APIC_LVTPC
);
728 apic_write(APIC_LVTPC
, v
| APIC_LVT_MASKED
);
731 /* lets not touch this if we didn't frob it */
732 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(X86_MCE_INTEL)
734 v
= apic_read(APIC_LVTTHMR
);
735 apic_write(APIC_LVTTHMR
, v
| APIC_LVT_MASKED
);
739 * Clean APIC state for other OSs:
741 apic_write(APIC_LVTT
, APIC_LVT_MASKED
);
742 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
743 apic_write(APIC_LVT1
, APIC_LVT_MASKED
);
745 apic_write(APIC_LVTERR
, APIC_LVT_MASKED
);
747 apic_write(APIC_LVTPC
, APIC_LVT_MASKED
);
749 /* Integrated APIC (!82489DX) ? */
750 if (lapic_is_integrated()) {
752 /* Clear ESR due to Pentium errata 3AP and 11AP */
753 apic_write(APIC_ESR
, 0);
759 * disable_local_APIC - clear and disable the local APIC
761 void disable_local_APIC(void)
768 * Disable APIC (implies clearing of registers
771 value
= apic_read(APIC_SPIV
);
772 value
&= ~APIC_SPIV_APIC_ENABLED
;
773 apic_write(APIC_SPIV
, value
);
777 * When LAPIC was disabled by the BIOS and enabled by the kernel,
778 * restore the disabled state.
780 if (enabled_via_apicbase
) {
783 rdmsr(MSR_IA32_APICBASE
, l
, h
);
784 l
&= ~MSR_IA32_APICBASE_ENABLE
;
785 wrmsr(MSR_IA32_APICBASE
, l
, h
);
791 * If Linux enabled the LAPIC against the BIOS default disable it down before
792 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
793 * not power-off. Additionally clear all LVT entries before disable_local_APIC
794 * for the case where Linux didn't enable the LAPIC.
796 void lapic_shutdown(void)
803 local_irq_save(flags
);
806 if (!enabled_via_apicbase
)
810 disable_local_APIC();
813 local_irq_restore(flags
);
817 * This is to verify that we're looking at a real local APIC.
818 * Check these against your board if the CPUs aren't getting
819 * started for no apparent reason.
821 int __init
verify_local_APIC(void)
823 unsigned int reg0
, reg1
;
826 * The version register is read-only in a real APIC.
828 reg0
= apic_read(APIC_LVR
);
829 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg0
);
830 apic_write(APIC_LVR
, reg0
^ APIC_LVR_MASK
);
831 reg1
= apic_read(APIC_LVR
);
832 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg1
);
835 * The two version reads above should print the same
836 * numbers. If the second one is different, then we
837 * poke at a non-APIC.
843 * Check if the version looks reasonably.
845 reg1
= GET_APIC_VERSION(reg0
);
846 if (reg1
== 0x00 || reg1
== 0xff)
848 reg1
= lapic_get_maxlvt();
849 if (reg1
< 0x02 || reg1
== 0xff)
853 * The ID register is read/write in a real APIC.
855 reg0
= apic_read(APIC_ID
);
856 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg0
);
857 apic_write(APIC_ID
, reg0
^ APIC_ID_MASK
);
858 reg1
= apic_read(APIC_ID
);
859 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg1
);
860 apic_write(APIC_ID
, reg0
);
861 if (reg1
!= (reg0
^ APIC_ID_MASK
))
865 * The next two are just to see if we have sane values.
866 * They're only really relevant if we're in Virtual Wire
867 * compatibility mode, but most boxes are anymore.
869 reg0
= apic_read(APIC_LVT0
);
870 apic_printk(APIC_DEBUG
, "Getting LVT0: %x\n", reg0
);
871 reg1
= apic_read(APIC_LVT1
);
872 apic_printk(APIC_DEBUG
, "Getting LVT1: %x\n", reg1
);
878 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
880 void __init
sync_Arb_IDs(void)
883 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
886 if (modern_apic() || boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
)
892 apic_wait_icr_idle();
894 apic_printk(APIC_DEBUG
, "Synchronizing Arb IDs.\n");
895 apic_write(APIC_ICR
, APIC_DEST_ALLINC
|
896 APIC_INT_LEVELTRIG
| APIC_DM_INIT
);
900 * An initial setup of the virtual wire mode.
902 void __init
init_bsp_APIC(void)
907 * Don't do the setup now if we have a SMP BIOS as the
908 * through-I/O-APIC virtual wire mode might be active.
910 if (smp_found_config
|| !cpu_has_apic
)
914 * Do not trust the local APIC being empty at bootup.
921 value
= apic_read(APIC_SPIV
);
922 value
&= ~APIC_VECTOR_MASK
;
923 value
|= APIC_SPIV_APIC_ENABLED
;
926 /* This bit is reserved on P4/Xeon and should be cleared */
927 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
) &&
928 (boot_cpu_data
.x86
== 15))
929 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
932 value
|= APIC_SPIV_FOCUS_DISABLED
;
933 value
|= SPURIOUS_APIC_VECTOR
;
934 apic_write(APIC_SPIV
, value
);
937 * Set up the virtual wire mode.
939 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
941 if (!lapic_is_integrated()) /* 82489DX */
942 value
|= APIC_LVT_LEVEL_TRIGGER
;
943 apic_write(APIC_LVT1
, value
);
946 static void __cpuinit
lapic_setup_esr(void)
948 unsigned long oldvalue
, value
, maxlvt
;
949 if (lapic_is_integrated() && !esr_disable
) {
952 * Something untraceable is creating bad interrupts on
953 * secondary quads ... for the moment, just leave the
954 * ESR disabled - we can't do anything useful with the
955 * errors anyway - mbligh
957 printk(KERN_INFO
"Leaving ESR disabled.\n");
961 maxlvt
= lapic_get_maxlvt();
962 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
963 apic_write(APIC_ESR
, 0);
964 oldvalue
= apic_read(APIC_ESR
);
966 /* enables sending errors */
967 value
= ERROR_APIC_VECTOR
;
968 apic_write(APIC_LVTERR
, value
);
970 * spec says clear errors after enabling vector.
973 apic_write(APIC_ESR
, 0);
974 value
= apic_read(APIC_ESR
);
975 if (value
!= oldvalue
)
976 apic_printk(APIC_VERBOSE
, "ESR value before enabling "
977 "vector: 0x%08lx after: 0x%08lx\n",
980 printk(KERN_INFO
"No ESR for 82489DX.\n");
986 * setup_local_APIC - setup the local APIC
988 void __cpuinit
setup_local_APIC(void)
994 /* Pound the ESR really hard over the head with a big hammer - mbligh */
996 apic_write(APIC_ESR
, 0);
997 apic_write(APIC_ESR
, 0);
998 apic_write(APIC_ESR
, 0);
999 apic_write(APIC_ESR
, 0);
1006 * Double-check whether this APIC is really registered.
1007 * This is meaningless in clustered apic mode, so we skip it.
1009 if (!apic_id_registered())
1013 * Intel recommends to set DFR, LDR and TPR before enabling
1014 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
1015 * document number 292116). So here it goes...
1020 * Set Task Priority to 'accept all'. We never change this
1023 value
= apic_read(APIC_TASKPRI
);
1024 value
&= ~APIC_TPRI_MASK
;
1025 apic_write(APIC_TASKPRI
, value
);
1028 * After a crash, we no longer service the interrupts and a pending
1029 * interrupt from previous kernel might still have ISR bit set.
1031 * Most probably by now CPU has serviced that pending interrupt and
1032 * it might not have done the ack_APIC_irq() because it thought,
1033 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
1034 * does not clear the ISR bit and cpu thinks it has already serivced
1035 * the interrupt. Hence a vector might get locked. It was noticed
1036 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
1038 for (i
= APIC_ISR_NR
- 1; i
>= 0; i
--) {
1039 value
= apic_read(APIC_ISR
+ i
*0x10);
1040 for (j
= 31; j
>= 0; j
--) {
1047 * Now that we are all set up, enable the APIC
1049 value
= apic_read(APIC_SPIV
);
1050 value
&= ~APIC_VECTOR_MASK
;
1054 value
|= APIC_SPIV_APIC_ENABLED
;
1056 #ifdef CONFIG_X86_32
1058 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1059 * certain networking cards. If high frequency interrupts are
1060 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1061 * entry is masked/unmasked at a high rate as well then sooner or
1062 * later IOAPIC line gets 'stuck', no more interrupts are received
1063 * from the device. If focus CPU is disabled then the hang goes
1066 * [ This bug can be reproduced easily with a level-triggered
1067 * PCI Ne2000 networking cards and PII/PIII processors, dual
1071 * Actually disabling the focus CPU check just makes the hang less
1072 * frequent as it makes the interrupt distributon model be more
1073 * like LRU than MRU (the short-term load is more even across CPUs).
1074 * See also the comment in end_level_ioapic_irq(). --macro
1078 * - enable focus processor (bit==0)
1079 * - 64bit mode always use processor focus
1080 * so no need to set it
1082 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
1086 * Set spurious IRQ vector
1088 value
|= SPURIOUS_APIC_VECTOR
;
1089 apic_write(APIC_SPIV
, value
);
1092 * Set up LVT0, LVT1:
1094 * set up through-local-APIC on the BP's LINT0. This is not
1095 * strictly necessary in pure symmetric-IO mode, but sometimes
1096 * we delegate interrupts to the 8259A.
1099 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1101 value
= apic_read(APIC_LVT0
) & APIC_LVT_MASKED
;
1102 if (!smp_processor_id() && (pic_mode
|| !value
)) {
1103 value
= APIC_DM_EXTINT
;
1104 apic_printk(APIC_VERBOSE
, "enabled ExtINT on CPU#%d\n",
1105 smp_processor_id());
1107 value
= APIC_DM_EXTINT
| APIC_LVT_MASKED
;
1108 apic_printk(APIC_VERBOSE
, "masked ExtINT on CPU#%d\n",
1109 smp_processor_id());
1111 apic_write(APIC_LVT0
, value
);
1114 * only the BP should see the LINT1 NMI signal, obviously.
1116 if (!smp_processor_id())
1117 value
= APIC_DM_NMI
;
1119 value
= APIC_DM_NMI
| APIC_LVT_MASKED
;
1120 if (!lapic_is_integrated()) /* 82489DX */
1121 value
|= APIC_LVT_LEVEL_TRIGGER
;
1122 apic_write(APIC_LVT1
, value
);
1127 void __cpuinit
end_local_APIC_setup(void)
1131 #ifdef CONFIG_X86_32
1134 /* Disable the local apic timer */
1135 value
= apic_read(APIC_LVTT
);
1136 value
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
1137 apic_write(APIC_LVTT
, value
);
1141 setup_apic_nmi_watchdog(NULL
);
1146 void check_x2apic(void)
1150 rdmsr(MSR_IA32_APICBASE
, msr
, msr2
);
1152 if (msr
& X2APIC_ENABLE
) {
1153 printk("x2apic enabled by BIOS, switching to x2apic ops\n");
1154 x2apic_preenabled
= x2apic
= 1;
1155 apic_ops
= &x2apic_ops
;
1159 void enable_x2apic(void)
1163 rdmsr(MSR_IA32_APICBASE
, msr
, msr2
);
1164 if (!(msr
& X2APIC_ENABLE
)) {
1165 printk("Enabling x2apic\n");
1166 wrmsr(MSR_IA32_APICBASE
, msr
| X2APIC_ENABLE
, 0);
1170 void enable_IR_x2apic(void)
1172 #ifdef CONFIG_INTR_REMAP
1174 unsigned long flags
;
1176 if (!cpu_has_x2apic
)
1179 if (!x2apic_preenabled
&& disable_x2apic
) {
1181 "Skipped enabling x2apic and Interrupt-remapping "
1182 "because of nox2apic\n");
1186 if (x2apic_preenabled
&& disable_x2apic
)
1187 panic("Bios already enabled x2apic, can't enforce nox2apic");
1189 if (!x2apic_preenabled
&& skip_ioapic_setup
) {
1191 "Skipped enabling x2apic and Interrupt-remapping "
1192 "because of skipping io-apic setup\n");
1196 ret
= dmar_table_init();
1199 "dmar_table_init() failed with %d:\n", ret
);
1201 if (x2apic_preenabled
)
1202 panic("x2apic enabled by bios. But IR enabling failed");
1205 "Not enabling x2apic,Intr-remapping\n");
1209 local_irq_save(flags
);
1211 save_mask_IO_APIC_setup();
1213 ret
= enable_intr_remapping(1);
1215 if (ret
&& x2apic_preenabled
) {
1216 local_irq_restore(flags
);
1217 panic("x2apic enabled by bios. But IR enabling failed");
1225 apic_ops
= &x2apic_ops
;
1231 * IR enabling failed
1233 restore_IO_APIC_setup();
1235 reinit_intr_remapped_IO_APIC(x2apic_preenabled
);
1238 local_irq_restore(flags
);
1241 if (!x2apic_preenabled
)
1243 "Enabled x2apic and interrupt-remapping\n");
1246 "Enabled Interrupt-remapping\n");
1249 "Failed to enable Interrupt-remapping and x2apic\n");
1251 if (!cpu_has_x2apic
)
1254 if (x2apic_preenabled
)
1255 panic("x2apic enabled prior OS handover,"
1256 " enable CONFIG_INTR_REMAP");
1258 printk(KERN_INFO
"Enable CONFIG_INTR_REMAP for enabling intr-remapping "
1264 #endif /* HAVE_X2APIC */
1266 #ifdef CONFIG_X86_64
1268 * Detect and enable local APICs on non-SMP boards.
1269 * Original code written by Keir Fraser.
1270 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1271 * not correctly set up (usually the APIC timer won't work etc.)
1273 static int __init
detect_init_APIC(void)
1275 if (!cpu_has_apic
) {
1276 printk(KERN_INFO
"No local APIC present\n");
1280 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
1281 boot_cpu_physical_apicid
= 0;
1286 * Detect and initialize APIC
1288 static int __init
detect_init_APIC(void)
1292 /* Disabled by kernel option? */
1296 switch (boot_cpu_data
.x86_vendor
) {
1297 case X86_VENDOR_AMD
:
1298 if ((boot_cpu_data
.x86
== 6 && boot_cpu_data
.x86_model
> 1) ||
1299 (boot_cpu_data
.x86
== 15))
1302 case X86_VENDOR_INTEL
:
1303 if (boot_cpu_data
.x86
== 6 || boot_cpu_data
.x86
== 15 ||
1304 (boot_cpu_data
.x86
== 5 && cpu_has_apic
))
1311 if (!cpu_has_apic
) {
1313 * Over-ride BIOS and try to enable the local APIC only if
1314 * "lapic" specified.
1316 if (!force_enable_local_apic
) {
1317 printk(KERN_INFO
"Local APIC disabled by BIOS -- "
1318 "you can enable it with \"lapic\"\n");
1322 * Some BIOSes disable the local APIC in the APIC_BASE
1323 * MSR. This can only be done in software for Intel P6 or later
1324 * and AMD K7 (Model > 1) or later.
1326 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1327 if (!(l
& MSR_IA32_APICBASE_ENABLE
)) {
1329 "Local APIC disabled by BIOS -- reenabling.\n");
1330 l
&= ~MSR_IA32_APICBASE_BASE
;
1331 l
|= MSR_IA32_APICBASE_ENABLE
| APIC_DEFAULT_PHYS_BASE
;
1332 wrmsr(MSR_IA32_APICBASE
, l
, h
);
1333 enabled_via_apicbase
= 1;
1337 * The APIC feature bit should now be enabled
1340 features
= cpuid_edx(1);
1341 if (!(features
& (1 << X86_FEATURE_APIC
))) {
1342 printk(KERN_WARNING
"Could not enable APIC!\n");
1345 set_cpu_cap(&boot_cpu_data
, X86_FEATURE_APIC
);
1346 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
1348 /* The BIOS may have set up the APIC at some other address */
1349 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1350 if (l
& MSR_IA32_APICBASE_ENABLE
)
1351 mp_lapic_addr
= l
& MSR_IA32_APICBASE_BASE
;
1353 printk(KERN_INFO
"Found and enabled local APIC!\n");
1360 printk(KERN_INFO
"No local APIC present or hardware disabled\n");
1365 #ifdef CONFIG_X86_64
1366 void __init
early_init_lapic_mapping(void)
1368 unsigned long phys_addr
;
1371 * If no local APIC can be found then go out
1372 * : it means there is no mpatable and MADT
1374 if (!smp_found_config
)
1377 phys_addr
= mp_lapic_addr
;
1379 set_fixmap_nocache(FIX_APIC_BASE
, phys_addr
);
1380 apic_printk(APIC_VERBOSE
, "mapped APIC to %16lx (%16lx)\n",
1381 APIC_BASE
, phys_addr
);
1384 * Fetch the APIC ID of the BSP in case we have a
1385 * default configuration (or the MP table is broken).
1387 boot_cpu_physical_apicid
= read_apic_id();
1392 * init_apic_mappings - initialize APIC mappings
1394 void __init
init_apic_mappings(void)
1398 boot_cpu_physical_apicid
= read_apic_id();
1404 * If no local APIC can be found then set up a fake all
1405 * zeroes page to simulate the local APIC and another
1406 * one for the IO-APIC.
1408 if (!smp_found_config
&& detect_init_APIC()) {
1409 apic_phys
= (unsigned long) alloc_bootmem_pages(PAGE_SIZE
);
1410 apic_phys
= __pa(apic_phys
);
1412 apic_phys
= mp_lapic_addr
;
1414 set_fixmap_nocache(FIX_APIC_BASE
, apic_phys
);
1415 apic_printk(APIC_VERBOSE
, "mapped APIC to %16lx (%16lx)\n",
1416 APIC_BASE
, apic_phys
);
1419 * Fetch the APIC ID of the BSP in case we have a
1420 * default configuration (or the MP table is broken).
1422 if (boot_cpu_physical_apicid
== -1U)
1423 boot_cpu_physical_apicid
= read_apic_id();
1427 * This initializes the IO-APIC and APIC hardware if this is
1430 int apic_version
[MAX_APICS
];
1432 int __init
APIC_init_uniprocessor(void)
1434 #ifdef CONFIG_X86_64
1436 printk(KERN_INFO
"Apic disabled\n");
1439 if (!cpu_has_apic
) {
1441 printk(KERN_INFO
"Apic disabled by BIOS\n");
1445 if (!smp_found_config
&& !cpu_has_apic
)
1449 * Complain if the BIOS pretends there is one.
1451 if (!cpu_has_apic
&&
1452 APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
])) {
1453 printk(KERN_ERR
"BIOS bug, local APIC #%d not detected!...\n",
1454 boot_cpu_physical_apicid
);
1455 clear_cpu_cap(&boot_cpu_data
, X86_FEATURE_APIC
);
1463 #ifdef CONFIG_X86_64
1464 setup_apic_routing();
1467 verify_local_APIC();
1470 #ifdef CONFIG_X86_64
1471 apic_write(APIC_ID
, SET_APIC_ID(boot_cpu_physical_apicid
));
1474 * Hack: In case of kdump, after a crash, kernel might be booting
1475 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
1476 * might be zero if read from MP tables. Get it from LAPIC.
1478 # ifdef CONFIG_CRASH_DUMP
1479 boot_cpu_physical_apicid
= read_apic_id();
1482 physid_set_mask_of_physid(boot_cpu_physical_apicid
, &phys_cpu_present_map
);
1485 #ifdef CONFIG_X86_64
1487 * Now enable IO-APICs, actually call clear_IO_APIC
1488 * We need clear_IO_APIC before enabling vector on BP
1490 if (!skip_ioapic_setup
&& nr_ioapics
)
1494 #ifdef CONFIG_X86_IO_APIC
1495 if (!smp_found_config
|| skip_ioapic_setup
|| !nr_ioapics
)
1497 localise_nmi_watchdog();
1498 end_local_APIC_setup();
1500 #ifdef CONFIG_X86_IO_APIC
1501 if (smp_found_config
&& !skip_ioapic_setup
&& nr_ioapics
)
1503 # ifdef CONFIG_X86_64
1509 #ifdef CONFIG_X86_64
1510 setup_boot_APIC_clock();
1511 check_nmi_watchdog();
1520 * Local APIC interrupts
1524 * This interrupt should _never_ happen with our APIC/SMP architecture
1526 asmlinkage
void smp_spurious_interrupt(void)
1532 * Check if this really is a spurious interrupt and ACK it
1533 * if it is a vectored one. Just in case...
1534 * Spurious interrupts should not be ACKed.
1536 v
= apic_read(APIC_ISR
+ ((SPURIOUS_APIC_VECTOR
& ~0x1f) >> 1));
1537 if (v
& (1 << (SPURIOUS_APIC_VECTOR
& 0x1f)))
1540 add_pda(irq_spurious_count
, 1);
1545 * This interrupt should never happen with our APIC/SMP architecture
1547 asmlinkage
void smp_error_interrupt(void)
1553 /* First tickle the hardware, only then report what went on. -- REW */
1554 v
= apic_read(APIC_ESR
);
1555 apic_write(APIC_ESR
, 0);
1556 v1
= apic_read(APIC_ESR
);
1558 atomic_inc(&irq_err_count
);
1560 /* Here is what the APIC error bits mean:
1563 2: Send accept error
1564 3: Receive accept error
1566 5: Send illegal vector
1567 6: Received illegal vector
1568 7: Illegal register address
1570 printk(KERN_DEBUG
"APIC error on CPU%d: %02x(%02x)\n",
1571 smp_processor_id(), v
, v1
);
1576 * connect_bsp_APIC - attach the APIC to the interrupt system
1578 void __init
connect_bsp_APIC(void)
1580 #ifdef CONFIG_X86_32
1583 * Do not trust the local APIC being empty at bootup.
1587 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
1588 * local APIC to INT and NMI lines.
1590 apic_printk(APIC_VERBOSE
, "leaving PIC mode, "
1591 "enabling APIC mode.\n");
1600 * disconnect_bsp_APIC - detach the APIC from the interrupt system
1601 * @virt_wire_setup: indicates, whether virtual wire mode is selected
1603 * Virtual wire mode is necessary to deliver legacy interrupts even when the
1606 void disconnect_bsp_APIC(int virt_wire_setup
)
1610 #ifdef CONFIG_X86_32
1613 * Put the board back into PIC mode (has an effect only on
1614 * certain older boards). Note that APIC interrupts, including
1615 * IPIs, won't work beyond this point! The only exception are
1618 apic_printk(APIC_VERBOSE
, "disabling APIC mode, "
1619 "entering PIC mode.\n");
1626 /* Go back to Virtual Wire compatibility mode */
1628 /* For the spurious interrupt use vector F, and enable it */
1629 value
= apic_read(APIC_SPIV
);
1630 value
&= ~APIC_VECTOR_MASK
;
1631 value
|= APIC_SPIV_APIC_ENABLED
;
1633 apic_write(APIC_SPIV
, value
);
1635 if (!virt_wire_setup
) {
1637 * For LVT0 make it edge triggered, active high,
1638 * external and enabled
1640 value
= apic_read(APIC_LVT0
);
1641 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1642 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1643 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1644 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1645 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_EXTINT
);
1646 apic_write(APIC_LVT0
, value
);
1649 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
1653 * For LVT1 make it edge triggered, active high,
1656 value
= apic_read(APIC_LVT1
);
1657 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1658 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1659 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1660 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1661 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_NMI
);
1662 apic_write(APIC_LVT1
, value
);
1665 void __cpuinit
generic_processor_info(int apicid
, int version
)
1673 if (version
== 0x0) {
1674 printk(KERN_WARNING
"BIOS bug, APIC version is 0 for CPU#%d! "
1675 "fixing up to 0x10. (tell your hw vendor)\n",
1679 apic_version
[apicid
] = version
;
1681 if (num_processors
>= NR_CPUS
) {
1682 printk(KERN_WARNING
"WARNING: NR_CPUS limit of %i reached."
1683 " Processor ignored.\n", NR_CPUS
);
1688 cpus_complement(tmp_map
, cpu_present_map
);
1689 cpu
= first_cpu(tmp_map
);
1691 physid_set(apicid
, phys_cpu_present_map
);
1692 if (apicid
== boot_cpu_physical_apicid
) {
1694 * x86_bios_cpu_apicid is required to have processors listed
1695 * in same order as logical cpu numbers. Hence the first
1696 * entry is BSP, and so on.
1700 if (apicid
> max_physical_apicid
)
1701 max_physical_apicid
= apicid
;
1703 #ifdef CONFIG_X86_32
1705 * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y
1706 * but we need to work other dependencies like SMP_SUSPEND etc
1707 * before this can be done without some confusion.
1708 * if (CPU_HOTPLUG_ENABLED || num_processors > 8)
1709 * - Ashok Raj <ashok.raj@intel.com>
1711 if (max_physical_apicid
>= 8) {
1712 switch (boot_cpu_data
.x86_vendor
) {
1713 case X86_VENDOR_INTEL
:
1714 if (!APIC_XAPIC(version
)) {
1718 /* If P4 and above fall through */
1719 case X86_VENDOR_AMD
:
1725 #if defined(CONFIG_X86_SMP) || defined(CONFIG_X86_64)
1726 /* are we being called early in kernel startup? */
1727 if (early_per_cpu_ptr(x86_cpu_to_apicid
)) {
1728 u16
*cpu_to_apicid
= early_per_cpu_ptr(x86_cpu_to_apicid
);
1729 u16
*bios_cpu_apicid
= early_per_cpu_ptr(x86_bios_cpu_apicid
);
1731 cpu_to_apicid
[cpu
] = apicid
;
1732 bios_cpu_apicid
[cpu
] = apicid
;
1734 per_cpu(x86_cpu_to_apicid
, cpu
) = apicid
;
1735 per_cpu(x86_bios_cpu_apicid
, cpu
) = apicid
;
1739 cpu_set(cpu
, cpu_possible_map
);
1740 cpu_set(cpu
, cpu_present_map
);
1743 #ifdef CONFIG_X86_64
1744 int hard_smp_processor_id(void)
1746 return read_apic_id();
1757 * 'active' is true if the local APIC was enabled by us and
1758 * not the BIOS; this signifies that we are also responsible
1759 * for disabling it before entering apm/acpi suspend
1762 /* r/w apic fields */
1763 unsigned int apic_id
;
1764 unsigned int apic_taskpri
;
1765 unsigned int apic_ldr
;
1766 unsigned int apic_dfr
;
1767 unsigned int apic_spiv
;
1768 unsigned int apic_lvtt
;
1769 unsigned int apic_lvtpc
;
1770 unsigned int apic_lvt0
;
1771 unsigned int apic_lvt1
;
1772 unsigned int apic_lvterr
;
1773 unsigned int apic_tmict
;
1774 unsigned int apic_tdcr
;
1775 unsigned int apic_thmr
;
1778 static int lapic_suspend(struct sys_device
*dev
, pm_message_t state
)
1780 unsigned long flags
;
1783 if (!apic_pm_state
.active
)
1786 maxlvt
= lapic_get_maxlvt();
1788 apic_pm_state
.apic_id
= apic_read(APIC_ID
);
1789 apic_pm_state
.apic_taskpri
= apic_read(APIC_TASKPRI
);
1790 apic_pm_state
.apic_ldr
= apic_read(APIC_LDR
);
1791 apic_pm_state
.apic_dfr
= apic_read(APIC_DFR
);
1792 apic_pm_state
.apic_spiv
= apic_read(APIC_SPIV
);
1793 apic_pm_state
.apic_lvtt
= apic_read(APIC_LVTT
);
1795 apic_pm_state
.apic_lvtpc
= apic_read(APIC_LVTPC
);
1796 apic_pm_state
.apic_lvt0
= apic_read(APIC_LVT0
);
1797 apic_pm_state
.apic_lvt1
= apic_read(APIC_LVT1
);
1798 apic_pm_state
.apic_lvterr
= apic_read(APIC_LVTERR
);
1799 apic_pm_state
.apic_tmict
= apic_read(APIC_TMICT
);
1800 apic_pm_state
.apic_tdcr
= apic_read(APIC_TDCR
);
1801 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
1803 apic_pm_state
.apic_thmr
= apic_read(APIC_LVTTHMR
);
1806 local_irq_save(flags
);
1807 disable_local_APIC();
1808 local_irq_restore(flags
);
1812 static int lapic_resume(struct sys_device
*dev
)
1815 unsigned long flags
;
1818 if (!apic_pm_state
.active
)
1821 maxlvt
= lapic_get_maxlvt();
1823 local_irq_save(flags
);
1832 * Make sure the APICBASE points to the right address
1834 * FIXME! This will be wrong if we ever support suspend on
1835 * SMP! We'll need to do this as part of the CPU restore!
1837 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1838 l
&= ~MSR_IA32_APICBASE_BASE
;
1839 l
|= MSR_IA32_APICBASE_ENABLE
| mp_lapic_addr
;
1840 wrmsr(MSR_IA32_APICBASE
, l
, h
);
1843 apic_write(APIC_LVTERR
, ERROR_APIC_VECTOR
| APIC_LVT_MASKED
);
1844 apic_write(APIC_ID
, apic_pm_state
.apic_id
);
1845 apic_write(APIC_DFR
, apic_pm_state
.apic_dfr
);
1846 apic_write(APIC_LDR
, apic_pm_state
.apic_ldr
);
1847 apic_write(APIC_TASKPRI
, apic_pm_state
.apic_taskpri
);
1848 apic_write(APIC_SPIV
, apic_pm_state
.apic_spiv
);
1849 apic_write(APIC_LVT0
, apic_pm_state
.apic_lvt0
);
1850 apic_write(APIC_LVT1
, apic_pm_state
.apic_lvt1
);
1851 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
1853 apic_write(APIC_LVTTHMR
, apic_pm_state
.apic_thmr
);
1856 apic_write(APIC_LVTPC
, apic_pm_state
.apic_lvtpc
);
1857 apic_write(APIC_LVTT
, apic_pm_state
.apic_lvtt
);
1858 apic_write(APIC_TDCR
, apic_pm_state
.apic_tdcr
);
1859 apic_write(APIC_TMICT
, apic_pm_state
.apic_tmict
);
1860 apic_write(APIC_ESR
, 0);
1861 apic_read(APIC_ESR
);
1862 apic_write(APIC_LVTERR
, apic_pm_state
.apic_lvterr
);
1863 apic_write(APIC_ESR
, 0);
1864 apic_read(APIC_ESR
);
1866 local_irq_restore(flags
);
1872 * This device has no shutdown method - fully functioning local APICs
1873 * are needed on every CPU up until machine_halt/restart/poweroff.
1876 static struct sysdev_class lapic_sysclass
= {
1878 .resume
= lapic_resume
,
1879 .suspend
= lapic_suspend
,
1882 static struct sys_device device_lapic
= {
1884 .cls
= &lapic_sysclass
,
1887 static void __cpuinit
apic_pm_activate(void)
1889 apic_pm_state
.active
= 1;
1892 static int __init
init_lapic_sysfs(void)
1898 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
1900 error
= sysdev_class_register(&lapic_sysclass
);
1902 error
= sysdev_register(&device_lapic
);
1905 device_initcall(init_lapic_sysfs
);
1907 #else /* CONFIG_PM */
1909 static void apic_pm_activate(void) { }
1911 #endif /* CONFIG_PM */
1913 #ifdef CONFIG_X86_64
1915 * apic_is_clustered_box() -- Check if we can expect good TSC
1917 * Thus far, the major user of this is IBM's Summit2 series:
1919 * Clustered boxes may have unsynced TSC problems if they are
1920 * multi-chassis. Use available data to take a good guess.
1921 * If in doubt, go HPET.
1923 __cpuinit
int apic_is_clustered_box(void)
1925 int i
, clusters
, zeros
;
1927 u16
*bios_cpu_apicid
;
1928 DECLARE_BITMAP(clustermap
, NUM_APIC_CLUSTERS
);
1931 * there is not this kind of box with AMD CPU yet.
1932 * Some AMD box with quadcore cpu and 8 sockets apicid
1933 * will be [4, 0x23] or [8, 0x27] could be thought to
1934 * vsmp box still need checking...
1936 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
) && !is_vsmp_box())
1939 bios_cpu_apicid
= early_per_cpu_ptr(x86_bios_cpu_apicid
);
1940 bitmap_zero(clustermap
, NUM_APIC_CLUSTERS
);
1942 for (i
= 0; i
< NR_CPUS
; i
++) {
1943 /* are we being called early in kernel startup? */
1944 if (bios_cpu_apicid
) {
1945 id
= bios_cpu_apicid
[i
];
1947 else if (i
< nr_cpu_ids
) {
1949 id
= per_cpu(x86_bios_cpu_apicid
, i
);
1956 if (id
!= BAD_APICID
)
1957 __set_bit(APIC_CLUSTERID(id
), clustermap
);
1960 /* Problem: Partially populated chassis may not have CPUs in some of
1961 * the APIC clusters they have been allocated. Only present CPUs have
1962 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap.
1963 * Since clusters are allocated sequentially, count zeros only if
1964 * they are bounded by ones.
1968 for (i
= 0; i
< NUM_APIC_CLUSTERS
; i
++) {
1969 if (test_bit(i
, clustermap
)) {
1970 clusters
+= 1 + zeros
;
1976 /* ScaleMP vSMPowered boxes have one cluster per board and TSCs are
1977 * not guaranteed to be synced between boards
1979 if (is_vsmp_box() && clusters
> 1)
1983 * If clusters > 2, then should be multi-chassis.
1984 * May have to revisit this when multi-core + hyperthreaded CPUs come
1985 * out, but AFAIK this will work even for them.
1987 return (clusters
> 2);
1992 * APIC command line parameters
1994 static int __init
setup_disableapic(char *arg
)
1997 setup_clear_cpu_cap(X86_FEATURE_APIC
);
2000 early_param("disableapic", setup_disableapic
);
2002 /* same as disableapic, for compatibility */
2003 static int __init
setup_nolapic(char *arg
)
2005 return setup_disableapic(arg
);
2007 early_param("nolapic", setup_nolapic
);
2009 static int __init
parse_lapic_timer_c2_ok(char *arg
)
2011 local_apic_timer_c2_ok
= 1;
2014 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok
);
2016 static int __init
parse_disable_apic_timer(char *arg
)
2018 disable_apic_timer
= 1;
2021 early_param("noapictimer", parse_disable_apic_timer
);
2023 static int __init
parse_nolapic_timer(char *arg
)
2025 disable_apic_timer
= 1;
2028 early_param("nolapic_timer", parse_nolapic_timer
);
2030 static int __init
apic_set_verbosity(char *arg
)
2033 #ifdef CONFIG_X86_64
2034 skip_ioapic_setup
= 0;
2040 if (strcmp("debug", arg
) == 0)
2041 apic_verbosity
= APIC_DEBUG
;
2042 else if (strcmp("verbose", arg
) == 0)
2043 apic_verbosity
= APIC_VERBOSE
;
2045 printk(KERN_WARNING
"APIC Verbosity level %s not recognised"
2046 " use apic=verbose or apic=debug\n", arg
);
2052 early_param("apic", apic_set_verbosity
);
2054 static int __init
lapic_insert_resource(void)
2059 /* Put local APIC into the resource map. */
2060 lapic_resource
.start
= apic_phys
;
2061 lapic_resource
.end
= lapic_resource
.start
+ PAGE_SIZE
- 1;
2062 insert_resource(&iomem_resource
, &lapic_resource
);
2068 * need call insert after e820_reserve_resources()
2069 * that is using request_resource
2071 late_initcall(lapic_insert_resource
);