2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/bootmem.h>
22 #include <linux/interrupt.h>
23 #include <linux/mc146818rtc.h>
24 #include <linux/kernel_stat.h>
25 #include <linux/sysdev.h>
26 #include <linux/module.h>
27 #include <linux/ioport.h>
28 #include <linux/clockchips.h>
29 #include <linux/acpi_pmtmr.h>
31 #include <asm/atomic.h>
34 #include <asm/mpspec.h>
35 #include <asm/pgalloc.h>
36 #include <asm/mach_apic.h>
39 #include <asm/proto.h>
40 #include <asm/timex.h>
45 int disable_apic_timer __cpuinitdata
;
46 static int apic_calibrate_pmtmr __initdata
;
49 /* Local APIC timer works in C2? */
50 int local_apic_timer_c2_ok
;
51 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok
);
53 static struct resource lapic_resource
= {
55 .flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
,
58 static unsigned int calibration_result
;
60 static int lapic_next_event(unsigned long delta
,
61 struct clock_event_device
*evt
);
62 static void lapic_timer_setup(enum clock_event_mode mode
,
63 struct clock_event_device
*evt
);
64 static void lapic_timer_broadcast(cpumask_t mask
);
65 static void apic_pm_activate(void);
67 static struct clock_event_device lapic_clockevent
= {
69 .features
= CLOCK_EVT_FEAT_PERIODIC
| CLOCK_EVT_FEAT_ONESHOT
70 | CLOCK_EVT_FEAT_C3STOP
| CLOCK_EVT_FEAT_DUMMY
,
72 .set_mode
= lapic_timer_setup
,
73 .set_next_event
= lapic_next_event
,
74 .broadcast
= lapic_timer_broadcast
,
78 static DEFINE_PER_CPU(struct clock_event_device
, lapic_events
);
81 * Get the LAPIC version
83 static inline int lapic_get_version(void)
85 return GET_APIC_VERSION(apic_read(APIC_LVR
));
89 * Check, if the APIC is integrated or a seperate chip
91 static inline int lapic_is_integrated(void)
97 * Check, whether this is a modern or a first generation APIC
99 static int modern_apic(void)
101 /* AMD systems use old APIC versions, so check the CPU */
102 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
&&
103 boot_cpu_data
.x86
>= 0xf)
105 return lapic_get_version() >= 0x14;
108 void apic_wait_icr_idle(void)
110 while (apic_read(APIC_ICR
) & APIC_ICR_BUSY
)
114 u32
safe_apic_wait_icr_idle(void)
121 send_status
= apic_read(APIC_ICR
) & APIC_ICR_BUSY
;
125 } while (timeout
++ < 1000);
131 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
133 void enable_NMI_through_LVT0(void *dummy
)
137 /* unmask and set to NMI */
139 apic_write(APIC_LVT0
, v
);
143 * lapic_get_maxlvt - get the maximum number of local vector table entries
145 int lapic_get_maxlvt(void)
147 unsigned int v
, maxlvt
;
149 v
= apic_read(APIC_LVR
);
150 maxlvt
= GET_APIC_MAXLVT(v
);
155 * This function sets up the local APIC timer, with a timeout of
156 * 'clocks' APIC bus clock. During calibration we actually call
157 * this function twice on the boot CPU, once with a bogus timeout
158 * value, second time for real. The other (noncalibrating) CPUs
159 * call this function only once, with the real, calibrated value.
161 * We do reads before writes even if unnecessary, to get around the
162 * P5 APIC double write bug.
165 static void __setup_APIC_LVTT(unsigned int clocks
, int oneshot
, int irqen
)
167 unsigned int lvtt_value
, tmp_value
;
169 lvtt_value
= LOCAL_TIMER_VECTOR
;
171 lvtt_value
|= APIC_LVT_TIMER_PERIODIC
;
173 lvtt_value
|= APIC_LVT_MASKED
;
175 apic_write(APIC_LVTT
, lvtt_value
);
180 tmp_value
= apic_read(APIC_TDCR
);
181 apic_write(APIC_TDCR
, (tmp_value
182 & ~(APIC_TDR_DIV_1
| APIC_TDR_DIV_TMBASE
))
186 apic_write(APIC_TMICT
, clocks
);
190 * Setup extended LVT (K8 specific)
192 void setup_APIC_extended_lvt(unsigned char lvt_off
, unsigned char vector
,
193 unsigned char msg_type
, unsigned char mask
)
195 unsigned long reg
= (lvt_off
<< 4) + K8_APIC_EXT_LVT_BASE
;
196 unsigned int v
= (mask
<< 16) | (msg_type
<< 8) | vector
;
202 * Program the next event, relative to now
204 static int lapic_next_event(unsigned long delta
,
205 struct clock_event_device
*evt
)
207 apic_write(APIC_TMICT
, delta
);
212 * Setup the lapic timer in periodic or oneshot mode
214 static void lapic_timer_setup(enum clock_event_mode mode
,
215 struct clock_event_device
*evt
)
220 /* Lapic used as dummy for broadcast ? */
221 if (evt
->features
& CLOCK_EVT_FEAT_DUMMY
)
224 local_irq_save(flags
);
227 case CLOCK_EVT_MODE_PERIODIC
:
228 case CLOCK_EVT_MODE_ONESHOT
:
229 __setup_APIC_LVTT(calibration_result
,
230 mode
!= CLOCK_EVT_MODE_PERIODIC
, 1);
232 case CLOCK_EVT_MODE_UNUSED
:
233 case CLOCK_EVT_MODE_SHUTDOWN
:
234 v
= apic_read(APIC_LVTT
);
235 v
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
236 apic_write(APIC_LVTT
, v
);
238 case CLOCK_EVT_MODE_RESUME
:
239 /* Nothing to do here */
243 local_irq_restore(flags
);
247 * Local APIC timer broadcast function
249 static void lapic_timer_broadcast(cpumask_t mask
)
252 send_IPI_mask(mask
, LOCAL_TIMER_VECTOR
);
257 * Setup the local APIC timer for this CPU. Copy the initilized values
258 * of the boot CPU and register the clock event in the framework.
260 static void setup_APIC_timer(void)
262 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
264 memcpy(levt
, &lapic_clockevent
, sizeof(*levt
));
265 levt
->cpumask
= cpumask_of_cpu(smp_processor_id());
267 clockevents_register_device(levt
);
271 * In this function we calibrate APIC bus clocks to the external
272 * timer. Unfortunately we cannot use jiffies and the timer irq
273 * to calibrate, since some later bootup code depends on getting
274 * the first irq? Ugh.
276 * We want to do the calibration only once since we
277 * want to have local timer irqs syncron. CPUs connected
278 * by the same APIC bus have the very same bus frequency.
279 * And we want to have irqs off anyways, no accidental
283 #define TICK_COUNT 100000000
285 static void __init
calibrate_APIC_clock(void)
287 unsigned apic
, apic_start
;
288 unsigned long tsc
, tsc_start
;
294 * Put whatever arbitrary (but long enough) timeout
295 * value into the APIC clock, we just want to get the
296 * counter running for calibration.
298 * No interrupt enable !
300 __setup_APIC_LVTT(250000000, 0, 0);
302 apic_start
= apic_read(APIC_TMCCT
);
303 #ifdef CONFIG_X86_PM_TIMER
304 if (apic_calibrate_pmtmr
&& pmtmr_ioport
) {
305 pmtimer_wait(5000); /* 5ms wait */
306 apic
= apic_read(APIC_TMCCT
);
307 result
= (apic_start
- apic
) * 1000L / 5;
314 apic
= apic_read(APIC_TMCCT
);
316 } while ((tsc
- tsc_start
) < TICK_COUNT
&&
317 (apic_start
- apic
) < TICK_COUNT
);
319 result
= (apic_start
- apic
) * 1000L * tsc_khz
/
325 printk(KERN_DEBUG
"APIC timer calibration result %d\n", result
);
327 printk(KERN_INFO
"Detected %d.%03d MHz APIC timer.\n",
328 result
/ 1000 / 1000, result
/ 1000 % 1000);
330 /* Calculate the scaled math multiplication factor */
331 lapic_clockevent
.mult
= div_sc(result
, NSEC_PER_SEC
, 32);
332 lapic_clockevent
.max_delta_ns
=
333 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent
);
334 lapic_clockevent
.min_delta_ns
=
335 clockevent_delta2ns(0xF, &lapic_clockevent
);
337 calibration_result
= result
/ HZ
;
340 void __init
setup_boot_APIC_clock(void)
343 * The local apic timer can be disabled via the kernel commandline.
344 * Register the lapic timer as a dummy clock event source on SMP
345 * systems, so the broadcast mechanism is used. On UP systems simply
348 if (disable_apic_timer
) {
349 printk(KERN_INFO
"Disabling APIC timer\n");
350 /* No broadcast on UP ! */
351 if (num_possible_cpus() > 1)
356 printk(KERN_INFO
"Using local APIC timer interrupts.\n");
357 calibrate_APIC_clock();
360 * If nmi_watchdog is set to IO_APIC, we need the
361 * PIT/HPET going. Otherwise register lapic as a dummy
364 if (nmi_watchdog
!= NMI_IO_APIC
)
365 lapic_clockevent
.features
&= ~CLOCK_EVT_FEAT_DUMMY
;
367 printk(KERN_WARNING
"APIC timer registered as dummy,"
368 " due to nmi_watchdog=1!\n");
374 * AMD C1E enabled CPUs have a real nasty problem: Some BIOSes set the
375 * C1E flag only in the secondary CPU, so when we detect the wreckage
376 * we already have enabled the boot CPU local apic timer. Check, if
377 * disable_apic_timer is set and the DUMMY flag is cleared. If yes,
378 * set the DUMMY flag again and force the broadcast mode in the
381 void __cpuinit
check_boot_apic_timer_broadcast(void)
383 if (!disable_apic_timer
||
384 (lapic_clockevent
.features
& CLOCK_EVT_FEAT_DUMMY
))
387 printk(KERN_INFO
"AMD C1E detected late. Force timer broadcast.\n");
388 lapic_clockevent
.features
|= CLOCK_EVT_FEAT_DUMMY
;
391 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE
, &boot_cpu_id
);
395 void __cpuinit
setup_secondary_APIC_clock(void)
397 check_boot_apic_timer_broadcast();
402 * The guts of the apic timer interrupt
404 static void local_apic_timer_interrupt(void)
406 int cpu
= smp_processor_id();
407 struct clock_event_device
*evt
= &per_cpu(lapic_events
, cpu
);
410 * Normally we should not be here till LAPIC has been initialized but
411 * in some cases like kdump, its possible that there is a pending LAPIC
412 * timer interrupt from previous kernel's context and is delivered in
413 * new kernel the moment interrupts are enabled.
415 * Interrupts are enabled early and LAPIC is setup much later, hence
416 * its possible that when we get here evt->event_handler is NULL.
417 * Check for event_handler being NULL and discard the interrupt as
420 if (!evt
->event_handler
) {
422 "Spurious LAPIC timer interrupt on cpu %d\n", cpu
);
424 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, evt
);
429 * the NMI deadlock-detector uses this.
431 add_pda(apic_timer_irqs
, 1);
433 evt
->event_handler(evt
);
437 * Local APIC timer interrupt. This is the most natural way for doing
438 * local interrupts, but local timer interrupts can be emulated by
439 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
441 * [ if a single-CPU system runs an SMP kernel then we call the local
442 * interrupt as well. Thus we cannot inline the local irq ... ]
444 void smp_apic_timer_interrupt(struct pt_regs
*regs
)
446 struct pt_regs
*old_regs
= set_irq_regs(regs
);
449 * NOTE! We'd better ACK the irq immediately,
450 * because timer handling can be slow.
454 * update_process_times() expects us to have done irq_enter().
455 * Besides, if we don't timer interrupts ignore the global
456 * interrupt lock, which is the WrongThing (tm) to do.
460 local_apic_timer_interrupt();
462 set_irq_regs(old_regs
);
465 int setup_profiling_timer(unsigned int multiplier
)
472 * Local APIC start and shutdown
476 * clear_local_APIC - shutdown the local APIC
478 * This is called, when a CPU is disabled and before rebooting, so the state of
479 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
480 * leftovers during boot.
482 void clear_local_APIC(void)
484 int maxlvt
= lapic_get_maxlvt();
488 * Masking an LVT entry can trigger a local APIC error
489 * if the vector is zero. Mask LVTERR first to prevent this.
492 v
= ERROR_APIC_VECTOR
; /* any non-zero vector will do */
493 apic_write(APIC_LVTERR
, v
| APIC_LVT_MASKED
);
496 * Careful: we have to set masks only first to deassert
497 * any level-triggered sources.
499 v
= apic_read(APIC_LVTT
);
500 apic_write(APIC_LVTT
, v
| APIC_LVT_MASKED
);
501 v
= apic_read(APIC_LVT0
);
502 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
503 v
= apic_read(APIC_LVT1
);
504 apic_write(APIC_LVT1
, v
| APIC_LVT_MASKED
);
506 v
= apic_read(APIC_LVTPC
);
507 apic_write(APIC_LVTPC
, v
| APIC_LVT_MASKED
);
511 * Clean APIC state for other OSs:
513 apic_write(APIC_LVTT
, APIC_LVT_MASKED
);
514 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
515 apic_write(APIC_LVT1
, APIC_LVT_MASKED
);
517 apic_write(APIC_LVTERR
, APIC_LVT_MASKED
);
519 apic_write(APIC_LVTPC
, APIC_LVT_MASKED
);
520 apic_write(APIC_ESR
, 0);
525 * disable_local_APIC - clear and disable the local APIC
527 void disable_local_APIC(void)
534 * Disable APIC (implies clearing of registers
537 value
= apic_read(APIC_SPIV
);
538 value
&= ~APIC_SPIV_APIC_ENABLED
;
539 apic_write(APIC_SPIV
, value
);
542 void lapic_shutdown(void)
549 local_irq_save(flags
);
551 disable_local_APIC();
553 local_irq_restore(flags
);
557 * This is to verify that we're looking at a real local APIC.
558 * Check these against your board if the CPUs aren't getting
559 * started for no apparent reason.
561 int __init
verify_local_APIC(void)
563 unsigned int reg0
, reg1
;
566 * The version register is read-only in a real APIC.
568 reg0
= apic_read(APIC_LVR
);
569 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg0
);
570 apic_write(APIC_LVR
, reg0
^ APIC_LVR_MASK
);
571 reg1
= apic_read(APIC_LVR
);
572 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg1
);
575 * The two version reads above should print the same
576 * numbers. If the second one is different, then we
577 * poke at a non-APIC.
583 * Check if the version looks reasonably.
585 reg1
= GET_APIC_VERSION(reg0
);
586 if (reg1
== 0x00 || reg1
== 0xff)
588 reg1
= lapic_get_maxlvt();
589 if (reg1
< 0x02 || reg1
== 0xff)
593 * The ID register is read/write in a real APIC.
595 reg0
= apic_read(APIC_ID
);
596 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg0
);
597 apic_write(APIC_ID
, reg0
^ APIC_ID_MASK
);
598 reg1
= apic_read(APIC_ID
);
599 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg1
);
600 apic_write(APIC_ID
, reg0
);
601 if (reg1
!= (reg0
^ APIC_ID_MASK
))
605 * The next two are just to see if we have sane values.
606 * They're only really relevant if we're in Virtual Wire
607 * compatibility mode, but most boxes are anymore.
609 reg0
= apic_read(APIC_LVT0
);
610 apic_printk(APIC_DEBUG
, "Getting LVT0: %x\n", reg0
);
611 reg1
= apic_read(APIC_LVT1
);
612 apic_printk(APIC_DEBUG
, "Getting LVT1: %x\n", reg1
);
618 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
620 void __init
sync_Arb_IDs(void)
622 /* Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 */
629 apic_wait_icr_idle();
631 apic_printk(APIC_DEBUG
, "Synchronizing Arb IDs.\n");
632 apic_write(APIC_ICR
, APIC_DEST_ALLINC
| APIC_INT_LEVELTRIG
637 * An initial setup of the virtual wire mode.
639 void __init
init_bsp_APIC(void)
644 * Don't do the setup now if we have a SMP BIOS as the
645 * through-I/O-APIC virtual wire mode might be active.
647 if (smp_found_config
|| !cpu_has_apic
)
650 value
= apic_read(APIC_LVR
);
653 * Do not trust the local APIC being empty at bootup.
660 value
= apic_read(APIC_SPIV
);
661 value
&= ~APIC_VECTOR_MASK
;
662 value
|= APIC_SPIV_APIC_ENABLED
;
663 value
|= APIC_SPIV_FOCUS_DISABLED
;
664 value
|= SPURIOUS_APIC_VECTOR
;
665 apic_write(APIC_SPIV
, value
);
668 * Set up the virtual wire mode.
670 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
672 apic_write(APIC_LVT1
, value
);
676 * setup_local_APIC - setup the local APIC
678 void __cpuinit
setup_local_APIC(void)
683 value
= apic_read(APIC_LVR
);
685 BUILD_BUG_ON((SPURIOUS_APIC_VECTOR
& 0x0f) != 0x0f);
688 * Double-check whether this APIC is really registered.
689 * This is meaningless in clustered apic mode, so we skip it.
691 if (!apic_id_registered())
695 * Intel recommends to set DFR, LDR and TPR before enabling
696 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
697 * document number 292116). So here it goes...
702 * Set Task Priority to 'accept all'. We never change this
705 value
= apic_read(APIC_TASKPRI
);
706 value
&= ~APIC_TPRI_MASK
;
707 apic_write(APIC_TASKPRI
, value
);
710 * After a crash, we no longer service the interrupts and a pending
711 * interrupt from previous kernel might still have ISR bit set.
713 * Most probably by now CPU has serviced that pending interrupt and
714 * it might not have done the ack_APIC_irq() because it thought,
715 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
716 * does not clear the ISR bit and cpu thinks it has already serivced
717 * the interrupt. Hence a vector might get locked. It was noticed
718 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
720 for (i
= APIC_ISR_NR
- 1; i
>= 0; i
--) {
721 value
= apic_read(APIC_ISR
+ i
*0x10);
722 for (j
= 31; j
>= 0; j
--) {
729 * Now that we are all set up, enable the APIC
731 value
= apic_read(APIC_SPIV
);
732 value
&= ~APIC_VECTOR_MASK
;
736 value
|= APIC_SPIV_APIC_ENABLED
;
738 /* We always use processor focus */
741 * Set spurious IRQ vector
743 value
|= SPURIOUS_APIC_VECTOR
;
744 apic_write(APIC_SPIV
, value
);
749 * set up through-local-APIC on the BP's LINT0. This is not
750 * strictly necessary in pure symmetric-IO mode, but sometimes
751 * we delegate interrupts to the 8259A.
754 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
756 value
= apic_read(APIC_LVT0
) & APIC_LVT_MASKED
;
757 if (!smp_processor_id() && !value
) {
758 value
= APIC_DM_EXTINT
;
759 apic_printk(APIC_VERBOSE
, "enabled ExtINT on CPU#%d\n",
762 value
= APIC_DM_EXTINT
| APIC_LVT_MASKED
;
763 apic_printk(APIC_VERBOSE
, "masked ExtINT on CPU#%d\n",
766 apic_write(APIC_LVT0
, value
);
769 * only the BP should see the LINT1 NMI signal, obviously.
771 if (!smp_processor_id())
774 value
= APIC_DM_NMI
| APIC_LVT_MASKED
;
775 apic_write(APIC_LVT1
, value
);
778 void __cpuinit
lapic_setup_esr(void)
780 unsigned maxlvt
= lapic_get_maxlvt();
782 apic_write(APIC_LVTERR
, ERROR_APIC_VECTOR
);
784 * spec says clear errors after enabling vector.
787 apic_write(APIC_ESR
, 0);
790 void __cpuinit
end_local_APIC_setup(void)
793 nmi_watchdog_default();
794 setup_apic_nmi_watchdog(NULL
);
799 * Detect and enable local APICs on non-SMP boards.
800 * Original code written by Keir Fraser.
801 * On AMD64 we trust the BIOS - if it says no APIC it is likely
802 * not correctly set up (usually the APIC timer won't work etc.)
804 static int __init
detect_init_APIC(void)
807 printk(KERN_INFO
"No local APIC present\n");
811 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
817 * init_apic_mappings - initialize APIC mappings
819 void __init
init_apic_mappings(void)
821 unsigned long apic_phys
;
824 * If no local APIC can be found then set up a fake all
825 * zeroes page to simulate the local APIC and another
826 * one for the IO-APIC.
828 if (!smp_found_config
&& detect_init_APIC()) {
829 apic_phys
= (unsigned long) alloc_bootmem_pages(PAGE_SIZE
);
830 apic_phys
= __pa(apic_phys
);
832 apic_phys
= mp_lapic_addr
;
834 set_fixmap_nocache(FIX_APIC_BASE
, apic_phys
);
835 apic_printk(APIC_VERBOSE
, "mapped APIC to %16lx (%16lx)\n",
836 APIC_BASE
, apic_phys
);
838 /* Put local APIC into the resource map. */
839 lapic_resource
.start
= apic_phys
;
840 lapic_resource
.end
= lapic_resource
.start
+ PAGE_SIZE
- 1;
841 insert_resource(&iomem_resource
, &lapic_resource
);
844 * Fetch the APIC ID of the BSP in case we have a
845 * default configuration (or the MP table is broken).
847 boot_cpu_id
= GET_APIC_ID(apic_read(APIC_ID
));
851 * This initializes the IO-APIC and APIC hardware if this is
854 int __init
APIC_init_uniprocessor(void)
857 printk(KERN_INFO
"Apic disabled\n");
862 printk(KERN_INFO
"Apic disabled by BIOS\n");
868 phys_cpu_present_map
= physid_mask_of_physid(boot_cpu_id
);
869 apic_write(APIC_ID
, SET_APIC_ID(boot_cpu_id
));
874 * Now enable IO-APICs, actually call clear_IO_APIC
875 * We need clear_IO_APIC before enabling vector on BP
877 if (!skip_ioapic_setup
&& nr_ioapics
)
880 end_local_APIC_setup();
882 if (smp_found_config
&& !skip_ioapic_setup
&& nr_ioapics
)
886 setup_boot_APIC_clock();
887 check_nmi_watchdog();
892 * Local APIC interrupts
896 * This interrupt should _never_ happen with our APIC/SMP architecture
898 asmlinkage
void smp_spurious_interrupt(void)
904 * Check if this really is a spurious interrupt and ACK it
905 * if it is a vectored one. Just in case...
906 * Spurious interrupts should not be ACKed.
908 v
= apic_read(APIC_ISR
+ ((SPURIOUS_APIC_VECTOR
& ~0x1f) >> 1));
909 if (v
& (1 << (SPURIOUS_APIC_VECTOR
& 0x1f)))
912 add_pda(irq_spurious_count
, 1);
917 * This interrupt should never happen with our APIC/SMP architecture
919 asmlinkage
void smp_error_interrupt(void)
925 /* First tickle the hardware, only then report what went on. -- REW */
926 v
= apic_read(APIC_ESR
);
927 apic_write(APIC_ESR
, 0);
928 v1
= apic_read(APIC_ESR
);
930 atomic_inc(&irq_err_count
);
932 /* Here is what the APIC error bits mean:
936 3: Receive accept error
938 5: Send illegal vector
939 6: Received illegal vector
940 7: Illegal register address
942 printk(KERN_DEBUG
"APIC error on CPU%d: %02x(%02x)\n",
943 smp_processor_id(), v
, v1
);
947 void disconnect_bsp_APIC(int virt_wire_setup
)
949 /* Go back to Virtual Wire compatibility mode */
952 /* For the spurious interrupt use vector F, and enable it */
953 value
= apic_read(APIC_SPIV
);
954 value
&= ~APIC_VECTOR_MASK
;
955 value
|= APIC_SPIV_APIC_ENABLED
;
957 apic_write(APIC_SPIV
, value
);
959 if (!virt_wire_setup
) {
961 * For LVT0 make it edge triggered, active high,
962 * external and enabled
964 value
= apic_read(APIC_LVT0
);
965 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
966 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
967 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
968 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
969 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_EXTINT
);
970 apic_write(APIC_LVT0
, value
);
973 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
976 /* For LVT1 make it edge triggered, active high, nmi and enabled */
977 value
= apic_read(APIC_LVT1
);
978 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
979 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
980 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
981 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
982 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_NMI
);
983 apic_write(APIC_LVT1
, value
);
992 /* 'active' is true if the local APIC was enabled by us and
993 not the BIOS; this signifies that we are also responsible
994 for disabling it before entering apm/acpi suspend */
996 /* r/w apic fields */
997 unsigned int apic_id
;
998 unsigned int apic_taskpri
;
999 unsigned int apic_ldr
;
1000 unsigned int apic_dfr
;
1001 unsigned int apic_spiv
;
1002 unsigned int apic_lvtt
;
1003 unsigned int apic_lvtpc
;
1004 unsigned int apic_lvt0
;
1005 unsigned int apic_lvt1
;
1006 unsigned int apic_lvterr
;
1007 unsigned int apic_tmict
;
1008 unsigned int apic_tdcr
;
1009 unsigned int apic_thmr
;
1012 static int lapic_suspend(struct sys_device
*dev
, pm_message_t state
)
1014 unsigned long flags
;
1017 if (!apic_pm_state
.active
)
1020 maxlvt
= lapic_get_maxlvt();
1022 apic_pm_state
.apic_id
= apic_read(APIC_ID
);
1023 apic_pm_state
.apic_taskpri
= apic_read(APIC_TASKPRI
);
1024 apic_pm_state
.apic_ldr
= apic_read(APIC_LDR
);
1025 apic_pm_state
.apic_dfr
= apic_read(APIC_DFR
);
1026 apic_pm_state
.apic_spiv
= apic_read(APIC_SPIV
);
1027 apic_pm_state
.apic_lvtt
= apic_read(APIC_LVTT
);
1029 apic_pm_state
.apic_lvtpc
= apic_read(APIC_LVTPC
);
1030 apic_pm_state
.apic_lvt0
= apic_read(APIC_LVT0
);
1031 apic_pm_state
.apic_lvt1
= apic_read(APIC_LVT1
);
1032 apic_pm_state
.apic_lvterr
= apic_read(APIC_LVTERR
);
1033 apic_pm_state
.apic_tmict
= apic_read(APIC_TMICT
);
1034 apic_pm_state
.apic_tdcr
= apic_read(APIC_TDCR
);
1035 #ifdef CONFIG_X86_MCE_INTEL
1037 apic_pm_state
.apic_thmr
= apic_read(APIC_LVTTHMR
);
1039 local_irq_save(flags
);
1040 disable_local_APIC();
1041 local_irq_restore(flags
);
1045 static int lapic_resume(struct sys_device
*dev
)
1048 unsigned long flags
;
1051 if (!apic_pm_state
.active
)
1054 maxlvt
= lapic_get_maxlvt();
1056 local_irq_save(flags
);
1057 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1058 l
&= ~MSR_IA32_APICBASE_BASE
;
1059 l
|= MSR_IA32_APICBASE_ENABLE
| mp_lapic_addr
;
1060 wrmsr(MSR_IA32_APICBASE
, l
, h
);
1061 apic_write(APIC_LVTERR
, ERROR_APIC_VECTOR
| APIC_LVT_MASKED
);
1062 apic_write(APIC_ID
, apic_pm_state
.apic_id
);
1063 apic_write(APIC_DFR
, apic_pm_state
.apic_dfr
);
1064 apic_write(APIC_LDR
, apic_pm_state
.apic_ldr
);
1065 apic_write(APIC_TASKPRI
, apic_pm_state
.apic_taskpri
);
1066 apic_write(APIC_SPIV
, apic_pm_state
.apic_spiv
);
1067 apic_write(APIC_LVT0
, apic_pm_state
.apic_lvt0
);
1068 apic_write(APIC_LVT1
, apic_pm_state
.apic_lvt1
);
1069 #ifdef CONFIG_X86_MCE_INTEL
1071 apic_write(APIC_LVTTHMR
, apic_pm_state
.apic_thmr
);
1074 apic_write(APIC_LVTPC
, apic_pm_state
.apic_lvtpc
);
1075 apic_write(APIC_LVTT
, apic_pm_state
.apic_lvtt
);
1076 apic_write(APIC_TDCR
, apic_pm_state
.apic_tdcr
);
1077 apic_write(APIC_TMICT
, apic_pm_state
.apic_tmict
);
1078 apic_write(APIC_ESR
, 0);
1079 apic_read(APIC_ESR
);
1080 apic_write(APIC_LVTERR
, apic_pm_state
.apic_lvterr
);
1081 apic_write(APIC_ESR
, 0);
1082 apic_read(APIC_ESR
);
1083 local_irq_restore(flags
);
1087 static struct sysdev_class lapic_sysclass
= {
1089 .resume
= lapic_resume
,
1090 .suspend
= lapic_suspend
,
1093 static struct sys_device device_lapic
= {
1095 .cls
= &lapic_sysclass
,
1098 static void __cpuinit
apic_pm_activate(void)
1100 apic_pm_state
.active
= 1;
1103 static int __init
init_lapic_sysfs(void)
1108 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
1109 error
= sysdev_class_register(&lapic_sysclass
);
1111 error
= sysdev_register(&device_lapic
);
1114 device_initcall(init_lapic_sysfs
);
1116 #else /* CONFIG_PM */
1118 static void apic_pm_activate(void) { }
1120 #endif /* CONFIG_PM */
1123 * apic_is_clustered_box() -- Check if we can expect good TSC
1125 * Thus far, the major user of this is IBM's Summit2 series:
1127 * Clustered boxes may have unsynced TSC problems if they are
1128 * multi-chassis. Use available data to take a good guess.
1129 * If in doubt, go HPET.
1131 __cpuinit
int apic_is_clustered_box(void)
1133 int i
, clusters
, zeros
;
1135 DECLARE_BITMAP(clustermap
, NUM_APIC_CLUSTERS
);
1137 bitmap_zero(clustermap
, NUM_APIC_CLUSTERS
);
1139 for (i
= 0; i
< NR_CPUS
; i
++) {
1140 id
= bios_cpu_apicid
[i
];
1141 if (id
!= BAD_APICID
)
1142 __set_bit(APIC_CLUSTERID(id
), clustermap
);
1145 /* Problem: Partially populated chassis may not have CPUs in some of
1146 * the APIC clusters they have been allocated. Only present CPUs have
1147 * bios_cpu_apicid entries, thus causing zeroes in the bitmap. Since
1148 * clusters are allocated sequentially, count zeros only if they are
1153 for (i
= 0; i
< NUM_APIC_CLUSTERS
; i
++) {
1154 if (test_bit(i
, clustermap
)) {
1155 clusters
+= 1 + zeros
;
1162 * If clusters > 2, then should be multi-chassis.
1163 * May have to revisit this when multi-core + hyperthreaded CPUs come
1164 * out, but AFAIK this will work even for them.
1166 return (clusters
> 2);
1170 * APIC command line parameters
1172 static int __init
apic_set_verbosity(char *str
)
1175 skip_ioapic_setup
= 0;
1179 if (strcmp("debug", str
) == 0)
1180 apic_verbosity
= APIC_DEBUG
;
1181 else if (strcmp("verbose", str
) == 0)
1182 apic_verbosity
= APIC_VERBOSE
;
1184 printk(KERN_WARNING
"APIC Verbosity level %s not recognised"
1185 " use apic=verbose or apic=debug\n", str
);
1191 early_param("apic", apic_set_verbosity
);
1193 static __init
int setup_disableapic(char *str
)
1196 clear_bit(X86_FEATURE_APIC
, boot_cpu_data
.x86_capability
);
1199 early_param("disableapic", setup_disableapic
);
1201 /* same as disableapic, for compatibility */
1202 static __init
int setup_nolapic(char *str
)
1204 return setup_disableapic(str
);
1206 early_param("nolapic", setup_nolapic
);
1208 static int __init
parse_lapic_timer_c2_ok(char *arg
)
1210 local_apic_timer_c2_ok
= 1;
1213 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok
);
1215 static __init
int setup_noapictimer(char *str
)
1217 if (str
[0] != ' ' && str
[0] != 0)
1219 disable_apic_timer
= 1;
1222 __setup("noapictimer", setup_noapictimer
);
1224 static __init
int setup_apicpmtimer(char *s
)
1226 apic_calibrate_pmtmr
= 1;
1230 __setup("apicpmtimer", setup_apicpmtimer
);