2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/bootmem.h>
22 #include <linux/interrupt.h>
23 #include <linux/mc146818rtc.h>
24 #include <linux/kernel_stat.h>
25 #include <linux/sysdev.h>
26 #include <linux/ioport.h>
27 #include <linux/clockchips.h>
28 #include <linux/acpi_pmtmr.h>
29 #include <linux/module.h>
30 #include <linux/dmar.h>
32 #include <asm/atomic.h>
35 #include <asm/mpspec.h>
38 #include <asm/pgalloc.h>
41 #include <asm/proto.h>
42 #include <asm/timex.h>
44 #include <asm/i8259.h>
47 #include <mach_apic.h>
52 #if ((SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F)
53 # error SPURIOUS_APIC_VECTOR definition error
58 * Knob to control our willingness to enable the local APIC.
62 static int force_enable_local_apic
;
64 * APIC command line parameters
66 static int __init
parse_lapic(char *arg
)
68 force_enable_local_apic
= 1;
71 early_param("lapic", parse_lapic
);
75 static int apic_calibrate_pmtmr __initdata
;
76 static __init
int setup_apicpmtimer(char *s
)
78 apic_calibrate_pmtmr
= 1;
82 __setup("apicpmtimer", setup_apicpmtimer
);
91 /* x2apic enabled before OS handover */
92 int x2apic_preenabled
;
94 static __init
int setup_nox2apic(char *str
)
97 setup_clear_cpu_cap(X86_FEATURE_X2APIC
);
100 early_param("nox2apic", setup_nox2apic
);
103 unsigned long mp_lapic_addr
;
105 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
106 static int disable_apic_timer __cpuinitdata
;
107 /* Local APIC timer works in C2 */
108 int local_apic_timer_c2_ok
;
109 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok
);
111 int first_system_vector
= 0xfe;
113 char system_vectors
[NR_VECTORS
] = { [0 ... NR_VECTORS
-1] = SYS_VECTOR_FREE
};
116 * Debug level, exported for io_apic.c
118 unsigned int apic_verbosity
;
122 /* Have we found an MP table */
123 int smp_found_config
;
125 static struct resource lapic_resource
= {
126 .name
= "Local APIC",
127 .flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
,
130 static unsigned int calibration_result
;
132 static int lapic_next_event(unsigned long delta
,
133 struct clock_event_device
*evt
);
134 static void lapic_timer_setup(enum clock_event_mode mode
,
135 struct clock_event_device
*evt
);
136 static void lapic_timer_broadcast(cpumask_t mask
);
137 static void apic_pm_activate(void);
140 * The local apic timer can be used for any function which is CPU local.
142 static struct clock_event_device lapic_clockevent
= {
144 .features
= CLOCK_EVT_FEAT_PERIODIC
| CLOCK_EVT_FEAT_ONESHOT
145 | CLOCK_EVT_FEAT_C3STOP
| CLOCK_EVT_FEAT_DUMMY
,
147 .set_mode
= lapic_timer_setup
,
148 .set_next_event
= lapic_next_event
,
149 .broadcast
= lapic_timer_broadcast
,
153 static DEFINE_PER_CPU(struct clock_event_device
, lapic_events
);
155 static unsigned long apic_phys
;
158 * Get the LAPIC version
160 static inline int lapic_get_version(void)
162 return GET_APIC_VERSION(apic_read(APIC_LVR
));
166 * Check, if the APIC is integrated or a separate chip
168 static inline int lapic_is_integrated(void)
173 return APIC_INTEGRATED(lapic_get_version());
178 * Check, whether this is a modern or a first generation APIC
180 static int modern_apic(void)
182 /* AMD systems use old APIC versions, so check the CPU */
183 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
&&
184 boot_cpu_data
.x86
>= 0xf)
186 return lapic_get_version() >= 0x14;
190 * Paravirt kernels also might be using these below ops. So we still
191 * use generic apic_read()/apic_write(), which might be pointing to different
192 * ops in PARAVIRT case.
194 void xapic_wait_icr_idle(void)
196 while (apic_read(APIC_ICR
) & APIC_ICR_BUSY
)
200 u32
safe_xapic_wait_icr_idle(void)
207 send_status
= apic_read(APIC_ICR
) & APIC_ICR_BUSY
;
211 } while (timeout
++ < 1000);
216 void xapic_icr_write(u32 low
, u32 id
)
218 apic_write(APIC_ICR2
, SET_APIC_DEST_FIELD(id
));
219 apic_write(APIC_ICR
, low
);
222 u64
xapic_icr_read(void)
226 icr2
= apic_read(APIC_ICR2
);
227 icr1
= apic_read(APIC_ICR
);
229 return icr1
| ((u64
)icr2
<< 32);
232 static struct apic_ops xapic_ops
= {
233 .read
= native_apic_mem_read
,
234 .write
= native_apic_mem_write
,
235 .icr_read
= xapic_icr_read
,
236 .icr_write
= xapic_icr_write
,
237 .wait_icr_idle
= xapic_wait_icr_idle
,
238 .safe_wait_icr_idle
= safe_xapic_wait_icr_idle
,
241 struct apic_ops __read_mostly
*apic_ops
= &xapic_ops
;
242 EXPORT_SYMBOL_GPL(apic_ops
);
245 static void x2apic_wait_icr_idle(void)
247 /* no need to wait for icr idle in x2apic */
251 static u32
safe_x2apic_wait_icr_idle(void)
253 /* no need to wait for icr idle in x2apic */
257 void x2apic_icr_write(u32 low
, u32 id
)
259 wrmsrl(APIC_BASE_MSR
+ (APIC_ICR
>> 4), ((__u64
) id
) << 32 | low
);
262 u64
x2apic_icr_read(void)
266 rdmsrl(APIC_BASE_MSR
+ (APIC_ICR
>> 4), val
);
270 static struct apic_ops x2apic_ops
= {
271 .read
= native_apic_msr_read
,
272 .write
= native_apic_msr_write
,
273 .icr_read
= x2apic_icr_read
,
274 .icr_write
= x2apic_icr_write
,
275 .wait_icr_idle
= x2apic_wait_icr_idle
,
276 .safe_wait_icr_idle
= safe_x2apic_wait_icr_idle
,
281 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
283 void __cpuinit
enable_NMI_through_LVT0(void)
287 /* unmask and set to NMI */
290 /* Level triggered for 82489DX (32bit mode) */
291 if (!lapic_is_integrated())
292 v
|= APIC_LVT_LEVEL_TRIGGER
;
294 apic_write(APIC_LVT0
, v
);
299 * get_physical_broadcast - Get number of physical broadcast IDs
301 int get_physical_broadcast(void)
303 return modern_apic() ? 0xff : 0xf;
308 * lapic_get_maxlvt - get the maximum number of local vector table entries
310 int lapic_get_maxlvt(void)
314 v
= apic_read(APIC_LVR
);
316 * - we always have APIC integrated on 64bit mode
317 * - 82489DXs do not report # of LVT entries
319 return APIC_INTEGRATED(GET_APIC_VERSION(v
)) ? GET_APIC_MAXLVT(v
) : 2;
328 #define APIC_DIVISOR 1
330 #define APIC_DIVISOR 16
334 * This function sets up the local APIC timer, with a timeout of
335 * 'clocks' APIC bus clock. During calibration we actually call
336 * this function twice on the boot CPU, once with a bogus timeout
337 * value, second time for real. The other (noncalibrating) CPUs
338 * call this function only once, with the real, calibrated value.
340 * We do reads before writes even if unnecessary, to get around the
341 * P5 APIC double write bug.
343 static void __setup_APIC_LVTT(unsigned int clocks
, int oneshot
, int irqen
)
345 unsigned int lvtt_value
, tmp_value
;
347 lvtt_value
= LOCAL_TIMER_VECTOR
;
349 lvtt_value
|= APIC_LVT_TIMER_PERIODIC
;
350 if (!lapic_is_integrated())
351 lvtt_value
|= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV
);
354 lvtt_value
|= APIC_LVT_MASKED
;
356 apic_write(APIC_LVTT
, lvtt_value
);
361 tmp_value
= apic_read(APIC_TDCR
);
362 apic_write(APIC_TDCR
,
363 (tmp_value
& ~(APIC_TDR_DIV_1
| APIC_TDR_DIV_TMBASE
)) |
367 apic_write(APIC_TMICT
, clocks
/ APIC_DIVISOR
);
371 * Setup extended LVT, AMD specific (K8, family 10h)
373 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
374 * MCE interrupts are supported. Thus MCE offset must be set to 0.
376 * If mask=1, the LVT entry does not generate interrupts while mask=0
377 * enables the vector. See also the BKDGs.
380 #define APIC_EILVT_LVTOFF_MCE 0
381 #define APIC_EILVT_LVTOFF_IBS 1
383 static void setup_APIC_eilvt(u8 lvt_off
, u8 vector
, u8 msg_type
, u8 mask
)
385 unsigned long reg
= (lvt_off
<< 4) + APIC_EILVT0
;
386 unsigned int v
= (mask
<< 16) | (msg_type
<< 8) | vector
;
391 u8
setup_APIC_eilvt_mce(u8 vector
, u8 msg_type
, u8 mask
)
393 setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE
, vector
, msg_type
, mask
);
394 return APIC_EILVT_LVTOFF_MCE
;
397 u8
setup_APIC_eilvt_ibs(u8 vector
, u8 msg_type
, u8 mask
)
399 setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS
, vector
, msg_type
, mask
);
400 return APIC_EILVT_LVTOFF_IBS
;
402 EXPORT_SYMBOL_GPL(setup_APIC_eilvt_ibs
);
405 * Program the next event, relative to now
407 static int lapic_next_event(unsigned long delta
,
408 struct clock_event_device
*evt
)
410 apic_write(APIC_TMICT
, delta
);
415 * Setup the lapic timer in periodic or oneshot mode
417 static void lapic_timer_setup(enum clock_event_mode mode
,
418 struct clock_event_device
*evt
)
423 /* Lapic used as dummy for broadcast ? */
424 if (evt
->features
& CLOCK_EVT_FEAT_DUMMY
)
427 local_irq_save(flags
);
430 case CLOCK_EVT_MODE_PERIODIC
:
431 case CLOCK_EVT_MODE_ONESHOT
:
432 __setup_APIC_LVTT(calibration_result
,
433 mode
!= CLOCK_EVT_MODE_PERIODIC
, 1);
435 case CLOCK_EVT_MODE_UNUSED
:
436 case CLOCK_EVT_MODE_SHUTDOWN
:
437 v
= apic_read(APIC_LVTT
);
438 v
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
439 apic_write(APIC_LVTT
, v
);
441 case CLOCK_EVT_MODE_RESUME
:
442 /* Nothing to do here */
446 local_irq_restore(flags
);
450 * Local APIC timer broadcast function
452 static void lapic_timer_broadcast(cpumask_t mask
)
455 send_IPI_mask(mask
, LOCAL_TIMER_VECTOR
);
460 * Setup the local APIC timer for this CPU. Copy the initilized values
461 * of the boot CPU and register the clock event in the framework.
463 static void __cpuinit
setup_APIC_timer(void)
465 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
467 memcpy(levt
, &lapic_clockevent
, sizeof(*levt
));
468 levt
->cpumask
= cpumask_of_cpu(smp_processor_id());
470 clockevents_register_device(levt
);
474 * In this function we calibrate APIC bus clocks to the external
475 * timer. Unfortunately we cannot use jiffies and the timer irq
476 * to calibrate, since some later bootup code depends on getting
477 * the first irq? Ugh.
479 * We want to do the calibration only once since we
480 * want to have local timer irqs syncron. CPUs connected
481 * by the same APIC bus have the very same bus frequency.
482 * And we want to have irqs off anyways, no accidental
486 #define TICK_COUNT 100000000
488 static int __init
calibrate_APIC_clock(void)
490 unsigned apic
, apic_start
;
491 unsigned long tsc
, tsc_start
;
497 * Put whatever arbitrary (but long enough) timeout
498 * value into the APIC clock, we just want to get the
499 * counter running for calibration.
501 * No interrupt enable !
503 __setup_APIC_LVTT(250000000, 0, 0);
505 apic_start
= apic_read(APIC_TMCCT
);
506 #ifdef CONFIG_X86_PM_TIMER
507 if (apic_calibrate_pmtmr
&& pmtmr_ioport
) {
508 pmtimer_wait(5000); /* 5ms wait */
509 apic
= apic_read(APIC_TMCCT
);
510 result
= (apic_start
- apic
) * 1000L / 5;
517 apic
= apic_read(APIC_TMCCT
);
519 } while ((tsc
- tsc_start
) < TICK_COUNT
&&
520 (apic_start
- apic
) < TICK_COUNT
);
522 result
= (apic_start
- apic
) * 1000L * tsc_khz
/
528 printk(KERN_DEBUG
"APIC timer calibration result %d\n", result
);
530 printk(KERN_INFO
"Detected %d.%03d MHz APIC timer.\n",
531 result
/ 1000 / 1000, result
/ 1000 % 1000);
533 /* Calculate the scaled math multiplication factor */
534 lapic_clockevent
.mult
= div_sc(result
, NSEC_PER_SEC
,
535 lapic_clockevent
.shift
);
536 lapic_clockevent
.max_delta_ns
=
537 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent
);
538 lapic_clockevent
.min_delta_ns
=
539 clockevent_delta2ns(0xF, &lapic_clockevent
);
541 calibration_result
= (result
* APIC_DIVISOR
) / HZ
;
544 * Do a sanity check on the APIC calibration result
546 if (calibration_result
< (1000000 / HZ
)) {
548 "APIC frequency too slow, disabling apic timer\n");
556 * Setup the boot APIC
558 * Calibrate and verify the result.
560 void __init
setup_boot_APIC_clock(void)
563 * The local apic timer can be disabled via the kernel
564 * commandline or from the CPU detection code. Register the lapic
565 * timer as a dummy clock event source on SMP systems, so the
566 * broadcast mechanism is used. On UP systems simply ignore it.
568 if (disable_apic_timer
) {
569 printk(KERN_INFO
"Disabling APIC timer\n");
570 /* No broadcast on UP ! */
571 if (num_possible_cpus() > 1) {
572 lapic_clockevent
.mult
= 1;
578 apic_printk(APIC_VERBOSE
, "Using local APIC timer interrupts.\n"
579 "calibrating APIC timer ...\n");
581 if (calibrate_APIC_clock()) {
582 /* No broadcast on UP ! */
583 if (num_possible_cpus() > 1)
589 * If nmi_watchdog is set to IO_APIC, we need the
590 * PIT/HPET going. Otherwise register lapic as a dummy
593 if (nmi_watchdog
!= NMI_IO_APIC
)
594 lapic_clockevent
.features
&= ~CLOCK_EVT_FEAT_DUMMY
;
596 printk(KERN_WARNING
"APIC timer registered as dummy,"
597 " due to nmi_watchdog=%d!\n", nmi_watchdog
);
599 /* Setup the lapic or request the broadcast */
603 void __cpuinit
setup_secondary_APIC_clock(void)
609 * The guts of the apic timer interrupt
611 static void local_apic_timer_interrupt(void)
613 int cpu
= smp_processor_id();
614 struct clock_event_device
*evt
= &per_cpu(lapic_events
, cpu
);
617 * Normally we should not be here till LAPIC has been initialized but
618 * in some cases like kdump, its possible that there is a pending LAPIC
619 * timer interrupt from previous kernel's context and is delivered in
620 * new kernel the moment interrupts are enabled.
622 * Interrupts are enabled early and LAPIC is setup much later, hence
623 * its possible that when we get here evt->event_handler is NULL.
624 * Check for event_handler being NULL and discard the interrupt as
627 if (!evt
->event_handler
) {
629 "Spurious LAPIC timer interrupt on cpu %d\n", cpu
);
631 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, evt
);
636 * the NMI deadlock-detector uses this.
639 add_pda(apic_timer_irqs
, 1);
641 per_cpu(irq_stat
, cpu
).apic_timer_irqs
++;
644 evt
->event_handler(evt
);
648 * Local APIC timer interrupt. This is the most natural way for doing
649 * local interrupts, but local timer interrupts can be emulated by
650 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
652 * [ if a single-CPU system runs an SMP kernel then we call the local
653 * interrupt as well. Thus we cannot inline the local irq ... ]
655 void smp_apic_timer_interrupt(struct pt_regs
*regs
)
657 struct pt_regs
*old_regs
= set_irq_regs(regs
);
660 * NOTE! We'd better ACK the irq immediately,
661 * because timer handling can be slow.
665 * update_process_times() expects us to have done irq_enter().
666 * Besides, if we don't timer interrupts ignore the global
667 * interrupt lock, which is the WrongThing (tm) to do.
673 local_apic_timer_interrupt();
676 set_irq_regs(old_regs
);
679 int setup_profiling_timer(unsigned int multiplier
)
686 * Local APIC start and shutdown
690 * clear_local_APIC - shutdown the local APIC
692 * This is called, when a CPU is disabled and before rebooting, so the state of
693 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
694 * leftovers during boot.
696 void clear_local_APIC(void)
701 /* APIC hasn't been mapped yet */
705 maxlvt
= lapic_get_maxlvt();
707 * Masking an LVT entry can trigger a local APIC error
708 * if the vector is zero. Mask LVTERR first to prevent this.
711 v
= ERROR_APIC_VECTOR
; /* any non-zero vector will do */
712 apic_write(APIC_LVTERR
, v
| APIC_LVT_MASKED
);
715 * Careful: we have to set masks only first to deassert
716 * any level-triggered sources.
718 v
= apic_read(APIC_LVTT
);
719 apic_write(APIC_LVTT
, v
| APIC_LVT_MASKED
);
720 v
= apic_read(APIC_LVT0
);
721 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
722 v
= apic_read(APIC_LVT1
);
723 apic_write(APIC_LVT1
, v
| APIC_LVT_MASKED
);
725 v
= apic_read(APIC_LVTPC
);
726 apic_write(APIC_LVTPC
, v
| APIC_LVT_MASKED
);
729 /* lets not touch this if we didn't frob it */
730 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(X86_MCE_INTEL)
732 v
= apic_read(APIC_LVTTHMR
);
733 apic_write(APIC_LVTTHMR
, v
| APIC_LVT_MASKED
);
737 * Clean APIC state for other OSs:
739 apic_write(APIC_LVTT
, APIC_LVT_MASKED
);
740 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
741 apic_write(APIC_LVT1
, APIC_LVT_MASKED
);
743 apic_write(APIC_LVTERR
, APIC_LVT_MASKED
);
745 apic_write(APIC_LVTPC
, APIC_LVT_MASKED
);
747 /* Integrated APIC (!82489DX) ? */
748 if (lapic_is_integrated()) {
750 /* Clear ESR due to Pentium errata 3AP and 11AP */
751 apic_write(APIC_ESR
, 0);
757 * disable_local_APIC - clear and disable the local APIC
759 void disable_local_APIC(void)
766 * Disable APIC (implies clearing of registers
769 value
= apic_read(APIC_SPIV
);
770 value
&= ~APIC_SPIV_APIC_ENABLED
;
771 apic_write(APIC_SPIV
, value
);
775 * When LAPIC was disabled by the BIOS and enabled by the kernel,
776 * restore the disabled state.
778 if (enabled_via_apicbase
) {
781 rdmsr(MSR_IA32_APICBASE
, l
, h
);
782 l
&= ~MSR_IA32_APICBASE_ENABLE
;
783 wrmsr(MSR_IA32_APICBASE
, l
, h
);
789 * If Linux enabled the LAPIC against the BIOS default disable it down before
790 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
791 * not power-off. Additionally clear all LVT entries before disable_local_APIC
792 * for the case where Linux didn't enable the LAPIC.
794 void lapic_shutdown(void)
801 local_irq_save(flags
);
804 if (!enabled_via_apicbase
)
808 disable_local_APIC();
811 local_irq_restore(flags
);
815 * This is to verify that we're looking at a real local APIC.
816 * Check these against your board if the CPUs aren't getting
817 * started for no apparent reason.
819 int __init
verify_local_APIC(void)
821 unsigned int reg0
, reg1
;
824 * The version register is read-only in a real APIC.
826 reg0
= apic_read(APIC_LVR
);
827 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg0
);
828 apic_write(APIC_LVR
, reg0
^ APIC_LVR_MASK
);
829 reg1
= apic_read(APIC_LVR
);
830 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg1
);
833 * The two version reads above should print the same
834 * numbers. If the second one is different, then we
835 * poke at a non-APIC.
841 * Check if the version looks reasonably.
843 reg1
= GET_APIC_VERSION(reg0
);
844 if (reg1
== 0x00 || reg1
== 0xff)
846 reg1
= lapic_get_maxlvt();
847 if (reg1
< 0x02 || reg1
== 0xff)
851 * The ID register is read/write in a real APIC.
853 reg0
= apic_read(APIC_ID
);
854 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg0
);
855 apic_write(APIC_ID
, reg0
^ APIC_ID_MASK
);
856 reg1
= apic_read(APIC_ID
);
857 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg1
);
858 apic_write(APIC_ID
, reg0
);
859 if (reg1
!= (reg0
^ APIC_ID_MASK
))
863 * The next two are just to see if we have sane values.
864 * They're only really relevant if we're in Virtual Wire
865 * compatibility mode, but most boxes are anymore.
867 reg0
= apic_read(APIC_LVT0
);
868 apic_printk(APIC_DEBUG
, "Getting LVT0: %x\n", reg0
);
869 reg1
= apic_read(APIC_LVT1
);
870 apic_printk(APIC_DEBUG
, "Getting LVT1: %x\n", reg1
);
876 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
878 void __init
sync_Arb_IDs(void)
881 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
884 if (modern_apic() || boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
)
890 apic_wait_icr_idle();
892 apic_printk(APIC_DEBUG
, "Synchronizing Arb IDs.\n");
893 apic_write(APIC_ICR
, APIC_DEST_ALLINC
|
894 APIC_INT_LEVELTRIG
| APIC_DM_INIT
);
898 * An initial setup of the virtual wire mode.
900 void __init
init_bsp_APIC(void)
905 * Don't do the setup now if we have a SMP BIOS as the
906 * through-I/O-APIC virtual wire mode might be active.
908 if (smp_found_config
|| !cpu_has_apic
)
912 * Do not trust the local APIC being empty at bootup.
919 value
= apic_read(APIC_SPIV
);
920 value
&= ~APIC_VECTOR_MASK
;
921 value
|= APIC_SPIV_APIC_ENABLED
;
924 /* This bit is reserved on P4/Xeon and should be cleared */
925 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
) &&
926 (boot_cpu_data
.x86
== 15))
927 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
930 value
|= APIC_SPIV_FOCUS_DISABLED
;
931 value
|= SPURIOUS_APIC_VECTOR
;
932 apic_write(APIC_SPIV
, value
);
935 * Set up the virtual wire mode.
937 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
939 if (!lapic_is_integrated()) /* 82489DX */
940 value
|= APIC_LVT_LEVEL_TRIGGER
;
941 apic_write(APIC_LVT1
, value
);
944 static void __cpuinit
lapic_setup_esr(void)
946 unsigned long oldvalue
, value
, maxlvt
;
947 if (lapic_is_integrated() && !esr_disable
) {
950 * Something untraceable is creating bad interrupts on
951 * secondary quads ... for the moment, just leave the
952 * ESR disabled - we can't do anything useful with the
953 * errors anyway - mbligh
955 printk(KERN_INFO
"Leaving ESR disabled.\n");
959 maxlvt
= lapic_get_maxlvt();
960 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
961 apic_write(APIC_ESR
, 0);
962 oldvalue
= apic_read(APIC_ESR
);
964 /* enables sending errors */
965 value
= ERROR_APIC_VECTOR
;
966 apic_write(APIC_LVTERR
, value
);
968 * spec says clear errors after enabling vector.
971 apic_write(APIC_ESR
, 0);
972 value
= apic_read(APIC_ESR
);
973 if (value
!= oldvalue
)
974 apic_printk(APIC_VERBOSE
, "ESR value before enabling "
975 "vector: 0x%08lx after: 0x%08lx\n",
978 printk(KERN_INFO
"No ESR for 82489DX.\n");
984 * setup_local_APIC - setup the local APIC
986 void __cpuinit
setup_local_APIC(void)
992 /* Pound the ESR really hard over the head with a big hammer - mbligh */
994 apic_write(APIC_ESR
, 0);
995 apic_write(APIC_ESR
, 0);
996 apic_write(APIC_ESR
, 0);
997 apic_write(APIC_ESR
, 0);
1004 * Double-check whether this APIC is really registered.
1005 * This is meaningless in clustered apic mode, so we skip it.
1007 if (!apic_id_registered())
1011 * Intel recommends to set DFR, LDR and TPR before enabling
1012 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
1013 * document number 292116). So here it goes...
1018 * Set Task Priority to 'accept all'. We never change this
1021 value
= apic_read(APIC_TASKPRI
);
1022 value
&= ~APIC_TPRI_MASK
;
1023 apic_write(APIC_TASKPRI
, value
);
1026 * After a crash, we no longer service the interrupts and a pending
1027 * interrupt from previous kernel might still have ISR bit set.
1029 * Most probably by now CPU has serviced that pending interrupt and
1030 * it might not have done the ack_APIC_irq() because it thought,
1031 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
1032 * does not clear the ISR bit and cpu thinks it has already serivced
1033 * the interrupt. Hence a vector might get locked. It was noticed
1034 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
1036 for (i
= APIC_ISR_NR
- 1; i
>= 0; i
--) {
1037 value
= apic_read(APIC_ISR
+ i
*0x10);
1038 for (j
= 31; j
>= 0; j
--) {
1045 * Now that we are all set up, enable the APIC
1047 value
= apic_read(APIC_SPIV
);
1048 value
&= ~APIC_VECTOR_MASK
;
1052 value
|= APIC_SPIV_APIC_ENABLED
;
1054 #ifdef CONFIG_X86_32
1056 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1057 * certain networking cards. If high frequency interrupts are
1058 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1059 * entry is masked/unmasked at a high rate as well then sooner or
1060 * later IOAPIC line gets 'stuck', no more interrupts are received
1061 * from the device. If focus CPU is disabled then the hang goes
1064 * [ This bug can be reproduced easily with a level-triggered
1065 * PCI Ne2000 networking cards and PII/PIII processors, dual
1069 * Actually disabling the focus CPU check just makes the hang less
1070 * frequent as it makes the interrupt distributon model be more
1071 * like LRU than MRU (the short-term load is more even across CPUs).
1072 * See also the comment in end_level_ioapic_irq(). --macro
1076 * - enable focus processor (bit==0)
1077 * - 64bit mode always use processor focus
1078 * so no need to set it
1080 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
1084 * Set spurious IRQ vector
1086 value
|= SPURIOUS_APIC_VECTOR
;
1087 apic_write(APIC_SPIV
, value
);
1090 * Set up LVT0, LVT1:
1092 * set up through-local-APIC on the BP's LINT0. This is not
1093 * strictly necessary in pure symmetric-IO mode, but sometimes
1094 * we delegate interrupts to the 8259A.
1097 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1099 value
= apic_read(APIC_LVT0
) & APIC_LVT_MASKED
;
1100 if (!smp_processor_id() && (pic_mode
|| !value
)) {
1101 value
= APIC_DM_EXTINT
;
1102 apic_printk(APIC_VERBOSE
, "enabled ExtINT on CPU#%d\n",
1103 smp_processor_id());
1105 value
= APIC_DM_EXTINT
| APIC_LVT_MASKED
;
1106 apic_printk(APIC_VERBOSE
, "masked ExtINT on CPU#%d\n",
1107 smp_processor_id());
1109 apic_write(APIC_LVT0
, value
);
1112 * only the BP should see the LINT1 NMI signal, obviously.
1114 if (!smp_processor_id())
1115 value
= APIC_DM_NMI
;
1117 value
= APIC_DM_NMI
| APIC_LVT_MASKED
;
1118 if (!lapic_is_integrated()) /* 82489DX */
1119 value
|= APIC_LVT_LEVEL_TRIGGER
;
1120 apic_write(APIC_LVT1
, value
);
1125 void __cpuinit
end_local_APIC_setup(void)
1129 #ifdef CONFIG_X86_32
1132 /* Disable the local apic timer */
1133 value
= apic_read(APIC_LVTT
);
1134 value
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
1135 apic_write(APIC_LVTT
, value
);
1139 setup_apic_nmi_watchdog(NULL
);
1144 void check_x2apic(void)
1148 rdmsr(MSR_IA32_APICBASE
, msr
, msr2
);
1150 if (msr
& X2APIC_ENABLE
) {
1151 printk("x2apic enabled by BIOS, switching to x2apic ops\n");
1152 x2apic_preenabled
= x2apic
= 1;
1153 apic_ops
= &x2apic_ops
;
1157 void enable_x2apic(void)
1161 rdmsr(MSR_IA32_APICBASE
, msr
, msr2
);
1162 if (!(msr
& X2APIC_ENABLE
)) {
1163 printk("Enabling x2apic\n");
1164 wrmsr(MSR_IA32_APICBASE
, msr
| X2APIC_ENABLE
, 0);
1168 void enable_IR_x2apic(void)
1170 #ifdef CONFIG_INTR_REMAP
1172 unsigned long flags
;
1174 if (!cpu_has_x2apic
)
1177 if (!x2apic_preenabled
&& disable_x2apic
) {
1179 "Skipped enabling x2apic and Interrupt-remapping "
1180 "because of nox2apic\n");
1184 if (x2apic_preenabled
&& disable_x2apic
)
1185 panic("Bios already enabled x2apic, can't enforce nox2apic");
1187 if (!x2apic_preenabled
&& skip_ioapic_setup
) {
1189 "Skipped enabling x2apic and Interrupt-remapping "
1190 "because of skipping io-apic setup\n");
1194 ret
= dmar_table_init();
1197 "dmar_table_init() failed with %d:\n", ret
);
1199 if (x2apic_preenabled
)
1200 panic("x2apic enabled by bios. But IR enabling failed");
1203 "Not enabling x2apic,Intr-remapping\n");
1207 local_irq_save(flags
);
1209 save_mask_IO_APIC_setup();
1211 ret
= enable_intr_remapping(1);
1213 if (ret
&& x2apic_preenabled
) {
1214 local_irq_restore(flags
);
1215 panic("x2apic enabled by bios. But IR enabling failed");
1223 apic_ops
= &x2apic_ops
;
1229 * IR enabling failed
1231 restore_IO_APIC_setup();
1233 reinit_intr_remapped_IO_APIC(x2apic_preenabled
);
1236 local_irq_restore(flags
);
1239 if (!x2apic_preenabled
)
1241 "Enabled x2apic and interrupt-remapping\n");
1244 "Enabled Interrupt-remapping\n");
1247 "Failed to enable Interrupt-remapping and x2apic\n");
1249 if (!cpu_has_x2apic
)
1252 if (x2apic_preenabled
)
1253 panic("x2apic enabled prior OS handover,"
1254 " enable CONFIG_INTR_REMAP");
1256 printk(KERN_INFO
"Enable CONFIG_INTR_REMAP for enabling intr-remapping "
1262 #endif /* HAVE_X2APIC */
1265 * Detect and enable local APICs on non-SMP boards.
1266 * Original code written by Keir Fraser.
1267 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1268 * not correctly set up (usually the APIC timer won't work etc.)
1270 static int __init
detect_init_APIC(void)
1272 if (!cpu_has_apic
) {
1273 printk(KERN_INFO
"No local APIC present\n");
1277 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
1278 boot_cpu_physical_apicid
= 0;
1282 void __init
early_init_lapic_mapping(void)
1284 unsigned long phys_addr
;
1287 * If no local APIC can be found then go out
1288 * : it means there is no mpatable and MADT
1290 if (!smp_found_config
)
1293 phys_addr
= mp_lapic_addr
;
1295 set_fixmap_nocache(FIX_APIC_BASE
, phys_addr
);
1296 apic_printk(APIC_VERBOSE
, "mapped APIC to %16lx (%16lx)\n",
1297 APIC_BASE
, phys_addr
);
1300 * Fetch the APIC ID of the BSP in case we have a
1301 * default configuration (or the MP table is broken).
1303 boot_cpu_physical_apicid
= read_apic_id();
1307 * init_apic_mappings - initialize APIC mappings
1309 void __init
init_apic_mappings(void)
1313 boot_cpu_physical_apicid
= read_apic_id();
1319 * If no local APIC can be found then set up a fake all
1320 * zeroes page to simulate the local APIC and another
1321 * one for the IO-APIC.
1323 if (!smp_found_config
&& detect_init_APIC()) {
1324 apic_phys
= (unsigned long) alloc_bootmem_pages(PAGE_SIZE
);
1325 apic_phys
= __pa(apic_phys
);
1327 apic_phys
= mp_lapic_addr
;
1329 set_fixmap_nocache(FIX_APIC_BASE
, apic_phys
);
1330 apic_printk(APIC_VERBOSE
, "mapped APIC to %16lx (%16lx)\n",
1331 APIC_BASE
, apic_phys
);
1334 * Fetch the APIC ID of the BSP in case we have a
1335 * default configuration (or the MP table is broken).
1337 boot_cpu_physical_apicid
= read_apic_id();
1341 * This initializes the IO-APIC and APIC hardware if this is
1344 int apic_version
[MAX_APICS
];
1346 int __init
APIC_init_uniprocessor(void)
1349 printk(KERN_INFO
"Apic disabled\n");
1352 if (!cpu_has_apic
) {
1354 printk(KERN_INFO
"Apic disabled by BIOS\n");
1360 setup_apic_routing();
1362 verify_local_APIC();
1366 physid_set_mask_of_physid(boot_cpu_physical_apicid
, &phys_cpu_present_map
);
1367 apic_write(APIC_ID
, SET_APIC_ID(boot_cpu_physical_apicid
));
1372 * Now enable IO-APICs, actually call clear_IO_APIC
1373 * We need clear_IO_APIC before enabling vector on BP
1375 if (!skip_ioapic_setup
&& nr_ioapics
)
1378 if (!smp_found_config
|| skip_ioapic_setup
|| !nr_ioapics
)
1379 localise_nmi_watchdog();
1380 end_local_APIC_setup();
1382 if (smp_found_config
&& !skip_ioapic_setup
&& nr_ioapics
)
1386 setup_boot_APIC_clock();
1387 check_nmi_watchdog();
1392 * Local APIC interrupts
1396 * This interrupt should _never_ happen with our APIC/SMP architecture
1398 asmlinkage
void smp_spurious_interrupt(void)
1404 * Check if this really is a spurious interrupt and ACK it
1405 * if it is a vectored one. Just in case...
1406 * Spurious interrupts should not be ACKed.
1408 v
= apic_read(APIC_ISR
+ ((SPURIOUS_APIC_VECTOR
& ~0x1f) >> 1));
1409 if (v
& (1 << (SPURIOUS_APIC_VECTOR
& 0x1f)))
1412 add_pda(irq_spurious_count
, 1);
1417 * This interrupt should never happen with our APIC/SMP architecture
1419 asmlinkage
void smp_error_interrupt(void)
1425 /* First tickle the hardware, only then report what went on. -- REW */
1426 v
= apic_read(APIC_ESR
);
1427 apic_write(APIC_ESR
, 0);
1428 v1
= apic_read(APIC_ESR
);
1430 atomic_inc(&irq_err_count
);
1432 /* Here is what the APIC error bits mean:
1435 2: Send accept error
1436 3: Receive accept error
1438 5: Send illegal vector
1439 6: Received illegal vector
1440 7: Illegal register address
1442 printk(KERN_DEBUG
"APIC error on CPU%d: %02x(%02x)\n",
1443 smp_processor_id(), v
, v1
);
1448 * connect_bsp_APIC - attach the APIC to the interrupt system
1450 void __init
connect_bsp_APIC(void)
1452 #ifdef CONFIG_X86_32
1455 * Do not trust the local APIC being empty at bootup.
1459 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
1460 * local APIC to INT and NMI lines.
1462 apic_printk(APIC_VERBOSE
, "leaving PIC mode, "
1463 "enabling APIC mode.\n");
1472 * disconnect_bsp_APIC - detach the APIC from the interrupt system
1473 * @virt_wire_setup: indicates, whether virtual wire mode is selected
1475 * Virtual wire mode is necessary to deliver legacy interrupts even when the
1478 void disconnect_bsp_APIC(int virt_wire_setup
)
1482 #ifdef CONFIG_X86_32
1485 * Put the board back into PIC mode (has an effect only on
1486 * certain older boards). Note that APIC interrupts, including
1487 * IPIs, won't work beyond this point! The only exception are
1490 apic_printk(APIC_VERBOSE
, "disabling APIC mode, "
1491 "entering PIC mode.\n");
1498 /* Go back to Virtual Wire compatibility mode */
1500 /* For the spurious interrupt use vector F, and enable it */
1501 value
= apic_read(APIC_SPIV
);
1502 value
&= ~APIC_VECTOR_MASK
;
1503 value
|= APIC_SPIV_APIC_ENABLED
;
1505 apic_write(APIC_SPIV
, value
);
1507 if (!virt_wire_setup
) {
1509 * For LVT0 make it edge triggered, active high,
1510 * external and enabled
1512 value
= apic_read(APIC_LVT0
);
1513 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1514 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1515 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1516 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1517 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_EXTINT
);
1518 apic_write(APIC_LVT0
, value
);
1521 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
1525 * For LVT1 make it edge triggered, active high,
1528 value
= apic_read(APIC_LVT1
);
1529 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1530 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1531 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1532 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1533 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_NMI
);
1534 apic_write(APIC_LVT1
, value
);
1537 void __cpuinit
generic_processor_info(int apicid
, int version
)
1545 if (version
== 0x0) {
1546 printk(KERN_WARNING
"BIOS bug, APIC version is 0 for CPU#%d! "
1547 "fixing up to 0x10. (tell your hw vendor)\n",
1551 apic_version
[apicid
] = version
;
1553 if (num_processors
>= NR_CPUS
) {
1554 printk(KERN_WARNING
"WARNING: NR_CPUS limit of %i reached."
1555 " Processor ignored.\n", NR_CPUS
);
1560 cpus_complement(tmp_map
, cpu_present_map
);
1561 cpu
= first_cpu(tmp_map
);
1563 physid_set(apicid
, phys_cpu_present_map
);
1564 if (apicid
== boot_cpu_physical_apicid
) {
1566 * x86_bios_cpu_apicid is required to have processors listed
1567 * in same order as logical cpu numbers. Hence the first
1568 * entry is BSP, and so on.
1572 if (apicid
> max_physical_apicid
)
1573 max_physical_apicid
= apicid
;
1575 #ifdef CONFIG_X86_32
1577 * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y
1578 * but we need to work other dependencies like SMP_SUSPEND etc
1579 * before this can be done without some confusion.
1580 * if (CPU_HOTPLUG_ENABLED || num_processors > 8)
1581 * - Ashok Raj <ashok.raj@intel.com>
1583 if (max_physical_apicid
>= 8) {
1584 switch (boot_cpu_data
.x86_vendor
) {
1585 case X86_VENDOR_INTEL
:
1586 if (!APIC_XAPIC(version
)) {
1590 /* If P4 and above fall through */
1591 case X86_VENDOR_AMD
:
1597 #if defined(CONFIG_X86_SMP) || defined(CONFIG_X86_64)
1598 /* are we being called early in kernel startup? */
1599 if (early_per_cpu_ptr(x86_cpu_to_apicid
)) {
1600 u16
*cpu_to_apicid
= early_per_cpu_ptr(x86_cpu_to_apicid
);
1601 u16
*bios_cpu_apicid
= early_per_cpu_ptr(x86_bios_cpu_apicid
);
1603 cpu_to_apicid
[cpu
] = apicid
;
1604 bios_cpu_apicid
[cpu
] = apicid
;
1606 per_cpu(x86_cpu_to_apicid
, cpu
) = apicid
;
1607 per_cpu(x86_bios_cpu_apicid
, cpu
) = apicid
;
1611 cpu_set(cpu
, cpu_possible_map
);
1612 cpu_set(cpu
, cpu_present_map
);
1615 int hard_smp_processor_id(void)
1617 return read_apic_id();
1627 * 'active' is true if the local APIC was enabled by us and
1628 * not the BIOS; this signifies that we are also responsible
1629 * for disabling it before entering apm/acpi suspend
1632 /* r/w apic fields */
1633 unsigned int apic_id
;
1634 unsigned int apic_taskpri
;
1635 unsigned int apic_ldr
;
1636 unsigned int apic_dfr
;
1637 unsigned int apic_spiv
;
1638 unsigned int apic_lvtt
;
1639 unsigned int apic_lvtpc
;
1640 unsigned int apic_lvt0
;
1641 unsigned int apic_lvt1
;
1642 unsigned int apic_lvterr
;
1643 unsigned int apic_tmict
;
1644 unsigned int apic_tdcr
;
1645 unsigned int apic_thmr
;
1648 static int lapic_suspend(struct sys_device
*dev
, pm_message_t state
)
1650 unsigned long flags
;
1653 if (!apic_pm_state
.active
)
1656 maxlvt
= lapic_get_maxlvt();
1658 apic_pm_state
.apic_id
= apic_read(APIC_ID
);
1659 apic_pm_state
.apic_taskpri
= apic_read(APIC_TASKPRI
);
1660 apic_pm_state
.apic_ldr
= apic_read(APIC_LDR
);
1661 apic_pm_state
.apic_dfr
= apic_read(APIC_DFR
);
1662 apic_pm_state
.apic_spiv
= apic_read(APIC_SPIV
);
1663 apic_pm_state
.apic_lvtt
= apic_read(APIC_LVTT
);
1665 apic_pm_state
.apic_lvtpc
= apic_read(APIC_LVTPC
);
1666 apic_pm_state
.apic_lvt0
= apic_read(APIC_LVT0
);
1667 apic_pm_state
.apic_lvt1
= apic_read(APIC_LVT1
);
1668 apic_pm_state
.apic_lvterr
= apic_read(APIC_LVTERR
);
1669 apic_pm_state
.apic_tmict
= apic_read(APIC_TMICT
);
1670 apic_pm_state
.apic_tdcr
= apic_read(APIC_TDCR
);
1671 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
1673 apic_pm_state
.apic_thmr
= apic_read(APIC_LVTTHMR
);
1676 local_irq_save(flags
);
1677 disable_local_APIC();
1678 local_irq_restore(flags
);
1682 static int lapic_resume(struct sys_device
*dev
)
1685 unsigned long flags
;
1688 if (!apic_pm_state
.active
)
1691 maxlvt
= lapic_get_maxlvt();
1693 local_irq_save(flags
);
1702 * Make sure the APICBASE points to the right address
1704 * FIXME! This will be wrong if we ever support suspend on
1705 * SMP! We'll need to do this as part of the CPU restore!
1707 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1708 l
&= ~MSR_IA32_APICBASE_BASE
;
1709 l
|= MSR_IA32_APICBASE_ENABLE
| mp_lapic_addr
;
1710 wrmsr(MSR_IA32_APICBASE
, l
, h
);
1713 apic_write(APIC_LVTERR
, ERROR_APIC_VECTOR
| APIC_LVT_MASKED
);
1714 apic_write(APIC_ID
, apic_pm_state
.apic_id
);
1715 apic_write(APIC_DFR
, apic_pm_state
.apic_dfr
);
1716 apic_write(APIC_LDR
, apic_pm_state
.apic_ldr
);
1717 apic_write(APIC_TASKPRI
, apic_pm_state
.apic_taskpri
);
1718 apic_write(APIC_SPIV
, apic_pm_state
.apic_spiv
);
1719 apic_write(APIC_LVT0
, apic_pm_state
.apic_lvt0
);
1720 apic_write(APIC_LVT1
, apic_pm_state
.apic_lvt1
);
1721 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
1723 apic_write(APIC_LVTTHMR
, apic_pm_state
.apic_thmr
);
1726 apic_write(APIC_LVTPC
, apic_pm_state
.apic_lvtpc
);
1727 apic_write(APIC_LVTT
, apic_pm_state
.apic_lvtt
);
1728 apic_write(APIC_TDCR
, apic_pm_state
.apic_tdcr
);
1729 apic_write(APIC_TMICT
, apic_pm_state
.apic_tmict
);
1730 apic_write(APIC_ESR
, 0);
1731 apic_read(APIC_ESR
);
1732 apic_write(APIC_LVTERR
, apic_pm_state
.apic_lvterr
);
1733 apic_write(APIC_ESR
, 0);
1734 apic_read(APIC_ESR
);
1736 local_irq_restore(flags
);
1742 * This device has no shutdown method - fully functioning local APICs
1743 * are needed on every CPU up until machine_halt/restart/poweroff.
1746 static struct sysdev_class lapic_sysclass
= {
1748 .resume
= lapic_resume
,
1749 .suspend
= lapic_suspend
,
1752 static struct sys_device device_lapic
= {
1754 .cls
= &lapic_sysclass
,
1757 static void __cpuinit
apic_pm_activate(void)
1759 apic_pm_state
.active
= 1;
1762 static int __init
init_lapic_sysfs(void)
1768 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
1770 error
= sysdev_class_register(&lapic_sysclass
);
1772 error
= sysdev_register(&device_lapic
);
1775 device_initcall(init_lapic_sysfs
);
1777 #else /* CONFIG_PM */
1779 static void apic_pm_activate(void) { }
1781 #endif /* CONFIG_PM */
1784 * apic_is_clustered_box() -- Check if we can expect good TSC
1786 * Thus far, the major user of this is IBM's Summit2 series:
1788 * Clustered boxes may have unsynced TSC problems if they are
1789 * multi-chassis. Use available data to take a good guess.
1790 * If in doubt, go HPET.
1792 __cpuinit
int apic_is_clustered_box(void)
1794 int i
, clusters
, zeros
;
1796 u16
*bios_cpu_apicid
;
1797 DECLARE_BITMAP(clustermap
, NUM_APIC_CLUSTERS
);
1800 * there is not this kind of box with AMD CPU yet.
1801 * Some AMD box with quadcore cpu and 8 sockets apicid
1802 * will be [4, 0x23] or [8, 0x27] could be thought to
1803 * vsmp box still need checking...
1805 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
) && !is_vsmp_box())
1808 bios_cpu_apicid
= early_per_cpu_ptr(x86_bios_cpu_apicid
);
1809 bitmap_zero(clustermap
, NUM_APIC_CLUSTERS
);
1811 for (i
= 0; i
< NR_CPUS
; i
++) {
1812 /* are we being called early in kernel startup? */
1813 if (bios_cpu_apicid
) {
1814 id
= bios_cpu_apicid
[i
];
1816 else if (i
< nr_cpu_ids
) {
1818 id
= per_cpu(x86_bios_cpu_apicid
, i
);
1825 if (id
!= BAD_APICID
)
1826 __set_bit(APIC_CLUSTERID(id
), clustermap
);
1829 /* Problem: Partially populated chassis may not have CPUs in some of
1830 * the APIC clusters they have been allocated. Only present CPUs have
1831 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap.
1832 * Since clusters are allocated sequentially, count zeros only if
1833 * they are bounded by ones.
1837 for (i
= 0; i
< NUM_APIC_CLUSTERS
; i
++) {
1838 if (test_bit(i
, clustermap
)) {
1839 clusters
+= 1 + zeros
;
1845 /* ScaleMP vSMPowered boxes have one cluster per board and TSCs are
1846 * not guaranteed to be synced between boards
1848 if (is_vsmp_box() && clusters
> 1)
1852 * If clusters > 2, then should be multi-chassis.
1853 * May have to revisit this when multi-core + hyperthreaded CPUs come
1854 * out, but AFAIK this will work even for them.
1856 return (clusters
> 2);
1860 * APIC command line parameters
1862 static int __init
setup_disableapic(char *arg
)
1865 setup_clear_cpu_cap(X86_FEATURE_APIC
);
1868 early_param("disableapic", setup_disableapic
);
1870 /* same as disableapic, for compatibility */
1871 static int __init
setup_nolapic(char *arg
)
1873 return setup_disableapic(arg
);
1875 early_param("nolapic", setup_nolapic
);
1877 static int __init
parse_lapic_timer_c2_ok(char *arg
)
1879 local_apic_timer_c2_ok
= 1;
1882 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok
);
1884 static int __init
parse_disable_apic_timer(char *arg
)
1886 disable_apic_timer
= 1;
1889 early_param("noapictimer", parse_disable_apic_timer
);
1891 static int __init
parse_nolapic_timer(char *arg
)
1893 disable_apic_timer
= 1;
1896 early_param("nolapic_timer", parse_nolapic_timer
);
1898 static int __init
apic_set_verbosity(char *arg
)
1901 #ifdef CONFIG_X86_64
1902 skip_ioapic_setup
= 0;
1908 if (strcmp("debug", arg
) == 0)
1909 apic_verbosity
= APIC_DEBUG
;
1910 else if (strcmp("verbose", arg
) == 0)
1911 apic_verbosity
= APIC_VERBOSE
;
1913 printk(KERN_WARNING
"APIC Verbosity level %s not recognised"
1914 " use apic=verbose or apic=debug\n", arg
);
1920 early_param("apic", apic_set_verbosity
);
1922 static int __init
lapic_insert_resource(void)
1927 /* Put local APIC into the resource map. */
1928 lapic_resource
.start
= apic_phys
;
1929 lapic_resource
.end
= lapic_resource
.start
+ PAGE_SIZE
- 1;
1930 insert_resource(&iomem_resource
, &lapic_resource
);
1936 * need call insert after e820_reserve_resources()
1937 * that is using request_resource
1939 late_initcall(lapic_insert_resource
);