2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/bootmem.h>
22 #include <linux/interrupt.h>
23 #include <linux/mc146818rtc.h>
24 #include <linux/kernel_stat.h>
25 #include <linux/sysdev.h>
26 #include <linux/ioport.h>
27 #include <linux/cpu.h>
28 #include <linux/clockchips.h>
29 #include <linux/acpi_pmtmr.h>
30 #include <linux/module.h>
31 #include <linux/dmi.h>
32 #include <linux/dmar.h>
34 #include <asm/atomic.h>
37 #include <asm/mpspec.h>
39 #include <asm/arch_hooks.h>
41 #include <asm/pgalloc.h>
42 #include <asm/i8253.h>
45 #include <asm/proto.h>
46 #include <asm/timex.h>
48 #include <asm/i8259.h>
50 #include <mach_apic.h>
51 #include <mach_apicdef.h>
57 #if ((SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F)
58 # error SPURIOUS_APIC_VECTOR definition error
63 * Knob to control our willingness to enable the local APIC.
67 static int force_enable_local_apic
;
69 * APIC command line parameters
71 static int __init
parse_lapic(char *arg
)
73 force_enable_local_apic
= 1;
76 early_param("lapic", parse_lapic
);
77 /* Local APIC was disabled by the BIOS and enabled by the kernel */
78 static int enabled_via_apicbase
;
83 static int apic_calibrate_pmtmr __initdata
;
84 static __init
int setup_apicpmtimer(char *s
)
86 apic_calibrate_pmtmr
= 1;
90 __setup("apicpmtimer", setup_apicpmtimer
);
99 /* x2apic enabled before OS handover */
100 int x2apic_preenabled
;
102 static __init
int setup_nox2apic(char *str
)
105 setup_clear_cpu_cap(X86_FEATURE_X2APIC
);
108 early_param("nox2apic", setup_nox2apic
);
111 unsigned long mp_lapic_addr
;
113 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
114 static int disable_apic_timer __cpuinitdata
;
115 /* Local APIC timer works in C2 */
116 int local_apic_timer_c2_ok
;
117 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok
);
119 int first_system_vector
= 0xfe;
121 char system_vectors
[NR_VECTORS
] = { [0 ... NR_VECTORS
-1] = SYS_VECTOR_FREE
};
124 * Debug level, exported for io_apic.c
126 unsigned int apic_verbosity
;
130 /* Have we found an MP table */
131 int smp_found_config
;
133 static struct resource lapic_resource
= {
134 .name
= "Local APIC",
135 .flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
,
138 static unsigned int calibration_result
;
140 static int lapic_next_event(unsigned long delta
,
141 struct clock_event_device
*evt
);
142 static void lapic_timer_setup(enum clock_event_mode mode
,
143 struct clock_event_device
*evt
);
144 static void lapic_timer_broadcast(cpumask_t mask
);
145 static void apic_pm_activate(void);
148 * The local apic timer can be used for any function which is CPU local.
150 static struct clock_event_device lapic_clockevent
= {
152 .features
= CLOCK_EVT_FEAT_PERIODIC
| CLOCK_EVT_FEAT_ONESHOT
153 | CLOCK_EVT_FEAT_C3STOP
| CLOCK_EVT_FEAT_DUMMY
,
155 .set_mode
= lapic_timer_setup
,
156 .set_next_event
= lapic_next_event
,
157 .broadcast
= lapic_timer_broadcast
,
161 static DEFINE_PER_CPU(struct clock_event_device
, lapic_events
);
163 static unsigned long apic_phys
;
166 * Get the LAPIC version
168 static inline int lapic_get_version(void)
170 return GET_APIC_VERSION(apic_read(APIC_LVR
));
174 * Check, if the APIC is integrated or a separate chip
176 static inline int lapic_is_integrated(void)
181 return APIC_INTEGRATED(lapic_get_version());
186 * Check, whether this is a modern or a first generation APIC
188 static int modern_apic(void)
190 /* AMD systems use old APIC versions, so check the CPU */
191 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
&&
192 boot_cpu_data
.x86
>= 0xf)
194 return lapic_get_version() >= 0x14;
198 * Paravirt kernels also might be using these below ops. So we still
199 * use generic apic_read()/apic_write(), which might be pointing to different
200 * ops in PARAVIRT case.
202 void xapic_wait_icr_idle(void)
204 while (apic_read(APIC_ICR
) & APIC_ICR_BUSY
)
208 u32
safe_xapic_wait_icr_idle(void)
215 send_status
= apic_read(APIC_ICR
) & APIC_ICR_BUSY
;
219 } while (timeout
++ < 1000);
224 void xapic_icr_write(u32 low
, u32 id
)
226 apic_write(APIC_ICR2
, SET_APIC_DEST_FIELD(id
));
227 apic_write(APIC_ICR
, low
);
230 u64
xapic_icr_read(void)
234 icr2
= apic_read(APIC_ICR2
);
235 icr1
= apic_read(APIC_ICR
);
237 return icr1
| ((u64
)icr2
<< 32);
240 static struct apic_ops xapic_ops
= {
241 .read
= native_apic_mem_read
,
242 .write
= native_apic_mem_write
,
243 .icr_read
= xapic_icr_read
,
244 .icr_write
= xapic_icr_write
,
245 .wait_icr_idle
= xapic_wait_icr_idle
,
246 .safe_wait_icr_idle
= safe_xapic_wait_icr_idle
,
249 struct apic_ops __read_mostly
*apic_ops
= &xapic_ops
;
250 EXPORT_SYMBOL_GPL(apic_ops
);
253 static void x2apic_wait_icr_idle(void)
255 /* no need to wait for icr idle in x2apic */
259 static u32
safe_x2apic_wait_icr_idle(void)
261 /* no need to wait for icr idle in x2apic */
265 void x2apic_icr_write(u32 low
, u32 id
)
267 wrmsrl(APIC_BASE_MSR
+ (APIC_ICR
>> 4), ((__u64
) id
) << 32 | low
);
270 u64
x2apic_icr_read(void)
274 rdmsrl(APIC_BASE_MSR
+ (APIC_ICR
>> 4), val
);
278 static struct apic_ops x2apic_ops
= {
279 .read
= native_apic_msr_read
,
280 .write
= native_apic_msr_write
,
281 .icr_read
= x2apic_icr_read
,
282 .icr_write
= x2apic_icr_write
,
283 .wait_icr_idle
= x2apic_wait_icr_idle
,
284 .safe_wait_icr_idle
= safe_x2apic_wait_icr_idle
,
289 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
291 void __cpuinit
enable_NMI_through_LVT0(void)
295 /* unmask and set to NMI */
298 /* Level triggered for 82489DX (32bit mode) */
299 if (!lapic_is_integrated())
300 v
|= APIC_LVT_LEVEL_TRIGGER
;
302 apic_write(APIC_LVT0
, v
);
307 * get_physical_broadcast - Get number of physical broadcast IDs
309 int get_physical_broadcast(void)
311 return modern_apic() ? 0xff : 0xf;
316 * lapic_get_maxlvt - get the maximum number of local vector table entries
318 int lapic_get_maxlvt(void)
322 v
= apic_read(APIC_LVR
);
324 * - we always have APIC integrated on 64bit mode
325 * - 82489DXs do not report # of LVT entries
327 return APIC_INTEGRATED(GET_APIC_VERSION(v
)) ? GET_APIC_MAXLVT(v
) : 2;
336 #define APIC_DIVISOR 1
338 #define APIC_DIVISOR 16
342 * This function sets up the local APIC timer, with a timeout of
343 * 'clocks' APIC bus clock. During calibration we actually call
344 * this function twice on the boot CPU, once with a bogus timeout
345 * value, second time for real. The other (noncalibrating) CPUs
346 * call this function only once, with the real, calibrated value.
348 * We do reads before writes even if unnecessary, to get around the
349 * P5 APIC double write bug.
351 static void __setup_APIC_LVTT(unsigned int clocks
, int oneshot
, int irqen
)
353 unsigned int lvtt_value
, tmp_value
;
355 lvtt_value
= LOCAL_TIMER_VECTOR
;
357 lvtt_value
|= APIC_LVT_TIMER_PERIODIC
;
358 if (!lapic_is_integrated())
359 lvtt_value
|= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV
);
362 lvtt_value
|= APIC_LVT_MASKED
;
364 apic_write(APIC_LVTT
, lvtt_value
);
369 tmp_value
= apic_read(APIC_TDCR
);
370 apic_write(APIC_TDCR
,
371 (tmp_value
& ~(APIC_TDR_DIV_1
| APIC_TDR_DIV_TMBASE
)) |
375 apic_write(APIC_TMICT
, clocks
/ APIC_DIVISOR
);
379 * Setup extended LVT, AMD specific (K8, family 10h)
381 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
382 * MCE interrupts are supported. Thus MCE offset must be set to 0.
384 * If mask=1, the LVT entry does not generate interrupts while mask=0
385 * enables the vector. See also the BKDGs.
388 #define APIC_EILVT_LVTOFF_MCE 0
389 #define APIC_EILVT_LVTOFF_IBS 1
391 static void setup_APIC_eilvt(u8 lvt_off
, u8 vector
, u8 msg_type
, u8 mask
)
393 unsigned long reg
= (lvt_off
<< 4) + APIC_EILVT0
;
394 unsigned int v
= (mask
<< 16) | (msg_type
<< 8) | vector
;
399 u8
setup_APIC_eilvt_mce(u8 vector
, u8 msg_type
, u8 mask
)
401 setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE
, vector
, msg_type
, mask
);
402 return APIC_EILVT_LVTOFF_MCE
;
405 u8
setup_APIC_eilvt_ibs(u8 vector
, u8 msg_type
, u8 mask
)
407 setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS
, vector
, msg_type
, mask
);
408 return APIC_EILVT_LVTOFF_IBS
;
410 EXPORT_SYMBOL_GPL(setup_APIC_eilvt_ibs
);
413 * Program the next event, relative to now
415 static int lapic_next_event(unsigned long delta
,
416 struct clock_event_device
*evt
)
418 apic_write(APIC_TMICT
, delta
);
423 * Setup the lapic timer in periodic or oneshot mode
425 static void lapic_timer_setup(enum clock_event_mode mode
,
426 struct clock_event_device
*evt
)
431 /* Lapic used as dummy for broadcast ? */
432 if (evt
->features
& CLOCK_EVT_FEAT_DUMMY
)
435 local_irq_save(flags
);
438 case CLOCK_EVT_MODE_PERIODIC
:
439 case CLOCK_EVT_MODE_ONESHOT
:
440 __setup_APIC_LVTT(calibration_result
,
441 mode
!= CLOCK_EVT_MODE_PERIODIC
, 1);
443 case CLOCK_EVT_MODE_UNUSED
:
444 case CLOCK_EVT_MODE_SHUTDOWN
:
445 v
= apic_read(APIC_LVTT
);
446 v
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
447 apic_write(APIC_LVTT
, v
);
449 case CLOCK_EVT_MODE_RESUME
:
450 /* Nothing to do here */
454 local_irq_restore(flags
);
458 * Local APIC timer broadcast function
460 static void lapic_timer_broadcast(cpumask_t mask
)
463 send_IPI_mask(mask
, LOCAL_TIMER_VECTOR
);
468 * Setup the local APIC timer for this CPU. Copy the initilized values
469 * of the boot CPU and register the clock event in the framework.
471 static void __cpuinit
setup_APIC_timer(void)
473 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
475 memcpy(levt
, &lapic_clockevent
, sizeof(*levt
));
476 levt
->cpumask
= cpumask_of_cpu(smp_processor_id());
478 clockevents_register_device(levt
);
482 * In this function we calibrate APIC bus clocks to the external
483 * timer. Unfortunately we cannot use jiffies and the timer irq
484 * to calibrate, since some later bootup code depends on getting
485 * the first irq? Ugh.
487 * We want to do the calibration only once since we
488 * want to have local timer irqs syncron. CPUs connected
489 * by the same APIC bus have the very same bus frequency.
490 * And we want to have irqs off anyways, no accidental
494 #define TICK_COUNT 100000000
496 static int __init
calibrate_APIC_clock(void)
498 unsigned apic
, apic_start
;
499 unsigned long tsc
, tsc_start
;
505 * Put whatever arbitrary (but long enough) timeout
506 * value into the APIC clock, we just want to get the
507 * counter running for calibration.
509 * No interrupt enable !
511 __setup_APIC_LVTT(250000000, 0, 0);
513 apic_start
= apic_read(APIC_TMCCT
);
514 #ifdef CONFIG_X86_PM_TIMER
515 if (apic_calibrate_pmtmr
&& pmtmr_ioport
) {
516 pmtimer_wait(5000); /* 5ms wait */
517 apic
= apic_read(APIC_TMCCT
);
518 result
= (apic_start
- apic
) * 1000L / 5;
525 apic
= apic_read(APIC_TMCCT
);
527 } while ((tsc
- tsc_start
) < TICK_COUNT
&&
528 (apic_start
- apic
) < TICK_COUNT
);
530 result
= (apic_start
- apic
) * 1000L * tsc_khz
/
536 printk(KERN_DEBUG
"APIC timer calibration result %d\n", result
);
538 printk(KERN_INFO
"Detected %d.%03d MHz APIC timer.\n",
539 result
/ 1000 / 1000, result
/ 1000 % 1000);
541 /* Calculate the scaled math multiplication factor */
542 lapic_clockevent
.mult
= div_sc(result
, NSEC_PER_SEC
,
543 lapic_clockevent
.shift
);
544 lapic_clockevent
.max_delta_ns
=
545 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent
);
546 lapic_clockevent
.min_delta_ns
=
547 clockevent_delta2ns(0xF, &lapic_clockevent
);
549 calibration_result
= (result
* APIC_DIVISOR
) / HZ
;
552 * Do a sanity check on the APIC calibration result
554 if (calibration_result
< (1000000 / HZ
)) {
556 "APIC frequency too slow, disabling apic timer\n");
564 * Setup the boot APIC
566 * Calibrate and verify the result.
568 void __init
setup_boot_APIC_clock(void)
571 * The local apic timer can be disabled via the kernel
572 * commandline or from the CPU detection code. Register the lapic
573 * timer as a dummy clock event source on SMP systems, so the
574 * broadcast mechanism is used. On UP systems simply ignore it.
576 if (disable_apic_timer
) {
577 printk(KERN_INFO
"Disabling APIC timer\n");
578 /* No broadcast on UP ! */
579 if (num_possible_cpus() > 1) {
580 lapic_clockevent
.mult
= 1;
586 apic_printk(APIC_VERBOSE
, "Using local APIC timer interrupts.\n"
587 "calibrating APIC timer ...\n");
589 if (calibrate_APIC_clock()) {
590 /* No broadcast on UP ! */
591 if (num_possible_cpus() > 1)
597 * If nmi_watchdog is set to IO_APIC, we need the
598 * PIT/HPET going. Otherwise register lapic as a dummy
601 if (nmi_watchdog
!= NMI_IO_APIC
)
602 lapic_clockevent
.features
&= ~CLOCK_EVT_FEAT_DUMMY
;
604 printk(KERN_WARNING
"APIC timer registered as dummy,"
605 " due to nmi_watchdog=%d!\n", nmi_watchdog
);
607 /* Setup the lapic or request the broadcast */
611 void __cpuinit
setup_secondary_APIC_clock(void)
617 * The guts of the apic timer interrupt
619 static void local_apic_timer_interrupt(void)
621 int cpu
= smp_processor_id();
622 struct clock_event_device
*evt
= &per_cpu(lapic_events
, cpu
);
625 * Normally we should not be here till LAPIC has been initialized but
626 * in some cases like kdump, its possible that there is a pending LAPIC
627 * timer interrupt from previous kernel's context and is delivered in
628 * new kernel the moment interrupts are enabled.
630 * Interrupts are enabled early and LAPIC is setup much later, hence
631 * its possible that when we get here evt->event_handler is NULL.
632 * Check for event_handler being NULL and discard the interrupt as
635 if (!evt
->event_handler
) {
637 "Spurious LAPIC timer interrupt on cpu %d\n", cpu
);
639 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, evt
);
644 * the NMI deadlock-detector uses this.
647 add_pda(apic_timer_irqs
, 1);
649 per_cpu(irq_stat
, cpu
).apic_timer_irqs
++;
652 evt
->event_handler(evt
);
656 * Local APIC timer interrupt. This is the most natural way for doing
657 * local interrupts, but local timer interrupts can be emulated by
658 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
660 * [ if a single-CPU system runs an SMP kernel then we call the local
661 * interrupt as well. Thus we cannot inline the local irq ... ]
663 void smp_apic_timer_interrupt(struct pt_regs
*regs
)
665 struct pt_regs
*old_regs
= set_irq_regs(regs
);
668 * NOTE! We'd better ACK the irq immediately,
669 * because timer handling can be slow.
673 * update_process_times() expects us to have done irq_enter().
674 * Besides, if we don't timer interrupts ignore the global
675 * interrupt lock, which is the WrongThing (tm) to do.
681 local_apic_timer_interrupt();
684 set_irq_regs(old_regs
);
687 int setup_profiling_timer(unsigned int multiplier
)
693 * Local APIC start and shutdown
697 * clear_local_APIC - shutdown the local APIC
699 * This is called, when a CPU is disabled and before rebooting, so the state of
700 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
701 * leftovers during boot.
703 void clear_local_APIC(void)
708 /* APIC hasn't been mapped yet */
712 maxlvt
= lapic_get_maxlvt();
714 * Masking an LVT entry can trigger a local APIC error
715 * if the vector is zero. Mask LVTERR first to prevent this.
718 v
= ERROR_APIC_VECTOR
; /* any non-zero vector will do */
719 apic_write(APIC_LVTERR
, v
| APIC_LVT_MASKED
);
722 * Careful: we have to set masks only first to deassert
723 * any level-triggered sources.
725 v
= apic_read(APIC_LVTT
);
726 apic_write(APIC_LVTT
, v
| APIC_LVT_MASKED
);
727 v
= apic_read(APIC_LVT0
);
728 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
729 v
= apic_read(APIC_LVT1
);
730 apic_write(APIC_LVT1
, v
| APIC_LVT_MASKED
);
732 v
= apic_read(APIC_LVTPC
);
733 apic_write(APIC_LVTPC
, v
| APIC_LVT_MASKED
);
736 /* lets not touch this if we didn't frob it */
737 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(X86_MCE_INTEL)
739 v
= apic_read(APIC_LVTTHMR
);
740 apic_write(APIC_LVTTHMR
, v
| APIC_LVT_MASKED
);
744 * Clean APIC state for other OSs:
746 apic_write(APIC_LVTT
, APIC_LVT_MASKED
);
747 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
748 apic_write(APIC_LVT1
, APIC_LVT_MASKED
);
750 apic_write(APIC_LVTERR
, APIC_LVT_MASKED
);
752 apic_write(APIC_LVTPC
, APIC_LVT_MASKED
);
754 /* Integrated APIC (!82489DX) ? */
755 if (lapic_is_integrated()) {
757 /* Clear ESR due to Pentium errata 3AP and 11AP */
758 apic_write(APIC_ESR
, 0);
764 * disable_local_APIC - clear and disable the local APIC
766 void disable_local_APIC(void)
773 * Disable APIC (implies clearing of registers
776 value
= apic_read(APIC_SPIV
);
777 value
&= ~APIC_SPIV_APIC_ENABLED
;
778 apic_write(APIC_SPIV
, value
);
782 * When LAPIC was disabled by the BIOS and enabled by the kernel,
783 * restore the disabled state.
785 if (enabled_via_apicbase
) {
788 rdmsr(MSR_IA32_APICBASE
, l
, h
);
789 l
&= ~MSR_IA32_APICBASE_ENABLE
;
790 wrmsr(MSR_IA32_APICBASE
, l
, h
);
796 * If Linux enabled the LAPIC against the BIOS default disable it down before
797 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
798 * not power-off. Additionally clear all LVT entries before disable_local_APIC
799 * for the case where Linux didn't enable the LAPIC.
801 void lapic_shutdown(void)
808 local_irq_save(flags
);
811 if (!enabled_via_apicbase
)
815 disable_local_APIC();
818 local_irq_restore(flags
);
822 * This is to verify that we're looking at a real local APIC.
823 * Check these against your board if the CPUs aren't getting
824 * started for no apparent reason.
826 int __init
verify_local_APIC(void)
828 unsigned int reg0
, reg1
;
831 * The version register is read-only in a real APIC.
833 reg0
= apic_read(APIC_LVR
);
834 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg0
);
835 apic_write(APIC_LVR
, reg0
^ APIC_LVR_MASK
);
836 reg1
= apic_read(APIC_LVR
);
837 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg1
);
840 * The two version reads above should print the same
841 * numbers. If the second one is different, then we
842 * poke at a non-APIC.
848 * Check if the version looks reasonably.
850 reg1
= GET_APIC_VERSION(reg0
);
851 if (reg1
== 0x00 || reg1
== 0xff)
853 reg1
= lapic_get_maxlvt();
854 if (reg1
< 0x02 || reg1
== 0xff)
858 * The ID register is read/write in a real APIC.
860 reg0
= apic_read(APIC_ID
);
861 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg0
);
862 apic_write(APIC_ID
, reg0
^ APIC_ID_MASK
);
863 reg1
= apic_read(APIC_ID
);
864 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg1
);
865 apic_write(APIC_ID
, reg0
);
866 if (reg1
!= (reg0
^ APIC_ID_MASK
))
870 * The next two are just to see if we have sane values.
871 * They're only really relevant if we're in Virtual Wire
872 * compatibility mode, but most boxes are anymore.
874 reg0
= apic_read(APIC_LVT0
);
875 apic_printk(APIC_DEBUG
, "Getting LVT0: %x\n", reg0
);
876 reg1
= apic_read(APIC_LVT1
);
877 apic_printk(APIC_DEBUG
, "Getting LVT1: %x\n", reg1
);
883 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
885 void __init
sync_Arb_IDs(void)
888 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
891 if (modern_apic() || boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
)
897 apic_wait_icr_idle();
899 apic_printk(APIC_DEBUG
, "Synchronizing Arb IDs.\n");
900 apic_write(APIC_ICR
, APIC_DEST_ALLINC
|
901 APIC_INT_LEVELTRIG
| APIC_DM_INIT
);
905 * An initial setup of the virtual wire mode.
907 void __init
init_bsp_APIC(void)
912 * Don't do the setup now if we have a SMP BIOS as the
913 * through-I/O-APIC virtual wire mode might be active.
915 if (smp_found_config
|| !cpu_has_apic
)
919 * Do not trust the local APIC being empty at bootup.
926 value
= apic_read(APIC_SPIV
);
927 value
&= ~APIC_VECTOR_MASK
;
928 value
|= APIC_SPIV_APIC_ENABLED
;
931 /* This bit is reserved on P4/Xeon and should be cleared */
932 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
) &&
933 (boot_cpu_data
.x86
== 15))
934 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
937 value
|= APIC_SPIV_FOCUS_DISABLED
;
938 value
|= SPURIOUS_APIC_VECTOR
;
939 apic_write(APIC_SPIV
, value
);
942 * Set up the virtual wire mode.
944 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
946 if (!lapic_is_integrated()) /* 82489DX */
947 value
|= APIC_LVT_LEVEL_TRIGGER
;
948 apic_write(APIC_LVT1
, value
);
951 static void __cpuinit
lapic_setup_esr(void)
953 unsigned long oldvalue
, value
, maxlvt
;
954 if (lapic_is_integrated() && !esr_disable
) {
957 * Something untraceable is creating bad interrupts on
958 * secondary quads ... for the moment, just leave the
959 * ESR disabled - we can't do anything useful with the
960 * errors anyway - mbligh
962 printk(KERN_INFO
"Leaving ESR disabled.\n");
966 maxlvt
= lapic_get_maxlvt();
967 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
968 apic_write(APIC_ESR
, 0);
969 oldvalue
= apic_read(APIC_ESR
);
971 /* enables sending errors */
972 value
= ERROR_APIC_VECTOR
;
973 apic_write(APIC_LVTERR
, value
);
975 * spec says clear errors after enabling vector.
978 apic_write(APIC_ESR
, 0);
979 value
= apic_read(APIC_ESR
);
980 if (value
!= oldvalue
)
981 apic_printk(APIC_VERBOSE
, "ESR value before enabling "
982 "vector: 0x%08lx after: 0x%08lx\n",
985 printk(KERN_INFO
"No ESR for 82489DX.\n");
991 * setup_local_APIC - setup the local APIC
993 void __cpuinit
setup_local_APIC(void)
999 /* Pound the ESR really hard over the head with a big hammer - mbligh */
1001 apic_write(APIC_ESR
, 0);
1002 apic_write(APIC_ESR
, 0);
1003 apic_write(APIC_ESR
, 0);
1004 apic_write(APIC_ESR
, 0);
1011 * Double-check whether this APIC is really registered.
1012 * This is meaningless in clustered apic mode, so we skip it.
1014 if (!apic_id_registered())
1018 * Intel recommends to set DFR, LDR and TPR before enabling
1019 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
1020 * document number 292116). So here it goes...
1025 * Set Task Priority to 'accept all'. We never change this
1028 value
= apic_read(APIC_TASKPRI
);
1029 value
&= ~APIC_TPRI_MASK
;
1030 apic_write(APIC_TASKPRI
, value
);
1033 * After a crash, we no longer service the interrupts and a pending
1034 * interrupt from previous kernel might still have ISR bit set.
1036 * Most probably by now CPU has serviced that pending interrupt and
1037 * it might not have done the ack_APIC_irq() because it thought,
1038 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
1039 * does not clear the ISR bit and cpu thinks it has already serivced
1040 * the interrupt. Hence a vector might get locked. It was noticed
1041 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
1043 for (i
= APIC_ISR_NR
- 1; i
>= 0; i
--) {
1044 value
= apic_read(APIC_ISR
+ i
*0x10);
1045 for (j
= 31; j
>= 0; j
--) {
1052 * Now that we are all set up, enable the APIC
1054 value
= apic_read(APIC_SPIV
);
1055 value
&= ~APIC_VECTOR_MASK
;
1059 value
|= APIC_SPIV_APIC_ENABLED
;
1061 #ifdef CONFIG_X86_32
1063 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1064 * certain networking cards. If high frequency interrupts are
1065 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1066 * entry is masked/unmasked at a high rate as well then sooner or
1067 * later IOAPIC line gets 'stuck', no more interrupts are received
1068 * from the device. If focus CPU is disabled then the hang goes
1071 * [ This bug can be reproduced easily with a level-triggered
1072 * PCI Ne2000 networking cards and PII/PIII processors, dual
1076 * Actually disabling the focus CPU check just makes the hang less
1077 * frequent as it makes the interrupt distributon model be more
1078 * like LRU than MRU (the short-term load is more even across CPUs).
1079 * See also the comment in end_level_ioapic_irq(). --macro
1083 * - enable focus processor (bit==0)
1084 * - 64bit mode always use processor focus
1085 * so no need to set it
1087 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
1091 * Set spurious IRQ vector
1093 value
|= SPURIOUS_APIC_VECTOR
;
1094 apic_write(APIC_SPIV
, value
);
1097 * Set up LVT0, LVT1:
1099 * set up through-local-APIC on the BP's LINT0. This is not
1100 * strictly necessary in pure symmetric-IO mode, but sometimes
1101 * we delegate interrupts to the 8259A.
1104 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1106 value
= apic_read(APIC_LVT0
) & APIC_LVT_MASKED
;
1107 if (!smp_processor_id() && (pic_mode
|| !value
)) {
1108 value
= APIC_DM_EXTINT
;
1109 apic_printk(APIC_VERBOSE
, "enabled ExtINT on CPU#%d\n",
1110 smp_processor_id());
1112 value
= APIC_DM_EXTINT
| APIC_LVT_MASKED
;
1113 apic_printk(APIC_VERBOSE
, "masked ExtINT on CPU#%d\n",
1114 smp_processor_id());
1116 apic_write(APIC_LVT0
, value
);
1119 * only the BP should see the LINT1 NMI signal, obviously.
1121 if (!smp_processor_id())
1122 value
= APIC_DM_NMI
;
1124 value
= APIC_DM_NMI
| APIC_LVT_MASKED
;
1125 if (!lapic_is_integrated()) /* 82489DX */
1126 value
|= APIC_LVT_LEVEL_TRIGGER
;
1127 apic_write(APIC_LVT1
, value
);
1132 void __cpuinit
end_local_APIC_setup(void)
1136 #ifdef CONFIG_X86_32
1139 /* Disable the local apic timer */
1140 value
= apic_read(APIC_LVTT
);
1141 value
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
1142 apic_write(APIC_LVTT
, value
);
1146 setup_apic_nmi_watchdog(NULL
);
1151 void check_x2apic(void)
1155 rdmsr(MSR_IA32_APICBASE
, msr
, msr2
);
1157 if (msr
& X2APIC_ENABLE
) {
1158 printk("x2apic enabled by BIOS, switching to x2apic ops\n");
1159 x2apic_preenabled
= x2apic
= 1;
1160 apic_ops
= &x2apic_ops
;
1164 void enable_x2apic(void)
1168 rdmsr(MSR_IA32_APICBASE
, msr
, msr2
);
1169 if (!(msr
& X2APIC_ENABLE
)) {
1170 printk("Enabling x2apic\n");
1171 wrmsr(MSR_IA32_APICBASE
, msr
| X2APIC_ENABLE
, 0);
1175 void enable_IR_x2apic(void)
1177 #ifdef CONFIG_INTR_REMAP
1179 unsigned long flags
;
1181 if (!cpu_has_x2apic
)
1184 if (!x2apic_preenabled
&& disable_x2apic
) {
1186 "Skipped enabling x2apic and Interrupt-remapping "
1187 "because of nox2apic\n");
1191 if (x2apic_preenabled
&& disable_x2apic
)
1192 panic("Bios already enabled x2apic, can't enforce nox2apic");
1194 if (!x2apic_preenabled
&& skip_ioapic_setup
) {
1196 "Skipped enabling x2apic and Interrupt-remapping "
1197 "because of skipping io-apic setup\n");
1201 ret
= dmar_table_init();
1204 "dmar_table_init() failed with %d:\n", ret
);
1206 if (x2apic_preenabled
)
1207 panic("x2apic enabled by bios. But IR enabling failed");
1210 "Not enabling x2apic,Intr-remapping\n");
1214 local_irq_save(flags
);
1216 save_mask_IO_APIC_setup();
1218 ret
= enable_intr_remapping(1);
1220 if (ret
&& x2apic_preenabled
) {
1221 local_irq_restore(flags
);
1222 panic("x2apic enabled by bios. But IR enabling failed");
1230 apic_ops
= &x2apic_ops
;
1236 * IR enabling failed
1238 restore_IO_APIC_setup();
1240 reinit_intr_remapped_IO_APIC(x2apic_preenabled
);
1243 local_irq_restore(flags
);
1246 if (!x2apic_preenabled
)
1248 "Enabled x2apic and interrupt-remapping\n");
1251 "Enabled Interrupt-remapping\n");
1254 "Failed to enable Interrupt-remapping and x2apic\n");
1256 if (!cpu_has_x2apic
)
1259 if (x2apic_preenabled
)
1260 panic("x2apic enabled prior OS handover,"
1261 " enable CONFIG_INTR_REMAP");
1263 printk(KERN_INFO
"Enable CONFIG_INTR_REMAP for enabling intr-remapping "
1269 #endif /* HAVE_X2APIC */
1271 #ifdef CONFIG_X86_64
1273 * Detect and enable local APICs on non-SMP boards.
1274 * Original code written by Keir Fraser.
1275 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1276 * not correctly set up (usually the APIC timer won't work etc.)
1278 static int __init
detect_init_APIC(void)
1280 if (!cpu_has_apic
) {
1281 printk(KERN_INFO
"No local APIC present\n");
1285 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
1286 boot_cpu_physical_apicid
= 0;
1291 * Detect and initialize APIC
1293 static int __init
detect_init_APIC(void)
1297 /* Disabled by kernel option? */
1301 switch (boot_cpu_data
.x86_vendor
) {
1302 case X86_VENDOR_AMD
:
1303 if ((boot_cpu_data
.x86
== 6 && boot_cpu_data
.x86_model
> 1) ||
1304 (boot_cpu_data
.x86
== 15))
1307 case X86_VENDOR_INTEL
:
1308 if (boot_cpu_data
.x86
== 6 || boot_cpu_data
.x86
== 15 ||
1309 (boot_cpu_data
.x86
== 5 && cpu_has_apic
))
1316 if (!cpu_has_apic
) {
1318 * Over-ride BIOS and try to enable the local APIC only if
1319 * "lapic" specified.
1321 if (!force_enable_local_apic
) {
1322 printk(KERN_INFO
"Local APIC disabled by BIOS -- "
1323 "you can enable it with \"lapic\"\n");
1327 * Some BIOSes disable the local APIC in the APIC_BASE
1328 * MSR. This can only be done in software for Intel P6 or later
1329 * and AMD K7 (Model > 1) or later.
1331 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1332 if (!(l
& MSR_IA32_APICBASE_ENABLE
)) {
1334 "Local APIC disabled by BIOS -- reenabling.\n");
1335 l
&= ~MSR_IA32_APICBASE_BASE
;
1336 l
|= MSR_IA32_APICBASE_ENABLE
| APIC_DEFAULT_PHYS_BASE
;
1337 wrmsr(MSR_IA32_APICBASE
, l
, h
);
1338 enabled_via_apicbase
= 1;
1342 * The APIC feature bit should now be enabled
1345 features
= cpuid_edx(1);
1346 if (!(features
& (1 << X86_FEATURE_APIC
))) {
1347 printk(KERN_WARNING
"Could not enable APIC!\n");
1350 set_cpu_cap(&boot_cpu_data
, X86_FEATURE_APIC
);
1351 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
1353 /* The BIOS may have set up the APIC at some other address */
1354 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1355 if (l
& MSR_IA32_APICBASE_ENABLE
)
1356 mp_lapic_addr
= l
& MSR_IA32_APICBASE_BASE
;
1358 printk(KERN_INFO
"Found and enabled local APIC!\n");
1365 printk(KERN_INFO
"No local APIC present or hardware disabled\n");
1370 #ifdef CONFIG_X86_64
1371 void __init
early_init_lapic_mapping(void)
1373 unsigned long phys_addr
;
1376 * If no local APIC can be found then go out
1377 * : it means there is no mpatable and MADT
1379 if (!smp_found_config
)
1382 phys_addr
= mp_lapic_addr
;
1384 set_fixmap_nocache(FIX_APIC_BASE
, phys_addr
);
1385 apic_printk(APIC_VERBOSE
, "mapped APIC to %16lx (%16lx)\n",
1386 APIC_BASE
, phys_addr
);
1389 * Fetch the APIC ID of the BSP in case we have a
1390 * default configuration (or the MP table is broken).
1392 boot_cpu_physical_apicid
= read_apic_id();
1397 * init_apic_mappings - initialize APIC mappings
1399 void __init
init_apic_mappings(void)
1403 boot_cpu_physical_apicid
= read_apic_id();
1409 * If no local APIC can be found then set up a fake all
1410 * zeroes page to simulate the local APIC and another
1411 * one for the IO-APIC.
1413 if (!smp_found_config
&& detect_init_APIC()) {
1414 apic_phys
= (unsigned long) alloc_bootmem_pages(PAGE_SIZE
);
1415 apic_phys
= __pa(apic_phys
);
1417 apic_phys
= mp_lapic_addr
;
1419 set_fixmap_nocache(FIX_APIC_BASE
, apic_phys
);
1420 apic_printk(APIC_VERBOSE
, "mapped APIC to %16lx (%16lx)\n",
1421 APIC_BASE
, apic_phys
);
1424 * Fetch the APIC ID of the BSP in case we have a
1425 * default configuration (or the MP table is broken).
1427 if (boot_cpu_physical_apicid
== -1U)
1428 boot_cpu_physical_apicid
= read_apic_id();
1432 * This initializes the IO-APIC and APIC hardware if this is
1435 int apic_version
[MAX_APICS
];
1437 int __init
APIC_init_uniprocessor(void)
1439 #ifdef CONFIG_X86_64
1441 printk(KERN_INFO
"Apic disabled\n");
1444 if (!cpu_has_apic
) {
1446 printk(KERN_INFO
"Apic disabled by BIOS\n");
1450 if (!smp_found_config
&& !cpu_has_apic
)
1454 * Complain if the BIOS pretends there is one.
1456 if (!cpu_has_apic
&&
1457 APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
])) {
1458 printk(KERN_ERR
"BIOS bug, local APIC #%d not detected!...\n",
1459 boot_cpu_physical_apicid
);
1460 clear_cpu_cap(&boot_cpu_data
, X86_FEATURE_APIC
);
1468 #ifdef CONFIG_X86_64
1469 setup_apic_routing();
1472 verify_local_APIC();
1475 #ifdef CONFIG_X86_64
1476 apic_write(APIC_ID
, SET_APIC_ID(boot_cpu_physical_apicid
));
1479 * Hack: In case of kdump, after a crash, kernel might be booting
1480 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
1481 * might be zero if read from MP tables. Get it from LAPIC.
1483 # ifdef CONFIG_CRASH_DUMP
1484 boot_cpu_physical_apicid
= read_apic_id();
1487 physid_set_mask_of_physid(boot_cpu_physical_apicid
, &phys_cpu_present_map
);
1490 #ifdef CONFIG_X86_64
1492 * Now enable IO-APICs, actually call clear_IO_APIC
1493 * We need clear_IO_APIC before enabling vector on BP
1495 if (!skip_ioapic_setup
&& nr_ioapics
)
1499 #ifdef CONFIG_X86_IO_APIC
1500 if (!smp_found_config
|| skip_ioapic_setup
|| !nr_ioapics
)
1502 localise_nmi_watchdog();
1503 end_local_APIC_setup();
1505 #ifdef CONFIG_X86_IO_APIC
1506 if (smp_found_config
&& !skip_ioapic_setup
&& nr_ioapics
)
1508 # ifdef CONFIG_X86_64
1514 #ifdef CONFIG_X86_64
1515 setup_boot_APIC_clock();
1516 check_nmi_watchdog();
1525 * Local APIC interrupts
1529 * This interrupt should _never_ happen with our APIC/SMP architecture
1531 asmlinkage
void smp_spurious_interrupt(void)
1537 * Check if this really is a spurious interrupt and ACK it
1538 * if it is a vectored one. Just in case...
1539 * Spurious interrupts should not be ACKed.
1541 v
= apic_read(APIC_ISR
+ ((SPURIOUS_APIC_VECTOR
& ~0x1f) >> 1));
1542 if (v
& (1 << (SPURIOUS_APIC_VECTOR
& 0x1f)))
1545 add_pda(irq_spurious_count
, 1);
1550 * This interrupt should never happen with our APIC/SMP architecture
1552 asmlinkage
void smp_error_interrupt(void)
1558 /* First tickle the hardware, only then report what went on. -- REW */
1559 v
= apic_read(APIC_ESR
);
1560 apic_write(APIC_ESR
, 0);
1561 v1
= apic_read(APIC_ESR
);
1563 atomic_inc(&irq_err_count
);
1565 /* Here is what the APIC error bits mean:
1568 2: Send accept error
1569 3: Receive accept error
1571 5: Send illegal vector
1572 6: Received illegal vector
1573 7: Illegal register address
1575 printk(KERN_DEBUG
"APIC error on CPU%d: %02x(%02x)\n",
1576 smp_processor_id(), v
, v1
);
1581 * connect_bsp_APIC - attach the APIC to the interrupt system
1583 void __init
connect_bsp_APIC(void)
1585 #ifdef CONFIG_X86_32
1588 * Do not trust the local APIC being empty at bootup.
1592 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
1593 * local APIC to INT and NMI lines.
1595 apic_printk(APIC_VERBOSE
, "leaving PIC mode, "
1596 "enabling APIC mode.\n");
1605 * disconnect_bsp_APIC - detach the APIC from the interrupt system
1606 * @virt_wire_setup: indicates, whether virtual wire mode is selected
1608 * Virtual wire mode is necessary to deliver legacy interrupts even when the
1611 void disconnect_bsp_APIC(int virt_wire_setup
)
1615 #ifdef CONFIG_X86_32
1618 * Put the board back into PIC mode (has an effect only on
1619 * certain older boards). Note that APIC interrupts, including
1620 * IPIs, won't work beyond this point! The only exception are
1623 apic_printk(APIC_VERBOSE
, "disabling APIC mode, "
1624 "entering PIC mode.\n");
1631 /* Go back to Virtual Wire compatibility mode */
1633 /* For the spurious interrupt use vector F, and enable it */
1634 value
= apic_read(APIC_SPIV
);
1635 value
&= ~APIC_VECTOR_MASK
;
1636 value
|= APIC_SPIV_APIC_ENABLED
;
1638 apic_write(APIC_SPIV
, value
);
1640 if (!virt_wire_setup
) {
1642 * For LVT0 make it edge triggered, active high,
1643 * external and enabled
1645 value
= apic_read(APIC_LVT0
);
1646 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1647 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1648 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1649 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1650 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_EXTINT
);
1651 apic_write(APIC_LVT0
, value
);
1654 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
1658 * For LVT1 make it edge triggered, active high,
1661 value
= apic_read(APIC_LVT1
);
1662 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1663 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1664 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1665 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1666 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_NMI
);
1667 apic_write(APIC_LVT1
, value
);
1670 void __cpuinit
generic_processor_info(int apicid
, int version
)
1678 if (version
== 0x0) {
1679 printk(KERN_WARNING
"BIOS bug, APIC version is 0 for CPU#%d! "
1680 "fixing up to 0x10. (tell your hw vendor)\n",
1684 apic_version
[apicid
] = version
;
1686 if (num_processors
>= NR_CPUS
) {
1687 printk(KERN_WARNING
"WARNING: NR_CPUS limit of %i reached."
1688 " Processor ignored.\n", NR_CPUS
);
1693 cpus_complement(tmp_map
, cpu_present_map
);
1694 cpu
= first_cpu(tmp_map
);
1696 physid_set(apicid
, phys_cpu_present_map
);
1697 if (apicid
== boot_cpu_physical_apicid
) {
1699 * x86_bios_cpu_apicid is required to have processors listed
1700 * in same order as logical cpu numbers. Hence the first
1701 * entry is BSP, and so on.
1705 if (apicid
> max_physical_apicid
)
1706 max_physical_apicid
= apicid
;
1708 #ifdef CONFIG_X86_32
1710 * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y
1711 * but we need to work other dependencies like SMP_SUSPEND etc
1712 * before this can be done without some confusion.
1713 * if (CPU_HOTPLUG_ENABLED || num_processors > 8)
1714 * - Ashok Raj <ashok.raj@intel.com>
1716 if (max_physical_apicid
>= 8) {
1717 switch (boot_cpu_data
.x86_vendor
) {
1718 case X86_VENDOR_INTEL
:
1719 if (!APIC_XAPIC(version
)) {
1723 /* If P4 and above fall through */
1724 case X86_VENDOR_AMD
:
1730 #if defined(CONFIG_X86_SMP) || defined(CONFIG_X86_64)
1731 /* are we being called early in kernel startup? */
1732 if (early_per_cpu_ptr(x86_cpu_to_apicid
)) {
1733 u16
*cpu_to_apicid
= early_per_cpu_ptr(x86_cpu_to_apicid
);
1734 u16
*bios_cpu_apicid
= early_per_cpu_ptr(x86_bios_cpu_apicid
);
1736 cpu_to_apicid
[cpu
] = apicid
;
1737 bios_cpu_apicid
[cpu
] = apicid
;
1739 per_cpu(x86_cpu_to_apicid
, cpu
) = apicid
;
1740 per_cpu(x86_bios_cpu_apicid
, cpu
) = apicid
;
1744 cpu_set(cpu
, cpu_possible_map
);
1745 cpu_set(cpu
, cpu_present_map
);
1748 #ifdef CONFIG_X86_64
1749 int hard_smp_processor_id(void)
1751 return read_apic_id();
1762 * 'active' is true if the local APIC was enabled by us and
1763 * not the BIOS; this signifies that we are also responsible
1764 * for disabling it before entering apm/acpi suspend
1767 /* r/w apic fields */
1768 unsigned int apic_id
;
1769 unsigned int apic_taskpri
;
1770 unsigned int apic_ldr
;
1771 unsigned int apic_dfr
;
1772 unsigned int apic_spiv
;
1773 unsigned int apic_lvtt
;
1774 unsigned int apic_lvtpc
;
1775 unsigned int apic_lvt0
;
1776 unsigned int apic_lvt1
;
1777 unsigned int apic_lvterr
;
1778 unsigned int apic_tmict
;
1779 unsigned int apic_tdcr
;
1780 unsigned int apic_thmr
;
1783 static int lapic_suspend(struct sys_device
*dev
, pm_message_t state
)
1785 unsigned long flags
;
1788 if (!apic_pm_state
.active
)
1791 maxlvt
= lapic_get_maxlvt();
1793 apic_pm_state
.apic_id
= apic_read(APIC_ID
);
1794 apic_pm_state
.apic_taskpri
= apic_read(APIC_TASKPRI
);
1795 apic_pm_state
.apic_ldr
= apic_read(APIC_LDR
);
1796 apic_pm_state
.apic_dfr
= apic_read(APIC_DFR
);
1797 apic_pm_state
.apic_spiv
= apic_read(APIC_SPIV
);
1798 apic_pm_state
.apic_lvtt
= apic_read(APIC_LVTT
);
1800 apic_pm_state
.apic_lvtpc
= apic_read(APIC_LVTPC
);
1801 apic_pm_state
.apic_lvt0
= apic_read(APIC_LVT0
);
1802 apic_pm_state
.apic_lvt1
= apic_read(APIC_LVT1
);
1803 apic_pm_state
.apic_lvterr
= apic_read(APIC_LVTERR
);
1804 apic_pm_state
.apic_tmict
= apic_read(APIC_TMICT
);
1805 apic_pm_state
.apic_tdcr
= apic_read(APIC_TDCR
);
1806 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
1808 apic_pm_state
.apic_thmr
= apic_read(APIC_LVTTHMR
);
1811 local_irq_save(flags
);
1812 disable_local_APIC();
1813 local_irq_restore(flags
);
1817 static int lapic_resume(struct sys_device
*dev
)
1820 unsigned long flags
;
1823 if (!apic_pm_state
.active
)
1826 maxlvt
= lapic_get_maxlvt();
1828 local_irq_save(flags
);
1837 * Make sure the APICBASE points to the right address
1839 * FIXME! This will be wrong if we ever support suspend on
1840 * SMP! We'll need to do this as part of the CPU restore!
1842 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1843 l
&= ~MSR_IA32_APICBASE_BASE
;
1844 l
|= MSR_IA32_APICBASE_ENABLE
| mp_lapic_addr
;
1845 wrmsr(MSR_IA32_APICBASE
, l
, h
);
1848 apic_write(APIC_LVTERR
, ERROR_APIC_VECTOR
| APIC_LVT_MASKED
);
1849 apic_write(APIC_ID
, apic_pm_state
.apic_id
);
1850 apic_write(APIC_DFR
, apic_pm_state
.apic_dfr
);
1851 apic_write(APIC_LDR
, apic_pm_state
.apic_ldr
);
1852 apic_write(APIC_TASKPRI
, apic_pm_state
.apic_taskpri
);
1853 apic_write(APIC_SPIV
, apic_pm_state
.apic_spiv
);
1854 apic_write(APIC_LVT0
, apic_pm_state
.apic_lvt0
);
1855 apic_write(APIC_LVT1
, apic_pm_state
.apic_lvt1
);
1856 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
1858 apic_write(APIC_LVTTHMR
, apic_pm_state
.apic_thmr
);
1861 apic_write(APIC_LVTPC
, apic_pm_state
.apic_lvtpc
);
1862 apic_write(APIC_LVTT
, apic_pm_state
.apic_lvtt
);
1863 apic_write(APIC_TDCR
, apic_pm_state
.apic_tdcr
);
1864 apic_write(APIC_TMICT
, apic_pm_state
.apic_tmict
);
1865 apic_write(APIC_ESR
, 0);
1866 apic_read(APIC_ESR
);
1867 apic_write(APIC_LVTERR
, apic_pm_state
.apic_lvterr
);
1868 apic_write(APIC_ESR
, 0);
1869 apic_read(APIC_ESR
);
1871 local_irq_restore(flags
);
1877 * This device has no shutdown method - fully functioning local APICs
1878 * are needed on every CPU up until machine_halt/restart/poweroff.
1881 static struct sysdev_class lapic_sysclass
= {
1883 .resume
= lapic_resume
,
1884 .suspend
= lapic_suspend
,
1887 static struct sys_device device_lapic
= {
1889 .cls
= &lapic_sysclass
,
1892 static void __cpuinit
apic_pm_activate(void)
1894 apic_pm_state
.active
= 1;
1897 static int __init
init_lapic_sysfs(void)
1903 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
1905 error
= sysdev_class_register(&lapic_sysclass
);
1907 error
= sysdev_register(&device_lapic
);
1910 device_initcall(init_lapic_sysfs
);
1912 #else /* CONFIG_PM */
1914 static void apic_pm_activate(void) { }
1916 #endif /* CONFIG_PM */
1918 #ifdef CONFIG_X86_64
1920 * apic_is_clustered_box() -- Check if we can expect good TSC
1922 * Thus far, the major user of this is IBM's Summit2 series:
1924 * Clustered boxes may have unsynced TSC problems if they are
1925 * multi-chassis. Use available data to take a good guess.
1926 * If in doubt, go HPET.
1928 __cpuinit
int apic_is_clustered_box(void)
1930 int i
, clusters
, zeros
;
1932 u16
*bios_cpu_apicid
;
1933 DECLARE_BITMAP(clustermap
, NUM_APIC_CLUSTERS
);
1936 * there is not this kind of box with AMD CPU yet.
1937 * Some AMD box with quadcore cpu and 8 sockets apicid
1938 * will be [4, 0x23] or [8, 0x27] could be thought to
1939 * vsmp box still need checking...
1941 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
) && !is_vsmp_box())
1944 bios_cpu_apicid
= early_per_cpu_ptr(x86_bios_cpu_apicid
);
1945 bitmap_zero(clustermap
, NUM_APIC_CLUSTERS
);
1947 for (i
= 0; i
< NR_CPUS
; i
++) {
1948 /* are we being called early in kernel startup? */
1949 if (bios_cpu_apicid
) {
1950 id
= bios_cpu_apicid
[i
];
1952 else if (i
< nr_cpu_ids
) {
1954 id
= per_cpu(x86_bios_cpu_apicid
, i
);
1961 if (id
!= BAD_APICID
)
1962 __set_bit(APIC_CLUSTERID(id
), clustermap
);
1965 /* Problem: Partially populated chassis may not have CPUs in some of
1966 * the APIC clusters they have been allocated. Only present CPUs have
1967 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap.
1968 * Since clusters are allocated sequentially, count zeros only if
1969 * they are bounded by ones.
1973 for (i
= 0; i
< NUM_APIC_CLUSTERS
; i
++) {
1974 if (test_bit(i
, clustermap
)) {
1975 clusters
+= 1 + zeros
;
1981 /* ScaleMP vSMPowered boxes have one cluster per board and TSCs are
1982 * not guaranteed to be synced between boards
1984 if (is_vsmp_box() && clusters
> 1)
1988 * If clusters > 2, then should be multi-chassis.
1989 * May have to revisit this when multi-core + hyperthreaded CPUs come
1990 * out, but AFAIK this will work even for them.
1992 return (clusters
> 2);
1997 * APIC command line parameters
1999 static int __init
setup_disableapic(char *arg
)
2002 setup_clear_cpu_cap(X86_FEATURE_APIC
);
2005 early_param("disableapic", setup_disableapic
);
2007 /* same as disableapic, for compatibility */
2008 static int __init
setup_nolapic(char *arg
)
2010 return setup_disableapic(arg
);
2012 early_param("nolapic", setup_nolapic
);
2014 static int __init
parse_lapic_timer_c2_ok(char *arg
)
2016 local_apic_timer_c2_ok
= 1;
2019 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok
);
2021 static int __init
parse_disable_apic_timer(char *arg
)
2023 disable_apic_timer
= 1;
2026 early_param("noapictimer", parse_disable_apic_timer
);
2028 static int __init
parse_nolapic_timer(char *arg
)
2030 disable_apic_timer
= 1;
2033 early_param("nolapic_timer", parse_nolapic_timer
);
2035 static int __init
apic_set_verbosity(char *arg
)
2038 #ifdef CONFIG_X86_64
2039 skip_ioapic_setup
= 0;
2045 if (strcmp("debug", arg
) == 0)
2046 apic_verbosity
= APIC_DEBUG
;
2047 else if (strcmp("verbose", arg
) == 0)
2048 apic_verbosity
= APIC_VERBOSE
;
2050 printk(KERN_WARNING
"APIC Verbosity level %s not recognised"
2051 " use apic=verbose or apic=debug\n", arg
);
2057 early_param("apic", apic_set_verbosity
);
2059 static int __init
lapic_insert_resource(void)
2064 /* Put local APIC into the resource map. */
2065 lapic_resource
.start
= apic_phys
;
2066 lapic_resource
.end
= lapic_resource
.start
+ PAGE_SIZE
- 1;
2067 insert_resource(&iomem_resource
, &lapic_resource
);
2073 * need call insert after e820_reserve_resources()
2074 * that is using request_resource
2076 late_initcall(lapic_insert_resource
);