2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/bootmem.h>
22 #include <linux/interrupt.h>
23 #include <linux/mc146818rtc.h>
24 #include <linux/kernel_stat.h>
25 #include <linux/sysdev.h>
26 #include <linux/ioport.h>
27 #include <linux/clockchips.h>
28 #include <linux/acpi_pmtmr.h>
29 #include <linux/module.h>
30 #include <linux/dmar.h>
32 #include <asm/atomic.h>
35 #include <asm/mpspec.h>
37 #include <asm/pgalloc.h>
40 #include <asm/proto.h>
41 #include <asm/timex.h>
43 #include <asm/i8259.h>
46 #include <mach_apic.h>
48 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
49 static int disable_apic_timer __cpuinitdata
;
50 static int apic_calibrate_pmtmr __initdata
;
55 /* x2apic enabled before OS handover */
56 int x2apic_preenabled
;
58 /* Local APIC timer works in C2 */
59 int local_apic_timer_c2_ok
;
60 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok
);
63 * Debug level, exported for io_apic.c
65 unsigned int apic_verbosity
;
67 /* Have we found an MP table */
70 static struct resource lapic_resource
= {
72 .flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
,
75 static unsigned int calibration_result
;
77 static int lapic_next_event(unsigned long delta
,
78 struct clock_event_device
*evt
);
79 static void lapic_timer_setup(enum clock_event_mode mode
,
80 struct clock_event_device
*evt
);
81 static void lapic_timer_broadcast(cpumask_t mask
);
82 static void apic_pm_activate(void);
85 * The local apic timer can be used for any function which is CPU local.
87 static struct clock_event_device lapic_clockevent
= {
89 .features
= CLOCK_EVT_FEAT_PERIODIC
| CLOCK_EVT_FEAT_ONESHOT
90 | CLOCK_EVT_FEAT_C3STOP
| CLOCK_EVT_FEAT_DUMMY
,
92 .set_mode
= lapic_timer_setup
,
93 .set_next_event
= lapic_next_event
,
94 .broadcast
= lapic_timer_broadcast
,
98 static DEFINE_PER_CPU(struct clock_event_device
, lapic_events
);
100 static unsigned long apic_phys
;
101 unsigned int __cpuinitdata maxcpus
= NR_CPUS
;
103 unsigned long mp_lapic_addr
;
106 * Get the LAPIC version
108 static inline int lapic_get_version(void)
110 return GET_APIC_VERSION(apic_read(APIC_LVR
));
114 * Check, if the APIC is integrated or a separate chip
116 static inline int lapic_is_integrated(void)
121 return APIC_INTEGRATED(lapic_get_version());
126 * Check, whether this is a modern or a first generation APIC
128 static int modern_apic(void)
130 /* AMD systems use old APIC versions, so check the CPU */
131 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
&&
132 boot_cpu_data
.x86
>= 0xf)
134 return lapic_get_version() >= 0x14;
138 * Paravirt kernels also might be using these below ops. So we still
139 * use generic apic_read()/apic_write(), which might be pointing to different
140 * ops in PARAVIRT case.
142 void xapic_wait_icr_idle(void)
144 while (apic_read(APIC_ICR
) & APIC_ICR_BUSY
)
148 u32
safe_xapic_wait_icr_idle(void)
155 send_status
= apic_read(APIC_ICR
) & APIC_ICR_BUSY
;
159 } while (timeout
++ < 1000);
164 void xapic_icr_write(u32 low
, u32 id
)
166 apic_write(APIC_ICR2
, SET_APIC_DEST_FIELD(id
));
167 apic_write(APIC_ICR
, low
);
170 u64
xapic_icr_read(void)
174 icr2
= apic_read(APIC_ICR2
);
175 icr1
= apic_read(APIC_ICR
);
177 return icr1
| ((u64
)icr2
<< 32);
180 static struct apic_ops xapic_ops
= {
181 .read
= native_apic_mem_read
,
182 .write
= native_apic_mem_write
,
183 .icr_read
= xapic_icr_read
,
184 .icr_write
= xapic_icr_write
,
185 .wait_icr_idle
= xapic_wait_icr_idle
,
186 .safe_wait_icr_idle
= safe_xapic_wait_icr_idle
,
189 struct apic_ops __read_mostly
*apic_ops
= &xapic_ops
;
190 EXPORT_SYMBOL_GPL(apic_ops
);
192 static void x2apic_wait_icr_idle(void)
194 /* no need to wait for icr idle in x2apic */
198 static u32
safe_x2apic_wait_icr_idle(void)
200 /* no need to wait for icr idle in x2apic */
204 void x2apic_icr_write(u32 low
, u32 id
)
206 wrmsrl(APIC_BASE_MSR
+ (APIC_ICR
>> 4), ((__u64
) id
) << 32 | low
);
209 u64
x2apic_icr_read(void)
213 rdmsrl(APIC_BASE_MSR
+ (APIC_ICR
>> 4), val
);
217 static struct apic_ops x2apic_ops
= {
218 .read
= native_apic_msr_read
,
219 .write
= native_apic_msr_write
,
220 .icr_read
= x2apic_icr_read
,
221 .icr_write
= x2apic_icr_write
,
222 .wait_icr_idle
= x2apic_wait_icr_idle
,
223 .safe_wait_icr_idle
= safe_x2apic_wait_icr_idle
,
227 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
229 void __cpuinit
enable_NMI_through_LVT0(void)
233 /* unmask and set to NMI */
236 /* Level triggered for 82489DX (32bit mode) */
237 if (!lapic_is_integrated())
238 v
|= APIC_LVT_LEVEL_TRIGGER
;
240 apic_write(APIC_LVT0
, v
);
244 * lapic_get_maxlvt - get the maximum number of local vector table entries
246 int lapic_get_maxlvt(void)
250 v
= apic_read(APIC_LVR
);
252 * - we always have APIC integrated on 64bit mode
253 * - 82489DXs do not report # of LVT entries
255 return APIC_INTEGRATED(GET_APIC_VERSION(v
)) ? GET_APIC_MAXLVT(v
) : 2;
264 #define APIC_DIVISOR 1
266 #define APIC_DIVISOR 16
270 * This function sets up the local APIC timer, with a timeout of
271 * 'clocks' APIC bus clock. During calibration we actually call
272 * this function twice on the boot CPU, once with a bogus timeout
273 * value, second time for real. The other (noncalibrating) CPUs
274 * call this function only once, with the real, calibrated value.
276 * We do reads before writes even if unnecessary, to get around the
277 * P5 APIC double write bug.
279 static void __setup_APIC_LVTT(unsigned int clocks
, int oneshot
, int irqen
)
281 unsigned int lvtt_value
, tmp_value
;
283 lvtt_value
= LOCAL_TIMER_VECTOR
;
285 lvtt_value
|= APIC_LVT_TIMER_PERIODIC
;
286 if (!lapic_is_integrated())
287 lvtt_value
|= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV
);
290 lvtt_value
|= APIC_LVT_MASKED
;
292 apic_write(APIC_LVTT
, lvtt_value
);
297 tmp_value
= apic_read(APIC_TDCR
);
298 apic_write(APIC_TDCR
,
299 (tmp_value
& ~(APIC_TDR_DIV_1
| APIC_TDR_DIV_TMBASE
)) |
303 apic_write(APIC_TMICT
, clocks
/ APIC_DIVISOR
);
307 * Setup extended LVT, AMD specific (K8, family 10h)
309 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
310 * MCE interrupts are supported. Thus MCE offset must be set to 0.
313 #define APIC_EILVT_LVTOFF_MCE 0
314 #define APIC_EILVT_LVTOFF_IBS 1
316 static void setup_APIC_eilvt(u8 lvt_off
, u8 vector
, u8 msg_type
, u8 mask
)
318 unsigned long reg
= (lvt_off
<< 4) + APIC_EILVT0
;
319 unsigned int v
= (mask
<< 16) | (msg_type
<< 8) | vector
;
324 u8
setup_APIC_eilvt_mce(u8 vector
, u8 msg_type
, u8 mask
)
326 setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE
, vector
, msg_type
, mask
);
327 return APIC_EILVT_LVTOFF_MCE
;
330 u8
setup_APIC_eilvt_ibs(u8 vector
, u8 msg_type
, u8 mask
)
332 setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS
, vector
, msg_type
, mask
);
333 return APIC_EILVT_LVTOFF_IBS
;
337 * Program the next event, relative to now
339 static int lapic_next_event(unsigned long delta
,
340 struct clock_event_device
*evt
)
342 apic_write(APIC_TMICT
, delta
);
347 * Setup the lapic timer in periodic or oneshot mode
349 static void lapic_timer_setup(enum clock_event_mode mode
,
350 struct clock_event_device
*evt
)
355 /* Lapic used as dummy for broadcast ? */
356 if (evt
->features
& CLOCK_EVT_FEAT_DUMMY
)
359 local_irq_save(flags
);
362 case CLOCK_EVT_MODE_PERIODIC
:
363 case CLOCK_EVT_MODE_ONESHOT
:
364 __setup_APIC_LVTT(calibration_result
,
365 mode
!= CLOCK_EVT_MODE_PERIODIC
, 1);
367 case CLOCK_EVT_MODE_UNUSED
:
368 case CLOCK_EVT_MODE_SHUTDOWN
:
369 v
= apic_read(APIC_LVTT
);
370 v
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
371 apic_write(APIC_LVTT
, v
);
373 case CLOCK_EVT_MODE_RESUME
:
374 /* Nothing to do here */
378 local_irq_restore(flags
);
382 * Local APIC timer broadcast function
384 static void lapic_timer_broadcast(cpumask_t mask
)
387 send_IPI_mask(mask
, LOCAL_TIMER_VECTOR
);
392 * Setup the local APIC timer for this CPU. Copy the initilized values
393 * of the boot CPU and register the clock event in the framework.
395 static void setup_APIC_timer(void)
397 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
399 memcpy(levt
, &lapic_clockevent
, sizeof(*levt
));
400 levt
->cpumask
= cpumask_of_cpu(smp_processor_id());
402 clockevents_register_device(levt
);
406 * In this function we calibrate APIC bus clocks to the external
407 * timer. Unfortunately we cannot use jiffies and the timer irq
408 * to calibrate, since some later bootup code depends on getting
409 * the first irq? Ugh.
411 * We want to do the calibration only once since we
412 * want to have local timer irqs syncron. CPUs connected
413 * by the same APIC bus have the very same bus frequency.
414 * And we want to have irqs off anyways, no accidental
418 #define TICK_COUNT 100000000
420 static int __init
calibrate_APIC_clock(void)
422 unsigned apic
, apic_start
;
423 unsigned long tsc
, tsc_start
;
429 * Put whatever arbitrary (but long enough) timeout
430 * value into the APIC clock, we just want to get the
431 * counter running for calibration.
433 * No interrupt enable !
435 __setup_APIC_LVTT(250000000, 0, 0);
437 apic_start
= apic_read(APIC_TMCCT
);
438 #ifdef CONFIG_X86_PM_TIMER
439 if (apic_calibrate_pmtmr
&& pmtmr_ioport
) {
440 pmtimer_wait(5000); /* 5ms wait */
441 apic
= apic_read(APIC_TMCCT
);
442 result
= (apic_start
- apic
) * 1000L / 5;
449 apic
= apic_read(APIC_TMCCT
);
451 } while ((tsc
- tsc_start
) < TICK_COUNT
&&
452 (apic_start
- apic
) < TICK_COUNT
);
454 result
= (apic_start
- apic
) * 1000L * tsc_khz
/
460 printk(KERN_DEBUG
"APIC timer calibration result %d\n", result
);
462 printk(KERN_INFO
"Detected %d.%03d MHz APIC timer.\n",
463 result
/ 1000 / 1000, result
/ 1000 % 1000);
465 /* Calculate the scaled math multiplication factor */
466 lapic_clockevent
.mult
= div_sc(result
, NSEC_PER_SEC
,
467 lapic_clockevent
.shift
);
468 lapic_clockevent
.max_delta_ns
=
469 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent
);
470 lapic_clockevent
.min_delta_ns
=
471 clockevent_delta2ns(0xF, &lapic_clockevent
);
473 calibration_result
= (result
* APIC_DIVISOR
) / HZ
;
476 * Do a sanity check on the APIC calibration result
478 if (calibration_result
< (1000000 / HZ
)) {
480 "APIC frequency too slow, disabling apic timer\n");
488 * Setup the boot APIC
490 * Calibrate and verify the result.
492 void __init
setup_boot_APIC_clock(void)
495 * The local apic timer can be disabled via the kernel
496 * commandline or from the CPU detection code. Register the lapic
497 * timer as a dummy clock event source on SMP systems, so the
498 * broadcast mechanism is used. On UP systems simply ignore it.
500 if (disable_apic_timer
) {
501 printk(KERN_INFO
"Disabling APIC timer\n");
502 /* No broadcast on UP ! */
503 if (num_possible_cpus() > 1) {
504 lapic_clockevent
.mult
= 1;
510 apic_printk(APIC_VERBOSE
, "Using local APIC timer interrupts.\n"
511 "calibrating APIC timer ...\n");
513 if (calibrate_APIC_clock()) {
514 /* No broadcast on UP ! */
515 if (num_possible_cpus() > 1)
521 * If nmi_watchdog is set to IO_APIC, we need the
522 * PIT/HPET going. Otherwise register lapic as a dummy
525 if (nmi_watchdog
!= NMI_IO_APIC
)
526 lapic_clockevent
.features
&= ~CLOCK_EVT_FEAT_DUMMY
;
528 printk(KERN_WARNING
"APIC timer registered as dummy,"
529 " due to nmi_watchdog=%d!\n", nmi_watchdog
);
531 /* Setup the lapic or request the broadcast */
535 void __cpuinit
setup_secondary_APIC_clock(void)
541 * The guts of the apic timer interrupt
543 static void local_apic_timer_interrupt(void)
545 int cpu
= smp_processor_id();
546 struct clock_event_device
*evt
= &per_cpu(lapic_events
, cpu
);
549 * Normally we should not be here till LAPIC has been initialized but
550 * in some cases like kdump, its possible that there is a pending LAPIC
551 * timer interrupt from previous kernel's context and is delivered in
552 * new kernel the moment interrupts are enabled.
554 * Interrupts are enabled early and LAPIC is setup much later, hence
555 * its possible that when we get here evt->event_handler is NULL.
556 * Check for event_handler being NULL and discard the interrupt as
559 if (!evt
->event_handler
) {
561 "Spurious LAPIC timer interrupt on cpu %d\n", cpu
);
563 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, evt
);
568 * the NMI deadlock-detector uses this.
570 add_pda(apic_timer_irqs
, 1);
572 evt
->event_handler(evt
);
576 * Local APIC timer interrupt. This is the most natural way for doing
577 * local interrupts, but local timer interrupts can be emulated by
578 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
580 * [ if a single-CPU system runs an SMP kernel then we call the local
581 * interrupt as well. Thus we cannot inline the local irq ... ]
583 void smp_apic_timer_interrupt(struct pt_regs
*regs
)
585 struct pt_regs
*old_regs
= set_irq_regs(regs
);
588 * NOTE! We'd better ACK the irq immediately,
589 * because timer handling can be slow.
593 * update_process_times() expects us to have done irq_enter().
594 * Besides, if we don't timer interrupts ignore the global
595 * interrupt lock, which is the WrongThing (tm) to do.
599 local_apic_timer_interrupt();
602 set_irq_regs(old_regs
);
605 int setup_profiling_timer(unsigned int multiplier
)
612 * Local APIC start and shutdown
616 * clear_local_APIC - shutdown the local APIC
618 * This is called, when a CPU is disabled and before rebooting, so the state of
619 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
620 * leftovers during boot.
622 void clear_local_APIC(void)
627 /* APIC hasn't been mapped yet */
631 maxlvt
= lapic_get_maxlvt();
633 * Masking an LVT entry can trigger a local APIC error
634 * if the vector is zero. Mask LVTERR first to prevent this.
637 v
= ERROR_APIC_VECTOR
; /* any non-zero vector will do */
638 apic_write(APIC_LVTERR
, v
| APIC_LVT_MASKED
);
641 * Careful: we have to set masks only first to deassert
642 * any level-triggered sources.
644 v
= apic_read(APIC_LVTT
);
645 apic_write(APIC_LVTT
, v
| APIC_LVT_MASKED
);
646 v
= apic_read(APIC_LVT0
);
647 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
648 v
= apic_read(APIC_LVT1
);
649 apic_write(APIC_LVT1
, v
| APIC_LVT_MASKED
);
651 v
= apic_read(APIC_LVTPC
);
652 apic_write(APIC_LVTPC
, v
| APIC_LVT_MASKED
);
655 /* lets not touch this if we didn't frob it */
656 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(X86_MCE_INTEL)
658 v
= apic_read(APIC_LVTTHMR
);
659 apic_write(APIC_LVTTHMR
, v
| APIC_LVT_MASKED
);
663 * Clean APIC state for other OSs:
665 apic_write(APIC_LVTT
, APIC_LVT_MASKED
);
666 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
667 apic_write(APIC_LVT1
, APIC_LVT_MASKED
);
669 apic_write(APIC_LVTERR
, APIC_LVT_MASKED
);
671 apic_write(APIC_LVTPC
, APIC_LVT_MASKED
);
673 /* Integrated APIC (!82489DX) ? */
674 if (lapic_is_integrated()) {
676 /* Clear ESR due to Pentium errata 3AP and 11AP */
677 apic_write(APIC_ESR
, 0);
683 * disable_local_APIC - clear and disable the local APIC
685 void disable_local_APIC(void)
692 * Disable APIC (implies clearing of registers
695 value
= apic_read(APIC_SPIV
);
696 value
&= ~APIC_SPIV_APIC_ENABLED
;
697 apic_write(APIC_SPIV
, value
);
701 * When LAPIC was disabled by the BIOS and enabled by the kernel,
702 * restore the disabled state.
704 if (enabled_via_apicbase
) {
707 rdmsr(MSR_IA32_APICBASE
, l
, h
);
708 l
&= ~MSR_IA32_APICBASE_ENABLE
;
709 wrmsr(MSR_IA32_APICBASE
, l
, h
);
715 * If Linux enabled the LAPIC against the BIOS default disable it down before
716 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
717 * not power-off. Additionally clear all LVT entries before disable_local_APIC
718 * for the case where Linux didn't enable the LAPIC.
720 void lapic_shutdown(void)
727 local_irq_save(flags
);
730 if (!enabled_via_apicbase
)
734 disable_local_APIC();
737 local_irq_restore(flags
);
741 * This is to verify that we're looking at a real local APIC.
742 * Check these against your board if the CPUs aren't getting
743 * started for no apparent reason.
745 int __init
verify_local_APIC(void)
747 unsigned int reg0
, reg1
;
750 * The version register is read-only in a real APIC.
752 reg0
= apic_read(APIC_LVR
);
753 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg0
);
754 apic_write(APIC_LVR
, reg0
^ APIC_LVR_MASK
);
755 reg1
= apic_read(APIC_LVR
);
756 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg1
);
759 * The two version reads above should print the same
760 * numbers. If the second one is different, then we
761 * poke at a non-APIC.
767 * Check if the version looks reasonably.
769 reg1
= GET_APIC_VERSION(reg0
);
770 if (reg1
== 0x00 || reg1
== 0xff)
772 reg1
= lapic_get_maxlvt();
773 if (reg1
< 0x02 || reg1
== 0xff)
777 * The ID register is read/write in a real APIC.
779 reg0
= apic_read(APIC_ID
);
780 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg0
);
781 apic_write(APIC_ID
, reg0
^ APIC_ID_MASK
);
782 reg1
= apic_read(APIC_ID
);
783 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg1
);
784 apic_write(APIC_ID
, reg0
);
785 if (reg1
!= (reg0
^ APIC_ID_MASK
))
789 * The next two are just to see if we have sane values.
790 * They're only really relevant if we're in Virtual Wire
791 * compatibility mode, but most boxes are anymore.
793 reg0
= apic_read(APIC_LVT0
);
794 apic_printk(APIC_DEBUG
, "Getting LVT0: %x\n", reg0
);
795 reg1
= apic_read(APIC_LVT1
);
796 apic_printk(APIC_DEBUG
, "Getting LVT1: %x\n", reg1
);
802 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
804 void __init
sync_Arb_IDs(void)
807 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
810 if (modern_apic() || boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
)
816 apic_wait_icr_idle();
818 apic_printk(APIC_DEBUG
, "Synchronizing Arb IDs.\n");
819 apic_write(APIC_ICR
, APIC_DEST_ALLINC
|
820 APIC_INT_LEVELTRIG
| APIC_DM_INIT
);
824 * An initial setup of the virtual wire mode.
826 void __init
init_bsp_APIC(void)
831 * Don't do the setup now if we have a SMP BIOS as the
832 * through-I/O-APIC virtual wire mode might be active.
834 if (smp_found_config
|| !cpu_has_apic
)
838 * Do not trust the local APIC being empty at bootup.
845 value
= apic_read(APIC_SPIV
);
846 value
&= ~APIC_VECTOR_MASK
;
847 value
|= APIC_SPIV_APIC_ENABLED
;
850 /* This bit is reserved on P4/Xeon and should be cleared */
851 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
) &&
852 (boot_cpu_data
.x86
== 15))
853 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
856 value
|= APIC_SPIV_FOCUS_DISABLED
;
857 value
|= SPURIOUS_APIC_VECTOR
;
858 apic_write(APIC_SPIV
, value
);
861 * Set up the virtual wire mode.
863 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
865 if (!lapic_is_integrated()) /* 82489DX */
866 value
|= APIC_LVT_LEVEL_TRIGGER
;
867 apic_write(APIC_LVT1
, value
);
870 static void __cpuinit
lapic_setup_esr(void)
872 unsigned long oldvalue
, value
, maxlvt
;
873 if (lapic_is_integrated() && !esr_disable
) {
876 * Something untraceable is creating bad interrupts on
877 * secondary quads ... for the moment, just leave the
878 * ESR disabled - we can't do anything useful with the
879 * errors anyway - mbligh
881 printk(KERN_INFO
"Leaving ESR disabled.\n");
885 maxlvt
= lapic_get_maxlvt();
886 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
887 apic_write(APIC_ESR
, 0);
888 oldvalue
= apic_read(APIC_ESR
);
890 /* enables sending errors */
891 value
= ERROR_APIC_VECTOR
;
892 apic_write(APIC_LVTERR
, value
);
894 * spec says clear errors after enabling vector.
897 apic_write(APIC_ESR
, 0);
898 value
= apic_read(APIC_ESR
);
899 if (value
!= oldvalue
)
900 apic_printk(APIC_VERBOSE
, "ESR value before enabling "
901 "vector: 0x%08lx after: 0x%08lx\n",
904 printk(KERN_INFO
"No ESR for 82489DX.\n");
910 * setup_local_APIC - setup the local APIC
912 void __cpuinit
setup_local_APIC(void)
918 value
= apic_read(APIC_LVR
);
920 BUILD_BUG_ON((SPURIOUS_APIC_VECTOR
& 0x0f) != 0x0f);
923 * Double-check whether this APIC is really registered.
924 * This is meaningless in clustered apic mode, so we skip it.
926 if (!apic_id_registered())
930 * Intel recommends to set DFR, LDR and TPR before enabling
931 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
932 * document number 292116). So here it goes...
937 * Set Task Priority to 'accept all'. We never change this
940 value
= apic_read(APIC_TASKPRI
);
941 value
&= ~APIC_TPRI_MASK
;
942 apic_write(APIC_TASKPRI
, value
);
945 * After a crash, we no longer service the interrupts and a pending
946 * interrupt from previous kernel might still have ISR bit set.
948 * Most probably by now CPU has serviced that pending interrupt and
949 * it might not have done the ack_APIC_irq() because it thought,
950 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
951 * does not clear the ISR bit and cpu thinks it has already serivced
952 * the interrupt. Hence a vector might get locked. It was noticed
953 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
955 for (i
= APIC_ISR_NR
- 1; i
>= 0; i
--) {
956 value
= apic_read(APIC_ISR
+ i
*0x10);
957 for (j
= 31; j
>= 0; j
--) {
964 * Now that we are all set up, enable the APIC
966 value
= apic_read(APIC_SPIV
);
967 value
&= ~APIC_VECTOR_MASK
;
971 value
|= APIC_SPIV_APIC_ENABLED
;
973 /* We always use processor focus */
976 * Set spurious IRQ vector
978 value
|= SPURIOUS_APIC_VECTOR
;
979 apic_write(APIC_SPIV
, value
);
984 * set up through-local-APIC on the BP's LINT0. This is not
985 * strictly necessary in pure symmetric-IO mode, but sometimes
986 * we delegate interrupts to the 8259A.
989 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
991 value
= apic_read(APIC_LVT0
) & APIC_LVT_MASKED
;
992 if (!smp_processor_id() && !value
) {
993 value
= APIC_DM_EXTINT
;
994 apic_printk(APIC_VERBOSE
, "enabled ExtINT on CPU#%d\n",
997 value
= APIC_DM_EXTINT
| APIC_LVT_MASKED
;
998 apic_printk(APIC_VERBOSE
, "masked ExtINT on CPU#%d\n",
1001 apic_write(APIC_LVT0
, value
);
1004 * only the BP should see the LINT1 NMI signal, obviously.
1006 if (!smp_processor_id())
1007 value
= APIC_DM_NMI
;
1009 value
= APIC_DM_NMI
| APIC_LVT_MASKED
;
1010 apic_write(APIC_LVT1
, value
);
1014 void __cpuinit
end_local_APIC_setup(void)
1017 setup_apic_nmi_watchdog(NULL
);
1021 void check_x2apic(void)
1025 rdmsr(MSR_IA32_APICBASE
, msr
, msr2
);
1027 if (msr
& X2APIC_ENABLE
) {
1028 printk("x2apic enabled by BIOS, switching to x2apic ops\n");
1029 x2apic_preenabled
= x2apic
= 1;
1030 apic_ops
= &x2apic_ops
;
1034 void enable_x2apic(void)
1038 rdmsr(MSR_IA32_APICBASE
, msr
, msr2
);
1039 if (!(msr
& X2APIC_ENABLE
)) {
1040 printk("Enabling x2apic\n");
1041 wrmsr(MSR_IA32_APICBASE
, msr
| X2APIC_ENABLE
, 0);
1045 void enable_IR_x2apic(void)
1047 #ifdef CONFIG_INTR_REMAP
1049 unsigned long flags
;
1051 if (!cpu_has_x2apic
)
1054 if (!x2apic_preenabled
&& disable_x2apic
) {
1056 "Skipped enabling x2apic and Interrupt-remapping "
1057 "because of nox2apic\n");
1061 if (x2apic_preenabled
&& disable_x2apic
)
1062 panic("Bios already enabled x2apic, can't enforce nox2apic");
1064 if (!x2apic_preenabled
&& skip_ioapic_setup
) {
1066 "Skipped enabling x2apic and Interrupt-remapping "
1067 "because of skipping io-apic setup\n");
1071 ret
= dmar_table_init();
1074 "dmar_table_init() failed with %d:\n", ret
);
1076 if (x2apic_preenabled
)
1077 panic("x2apic enabled by bios. But IR enabling failed");
1080 "Not enabling x2apic,Intr-remapping\n");
1084 local_irq_save(flags
);
1086 save_mask_IO_APIC_setup();
1088 ret
= enable_intr_remapping(1);
1090 if (ret
&& x2apic_preenabled
) {
1091 local_irq_restore(flags
);
1092 panic("x2apic enabled by bios. But IR enabling failed");
1100 apic_ops
= &x2apic_ops
;
1106 * IR enabling failed
1108 restore_IO_APIC_setup();
1110 reinit_intr_remapped_IO_APIC(x2apic_preenabled
);
1113 local_irq_restore(flags
);
1116 if (!x2apic_preenabled
)
1118 "Enabled x2apic and interrupt-remapping\n");
1121 "Enabled Interrupt-remapping\n");
1124 "Failed to enable Interrupt-remapping and x2apic\n");
1126 if (!cpu_has_x2apic
)
1129 if (x2apic_preenabled
)
1130 panic("x2apic enabled prior OS handover,"
1131 " enable CONFIG_INTR_REMAP");
1133 printk(KERN_INFO
"Enable CONFIG_INTR_REMAP for enabling intr-remapping "
1141 * Detect and enable local APICs on non-SMP boards.
1142 * Original code written by Keir Fraser.
1143 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1144 * not correctly set up (usually the APIC timer won't work etc.)
1146 static int __init
detect_init_APIC(void)
1148 if (!cpu_has_apic
) {
1149 printk(KERN_INFO
"No local APIC present\n");
1153 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
1154 boot_cpu_physical_apicid
= 0;
1158 void __init
early_init_lapic_mapping(void)
1160 unsigned long phys_addr
;
1163 * If no local APIC can be found then go out
1164 * : it means there is no mpatable and MADT
1166 if (!smp_found_config
)
1169 phys_addr
= mp_lapic_addr
;
1171 set_fixmap_nocache(FIX_APIC_BASE
, phys_addr
);
1172 apic_printk(APIC_VERBOSE
, "mapped APIC to %16lx (%16lx)\n",
1173 APIC_BASE
, phys_addr
);
1176 * Fetch the APIC ID of the BSP in case we have a
1177 * default configuration (or the MP table is broken).
1179 boot_cpu_physical_apicid
= read_apic_id();
1183 * init_apic_mappings - initialize APIC mappings
1185 void __init
init_apic_mappings(void)
1188 boot_cpu_physical_apicid
= read_apic_id();
1193 * If no local APIC can be found then set up a fake all
1194 * zeroes page to simulate the local APIC and another
1195 * one for the IO-APIC.
1197 if (!smp_found_config
&& detect_init_APIC()) {
1198 apic_phys
= (unsigned long) alloc_bootmem_pages(PAGE_SIZE
);
1199 apic_phys
= __pa(apic_phys
);
1201 apic_phys
= mp_lapic_addr
;
1203 set_fixmap_nocache(FIX_APIC_BASE
, apic_phys
);
1204 apic_printk(APIC_VERBOSE
, "mapped APIC to %16lx (%16lx)\n",
1205 APIC_BASE
, apic_phys
);
1208 * Fetch the APIC ID of the BSP in case we have a
1209 * default configuration (or the MP table is broken).
1211 boot_cpu_physical_apicid
= read_apic_id();
1215 * This initializes the IO-APIC and APIC hardware if this is
1218 int apic_version
[MAX_APICS
];
1220 int __init
APIC_init_uniprocessor(void)
1223 printk(KERN_INFO
"Apic disabled\n");
1226 if (!cpu_has_apic
) {
1228 printk(KERN_INFO
"Apic disabled by BIOS\n");
1233 setup_apic_routing();
1235 verify_local_APIC();
1239 physid_set_mask_of_physid(boot_cpu_physical_apicid
, &phys_cpu_present_map
);
1240 apic_write(APIC_ID
, SET_APIC_ID(boot_cpu_physical_apicid
));
1245 * Now enable IO-APICs, actually call clear_IO_APIC
1246 * We need clear_IO_APIC before enabling vector on BP
1248 if (!skip_ioapic_setup
&& nr_ioapics
)
1251 if (!smp_found_config
|| skip_ioapic_setup
|| !nr_ioapics
)
1252 localise_nmi_watchdog();
1253 end_local_APIC_setup();
1255 if (smp_found_config
&& !skip_ioapic_setup
&& nr_ioapics
)
1259 setup_boot_APIC_clock();
1260 check_nmi_watchdog();
1265 * Local APIC interrupts
1269 * This interrupt should _never_ happen with our APIC/SMP architecture
1271 asmlinkage
void smp_spurious_interrupt(void)
1277 * Check if this really is a spurious interrupt and ACK it
1278 * if it is a vectored one. Just in case...
1279 * Spurious interrupts should not be ACKed.
1281 v
= apic_read(APIC_ISR
+ ((SPURIOUS_APIC_VECTOR
& ~0x1f) >> 1));
1282 if (v
& (1 << (SPURIOUS_APIC_VECTOR
& 0x1f)))
1285 add_pda(irq_spurious_count
, 1);
1290 * This interrupt should never happen with our APIC/SMP architecture
1292 asmlinkage
void smp_error_interrupt(void)
1298 /* First tickle the hardware, only then report what went on. -- REW */
1299 v
= apic_read(APIC_ESR
);
1300 apic_write(APIC_ESR
, 0);
1301 v1
= apic_read(APIC_ESR
);
1303 atomic_inc(&irq_err_count
);
1305 /* Here is what the APIC error bits mean:
1308 2: Send accept error
1309 3: Receive accept error
1311 5: Send illegal vector
1312 6: Received illegal vector
1313 7: Illegal register address
1315 printk(KERN_DEBUG
"APIC error on CPU%d: %02x(%02x)\n",
1316 smp_processor_id(), v
, v1
);
1321 * connect_bsp_APIC - attach the APIC to the interrupt system
1323 void __init
connect_bsp_APIC(void)
1325 #ifdef CONFIG_X86_32
1328 * Do not trust the local APIC being empty at bootup.
1332 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
1333 * local APIC to INT and NMI lines.
1335 apic_printk(APIC_VERBOSE
, "leaving PIC mode, "
1336 "enabling APIC mode.\n");
1345 * disconnect_bsp_APIC - detach the APIC from the interrupt system
1346 * @virt_wire_setup: indicates, whether virtual wire mode is selected
1348 * Virtual wire mode is necessary to deliver legacy interrupts even when the
1351 void disconnect_bsp_APIC(int virt_wire_setup
)
1353 #ifdef CONFIG_X86_32
1356 * Put the board back into PIC mode (has an effect only on
1357 * certain older boards). Note that APIC interrupts, including
1358 * IPIs, won't work beyond this point! The only exception are
1361 apic_printk(APIC_VERBOSE
, "disabling APIC mode, "
1362 "entering PIC mode.\n");
1369 /* Go back to Virtual Wire compatibility mode */
1372 /* For the spurious interrupt use vector F, and enable it */
1373 value
= apic_read(APIC_SPIV
);
1374 value
&= ~APIC_VECTOR_MASK
;
1375 value
|= APIC_SPIV_APIC_ENABLED
;
1377 apic_write(APIC_SPIV
, value
);
1379 if (!virt_wire_setup
) {
1381 * For LVT0 make it edge triggered, active high,
1382 * external and enabled
1384 value
= apic_read(APIC_LVT0
);
1385 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1386 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1387 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1388 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1389 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_EXTINT
);
1390 apic_write(APIC_LVT0
, value
);
1393 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
1397 * For LVT1 make it edge triggered, active high,
1400 value
= apic_read(APIC_LVT1
);
1401 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1402 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1403 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1404 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1405 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_NMI
);
1406 apic_write(APIC_LVT1
, value
);
1409 void __cpuinit
generic_processor_info(int apicid
, int version
)
1417 if (version
== 0x0) {
1418 printk(KERN_WARNING
"BIOS bug, APIC version is 0 for CPU#%d! "
1419 "fixing up to 0x10. (tell your hw vendor)\n",
1423 apic_version
[apicid
] = version
;
1425 if (num_processors
>= NR_CPUS
) {
1426 printk(KERN_WARNING
"WARNING: NR_CPUS limit of %i reached."
1427 " Processor ignored.\n", NR_CPUS
);
1431 if (num_processors
>= maxcpus
) {
1432 printk(KERN_WARNING
"WARNING: maxcpus limit of %i reached."
1433 " Processor ignored.\n", maxcpus
);
1438 cpus_complement(tmp_map
, cpu_present_map
);
1439 cpu
= first_cpu(tmp_map
);
1441 physid_set(apicid
, phys_cpu_present_map
);
1442 if (apicid
== boot_cpu_physical_apicid
) {
1444 * x86_bios_cpu_apicid is required to have processors listed
1445 * in same order as logical cpu numbers. Hence the first
1446 * entry is BSP, and so on.
1450 if (apicid
> max_physical_apicid
)
1451 max_physical_apicid
= apicid
;
1453 #ifdef CONFIG_X86_32
1455 * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y
1456 * but we need to work other dependencies like SMP_SUSPEND etc
1457 * before this can be done without some confusion.
1458 * if (CPU_HOTPLUG_ENABLED || num_processors > 8)
1459 * - Ashok Raj <ashok.raj@intel.com>
1461 if (max_physical_apicid
>= 8) {
1462 switch (boot_cpu_data
.x86_vendor
) {
1463 case X86_VENDOR_INTEL
:
1464 if (!APIC_XAPIC(version
)) {
1468 /* If P4 and above fall through */
1469 case X86_VENDOR_AMD
:
1475 #if defined(CONFIG_X86_SMP) || defined(CONFIG_X86_64)
1476 /* are we being called early in kernel startup? */
1477 if (early_per_cpu_ptr(x86_cpu_to_apicid
)) {
1478 u16
*cpu_to_apicid
= early_per_cpu_ptr(x86_cpu_to_apicid
);
1479 u16
*bios_cpu_apicid
= early_per_cpu_ptr(x86_bios_cpu_apicid
);
1481 cpu_to_apicid
[cpu
] = apicid
;
1482 bios_cpu_apicid
[cpu
] = apicid
;
1484 per_cpu(x86_cpu_to_apicid
, cpu
) = apicid
;
1485 per_cpu(x86_bios_cpu_apicid
, cpu
) = apicid
;
1489 cpu_set(cpu
, cpu_possible_map
);
1490 cpu_set(cpu
, cpu_present_map
);
1493 int hard_smp_processor_id(void)
1495 return read_apic_id();
1505 * 'active' is true if the local APIC was enabled by us and
1506 * not the BIOS; this signifies that we are also responsible
1507 * for disabling it before entering apm/acpi suspend
1510 /* r/w apic fields */
1511 unsigned int apic_id
;
1512 unsigned int apic_taskpri
;
1513 unsigned int apic_ldr
;
1514 unsigned int apic_dfr
;
1515 unsigned int apic_spiv
;
1516 unsigned int apic_lvtt
;
1517 unsigned int apic_lvtpc
;
1518 unsigned int apic_lvt0
;
1519 unsigned int apic_lvt1
;
1520 unsigned int apic_lvterr
;
1521 unsigned int apic_tmict
;
1522 unsigned int apic_tdcr
;
1523 unsigned int apic_thmr
;
1526 static int lapic_suspend(struct sys_device
*dev
, pm_message_t state
)
1528 unsigned long flags
;
1531 if (!apic_pm_state
.active
)
1534 maxlvt
= lapic_get_maxlvt();
1536 apic_pm_state
.apic_id
= apic_read(APIC_ID
);
1537 apic_pm_state
.apic_taskpri
= apic_read(APIC_TASKPRI
);
1538 apic_pm_state
.apic_ldr
= apic_read(APIC_LDR
);
1539 apic_pm_state
.apic_dfr
= apic_read(APIC_DFR
);
1540 apic_pm_state
.apic_spiv
= apic_read(APIC_SPIV
);
1541 apic_pm_state
.apic_lvtt
= apic_read(APIC_LVTT
);
1543 apic_pm_state
.apic_lvtpc
= apic_read(APIC_LVTPC
);
1544 apic_pm_state
.apic_lvt0
= apic_read(APIC_LVT0
);
1545 apic_pm_state
.apic_lvt1
= apic_read(APIC_LVT1
);
1546 apic_pm_state
.apic_lvterr
= apic_read(APIC_LVTERR
);
1547 apic_pm_state
.apic_tmict
= apic_read(APIC_TMICT
);
1548 apic_pm_state
.apic_tdcr
= apic_read(APIC_TDCR
);
1549 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
1551 apic_pm_state
.apic_thmr
= apic_read(APIC_LVTTHMR
);
1554 local_irq_save(flags
);
1555 disable_local_APIC();
1556 local_irq_restore(flags
);
1560 static int lapic_resume(struct sys_device
*dev
)
1563 unsigned long flags
;
1566 if (!apic_pm_state
.active
)
1569 maxlvt
= lapic_get_maxlvt();
1571 local_irq_save(flags
);
1573 #ifdef CONFIG_X86_64
1580 * Make sure the APICBASE points to the right address
1582 * FIXME! This will be wrong if we ever support suspend on
1583 * SMP! We'll need to do this as part of the CPU restore!
1585 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1586 l
&= ~MSR_IA32_APICBASE_BASE
;
1587 l
|= MSR_IA32_APICBASE_ENABLE
| mp_lapic_addr
;
1588 wrmsr(MSR_IA32_APICBASE
, l
, h
);
1591 apic_write(APIC_LVTERR
, ERROR_APIC_VECTOR
| APIC_LVT_MASKED
);
1592 apic_write(APIC_ID
, apic_pm_state
.apic_id
);
1593 apic_write(APIC_DFR
, apic_pm_state
.apic_dfr
);
1594 apic_write(APIC_LDR
, apic_pm_state
.apic_ldr
);
1595 apic_write(APIC_TASKPRI
, apic_pm_state
.apic_taskpri
);
1596 apic_write(APIC_SPIV
, apic_pm_state
.apic_spiv
);
1597 apic_write(APIC_LVT0
, apic_pm_state
.apic_lvt0
);
1598 apic_write(APIC_LVT1
, apic_pm_state
.apic_lvt1
);
1599 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
1601 apic_write(APIC_LVTTHMR
, apic_pm_state
.apic_thmr
);
1604 apic_write(APIC_LVTPC
, apic_pm_state
.apic_lvtpc
);
1605 apic_write(APIC_LVTT
, apic_pm_state
.apic_lvtt
);
1606 apic_write(APIC_TDCR
, apic_pm_state
.apic_tdcr
);
1607 apic_write(APIC_TMICT
, apic_pm_state
.apic_tmict
);
1608 apic_write(APIC_ESR
, 0);
1609 apic_read(APIC_ESR
);
1610 apic_write(APIC_LVTERR
, apic_pm_state
.apic_lvterr
);
1611 apic_write(APIC_ESR
, 0);
1612 apic_read(APIC_ESR
);
1614 local_irq_restore(flags
);
1620 * This device has no shutdown method - fully functioning local APICs
1621 * are needed on every CPU up until machine_halt/restart/poweroff.
1624 static struct sysdev_class lapic_sysclass
= {
1626 .resume
= lapic_resume
,
1627 .suspend
= lapic_suspend
,
1630 static struct sys_device device_lapic
= {
1632 .cls
= &lapic_sysclass
,
1635 static void __cpuinit
apic_pm_activate(void)
1637 apic_pm_state
.active
= 1;
1640 static int __init
init_lapic_sysfs(void)
1646 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
1648 error
= sysdev_class_register(&lapic_sysclass
);
1650 error
= sysdev_register(&device_lapic
);
1653 device_initcall(init_lapic_sysfs
);
1655 #else /* CONFIG_PM */
1657 static void apic_pm_activate(void) { }
1659 #endif /* CONFIG_PM */
1662 * apic_is_clustered_box() -- Check if we can expect good TSC
1664 * Thus far, the major user of this is IBM's Summit2 series:
1666 * Clustered boxes may have unsynced TSC problems if they are
1667 * multi-chassis. Use available data to take a good guess.
1668 * If in doubt, go HPET.
1670 __cpuinit
int apic_is_clustered_box(void)
1672 int i
, clusters
, zeros
;
1674 u16
*bios_cpu_apicid
;
1675 DECLARE_BITMAP(clustermap
, NUM_APIC_CLUSTERS
);
1678 * there is not this kind of box with AMD CPU yet.
1679 * Some AMD box with quadcore cpu and 8 sockets apicid
1680 * will be [4, 0x23] or [8, 0x27] could be thought to
1681 * vsmp box still need checking...
1683 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
) && !is_vsmp_box())
1686 bios_cpu_apicid
= early_per_cpu_ptr(x86_bios_cpu_apicid
);
1687 bitmap_zero(clustermap
, NUM_APIC_CLUSTERS
);
1689 for (i
= 0; i
< NR_CPUS
; i
++) {
1690 /* are we being called early in kernel startup? */
1691 if (bios_cpu_apicid
) {
1692 id
= bios_cpu_apicid
[i
];
1694 else if (i
< nr_cpu_ids
) {
1696 id
= per_cpu(x86_bios_cpu_apicid
, i
);
1703 if (id
!= BAD_APICID
)
1704 __set_bit(APIC_CLUSTERID(id
), clustermap
);
1707 /* Problem: Partially populated chassis may not have CPUs in some of
1708 * the APIC clusters they have been allocated. Only present CPUs have
1709 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap.
1710 * Since clusters are allocated sequentially, count zeros only if
1711 * they are bounded by ones.
1715 for (i
= 0; i
< NUM_APIC_CLUSTERS
; i
++) {
1716 if (test_bit(i
, clustermap
)) {
1717 clusters
+= 1 + zeros
;
1723 /* ScaleMP vSMPowered boxes have one cluster per board and TSCs are
1724 * not guaranteed to be synced between boards
1726 if (is_vsmp_box() && clusters
> 1)
1730 * If clusters > 2, then should be multi-chassis.
1731 * May have to revisit this when multi-core + hyperthreaded CPUs come
1732 * out, but AFAIK this will work even for them.
1734 return (clusters
> 2);
1737 static __init
int setup_nox2apic(char *str
)
1740 clear_cpu_cap(&boot_cpu_data
, X86_FEATURE_X2APIC
);
1743 early_param("nox2apic", setup_nox2apic
);
1747 * APIC command line parameters
1749 static int __init
apic_set_verbosity(char *str
)
1752 skip_ioapic_setup
= 0;
1756 if (strcmp("debug", str
) == 0)
1757 apic_verbosity
= APIC_DEBUG
;
1758 else if (strcmp("verbose", str
) == 0)
1759 apic_verbosity
= APIC_VERBOSE
;
1761 printk(KERN_WARNING
"APIC Verbosity level %s not recognised"
1762 " use apic=verbose or apic=debug\n", str
);
1768 early_param("apic", apic_set_verbosity
);
1770 static __init
int setup_disableapic(char *str
)
1773 setup_clear_cpu_cap(X86_FEATURE_APIC
);
1776 early_param("disableapic", setup_disableapic
);
1778 /* same as disableapic, for compatibility */
1779 static __init
int setup_nolapic(char *str
)
1781 return setup_disableapic(str
);
1783 early_param("nolapic", setup_nolapic
);
1785 static int __init
parse_lapic_timer_c2_ok(char *arg
)
1787 local_apic_timer_c2_ok
= 1;
1790 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok
);
1792 static int __init
parse_disable_apic_timer(char *arg
)
1794 disable_apic_timer
= 1;
1797 early_param("noapictimer", parse_disable_apic_timer
);
1799 static int __init
parse_nolapic_timer(char *arg
)
1801 disable_apic_timer
= 1;
1804 early_param("nolapic_timer", parse_nolapic_timer
);
1806 static __init
int setup_apicpmtimer(char *s
)
1808 apic_calibrate_pmtmr
= 1;
1812 __setup("apicpmtimer", setup_apicpmtimer
);
1814 static int __init
lapic_insert_resource(void)
1819 /* Put local APIC into the resource map. */
1820 lapic_resource
.start
= apic_phys
;
1821 lapic_resource
.end
= lapic_resource
.start
+ PAGE_SIZE
- 1;
1822 insert_resource(&iomem_resource
, &lapic_resource
);
1828 * need call insert after e820_reserve_resources()
1829 * that is using request_resource
1831 late_initcall(lapic_insert_resource
);