2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/bootmem.h>
22 #include <linux/interrupt.h>
23 #include <linux/mc146818rtc.h>
24 #include <linux/kernel_stat.h>
25 #include <linux/sysdev.h>
26 #include <linux/ioport.h>
27 #include <linux/clockchips.h>
28 #include <linux/acpi_pmtmr.h>
29 #include <linux/module.h>
30 #include <linux/dmar.h>
32 #include <asm/atomic.h>
35 #include <asm/mpspec.h>
37 #include <asm/pgalloc.h>
40 #include <asm/proto.h>
41 #include <asm/timex.h>
43 #include <asm/i8259.h>
46 #include <mach_apic.h>
48 static int disable_apic_timer __cpuinitdata
;
49 static int apic_calibrate_pmtmr __initdata
;
54 /* x2apic enabled before OS handover */
55 int x2apic_preenabled
;
57 /* Local APIC timer works in C2 */
58 int local_apic_timer_c2_ok
;
59 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok
);
62 * Debug level, exported for io_apic.c
64 unsigned int apic_verbosity
;
66 /* Have we found an MP table */
69 static struct resource lapic_resource
= {
71 .flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
,
74 static unsigned int calibration_result
;
76 static int lapic_next_event(unsigned long delta
,
77 struct clock_event_device
*evt
);
78 static void lapic_timer_setup(enum clock_event_mode mode
,
79 struct clock_event_device
*evt
);
80 static void lapic_timer_broadcast(cpumask_t mask
);
81 static void apic_pm_activate(void);
83 static struct clock_event_device lapic_clockevent
= {
85 .features
= CLOCK_EVT_FEAT_PERIODIC
| CLOCK_EVT_FEAT_ONESHOT
86 | CLOCK_EVT_FEAT_C3STOP
| CLOCK_EVT_FEAT_DUMMY
,
88 .set_mode
= lapic_timer_setup
,
89 .set_next_event
= lapic_next_event
,
90 .broadcast
= lapic_timer_broadcast
,
94 static DEFINE_PER_CPU(struct clock_event_device
, lapic_events
);
96 static unsigned long apic_phys
;
98 unsigned long mp_lapic_addr
;
101 * Get the LAPIC version
103 static inline int lapic_get_version(void)
105 return GET_APIC_VERSION(apic_read(APIC_LVR
));
109 * Check, if the APIC is integrated or a seperate chip
111 static inline int lapic_is_integrated(void)
117 * Check, whether this is a modern or a first generation APIC
119 static int modern_apic(void)
121 /* AMD systems use old APIC versions, so check the CPU */
122 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
&&
123 boot_cpu_data
.x86
>= 0xf)
125 return lapic_get_version() >= 0x14;
128 void xapic_wait_icr_idle(void)
130 while (apic_read(APIC_ICR
) & APIC_ICR_BUSY
)
134 u32
safe_xapic_wait_icr_idle(void)
141 send_status
= apic_read(APIC_ICR
) & APIC_ICR_BUSY
;
145 } while (timeout
++ < 1000);
150 void xapic_icr_write(u32 low
, u32 id
)
152 apic_write(APIC_ICR2
, id
<< 24);
153 apic_write(APIC_ICR
, low
);
156 u64
xapic_icr_read(void)
160 icr2
= apic_read(APIC_ICR2
);
161 icr1
= apic_read(APIC_ICR
);
163 return (icr1
| ((u64
)icr2
<< 32));
166 static struct apic_ops xapic_ops
= {
167 .read
= native_apic_mem_read
,
168 .write
= native_apic_mem_write
,
169 .icr_read
= xapic_icr_read
,
170 .icr_write
= xapic_icr_write
,
171 .wait_icr_idle
= xapic_wait_icr_idle
,
172 .safe_wait_icr_idle
= safe_xapic_wait_icr_idle
,
175 struct apic_ops __read_mostly
*apic_ops
= &xapic_ops
;
177 EXPORT_SYMBOL_GPL(apic_ops
);
179 static void x2apic_wait_icr_idle(void)
181 /* no need to wait for icr idle in x2apic */
185 static u32
safe_x2apic_wait_icr_idle(void)
187 /* no need to wait for icr idle in x2apic */
191 void x2apic_icr_write(u32 low
, u32 id
)
193 wrmsrl(APIC_BASE_MSR
+ (APIC_ICR
>> 4), ((__u64
) id
) << 32 | low
);
196 u64
x2apic_icr_read(void)
200 rdmsrl(APIC_BASE_MSR
+ (APIC_ICR
>> 4), val
);
204 static struct apic_ops x2apic_ops
= {
205 .read
= native_apic_msr_read
,
206 .write
= native_apic_msr_write
,
207 .icr_read
= x2apic_icr_read
,
208 .icr_write
= x2apic_icr_write
,
209 .wait_icr_idle
= x2apic_wait_icr_idle
,
210 .safe_wait_icr_idle
= safe_x2apic_wait_icr_idle
,
214 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
216 void __cpuinit
enable_NMI_through_LVT0(void)
220 /* unmask and set to NMI */
222 apic_write(APIC_LVT0
, v
);
226 * lapic_get_maxlvt - get the maximum number of local vector table entries
228 int lapic_get_maxlvt(void)
230 unsigned int v
, maxlvt
;
232 v
= apic_read(APIC_LVR
);
233 maxlvt
= GET_APIC_MAXLVT(v
);
238 * This function sets up the local APIC timer, with a timeout of
239 * 'clocks' APIC bus clock. During calibration we actually call
240 * this function twice on the boot CPU, once with a bogus timeout
241 * value, second time for real. The other (noncalibrating) CPUs
242 * call this function only once, with the real, calibrated value.
244 * We do reads before writes even if unnecessary, to get around the
245 * P5 APIC double write bug.
248 static void __setup_APIC_LVTT(unsigned int clocks
, int oneshot
, int irqen
)
250 unsigned int lvtt_value
, tmp_value
;
252 lvtt_value
= LOCAL_TIMER_VECTOR
;
254 lvtt_value
|= APIC_LVT_TIMER_PERIODIC
;
256 lvtt_value
|= APIC_LVT_MASKED
;
258 apic_write(APIC_LVTT
, lvtt_value
);
263 tmp_value
= apic_read(APIC_TDCR
);
264 apic_write(APIC_TDCR
, (tmp_value
265 & ~(APIC_TDR_DIV_1
| APIC_TDR_DIV_TMBASE
))
269 apic_write(APIC_TMICT
, clocks
);
273 * Setup extended LVT, AMD specific (K8, family 10h)
275 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
276 * MCE interrupts are supported. Thus MCE offset must be set to 0.
279 #define APIC_EILVT_LVTOFF_MCE 0
280 #define APIC_EILVT_LVTOFF_IBS 1
282 static void setup_APIC_eilvt(u8 lvt_off
, u8 vector
, u8 msg_type
, u8 mask
)
284 unsigned long reg
= (lvt_off
<< 4) + APIC_EILVT0
;
285 unsigned int v
= (mask
<< 16) | (msg_type
<< 8) | vector
;
290 u8
setup_APIC_eilvt_mce(u8 vector
, u8 msg_type
, u8 mask
)
292 setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE
, vector
, msg_type
, mask
);
293 return APIC_EILVT_LVTOFF_MCE
;
296 u8
setup_APIC_eilvt_ibs(u8 vector
, u8 msg_type
, u8 mask
)
298 setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS
, vector
, msg_type
, mask
);
299 return APIC_EILVT_LVTOFF_IBS
;
303 * Program the next event, relative to now
305 static int lapic_next_event(unsigned long delta
,
306 struct clock_event_device
*evt
)
308 apic_write(APIC_TMICT
, delta
);
313 * Setup the lapic timer in periodic or oneshot mode
315 static void lapic_timer_setup(enum clock_event_mode mode
,
316 struct clock_event_device
*evt
)
321 /* Lapic used as dummy for broadcast ? */
322 if (evt
->features
& CLOCK_EVT_FEAT_DUMMY
)
325 local_irq_save(flags
);
328 case CLOCK_EVT_MODE_PERIODIC
:
329 case CLOCK_EVT_MODE_ONESHOT
:
330 __setup_APIC_LVTT(calibration_result
,
331 mode
!= CLOCK_EVT_MODE_PERIODIC
, 1);
333 case CLOCK_EVT_MODE_UNUSED
:
334 case CLOCK_EVT_MODE_SHUTDOWN
:
335 v
= apic_read(APIC_LVTT
);
336 v
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
337 apic_write(APIC_LVTT
, v
);
339 case CLOCK_EVT_MODE_RESUME
:
340 /* Nothing to do here */
344 local_irq_restore(flags
);
348 * Local APIC timer broadcast function
350 static void lapic_timer_broadcast(cpumask_t mask
)
353 send_IPI_mask(mask
, LOCAL_TIMER_VECTOR
);
358 * Setup the local APIC timer for this CPU. Copy the initilized values
359 * of the boot CPU and register the clock event in the framework.
361 static void setup_APIC_timer(void)
363 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
365 memcpy(levt
, &lapic_clockevent
, sizeof(*levt
));
366 levt
->cpumask
= cpumask_of_cpu(smp_processor_id());
368 clockevents_register_device(levt
);
372 * In this function we calibrate APIC bus clocks to the external
373 * timer. Unfortunately we cannot use jiffies and the timer irq
374 * to calibrate, since some later bootup code depends on getting
375 * the first irq? Ugh.
377 * We want to do the calibration only once since we
378 * want to have local timer irqs syncron. CPUs connected
379 * by the same APIC bus have the very same bus frequency.
380 * And we want to have irqs off anyways, no accidental
384 #define TICK_COUNT 100000000
386 static int __init
calibrate_APIC_clock(void)
388 unsigned apic
, apic_start
;
389 unsigned long tsc
, tsc_start
;
395 * Put whatever arbitrary (but long enough) timeout
396 * value into the APIC clock, we just want to get the
397 * counter running for calibration.
399 * No interrupt enable !
401 __setup_APIC_LVTT(250000000, 0, 0);
403 apic_start
= apic_read(APIC_TMCCT
);
404 #ifdef CONFIG_X86_PM_TIMER
405 if (apic_calibrate_pmtmr
&& pmtmr_ioport
) {
406 pmtimer_wait(5000); /* 5ms wait */
407 apic
= apic_read(APIC_TMCCT
);
408 result
= (apic_start
- apic
) * 1000L / 5;
415 apic
= apic_read(APIC_TMCCT
);
417 } while ((tsc
- tsc_start
) < TICK_COUNT
&&
418 (apic_start
- apic
) < TICK_COUNT
);
420 result
= (apic_start
- apic
) * 1000L * tsc_khz
/
426 printk(KERN_DEBUG
"APIC timer calibration result %d\n", result
);
428 printk(KERN_INFO
"Detected %d.%03d MHz APIC timer.\n",
429 result
/ 1000 / 1000, result
/ 1000 % 1000);
431 /* Calculate the scaled math multiplication factor */
432 lapic_clockevent
.mult
= div_sc(result
, NSEC_PER_SEC
,
433 lapic_clockevent
.shift
);
434 lapic_clockevent
.max_delta_ns
=
435 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent
);
436 lapic_clockevent
.min_delta_ns
=
437 clockevent_delta2ns(0xF, &lapic_clockevent
);
439 calibration_result
= result
/ HZ
;
442 * Do a sanity check on the APIC calibration result
444 if (calibration_result
< (1000000 / HZ
)) {
446 "APIC frequency too slow, disabling apic timer\n");
454 * Setup the boot APIC
456 * Calibrate and verify the result.
458 void __init
setup_boot_APIC_clock(void)
461 * The local apic timer can be disabled via the kernel commandline.
462 * Register the lapic timer as a dummy clock event source on SMP
463 * systems, so the broadcast mechanism is used. On UP systems simply
466 if (disable_apic_timer
) {
467 printk(KERN_INFO
"Disabling APIC timer\n");
468 /* No broadcast on UP ! */
469 if (num_possible_cpus() > 1) {
470 lapic_clockevent
.mult
= 1;
476 printk(KERN_INFO
"Using local APIC timer interrupts.\n");
477 if (calibrate_APIC_clock()) {
478 /* No broadcast on UP ! */
479 if (num_possible_cpus() > 1)
485 * If nmi_watchdog is set to IO_APIC, we need the
486 * PIT/HPET going. Otherwise register lapic as a dummy
489 if (nmi_watchdog
!= NMI_IO_APIC
)
490 lapic_clockevent
.features
&= ~CLOCK_EVT_FEAT_DUMMY
;
492 printk(KERN_WARNING
"APIC timer registered as dummy,"
493 " due to nmi_watchdog=%d!\n", nmi_watchdog
);
498 void __cpuinit
setup_secondary_APIC_clock(void)
504 * The guts of the apic timer interrupt
506 static void local_apic_timer_interrupt(void)
508 int cpu
= smp_processor_id();
509 struct clock_event_device
*evt
= &per_cpu(lapic_events
, cpu
);
512 * Normally we should not be here till LAPIC has been initialized but
513 * in some cases like kdump, its possible that there is a pending LAPIC
514 * timer interrupt from previous kernel's context and is delivered in
515 * new kernel the moment interrupts are enabled.
517 * Interrupts are enabled early and LAPIC is setup much later, hence
518 * its possible that when we get here evt->event_handler is NULL.
519 * Check for event_handler being NULL and discard the interrupt as
522 if (!evt
->event_handler
) {
524 "Spurious LAPIC timer interrupt on cpu %d\n", cpu
);
526 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, evt
);
531 * the NMI deadlock-detector uses this.
533 add_pda(apic_timer_irqs
, 1);
535 evt
->event_handler(evt
);
539 * Local APIC timer interrupt. This is the most natural way for doing
540 * local interrupts, but local timer interrupts can be emulated by
541 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
543 * [ if a single-CPU system runs an SMP kernel then we call the local
544 * interrupt as well. Thus we cannot inline the local irq ... ]
546 void smp_apic_timer_interrupt(struct pt_regs
*regs
)
548 struct pt_regs
*old_regs
= set_irq_regs(regs
);
551 * NOTE! We'd better ACK the irq immediately,
552 * because timer handling can be slow.
556 * update_process_times() expects us to have done irq_enter().
557 * Besides, if we don't timer interrupts ignore the global
558 * interrupt lock, which is the WrongThing (tm) to do.
562 local_apic_timer_interrupt();
564 set_irq_regs(old_regs
);
567 int setup_profiling_timer(unsigned int multiplier
)
574 * Local APIC start and shutdown
578 * clear_local_APIC - shutdown the local APIC
580 * This is called, when a CPU is disabled and before rebooting, so the state of
581 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
582 * leftovers during boot.
584 void clear_local_APIC(void)
589 /* APIC hasn't been mapped yet */
593 maxlvt
= lapic_get_maxlvt();
595 * Masking an LVT entry can trigger a local APIC error
596 * if the vector is zero. Mask LVTERR first to prevent this.
599 v
= ERROR_APIC_VECTOR
; /* any non-zero vector will do */
600 apic_write(APIC_LVTERR
, v
| APIC_LVT_MASKED
);
603 * Careful: we have to set masks only first to deassert
604 * any level-triggered sources.
606 v
= apic_read(APIC_LVTT
);
607 apic_write(APIC_LVTT
, v
| APIC_LVT_MASKED
);
608 v
= apic_read(APIC_LVT0
);
609 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
610 v
= apic_read(APIC_LVT1
);
611 apic_write(APIC_LVT1
, v
| APIC_LVT_MASKED
);
613 v
= apic_read(APIC_LVTPC
);
614 apic_write(APIC_LVTPC
, v
| APIC_LVT_MASKED
);
618 * Clean APIC state for other OSs:
620 apic_write(APIC_LVTT
, APIC_LVT_MASKED
);
621 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
622 apic_write(APIC_LVT1
, APIC_LVT_MASKED
);
624 apic_write(APIC_LVTERR
, APIC_LVT_MASKED
);
626 apic_write(APIC_LVTPC
, APIC_LVT_MASKED
);
627 apic_write(APIC_ESR
, 0);
632 * disable_local_APIC - clear and disable the local APIC
634 void disable_local_APIC(void)
641 * Disable APIC (implies clearing of registers
644 value
= apic_read(APIC_SPIV
);
645 value
&= ~APIC_SPIV_APIC_ENABLED
;
646 apic_write(APIC_SPIV
, value
);
649 void lapic_shutdown(void)
656 local_irq_save(flags
);
658 disable_local_APIC();
660 local_irq_restore(flags
);
664 * This is to verify that we're looking at a real local APIC.
665 * Check these against your board if the CPUs aren't getting
666 * started for no apparent reason.
668 int __init
verify_local_APIC(void)
670 unsigned int reg0
, reg1
;
673 * The version register is read-only in a real APIC.
675 reg0
= apic_read(APIC_LVR
);
676 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg0
);
677 apic_write(APIC_LVR
, reg0
^ APIC_LVR_MASK
);
678 reg1
= apic_read(APIC_LVR
);
679 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg1
);
682 * The two version reads above should print the same
683 * numbers. If the second one is different, then we
684 * poke at a non-APIC.
690 * Check if the version looks reasonably.
692 reg1
= GET_APIC_VERSION(reg0
);
693 if (reg1
== 0x00 || reg1
== 0xff)
695 reg1
= lapic_get_maxlvt();
696 if (reg1
< 0x02 || reg1
== 0xff)
700 * The ID register is read/write in a real APIC.
702 reg0
= apic_read(APIC_ID
);
703 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg0
);
704 apic_write(APIC_ID
, reg0
^ APIC_ID_MASK
);
705 reg1
= apic_read(APIC_ID
);
706 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg1
);
707 apic_write(APIC_ID
, reg0
);
708 if (reg1
!= (reg0
^ APIC_ID_MASK
))
712 * The next two are just to see if we have sane values.
713 * They're only really relevant if we're in Virtual Wire
714 * compatibility mode, but most boxes are anymore.
716 reg0
= apic_read(APIC_LVT0
);
717 apic_printk(APIC_DEBUG
, "Getting LVT0: %x\n", reg0
);
718 reg1
= apic_read(APIC_LVT1
);
719 apic_printk(APIC_DEBUG
, "Getting LVT1: %x\n", reg1
);
725 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
727 void __init
sync_Arb_IDs(void)
729 /* Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 */
736 apic_wait_icr_idle();
738 apic_printk(APIC_DEBUG
, "Synchronizing Arb IDs.\n");
739 apic_write(APIC_ICR
, APIC_DEST_ALLINC
| APIC_INT_LEVELTRIG
744 * An initial setup of the virtual wire mode.
746 void __init
init_bsp_APIC(void)
751 * Don't do the setup now if we have a SMP BIOS as the
752 * through-I/O-APIC virtual wire mode might be active.
754 if (smp_found_config
|| !cpu_has_apic
)
757 value
= apic_read(APIC_LVR
);
760 * Do not trust the local APIC being empty at bootup.
767 value
= apic_read(APIC_SPIV
);
768 value
&= ~APIC_VECTOR_MASK
;
769 value
|= APIC_SPIV_APIC_ENABLED
;
770 value
|= APIC_SPIV_FOCUS_DISABLED
;
771 value
|= SPURIOUS_APIC_VECTOR
;
772 apic_write(APIC_SPIV
, value
);
775 * Set up the virtual wire mode.
777 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
779 apic_write(APIC_LVT1
, value
);
783 * setup_local_APIC - setup the local APIC
785 void __cpuinit
setup_local_APIC(void)
791 value
= apic_read(APIC_LVR
);
793 BUILD_BUG_ON((SPURIOUS_APIC_VECTOR
& 0x0f) != 0x0f);
796 * Double-check whether this APIC is really registered.
797 * This is meaningless in clustered apic mode, so we skip it.
799 if (!apic_id_registered())
803 * Intel recommends to set DFR, LDR and TPR before enabling
804 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
805 * document number 292116). So here it goes...
810 * Set Task Priority to 'accept all'. We never change this
813 value
= apic_read(APIC_TASKPRI
);
814 value
&= ~APIC_TPRI_MASK
;
815 apic_write(APIC_TASKPRI
, value
);
818 * After a crash, we no longer service the interrupts and a pending
819 * interrupt from previous kernel might still have ISR bit set.
821 * Most probably by now CPU has serviced that pending interrupt and
822 * it might not have done the ack_APIC_irq() because it thought,
823 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
824 * does not clear the ISR bit and cpu thinks it has already serivced
825 * the interrupt. Hence a vector might get locked. It was noticed
826 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
828 for (i
= APIC_ISR_NR
- 1; i
>= 0; i
--) {
829 value
= apic_read(APIC_ISR
+ i
*0x10);
830 for (j
= 31; j
>= 0; j
--) {
837 * Now that we are all set up, enable the APIC
839 value
= apic_read(APIC_SPIV
);
840 value
&= ~APIC_VECTOR_MASK
;
844 value
|= APIC_SPIV_APIC_ENABLED
;
846 /* We always use processor focus */
849 * Set spurious IRQ vector
851 value
|= SPURIOUS_APIC_VECTOR
;
852 apic_write(APIC_SPIV
, value
);
857 * set up through-local-APIC on the BP's LINT0. This is not
858 * strictly necessary in pure symmetric-IO mode, but sometimes
859 * we delegate interrupts to the 8259A.
862 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
864 value
= apic_read(APIC_LVT0
) & APIC_LVT_MASKED
;
865 if (!smp_processor_id() && !value
) {
866 value
= APIC_DM_EXTINT
;
867 apic_printk(APIC_VERBOSE
, "enabled ExtINT on CPU#%d\n",
870 value
= APIC_DM_EXTINT
| APIC_LVT_MASKED
;
871 apic_printk(APIC_VERBOSE
, "masked ExtINT on CPU#%d\n",
874 apic_write(APIC_LVT0
, value
);
877 * only the BP should see the LINT1 NMI signal, obviously.
879 if (!smp_processor_id())
882 value
= APIC_DM_NMI
| APIC_LVT_MASKED
;
883 apic_write(APIC_LVT1
, value
);
887 static void __cpuinit
lapic_setup_esr(void)
889 unsigned maxlvt
= lapic_get_maxlvt();
891 apic_write(APIC_LVTERR
, ERROR_APIC_VECTOR
);
893 * spec says clear errors after enabling vector.
896 apic_write(APIC_ESR
, 0);
899 void __cpuinit
end_local_APIC_setup(void)
902 setup_apic_nmi_watchdog(NULL
);
906 void check_x2apic(void)
910 rdmsr(MSR_IA32_APICBASE
, msr
, msr2
);
912 if (msr
& X2APIC_ENABLE
) {
913 printk("x2apic enabled by BIOS, switching to x2apic ops\n");
914 x2apic_preenabled
= x2apic
= 1;
915 apic_ops
= &x2apic_ops
;
919 void enable_x2apic(void)
923 rdmsr(MSR_IA32_APICBASE
, msr
, msr2
);
924 if (!(msr
& X2APIC_ENABLE
)) {
925 printk("Enabling x2apic\n");
926 wrmsr(MSR_IA32_APICBASE
, msr
| X2APIC_ENABLE
, 0);
930 void enable_IR_x2apic(void)
932 #ifdef CONFIG_INTR_REMAP
939 if (!x2apic_preenabled
&& disable_x2apic
) {
941 "Skipped enabling x2apic and Interrupt-remapping "
942 "because of nox2apic\n");
946 if (x2apic_preenabled
&& disable_x2apic
)
947 panic("Bios already enabled x2apic, can't enforce nox2apic");
949 if (!x2apic_preenabled
&& skip_ioapic_setup
) {
951 "Skipped enabling x2apic and Interrupt-remapping "
952 "because of skipping io-apic setup\n");
956 ret
= dmar_table_init();
959 "dmar_table_init() failed with %d:\n", ret
);
961 if (x2apic_preenabled
)
962 panic("x2apic enabled by bios. But IR enabling failed");
965 "Not enabling x2apic,Intr-remapping\n");
969 local_irq_save(flags
);
971 save_mask_IO_APIC_setup();
973 ret
= enable_intr_remapping(1);
975 if (ret
&& x2apic_preenabled
) {
976 local_irq_restore(flags
);
977 panic("x2apic enabled by bios. But IR enabling failed");
985 apic_ops
= &x2apic_ops
;
993 restore_IO_APIC_setup();
995 reinit_intr_remapped_IO_APIC(x2apic_preenabled
);
998 local_irq_restore(flags
);
1001 if (!x2apic_preenabled
)
1003 "Enabled x2apic and interrupt-remapping\n");
1006 "Enabled Interrupt-remapping\n");
1009 "Failed to enable Interrupt-remapping and x2apic\n");
1011 if (!cpu_has_x2apic
)
1014 if (x2apic_preenabled
)
1015 panic("x2apic enabled prior OS handover,"
1016 " enable CONFIG_INTR_REMAP");
1018 printk(KERN_INFO
"Enable CONFIG_INTR_REMAP for enabling intr-remapping "
1026 * Detect and enable local APICs on non-SMP boards.
1027 * Original code written by Keir Fraser.
1028 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1029 * not correctly set up (usually the APIC timer won't work etc.)
1031 static int __init
detect_init_APIC(void)
1033 if (!cpu_has_apic
) {
1034 printk(KERN_INFO
"No local APIC present\n");
1038 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
1039 boot_cpu_physical_apicid
= 0;
1043 void __init
early_init_lapic_mapping(void)
1045 unsigned long phys_addr
;
1048 * If no local APIC can be found then go out
1049 * : it means there is no mpatable and MADT
1051 if (!smp_found_config
)
1054 phys_addr
= mp_lapic_addr
;
1056 set_fixmap_nocache(FIX_APIC_BASE
, phys_addr
);
1057 apic_printk(APIC_VERBOSE
, "mapped APIC to %16lx (%16lx)\n",
1058 APIC_BASE
, phys_addr
);
1061 * Fetch the APIC ID of the BSP in case we have a
1062 * default configuration (or the MP table is broken).
1064 boot_cpu_physical_apicid
= read_apic_id();
1068 * init_apic_mappings - initialize APIC mappings
1070 void __init
init_apic_mappings(void)
1073 boot_cpu_physical_apicid
= read_apic_id();
1078 * If no local APIC can be found then set up a fake all
1079 * zeroes page to simulate the local APIC and another
1080 * one for the IO-APIC.
1082 if (!smp_found_config
&& detect_init_APIC()) {
1083 apic_phys
= (unsigned long) alloc_bootmem_pages(PAGE_SIZE
);
1084 apic_phys
= __pa(apic_phys
);
1086 apic_phys
= mp_lapic_addr
;
1088 set_fixmap_nocache(FIX_APIC_BASE
, apic_phys
);
1089 apic_printk(APIC_VERBOSE
, "mapped APIC to %16lx (%16lx)\n",
1090 APIC_BASE
, apic_phys
);
1093 * Fetch the APIC ID of the BSP in case we have a
1094 * default configuration (or the MP table is broken).
1096 boot_cpu_physical_apicid
= read_apic_id();
1100 * This initializes the IO-APIC and APIC hardware if this is
1103 int __init
APIC_init_uniprocessor(void)
1106 printk(KERN_INFO
"Apic disabled\n");
1109 if (!cpu_has_apic
) {
1111 printk(KERN_INFO
"Apic disabled by BIOS\n");
1116 setup_apic_routing();
1118 verify_local_APIC();
1122 physid_set_mask_of_physid(boot_cpu_physical_apicid
, &phys_cpu_present_map
);
1123 apic_write(APIC_ID
, SET_APIC_ID(boot_cpu_physical_apicid
));
1128 * Now enable IO-APICs, actually call clear_IO_APIC
1129 * We need clear_IO_APIC before enabling vector on BP
1131 if (!skip_ioapic_setup
&& nr_ioapics
)
1134 if (!smp_found_config
|| skip_ioapic_setup
|| !nr_ioapics
)
1135 localise_nmi_watchdog();
1136 end_local_APIC_setup();
1138 if (smp_found_config
&& !skip_ioapic_setup
&& nr_ioapics
)
1142 setup_boot_APIC_clock();
1143 check_nmi_watchdog();
1148 * Local APIC interrupts
1152 * This interrupt should _never_ happen with our APIC/SMP architecture
1154 asmlinkage
void smp_spurious_interrupt(void)
1160 * Check if this really is a spurious interrupt and ACK it
1161 * if it is a vectored one. Just in case...
1162 * Spurious interrupts should not be ACKed.
1164 v
= apic_read(APIC_ISR
+ ((SPURIOUS_APIC_VECTOR
& ~0x1f) >> 1));
1165 if (v
& (1 << (SPURIOUS_APIC_VECTOR
& 0x1f)))
1168 add_pda(irq_spurious_count
, 1);
1173 * This interrupt should never happen with our APIC/SMP architecture
1175 asmlinkage
void smp_error_interrupt(void)
1181 /* First tickle the hardware, only then report what went on. -- REW */
1182 v
= apic_read(APIC_ESR
);
1183 apic_write(APIC_ESR
, 0);
1184 v1
= apic_read(APIC_ESR
);
1186 atomic_inc(&irq_err_count
);
1188 /* Here is what the APIC error bits mean:
1191 2: Send accept error
1192 3: Receive accept error
1194 5: Send illegal vector
1195 6: Received illegal vector
1196 7: Illegal register address
1198 printk(KERN_DEBUG
"APIC error on CPU%d: %02x(%02x)\n",
1199 smp_processor_id(), v
, v1
);
1204 * * connect_bsp_APIC - attach the APIC to the interrupt system
1206 void __init
connect_bsp_APIC(void)
1211 void disconnect_bsp_APIC(int virt_wire_setup
)
1213 /* Go back to Virtual Wire compatibility mode */
1214 unsigned long value
;
1216 /* For the spurious interrupt use vector F, and enable it */
1217 value
= apic_read(APIC_SPIV
);
1218 value
&= ~APIC_VECTOR_MASK
;
1219 value
|= APIC_SPIV_APIC_ENABLED
;
1221 apic_write(APIC_SPIV
, value
);
1223 if (!virt_wire_setup
) {
1225 * For LVT0 make it edge triggered, active high,
1226 * external and enabled
1228 value
= apic_read(APIC_LVT0
);
1229 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1230 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1231 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1232 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1233 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_EXTINT
);
1234 apic_write(APIC_LVT0
, value
);
1237 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
1240 /* For LVT1 make it edge triggered, active high, nmi and enabled */
1241 value
= apic_read(APIC_LVT1
);
1242 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1243 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1244 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1245 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1246 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_NMI
);
1247 apic_write(APIC_LVT1
, value
);
1250 void __cpuinit
generic_processor_info(int apicid
, int version
)
1255 if (num_processors
>= NR_CPUS
) {
1256 printk(KERN_WARNING
"WARNING: NR_CPUS limit of %i reached."
1257 " Processor ignored.\n", NR_CPUS
);
1262 cpus_complement(tmp_map
, cpu_present_map
);
1263 cpu
= first_cpu(tmp_map
);
1265 physid_set(apicid
, phys_cpu_present_map
);
1266 if (apicid
== boot_cpu_physical_apicid
) {
1268 * x86_bios_cpu_apicid is required to have processors listed
1269 * in same order as logical cpu numbers. Hence the first
1270 * entry is BSP, and so on.
1274 if (apicid
> max_physical_apicid
)
1275 max_physical_apicid
= apicid
;
1277 /* are we being called early in kernel startup? */
1278 if (early_per_cpu_ptr(x86_cpu_to_apicid
)) {
1279 u16
*cpu_to_apicid
= early_per_cpu_ptr(x86_cpu_to_apicid
);
1280 u16
*bios_cpu_apicid
= early_per_cpu_ptr(x86_bios_cpu_apicid
);
1282 cpu_to_apicid
[cpu
] = apicid
;
1283 bios_cpu_apicid
[cpu
] = apicid
;
1285 per_cpu(x86_cpu_to_apicid
, cpu
) = apicid
;
1286 per_cpu(x86_bios_cpu_apicid
, cpu
) = apicid
;
1289 cpu_set(cpu
, cpu_possible_map
);
1290 cpu_set(cpu
, cpu_present_map
);
1293 int hard_smp_processor_id(void)
1295 return read_apic_id();
1304 /* 'active' is true if the local APIC was enabled by us and
1305 not the BIOS; this signifies that we are also responsible
1306 for disabling it before entering apm/acpi suspend */
1308 /* r/w apic fields */
1309 unsigned int apic_id
;
1310 unsigned int apic_taskpri
;
1311 unsigned int apic_ldr
;
1312 unsigned int apic_dfr
;
1313 unsigned int apic_spiv
;
1314 unsigned int apic_lvtt
;
1315 unsigned int apic_lvtpc
;
1316 unsigned int apic_lvt0
;
1317 unsigned int apic_lvt1
;
1318 unsigned int apic_lvterr
;
1319 unsigned int apic_tmict
;
1320 unsigned int apic_tdcr
;
1321 unsigned int apic_thmr
;
1324 static int lapic_suspend(struct sys_device
*dev
, pm_message_t state
)
1326 unsigned long flags
;
1329 if (!apic_pm_state
.active
)
1332 maxlvt
= lapic_get_maxlvt();
1334 apic_pm_state
.apic_id
= apic_read(APIC_ID
);
1335 apic_pm_state
.apic_taskpri
= apic_read(APIC_TASKPRI
);
1336 apic_pm_state
.apic_ldr
= apic_read(APIC_LDR
);
1337 apic_pm_state
.apic_dfr
= apic_read(APIC_DFR
);
1338 apic_pm_state
.apic_spiv
= apic_read(APIC_SPIV
);
1339 apic_pm_state
.apic_lvtt
= apic_read(APIC_LVTT
);
1341 apic_pm_state
.apic_lvtpc
= apic_read(APIC_LVTPC
);
1342 apic_pm_state
.apic_lvt0
= apic_read(APIC_LVT0
);
1343 apic_pm_state
.apic_lvt1
= apic_read(APIC_LVT1
);
1344 apic_pm_state
.apic_lvterr
= apic_read(APIC_LVTERR
);
1345 apic_pm_state
.apic_tmict
= apic_read(APIC_TMICT
);
1346 apic_pm_state
.apic_tdcr
= apic_read(APIC_TDCR
);
1347 #ifdef CONFIG_X86_MCE_INTEL
1349 apic_pm_state
.apic_thmr
= apic_read(APIC_LVTTHMR
);
1351 local_irq_save(flags
);
1352 disable_local_APIC();
1353 local_irq_restore(flags
);
1357 static int lapic_resume(struct sys_device
*dev
)
1360 unsigned long flags
;
1363 if (!apic_pm_state
.active
)
1366 maxlvt
= lapic_get_maxlvt();
1368 local_irq_save(flags
);
1370 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1371 l
&= ~MSR_IA32_APICBASE_BASE
;
1372 l
|= MSR_IA32_APICBASE_ENABLE
| mp_lapic_addr
;
1373 wrmsr(MSR_IA32_APICBASE
, l
, h
);
1377 apic_write(APIC_LVTERR
, ERROR_APIC_VECTOR
| APIC_LVT_MASKED
);
1378 apic_write(APIC_ID
, apic_pm_state
.apic_id
);
1379 apic_write(APIC_DFR
, apic_pm_state
.apic_dfr
);
1380 apic_write(APIC_LDR
, apic_pm_state
.apic_ldr
);
1381 apic_write(APIC_TASKPRI
, apic_pm_state
.apic_taskpri
);
1382 apic_write(APIC_SPIV
, apic_pm_state
.apic_spiv
);
1383 apic_write(APIC_LVT0
, apic_pm_state
.apic_lvt0
);
1384 apic_write(APIC_LVT1
, apic_pm_state
.apic_lvt1
);
1385 #ifdef CONFIG_X86_MCE_INTEL
1387 apic_write(APIC_LVTTHMR
, apic_pm_state
.apic_thmr
);
1390 apic_write(APIC_LVTPC
, apic_pm_state
.apic_lvtpc
);
1391 apic_write(APIC_LVTT
, apic_pm_state
.apic_lvtt
);
1392 apic_write(APIC_TDCR
, apic_pm_state
.apic_tdcr
);
1393 apic_write(APIC_TMICT
, apic_pm_state
.apic_tmict
);
1394 apic_write(APIC_ESR
, 0);
1395 apic_read(APIC_ESR
);
1396 apic_write(APIC_LVTERR
, apic_pm_state
.apic_lvterr
);
1397 apic_write(APIC_ESR
, 0);
1398 apic_read(APIC_ESR
);
1399 local_irq_restore(flags
);
1403 static struct sysdev_class lapic_sysclass
= {
1405 .resume
= lapic_resume
,
1406 .suspend
= lapic_suspend
,
1409 static struct sys_device device_lapic
= {
1411 .cls
= &lapic_sysclass
,
1414 static void __cpuinit
apic_pm_activate(void)
1416 apic_pm_state
.active
= 1;
1419 static int __init
init_lapic_sysfs(void)
1425 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
1427 error
= sysdev_class_register(&lapic_sysclass
);
1429 error
= sysdev_register(&device_lapic
);
1432 device_initcall(init_lapic_sysfs
);
1434 #else /* CONFIG_PM */
1436 static void apic_pm_activate(void) { }
1438 #endif /* CONFIG_PM */
1441 * apic_is_clustered_box() -- Check if we can expect good TSC
1443 * Thus far, the major user of this is IBM's Summit2 series:
1445 * Clustered boxes may have unsynced TSC problems if they are
1446 * multi-chassis. Use available data to take a good guess.
1447 * If in doubt, go HPET.
1449 __cpuinit
int apic_is_clustered_box(void)
1451 int i
, clusters
, zeros
;
1453 u16
*bios_cpu_apicid
;
1454 DECLARE_BITMAP(clustermap
, NUM_APIC_CLUSTERS
);
1457 * there is not this kind of box with AMD CPU yet.
1458 * Some AMD box with quadcore cpu and 8 sockets apicid
1459 * will be [4, 0x23] or [8, 0x27] could be thought to
1460 * vsmp box still need checking...
1462 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
) && !is_vsmp_box())
1465 bios_cpu_apicid
= early_per_cpu_ptr(x86_bios_cpu_apicid
);
1466 bitmap_zero(clustermap
, NUM_APIC_CLUSTERS
);
1468 for (i
= 0; i
< NR_CPUS
; i
++) {
1469 /* are we being called early in kernel startup? */
1470 if (bios_cpu_apicid
) {
1471 id
= bios_cpu_apicid
[i
];
1473 else if (i
< nr_cpu_ids
) {
1475 id
= per_cpu(x86_bios_cpu_apicid
, i
);
1482 if (id
!= BAD_APICID
)
1483 __set_bit(APIC_CLUSTERID(id
), clustermap
);
1486 /* Problem: Partially populated chassis may not have CPUs in some of
1487 * the APIC clusters they have been allocated. Only present CPUs have
1488 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap.
1489 * Since clusters are allocated sequentially, count zeros only if
1490 * they are bounded by ones.
1494 for (i
= 0; i
< NUM_APIC_CLUSTERS
; i
++) {
1495 if (test_bit(i
, clustermap
)) {
1496 clusters
+= 1 + zeros
;
1502 /* ScaleMP vSMPowered boxes have one cluster per board and TSCs are
1503 * not guaranteed to be synced between boards
1505 if (is_vsmp_box() && clusters
> 1)
1509 * If clusters > 2, then should be multi-chassis.
1510 * May have to revisit this when multi-core + hyperthreaded CPUs come
1511 * out, but AFAIK this will work even for them.
1513 return (clusters
> 2);
1516 static __init
int setup_nox2apic(char *str
)
1519 clear_cpu_cap(&boot_cpu_data
, X86_FEATURE_X2APIC
);
1522 early_param("nox2apic", setup_nox2apic
);
1526 * APIC command line parameters
1528 static int __init
apic_set_verbosity(char *str
)
1531 skip_ioapic_setup
= 0;
1535 if (strcmp("debug", str
) == 0)
1536 apic_verbosity
= APIC_DEBUG
;
1537 else if (strcmp("verbose", str
) == 0)
1538 apic_verbosity
= APIC_VERBOSE
;
1540 printk(KERN_WARNING
"APIC Verbosity level %s not recognised"
1541 " use apic=verbose or apic=debug\n", str
);
1547 early_param("apic", apic_set_verbosity
);
1549 static __init
int setup_disableapic(char *str
)
1552 setup_clear_cpu_cap(X86_FEATURE_APIC
);
1555 early_param("disableapic", setup_disableapic
);
1557 /* same as disableapic, for compatibility */
1558 static __init
int setup_nolapic(char *str
)
1560 return setup_disableapic(str
);
1562 early_param("nolapic", setup_nolapic
);
1564 static int __init
parse_lapic_timer_c2_ok(char *arg
)
1566 local_apic_timer_c2_ok
= 1;
1569 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok
);
1571 static __init
int setup_noapictimer(char *str
)
1573 if (str
[0] != ' ' && str
[0] != 0)
1575 disable_apic_timer
= 1;
1578 __setup("noapictimer", setup_noapictimer
);
1580 static __init
int setup_apicpmtimer(char *s
)
1582 apic_calibrate_pmtmr
= 1;
1586 __setup("apicpmtimer", setup_apicpmtimer
);
1588 static int __init
lapic_insert_resource(void)
1593 /* Put local APIC into the resource map. */
1594 lapic_resource
.start
= apic_phys
;
1595 lapic_resource
.end
= lapic_resource
.start
+ PAGE_SIZE
- 1;
1596 insert_resource(&iomem_resource
, &lapic_resource
);
1602 * need call insert after e820_reserve_resources()
1603 * that is using request_resource
1605 late_initcall(lapic_insert_resource
);