2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/bootmem.h>
22 #include <linux/interrupt.h>
23 #include <linux/mc146818rtc.h>
24 #include <linux/kernel_stat.h>
25 #include <linux/sysdev.h>
26 #include <linux/ioport.h>
27 #include <linux/clockchips.h>
28 #include <linux/acpi_pmtmr.h>
29 #include <linux/module.h>
30 #include <linux/dmar.h>
32 #include <asm/atomic.h>
35 #include <asm/mpspec.h>
37 #include <asm/pgalloc.h>
40 #include <asm/proto.h>
41 #include <asm/timex.h>
43 #include <asm/i8259.h>
46 #include <mach_apic.h>
48 static int disable_apic_timer __cpuinitdata
;
49 static int apic_calibrate_pmtmr __initdata
;
54 /* x2apic enabled before OS handover */
55 int x2apic_preenabled
;
57 /* Local APIC timer works in C2 */
58 int local_apic_timer_c2_ok
;
59 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok
);
62 * Debug level, exported for io_apic.c
64 unsigned int apic_verbosity
;
66 /* Have we found an MP table */
69 static struct resource lapic_resource
= {
71 .flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
,
74 static unsigned int calibration_result
;
76 static int lapic_next_event(unsigned long delta
,
77 struct clock_event_device
*evt
);
78 static void lapic_timer_setup(enum clock_event_mode mode
,
79 struct clock_event_device
*evt
);
80 static void lapic_timer_broadcast(cpumask_t mask
);
81 static void apic_pm_activate(void);
83 static struct clock_event_device lapic_clockevent
= {
85 .features
= CLOCK_EVT_FEAT_PERIODIC
| CLOCK_EVT_FEAT_ONESHOT
86 | CLOCK_EVT_FEAT_C3STOP
| CLOCK_EVT_FEAT_DUMMY
,
88 .set_mode
= lapic_timer_setup
,
89 .set_next_event
= lapic_next_event
,
90 .broadcast
= lapic_timer_broadcast
,
94 static DEFINE_PER_CPU(struct clock_event_device
, lapic_events
);
96 static unsigned long apic_phys
;
98 unsigned long mp_lapic_addr
;
101 * Get the LAPIC version
103 static inline int lapic_get_version(void)
105 return GET_APIC_VERSION(apic_read(APIC_LVR
));
109 * Check, if the APIC is integrated or a seperate chip
111 static inline int lapic_is_integrated(void)
117 * Check, whether this is a modern or a first generation APIC
119 static int modern_apic(void)
121 /* AMD systems use old APIC versions, so check the CPU */
122 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
&&
123 boot_cpu_data
.x86
>= 0xf)
125 return lapic_get_version() >= 0x14;
128 void xapic_wait_icr_idle(void)
130 while (apic_read(APIC_ICR
) & APIC_ICR_BUSY
)
134 u32
safe_xapic_wait_icr_idle(void)
141 send_status
= apic_read(APIC_ICR
) & APIC_ICR_BUSY
;
145 } while (timeout
++ < 1000);
150 void xapic_icr_write(u32 low
, u32 id
)
152 apic_write(APIC_ICR2
, id
<< 24);
153 apic_write(APIC_ICR
, low
);
156 u64
xapic_icr_read(void)
160 icr2
= apic_read(APIC_ICR2
);
161 icr1
= apic_read(APIC_ICR
);
163 return (icr1
| ((u64
)icr2
<< 32));
166 static struct apic_ops xapic_ops
= {
167 .read
= native_apic_mem_read
,
168 .write
= native_apic_mem_write
,
169 .icr_read
= xapic_icr_read
,
170 .icr_write
= xapic_icr_write
,
171 .wait_icr_idle
= xapic_wait_icr_idle
,
172 .safe_wait_icr_idle
= safe_xapic_wait_icr_idle
,
175 struct apic_ops __read_mostly
*apic_ops
= &xapic_ops
;
177 EXPORT_SYMBOL_GPL(apic_ops
);
179 static void x2apic_wait_icr_idle(void)
181 /* no need to wait for icr idle in x2apic */
185 static u32
safe_x2apic_wait_icr_idle(void)
187 /* no need to wait for icr idle in x2apic */
191 void x2apic_icr_write(u32 low
, u32 id
)
193 wrmsrl(APIC_BASE_MSR
+ (APIC_ICR
>> 4), ((__u64
) id
) << 32 | low
);
196 u64
x2apic_icr_read(void)
200 rdmsrl(APIC_BASE_MSR
+ (APIC_ICR
>> 4), val
);
204 static struct apic_ops x2apic_ops
= {
205 .read
= native_apic_msr_read
,
206 .write
= native_apic_msr_write
,
207 .icr_read
= x2apic_icr_read
,
208 .icr_write
= x2apic_icr_write
,
209 .wait_icr_idle
= x2apic_wait_icr_idle
,
210 .safe_wait_icr_idle
= safe_x2apic_wait_icr_idle
,
214 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
216 void __cpuinit
enable_NMI_through_LVT0(void)
220 /* unmask and set to NMI */
223 /* Level triggered for 82489DX (32bit mode) */
224 if (!lapic_is_integrated())
225 v
|= APIC_LVT_LEVEL_TRIGGER
;
227 apic_write(APIC_LVT0
, v
);
231 * lapic_get_maxlvt - get the maximum number of local vector table entries
233 int lapic_get_maxlvt(void)
237 v
= apic_read(APIC_LVR
);
239 * - we always have APIC integrated on 64bit mode
240 * - 82489DXs do not report # of LVT entries
242 return APIC_INTEGRATED(GET_APIC_VERSION(v
)) ? GET_APIC_MAXLVT(v
) : 2;
246 * This function sets up the local APIC timer, with a timeout of
247 * 'clocks' APIC bus clock. During calibration we actually call
248 * this function twice on the boot CPU, once with a bogus timeout
249 * value, second time for real. The other (noncalibrating) CPUs
250 * call this function only once, with the real, calibrated value.
252 * We do reads before writes even if unnecessary, to get around the
253 * P5 APIC double write bug.
256 static void __setup_APIC_LVTT(unsigned int clocks
, int oneshot
, int irqen
)
258 unsigned int lvtt_value
, tmp_value
;
260 lvtt_value
= LOCAL_TIMER_VECTOR
;
262 lvtt_value
|= APIC_LVT_TIMER_PERIODIC
;
264 lvtt_value
|= APIC_LVT_MASKED
;
266 apic_write(APIC_LVTT
, lvtt_value
);
271 tmp_value
= apic_read(APIC_TDCR
);
272 apic_write(APIC_TDCR
, (tmp_value
273 & ~(APIC_TDR_DIV_1
| APIC_TDR_DIV_TMBASE
))
277 apic_write(APIC_TMICT
, clocks
);
281 * Setup extended LVT, AMD specific (K8, family 10h)
283 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
284 * MCE interrupts are supported. Thus MCE offset must be set to 0.
287 #define APIC_EILVT_LVTOFF_MCE 0
288 #define APIC_EILVT_LVTOFF_IBS 1
290 static void setup_APIC_eilvt(u8 lvt_off
, u8 vector
, u8 msg_type
, u8 mask
)
292 unsigned long reg
= (lvt_off
<< 4) + APIC_EILVT0
;
293 unsigned int v
= (mask
<< 16) | (msg_type
<< 8) | vector
;
298 u8
setup_APIC_eilvt_mce(u8 vector
, u8 msg_type
, u8 mask
)
300 setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE
, vector
, msg_type
, mask
);
301 return APIC_EILVT_LVTOFF_MCE
;
304 u8
setup_APIC_eilvt_ibs(u8 vector
, u8 msg_type
, u8 mask
)
306 setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS
, vector
, msg_type
, mask
);
307 return APIC_EILVT_LVTOFF_IBS
;
311 * Program the next event, relative to now
313 static int lapic_next_event(unsigned long delta
,
314 struct clock_event_device
*evt
)
316 apic_write(APIC_TMICT
, delta
);
321 * Setup the lapic timer in periodic or oneshot mode
323 static void lapic_timer_setup(enum clock_event_mode mode
,
324 struct clock_event_device
*evt
)
329 /* Lapic used as dummy for broadcast ? */
330 if (evt
->features
& CLOCK_EVT_FEAT_DUMMY
)
333 local_irq_save(flags
);
336 case CLOCK_EVT_MODE_PERIODIC
:
337 case CLOCK_EVT_MODE_ONESHOT
:
338 __setup_APIC_LVTT(calibration_result
,
339 mode
!= CLOCK_EVT_MODE_PERIODIC
, 1);
341 case CLOCK_EVT_MODE_UNUSED
:
342 case CLOCK_EVT_MODE_SHUTDOWN
:
343 v
= apic_read(APIC_LVTT
);
344 v
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
345 apic_write(APIC_LVTT
, v
);
347 case CLOCK_EVT_MODE_RESUME
:
348 /* Nothing to do here */
352 local_irq_restore(flags
);
356 * Local APIC timer broadcast function
358 static void lapic_timer_broadcast(cpumask_t mask
)
361 send_IPI_mask(mask
, LOCAL_TIMER_VECTOR
);
366 * Setup the local APIC timer for this CPU. Copy the initilized values
367 * of the boot CPU and register the clock event in the framework.
369 static void setup_APIC_timer(void)
371 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
373 memcpy(levt
, &lapic_clockevent
, sizeof(*levt
));
374 levt
->cpumask
= cpumask_of_cpu(smp_processor_id());
376 clockevents_register_device(levt
);
380 * In this function we calibrate APIC bus clocks to the external
381 * timer. Unfortunately we cannot use jiffies and the timer irq
382 * to calibrate, since some later bootup code depends on getting
383 * the first irq? Ugh.
385 * We want to do the calibration only once since we
386 * want to have local timer irqs syncron. CPUs connected
387 * by the same APIC bus have the very same bus frequency.
388 * And we want to have irqs off anyways, no accidental
392 #define TICK_COUNT 100000000
394 static int __init
calibrate_APIC_clock(void)
396 unsigned apic
, apic_start
;
397 unsigned long tsc
, tsc_start
;
403 * Put whatever arbitrary (but long enough) timeout
404 * value into the APIC clock, we just want to get the
405 * counter running for calibration.
407 * No interrupt enable !
409 __setup_APIC_LVTT(250000000, 0, 0);
411 apic_start
= apic_read(APIC_TMCCT
);
412 #ifdef CONFIG_X86_PM_TIMER
413 if (apic_calibrate_pmtmr
&& pmtmr_ioport
) {
414 pmtimer_wait(5000); /* 5ms wait */
415 apic
= apic_read(APIC_TMCCT
);
416 result
= (apic_start
- apic
) * 1000L / 5;
423 apic
= apic_read(APIC_TMCCT
);
425 } while ((tsc
- tsc_start
) < TICK_COUNT
&&
426 (apic_start
- apic
) < TICK_COUNT
);
428 result
= (apic_start
- apic
) * 1000L * tsc_khz
/
434 printk(KERN_DEBUG
"APIC timer calibration result %d\n", result
);
436 printk(KERN_INFO
"Detected %d.%03d MHz APIC timer.\n",
437 result
/ 1000 / 1000, result
/ 1000 % 1000);
439 /* Calculate the scaled math multiplication factor */
440 lapic_clockevent
.mult
= div_sc(result
, NSEC_PER_SEC
,
441 lapic_clockevent
.shift
);
442 lapic_clockevent
.max_delta_ns
=
443 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent
);
444 lapic_clockevent
.min_delta_ns
=
445 clockevent_delta2ns(0xF, &lapic_clockevent
);
447 calibration_result
= result
/ HZ
;
450 * Do a sanity check on the APIC calibration result
452 if (calibration_result
< (1000000 / HZ
)) {
454 "APIC frequency too slow, disabling apic timer\n");
462 * Setup the boot APIC
464 * Calibrate and verify the result.
466 void __init
setup_boot_APIC_clock(void)
469 * The local apic timer can be disabled via the kernel commandline.
470 * Register the lapic timer as a dummy clock event source on SMP
471 * systems, so the broadcast mechanism is used. On UP systems simply
474 if (disable_apic_timer
) {
475 printk(KERN_INFO
"Disabling APIC timer\n");
476 /* No broadcast on UP ! */
477 if (num_possible_cpus() > 1) {
478 lapic_clockevent
.mult
= 1;
484 printk(KERN_INFO
"Using local APIC timer interrupts.\n");
485 if (calibrate_APIC_clock()) {
486 /* No broadcast on UP ! */
487 if (num_possible_cpus() > 1)
493 * If nmi_watchdog is set to IO_APIC, we need the
494 * PIT/HPET going. Otherwise register lapic as a dummy
497 if (nmi_watchdog
!= NMI_IO_APIC
)
498 lapic_clockevent
.features
&= ~CLOCK_EVT_FEAT_DUMMY
;
500 printk(KERN_WARNING
"APIC timer registered as dummy,"
501 " due to nmi_watchdog=%d!\n", nmi_watchdog
);
506 void __cpuinit
setup_secondary_APIC_clock(void)
512 * The guts of the apic timer interrupt
514 static void local_apic_timer_interrupt(void)
516 int cpu
= smp_processor_id();
517 struct clock_event_device
*evt
= &per_cpu(lapic_events
, cpu
);
520 * Normally we should not be here till LAPIC has been initialized but
521 * in some cases like kdump, its possible that there is a pending LAPIC
522 * timer interrupt from previous kernel's context and is delivered in
523 * new kernel the moment interrupts are enabled.
525 * Interrupts are enabled early and LAPIC is setup much later, hence
526 * its possible that when we get here evt->event_handler is NULL.
527 * Check for event_handler being NULL and discard the interrupt as
530 if (!evt
->event_handler
) {
532 "Spurious LAPIC timer interrupt on cpu %d\n", cpu
);
534 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, evt
);
539 * the NMI deadlock-detector uses this.
541 add_pda(apic_timer_irqs
, 1);
543 evt
->event_handler(evt
);
547 * Local APIC timer interrupt. This is the most natural way for doing
548 * local interrupts, but local timer interrupts can be emulated by
549 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
551 * [ if a single-CPU system runs an SMP kernel then we call the local
552 * interrupt as well. Thus we cannot inline the local irq ... ]
554 void smp_apic_timer_interrupt(struct pt_regs
*regs
)
556 struct pt_regs
*old_regs
= set_irq_regs(regs
);
559 * NOTE! We'd better ACK the irq immediately,
560 * because timer handling can be slow.
564 * update_process_times() expects us to have done irq_enter().
565 * Besides, if we don't timer interrupts ignore the global
566 * interrupt lock, which is the WrongThing (tm) to do.
570 local_apic_timer_interrupt();
572 set_irq_regs(old_regs
);
575 int setup_profiling_timer(unsigned int multiplier
)
582 * Local APIC start and shutdown
586 * clear_local_APIC - shutdown the local APIC
588 * This is called, when a CPU is disabled and before rebooting, so the state of
589 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
590 * leftovers during boot.
592 void clear_local_APIC(void)
597 /* APIC hasn't been mapped yet */
601 maxlvt
= lapic_get_maxlvt();
603 * Masking an LVT entry can trigger a local APIC error
604 * if the vector is zero. Mask LVTERR first to prevent this.
607 v
= ERROR_APIC_VECTOR
; /* any non-zero vector will do */
608 apic_write(APIC_LVTERR
, v
| APIC_LVT_MASKED
);
611 * Careful: we have to set masks only first to deassert
612 * any level-triggered sources.
614 v
= apic_read(APIC_LVTT
);
615 apic_write(APIC_LVTT
, v
| APIC_LVT_MASKED
);
616 v
= apic_read(APIC_LVT0
);
617 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
618 v
= apic_read(APIC_LVT1
);
619 apic_write(APIC_LVT1
, v
| APIC_LVT_MASKED
);
621 v
= apic_read(APIC_LVTPC
);
622 apic_write(APIC_LVTPC
, v
| APIC_LVT_MASKED
);
626 * Clean APIC state for other OSs:
628 apic_write(APIC_LVTT
, APIC_LVT_MASKED
);
629 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
630 apic_write(APIC_LVT1
, APIC_LVT_MASKED
);
632 apic_write(APIC_LVTERR
, APIC_LVT_MASKED
);
634 apic_write(APIC_LVTPC
, APIC_LVT_MASKED
);
635 apic_write(APIC_ESR
, 0);
640 * disable_local_APIC - clear and disable the local APIC
642 void disable_local_APIC(void)
649 * Disable APIC (implies clearing of registers
652 value
= apic_read(APIC_SPIV
);
653 value
&= ~APIC_SPIV_APIC_ENABLED
;
654 apic_write(APIC_SPIV
, value
);
657 void lapic_shutdown(void)
664 local_irq_save(flags
);
666 disable_local_APIC();
668 local_irq_restore(flags
);
672 * This is to verify that we're looking at a real local APIC.
673 * Check these against your board if the CPUs aren't getting
674 * started for no apparent reason.
676 int __init
verify_local_APIC(void)
678 unsigned int reg0
, reg1
;
681 * The version register is read-only in a real APIC.
683 reg0
= apic_read(APIC_LVR
);
684 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg0
);
685 apic_write(APIC_LVR
, reg0
^ APIC_LVR_MASK
);
686 reg1
= apic_read(APIC_LVR
);
687 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg1
);
690 * The two version reads above should print the same
691 * numbers. If the second one is different, then we
692 * poke at a non-APIC.
698 * Check if the version looks reasonably.
700 reg1
= GET_APIC_VERSION(reg0
);
701 if (reg1
== 0x00 || reg1
== 0xff)
703 reg1
= lapic_get_maxlvt();
704 if (reg1
< 0x02 || reg1
== 0xff)
708 * The ID register is read/write in a real APIC.
710 reg0
= apic_read(APIC_ID
);
711 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg0
);
712 apic_write(APIC_ID
, reg0
^ APIC_ID_MASK
);
713 reg1
= apic_read(APIC_ID
);
714 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg1
);
715 apic_write(APIC_ID
, reg0
);
716 if (reg1
!= (reg0
^ APIC_ID_MASK
))
720 * The next two are just to see if we have sane values.
721 * They're only really relevant if we're in Virtual Wire
722 * compatibility mode, but most boxes are anymore.
724 reg0
= apic_read(APIC_LVT0
);
725 apic_printk(APIC_DEBUG
, "Getting LVT0: %x\n", reg0
);
726 reg1
= apic_read(APIC_LVT1
);
727 apic_printk(APIC_DEBUG
, "Getting LVT1: %x\n", reg1
);
733 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
735 void __init
sync_Arb_IDs(void)
737 /* Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 */
744 apic_wait_icr_idle();
746 apic_printk(APIC_DEBUG
, "Synchronizing Arb IDs.\n");
747 apic_write(APIC_ICR
, APIC_DEST_ALLINC
| APIC_INT_LEVELTRIG
752 * An initial setup of the virtual wire mode.
754 void __init
init_bsp_APIC(void)
759 * Don't do the setup now if we have a SMP BIOS as the
760 * through-I/O-APIC virtual wire mode might be active.
762 if (smp_found_config
|| !cpu_has_apic
)
765 value
= apic_read(APIC_LVR
);
768 * Do not trust the local APIC being empty at bootup.
775 value
= apic_read(APIC_SPIV
);
776 value
&= ~APIC_VECTOR_MASK
;
777 value
|= APIC_SPIV_APIC_ENABLED
;
778 value
|= APIC_SPIV_FOCUS_DISABLED
;
779 value
|= SPURIOUS_APIC_VECTOR
;
780 apic_write(APIC_SPIV
, value
);
783 * Set up the virtual wire mode.
785 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
787 apic_write(APIC_LVT1
, value
);
791 * setup_local_APIC - setup the local APIC
793 void __cpuinit
setup_local_APIC(void)
799 value
= apic_read(APIC_LVR
);
801 BUILD_BUG_ON((SPURIOUS_APIC_VECTOR
& 0x0f) != 0x0f);
804 * Double-check whether this APIC is really registered.
805 * This is meaningless in clustered apic mode, so we skip it.
807 if (!apic_id_registered())
811 * Intel recommends to set DFR, LDR and TPR before enabling
812 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
813 * document number 292116). So here it goes...
818 * Set Task Priority to 'accept all'. We never change this
821 value
= apic_read(APIC_TASKPRI
);
822 value
&= ~APIC_TPRI_MASK
;
823 apic_write(APIC_TASKPRI
, value
);
826 * After a crash, we no longer service the interrupts and a pending
827 * interrupt from previous kernel might still have ISR bit set.
829 * Most probably by now CPU has serviced that pending interrupt and
830 * it might not have done the ack_APIC_irq() because it thought,
831 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
832 * does not clear the ISR bit and cpu thinks it has already serivced
833 * the interrupt. Hence a vector might get locked. It was noticed
834 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
836 for (i
= APIC_ISR_NR
- 1; i
>= 0; i
--) {
837 value
= apic_read(APIC_ISR
+ i
*0x10);
838 for (j
= 31; j
>= 0; j
--) {
845 * Now that we are all set up, enable the APIC
847 value
= apic_read(APIC_SPIV
);
848 value
&= ~APIC_VECTOR_MASK
;
852 value
|= APIC_SPIV_APIC_ENABLED
;
854 /* We always use processor focus */
857 * Set spurious IRQ vector
859 value
|= SPURIOUS_APIC_VECTOR
;
860 apic_write(APIC_SPIV
, value
);
865 * set up through-local-APIC on the BP's LINT0. This is not
866 * strictly necessary in pure symmetric-IO mode, but sometimes
867 * we delegate interrupts to the 8259A.
870 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
872 value
= apic_read(APIC_LVT0
) & APIC_LVT_MASKED
;
873 if (!smp_processor_id() && !value
) {
874 value
= APIC_DM_EXTINT
;
875 apic_printk(APIC_VERBOSE
, "enabled ExtINT on CPU#%d\n",
878 value
= APIC_DM_EXTINT
| APIC_LVT_MASKED
;
879 apic_printk(APIC_VERBOSE
, "masked ExtINT on CPU#%d\n",
882 apic_write(APIC_LVT0
, value
);
885 * only the BP should see the LINT1 NMI signal, obviously.
887 if (!smp_processor_id())
890 value
= APIC_DM_NMI
| APIC_LVT_MASKED
;
891 apic_write(APIC_LVT1
, value
);
895 static void __cpuinit
lapic_setup_esr(void)
897 unsigned maxlvt
= lapic_get_maxlvt();
899 apic_write(APIC_LVTERR
, ERROR_APIC_VECTOR
);
901 * spec says clear errors after enabling vector.
904 apic_write(APIC_ESR
, 0);
907 void __cpuinit
end_local_APIC_setup(void)
910 setup_apic_nmi_watchdog(NULL
);
914 void check_x2apic(void)
918 rdmsr(MSR_IA32_APICBASE
, msr
, msr2
);
920 if (msr
& X2APIC_ENABLE
) {
921 printk("x2apic enabled by BIOS, switching to x2apic ops\n");
922 x2apic_preenabled
= x2apic
= 1;
923 apic_ops
= &x2apic_ops
;
927 void enable_x2apic(void)
931 rdmsr(MSR_IA32_APICBASE
, msr
, msr2
);
932 if (!(msr
& X2APIC_ENABLE
)) {
933 printk("Enabling x2apic\n");
934 wrmsr(MSR_IA32_APICBASE
, msr
| X2APIC_ENABLE
, 0);
938 void enable_IR_x2apic(void)
940 #ifdef CONFIG_INTR_REMAP
947 if (!x2apic_preenabled
&& disable_x2apic
) {
949 "Skipped enabling x2apic and Interrupt-remapping "
950 "because of nox2apic\n");
954 if (x2apic_preenabled
&& disable_x2apic
)
955 panic("Bios already enabled x2apic, can't enforce nox2apic");
957 if (!x2apic_preenabled
&& skip_ioapic_setup
) {
959 "Skipped enabling x2apic and Interrupt-remapping "
960 "because of skipping io-apic setup\n");
964 ret
= dmar_table_init();
967 "dmar_table_init() failed with %d:\n", ret
);
969 if (x2apic_preenabled
)
970 panic("x2apic enabled by bios. But IR enabling failed");
973 "Not enabling x2apic,Intr-remapping\n");
977 local_irq_save(flags
);
979 save_mask_IO_APIC_setup();
981 ret
= enable_intr_remapping(1);
983 if (ret
&& x2apic_preenabled
) {
984 local_irq_restore(flags
);
985 panic("x2apic enabled by bios. But IR enabling failed");
993 apic_ops
= &x2apic_ops
;
1001 restore_IO_APIC_setup();
1003 reinit_intr_remapped_IO_APIC(x2apic_preenabled
);
1006 local_irq_restore(flags
);
1009 if (!x2apic_preenabled
)
1011 "Enabled x2apic and interrupt-remapping\n");
1014 "Enabled Interrupt-remapping\n");
1017 "Failed to enable Interrupt-remapping and x2apic\n");
1019 if (!cpu_has_x2apic
)
1022 if (x2apic_preenabled
)
1023 panic("x2apic enabled prior OS handover,"
1024 " enable CONFIG_INTR_REMAP");
1026 printk(KERN_INFO
"Enable CONFIG_INTR_REMAP for enabling intr-remapping "
1034 * Detect and enable local APICs on non-SMP boards.
1035 * Original code written by Keir Fraser.
1036 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1037 * not correctly set up (usually the APIC timer won't work etc.)
1039 static int __init
detect_init_APIC(void)
1041 if (!cpu_has_apic
) {
1042 printk(KERN_INFO
"No local APIC present\n");
1046 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
1047 boot_cpu_physical_apicid
= 0;
1051 void __init
early_init_lapic_mapping(void)
1053 unsigned long phys_addr
;
1056 * If no local APIC can be found then go out
1057 * : it means there is no mpatable and MADT
1059 if (!smp_found_config
)
1062 phys_addr
= mp_lapic_addr
;
1064 set_fixmap_nocache(FIX_APIC_BASE
, phys_addr
);
1065 apic_printk(APIC_VERBOSE
, "mapped APIC to %16lx (%16lx)\n",
1066 APIC_BASE
, phys_addr
);
1069 * Fetch the APIC ID of the BSP in case we have a
1070 * default configuration (or the MP table is broken).
1072 boot_cpu_physical_apicid
= read_apic_id();
1076 * init_apic_mappings - initialize APIC mappings
1078 void __init
init_apic_mappings(void)
1081 boot_cpu_physical_apicid
= read_apic_id();
1086 * If no local APIC can be found then set up a fake all
1087 * zeroes page to simulate the local APIC and another
1088 * one for the IO-APIC.
1090 if (!smp_found_config
&& detect_init_APIC()) {
1091 apic_phys
= (unsigned long) alloc_bootmem_pages(PAGE_SIZE
);
1092 apic_phys
= __pa(apic_phys
);
1094 apic_phys
= mp_lapic_addr
;
1096 set_fixmap_nocache(FIX_APIC_BASE
, apic_phys
);
1097 apic_printk(APIC_VERBOSE
, "mapped APIC to %16lx (%16lx)\n",
1098 APIC_BASE
, apic_phys
);
1101 * Fetch the APIC ID of the BSP in case we have a
1102 * default configuration (or the MP table is broken).
1104 boot_cpu_physical_apicid
= read_apic_id();
1108 * This initializes the IO-APIC and APIC hardware if this is
1111 int __init
APIC_init_uniprocessor(void)
1114 printk(KERN_INFO
"Apic disabled\n");
1117 if (!cpu_has_apic
) {
1119 printk(KERN_INFO
"Apic disabled by BIOS\n");
1124 setup_apic_routing();
1126 verify_local_APIC();
1130 physid_set_mask_of_physid(boot_cpu_physical_apicid
, &phys_cpu_present_map
);
1131 apic_write(APIC_ID
, SET_APIC_ID(boot_cpu_physical_apicid
));
1136 * Now enable IO-APICs, actually call clear_IO_APIC
1137 * We need clear_IO_APIC before enabling vector on BP
1139 if (!skip_ioapic_setup
&& nr_ioapics
)
1142 if (!smp_found_config
|| skip_ioapic_setup
|| !nr_ioapics
)
1143 localise_nmi_watchdog();
1144 end_local_APIC_setup();
1146 if (smp_found_config
&& !skip_ioapic_setup
&& nr_ioapics
)
1150 setup_boot_APIC_clock();
1151 check_nmi_watchdog();
1156 * Local APIC interrupts
1160 * This interrupt should _never_ happen with our APIC/SMP architecture
1162 asmlinkage
void smp_spurious_interrupt(void)
1168 * Check if this really is a spurious interrupt and ACK it
1169 * if it is a vectored one. Just in case...
1170 * Spurious interrupts should not be ACKed.
1172 v
= apic_read(APIC_ISR
+ ((SPURIOUS_APIC_VECTOR
& ~0x1f) >> 1));
1173 if (v
& (1 << (SPURIOUS_APIC_VECTOR
& 0x1f)))
1176 add_pda(irq_spurious_count
, 1);
1181 * This interrupt should never happen with our APIC/SMP architecture
1183 asmlinkage
void smp_error_interrupt(void)
1189 /* First tickle the hardware, only then report what went on. -- REW */
1190 v
= apic_read(APIC_ESR
);
1191 apic_write(APIC_ESR
, 0);
1192 v1
= apic_read(APIC_ESR
);
1194 atomic_inc(&irq_err_count
);
1196 /* Here is what the APIC error bits mean:
1199 2: Send accept error
1200 3: Receive accept error
1202 5: Send illegal vector
1203 6: Received illegal vector
1204 7: Illegal register address
1206 printk(KERN_DEBUG
"APIC error on CPU%d: %02x(%02x)\n",
1207 smp_processor_id(), v
, v1
);
1212 * * connect_bsp_APIC - attach the APIC to the interrupt system
1214 void __init
connect_bsp_APIC(void)
1219 void disconnect_bsp_APIC(int virt_wire_setup
)
1221 /* Go back to Virtual Wire compatibility mode */
1222 unsigned long value
;
1224 /* For the spurious interrupt use vector F, and enable it */
1225 value
= apic_read(APIC_SPIV
);
1226 value
&= ~APIC_VECTOR_MASK
;
1227 value
|= APIC_SPIV_APIC_ENABLED
;
1229 apic_write(APIC_SPIV
, value
);
1231 if (!virt_wire_setup
) {
1233 * For LVT0 make it edge triggered, active high,
1234 * external and enabled
1236 value
= apic_read(APIC_LVT0
);
1237 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1238 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1239 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1240 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1241 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_EXTINT
);
1242 apic_write(APIC_LVT0
, value
);
1245 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
1248 /* For LVT1 make it edge triggered, active high, nmi and enabled */
1249 value
= apic_read(APIC_LVT1
);
1250 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1251 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1252 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1253 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1254 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_NMI
);
1255 apic_write(APIC_LVT1
, value
);
1258 void __cpuinit
generic_processor_info(int apicid
, int version
)
1263 if (num_processors
>= NR_CPUS
) {
1264 printk(KERN_WARNING
"WARNING: NR_CPUS limit of %i reached."
1265 " Processor ignored.\n", NR_CPUS
);
1270 cpus_complement(tmp_map
, cpu_present_map
);
1271 cpu
= first_cpu(tmp_map
);
1273 physid_set(apicid
, phys_cpu_present_map
);
1274 if (apicid
== boot_cpu_physical_apicid
) {
1276 * x86_bios_cpu_apicid is required to have processors listed
1277 * in same order as logical cpu numbers. Hence the first
1278 * entry is BSP, and so on.
1282 if (apicid
> max_physical_apicid
)
1283 max_physical_apicid
= apicid
;
1285 /* are we being called early in kernel startup? */
1286 if (early_per_cpu_ptr(x86_cpu_to_apicid
)) {
1287 u16
*cpu_to_apicid
= early_per_cpu_ptr(x86_cpu_to_apicid
);
1288 u16
*bios_cpu_apicid
= early_per_cpu_ptr(x86_bios_cpu_apicid
);
1290 cpu_to_apicid
[cpu
] = apicid
;
1291 bios_cpu_apicid
[cpu
] = apicid
;
1293 per_cpu(x86_cpu_to_apicid
, cpu
) = apicid
;
1294 per_cpu(x86_bios_cpu_apicid
, cpu
) = apicid
;
1297 cpu_set(cpu
, cpu_possible_map
);
1298 cpu_set(cpu
, cpu_present_map
);
1301 int hard_smp_processor_id(void)
1303 return read_apic_id();
1312 /* 'active' is true if the local APIC was enabled by us and
1313 not the BIOS; this signifies that we are also responsible
1314 for disabling it before entering apm/acpi suspend */
1316 /* r/w apic fields */
1317 unsigned int apic_id
;
1318 unsigned int apic_taskpri
;
1319 unsigned int apic_ldr
;
1320 unsigned int apic_dfr
;
1321 unsigned int apic_spiv
;
1322 unsigned int apic_lvtt
;
1323 unsigned int apic_lvtpc
;
1324 unsigned int apic_lvt0
;
1325 unsigned int apic_lvt1
;
1326 unsigned int apic_lvterr
;
1327 unsigned int apic_tmict
;
1328 unsigned int apic_tdcr
;
1329 unsigned int apic_thmr
;
1332 static int lapic_suspend(struct sys_device
*dev
, pm_message_t state
)
1334 unsigned long flags
;
1337 if (!apic_pm_state
.active
)
1340 maxlvt
= lapic_get_maxlvt();
1342 apic_pm_state
.apic_id
= apic_read(APIC_ID
);
1343 apic_pm_state
.apic_taskpri
= apic_read(APIC_TASKPRI
);
1344 apic_pm_state
.apic_ldr
= apic_read(APIC_LDR
);
1345 apic_pm_state
.apic_dfr
= apic_read(APIC_DFR
);
1346 apic_pm_state
.apic_spiv
= apic_read(APIC_SPIV
);
1347 apic_pm_state
.apic_lvtt
= apic_read(APIC_LVTT
);
1349 apic_pm_state
.apic_lvtpc
= apic_read(APIC_LVTPC
);
1350 apic_pm_state
.apic_lvt0
= apic_read(APIC_LVT0
);
1351 apic_pm_state
.apic_lvt1
= apic_read(APIC_LVT1
);
1352 apic_pm_state
.apic_lvterr
= apic_read(APIC_LVTERR
);
1353 apic_pm_state
.apic_tmict
= apic_read(APIC_TMICT
);
1354 apic_pm_state
.apic_tdcr
= apic_read(APIC_TDCR
);
1355 #ifdef CONFIG_X86_MCE_INTEL
1357 apic_pm_state
.apic_thmr
= apic_read(APIC_LVTTHMR
);
1359 local_irq_save(flags
);
1360 disable_local_APIC();
1361 local_irq_restore(flags
);
1365 static int lapic_resume(struct sys_device
*dev
)
1368 unsigned long flags
;
1371 if (!apic_pm_state
.active
)
1374 maxlvt
= lapic_get_maxlvt();
1376 local_irq_save(flags
);
1378 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1379 l
&= ~MSR_IA32_APICBASE_BASE
;
1380 l
|= MSR_IA32_APICBASE_ENABLE
| mp_lapic_addr
;
1381 wrmsr(MSR_IA32_APICBASE
, l
, h
);
1385 apic_write(APIC_LVTERR
, ERROR_APIC_VECTOR
| APIC_LVT_MASKED
);
1386 apic_write(APIC_ID
, apic_pm_state
.apic_id
);
1387 apic_write(APIC_DFR
, apic_pm_state
.apic_dfr
);
1388 apic_write(APIC_LDR
, apic_pm_state
.apic_ldr
);
1389 apic_write(APIC_TASKPRI
, apic_pm_state
.apic_taskpri
);
1390 apic_write(APIC_SPIV
, apic_pm_state
.apic_spiv
);
1391 apic_write(APIC_LVT0
, apic_pm_state
.apic_lvt0
);
1392 apic_write(APIC_LVT1
, apic_pm_state
.apic_lvt1
);
1393 #ifdef CONFIG_X86_MCE_INTEL
1395 apic_write(APIC_LVTTHMR
, apic_pm_state
.apic_thmr
);
1398 apic_write(APIC_LVTPC
, apic_pm_state
.apic_lvtpc
);
1399 apic_write(APIC_LVTT
, apic_pm_state
.apic_lvtt
);
1400 apic_write(APIC_TDCR
, apic_pm_state
.apic_tdcr
);
1401 apic_write(APIC_TMICT
, apic_pm_state
.apic_tmict
);
1402 apic_write(APIC_ESR
, 0);
1403 apic_read(APIC_ESR
);
1404 apic_write(APIC_LVTERR
, apic_pm_state
.apic_lvterr
);
1405 apic_write(APIC_ESR
, 0);
1406 apic_read(APIC_ESR
);
1407 local_irq_restore(flags
);
1411 static struct sysdev_class lapic_sysclass
= {
1413 .resume
= lapic_resume
,
1414 .suspend
= lapic_suspend
,
1417 static struct sys_device device_lapic
= {
1419 .cls
= &lapic_sysclass
,
1422 static void __cpuinit
apic_pm_activate(void)
1424 apic_pm_state
.active
= 1;
1427 static int __init
init_lapic_sysfs(void)
1433 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
1435 error
= sysdev_class_register(&lapic_sysclass
);
1437 error
= sysdev_register(&device_lapic
);
1440 device_initcall(init_lapic_sysfs
);
1442 #else /* CONFIG_PM */
1444 static void apic_pm_activate(void) { }
1446 #endif /* CONFIG_PM */
1449 * apic_is_clustered_box() -- Check if we can expect good TSC
1451 * Thus far, the major user of this is IBM's Summit2 series:
1453 * Clustered boxes may have unsynced TSC problems if they are
1454 * multi-chassis. Use available data to take a good guess.
1455 * If in doubt, go HPET.
1457 __cpuinit
int apic_is_clustered_box(void)
1459 int i
, clusters
, zeros
;
1461 u16
*bios_cpu_apicid
;
1462 DECLARE_BITMAP(clustermap
, NUM_APIC_CLUSTERS
);
1465 * there is not this kind of box with AMD CPU yet.
1466 * Some AMD box with quadcore cpu and 8 sockets apicid
1467 * will be [4, 0x23] or [8, 0x27] could be thought to
1468 * vsmp box still need checking...
1470 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
) && !is_vsmp_box())
1473 bios_cpu_apicid
= early_per_cpu_ptr(x86_bios_cpu_apicid
);
1474 bitmap_zero(clustermap
, NUM_APIC_CLUSTERS
);
1476 for (i
= 0; i
< NR_CPUS
; i
++) {
1477 /* are we being called early in kernel startup? */
1478 if (bios_cpu_apicid
) {
1479 id
= bios_cpu_apicid
[i
];
1481 else if (i
< nr_cpu_ids
) {
1483 id
= per_cpu(x86_bios_cpu_apicid
, i
);
1490 if (id
!= BAD_APICID
)
1491 __set_bit(APIC_CLUSTERID(id
), clustermap
);
1494 /* Problem: Partially populated chassis may not have CPUs in some of
1495 * the APIC clusters they have been allocated. Only present CPUs have
1496 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap.
1497 * Since clusters are allocated sequentially, count zeros only if
1498 * they are bounded by ones.
1502 for (i
= 0; i
< NUM_APIC_CLUSTERS
; i
++) {
1503 if (test_bit(i
, clustermap
)) {
1504 clusters
+= 1 + zeros
;
1510 /* ScaleMP vSMPowered boxes have one cluster per board and TSCs are
1511 * not guaranteed to be synced between boards
1513 if (is_vsmp_box() && clusters
> 1)
1517 * If clusters > 2, then should be multi-chassis.
1518 * May have to revisit this when multi-core + hyperthreaded CPUs come
1519 * out, but AFAIK this will work even for them.
1521 return (clusters
> 2);
1524 static __init
int setup_nox2apic(char *str
)
1527 clear_cpu_cap(&boot_cpu_data
, X86_FEATURE_X2APIC
);
1530 early_param("nox2apic", setup_nox2apic
);
1534 * APIC command line parameters
1536 static int __init
apic_set_verbosity(char *str
)
1539 skip_ioapic_setup
= 0;
1543 if (strcmp("debug", str
) == 0)
1544 apic_verbosity
= APIC_DEBUG
;
1545 else if (strcmp("verbose", str
) == 0)
1546 apic_verbosity
= APIC_VERBOSE
;
1548 printk(KERN_WARNING
"APIC Verbosity level %s not recognised"
1549 " use apic=verbose or apic=debug\n", str
);
1555 early_param("apic", apic_set_verbosity
);
1557 static __init
int setup_disableapic(char *str
)
1560 setup_clear_cpu_cap(X86_FEATURE_APIC
);
1563 early_param("disableapic", setup_disableapic
);
1565 /* same as disableapic, for compatibility */
1566 static __init
int setup_nolapic(char *str
)
1568 return setup_disableapic(str
);
1570 early_param("nolapic", setup_nolapic
);
1572 static int __init
parse_lapic_timer_c2_ok(char *arg
)
1574 local_apic_timer_c2_ok
= 1;
1577 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok
);
1579 static __init
int setup_noapictimer(char *str
)
1581 if (str
[0] != ' ' && str
[0] != 0)
1583 disable_apic_timer
= 1;
1586 __setup("noapictimer", setup_noapictimer
);
1588 static __init
int setup_apicpmtimer(char *s
)
1590 apic_calibrate_pmtmr
= 1;
1594 __setup("apicpmtimer", setup_apicpmtimer
);
1596 static int __init
lapic_insert_resource(void)
1601 /* Put local APIC into the resource map. */
1602 lapic_resource
.start
= apic_phys
;
1603 lapic_resource
.end
= lapic_resource
.start
+ PAGE_SIZE
- 1;
1604 insert_resource(&iomem_resource
, &lapic_resource
);
1610 * need call insert after e820_reserve_resources()
1611 * that is using request_resource
1613 late_initcall(lapic_insert_resource
);