2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/bootmem.h>
22 #include <linux/interrupt.h>
23 #include <linux/mc146818rtc.h>
24 #include <linux/kernel_stat.h>
25 #include <linux/sysdev.h>
26 #include <linux/ioport.h>
27 #include <linux/clockchips.h>
28 #include <linux/acpi_pmtmr.h>
29 #include <linux/module.h>
30 #include <linux/dmar.h>
32 #include <asm/atomic.h>
35 #include <asm/mpspec.h>
37 #include <asm/pgalloc.h>
40 #include <asm/proto.h>
41 #include <asm/timex.h>
43 #include <asm/i8259.h>
46 #include <mach_apic.h>
48 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
49 static int disable_apic_timer __cpuinitdata
;
50 static int apic_calibrate_pmtmr __initdata
;
55 /* x2apic enabled before OS handover */
56 int x2apic_preenabled
;
58 /* Local APIC timer works in C2 */
59 int local_apic_timer_c2_ok
;
60 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok
);
63 * Debug level, exported for io_apic.c
65 unsigned int apic_verbosity
;
67 /* Have we found an MP table */
70 static struct resource lapic_resource
= {
72 .flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
,
75 static unsigned int calibration_result
;
77 static int lapic_next_event(unsigned long delta
,
78 struct clock_event_device
*evt
);
79 static void lapic_timer_setup(enum clock_event_mode mode
,
80 struct clock_event_device
*evt
);
81 static void lapic_timer_broadcast(cpumask_t mask
);
82 static void apic_pm_activate(void);
85 * The local apic timer can be used for any function which is CPU local.
87 static struct clock_event_device lapic_clockevent
= {
89 .features
= CLOCK_EVT_FEAT_PERIODIC
| CLOCK_EVT_FEAT_ONESHOT
90 | CLOCK_EVT_FEAT_C3STOP
| CLOCK_EVT_FEAT_DUMMY
,
92 .set_mode
= lapic_timer_setup
,
93 .set_next_event
= lapic_next_event
,
94 .broadcast
= lapic_timer_broadcast
,
98 static DEFINE_PER_CPU(struct clock_event_device
, lapic_events
);
100 static unsigned long apic_phys
;
102 unsigned long mp_lapic_addr
;
105 * Get the LAPIC version
107 static inline int lapic_get_version(void)
109 return GET_APIC_VERSION(apic_read(APIC_LVR
));
113 * Check, if the APIC is integrated or a separate chip
115 static inline int lapic_is_integrated(void)
120 return APIC_INTEGRATED(lapic_get_version());
125 * Check, whether this is a modern or a first generation APIC
127 static int modern_apic(void)
129 /* AMD systems use old APIC versions, so check the CPU */
130 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
&&
131 boot_cpu_data
.x86
>= 0xf)
133 return lapic_get_version() >= 0x14;
137 * Paravirt kernels also might be using these below ops. So we still
138 * use generic apic_read()/apic_write(), which might be pointing to different
139 * ops in PARAVIRT case.
141 void xapic_wait_icr_idle(void)
143 while (apic_read(APIC_ICR
) & APIC_ICR_BUSY
)
147 u32
safe_xapic_wait_icr_idle(void)
154 send_status
= apic_read(APIC_ICR
) & APIC_ICR_BUSY
;
158 } while (timeout
++ < 1000);
163 void xapic_icr_write(u32 low
, u32 id
)
165 apic_write(APIC_ICR2
, SET_APIC_DEST_FIELD(id
));
166 apic_write(APIC_ICR
, low
);
169 u64
xapic_icr_read(void)
173 icr2
= apic_read(APIC_ICR2
);
174 icr1
= apic_read(APIC_ICR
);
176 return icr1
| ((u64
)icr2
<< 32);
179 static struct apic_ops xapic_ops
= {
180 .read
= native_apic_mem_read
,
181 .write
= native_apic_mem_write
,
182 .icr_read
= xapic_icr_read
,
183 .icr_write
= xapic_icr_write
,
184 .wait_icr_idle
= xapic_wait_icr_idle
,
185 .safe_wait_icr_idle
= safe_xapic_wait_icr_idle
,
188 struct apic_ops __read_mostly
*apic_ops
= &xapic_ops
;
189 EXPORT_SYMBOL_GPL(apic_ops
);
191 static void x2apic_wait_icr_idle(void)
193 /* no need to wait for icr idle in x2apic */
197 static u32
safe_x2apic_wait_icr_idle(void)
199 /* no need to wait for icr idle in x2apic */
203 void x2apic_icr_write(u32 low
, u32 id
)
205 wrmsrl(APIC_BASE_MSR
+ (APIC_ICR
>> 4), ((__u64
) id
) << 32 | low
);
208 u64
x2apic_icr_read(void)
212 rdmsrl(APIC_BASE_MSR
+ (APIC_ICR
>> 4), val
);
216 static struct apic_ops x2apic_ops
= {
217 .read
= native_apic_msr_read
,
218 .write
= native_apic_msr_write
,
219 .icr_read
= x2apic_icr_read
,
220 .icr_write
= x2apic_icr_write
,
221 .wait_icr_idle
= x2apic_wait_icr_idle
,
222 .safe_wait_icr_idle
= safe_x2apic_wait_icr_idle
,
226 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
228 void __cpuinit
enable_NMI_through_LVT0(void)
232 /* unmask and set to NMI */
235 /* Level triggered for 82489DX (32bit mode) */
236 if (!lapic_is_integrated())
237 v
|= APIC_LVT_LEVEL_TRIGGER
;
239 apic_write(APIC_LVT0
, v
);
243 * lapic_get_maxlvt - get the maximum number of local vector table entries
245 int lapic_get_maxlvt(void)
249 v
= apic_read(APIC_LVR
);
251 * - we always have APIC integrated on 64bit mode
252 * - 82489DXs do not report # of LVT entries
254 return APIC_INTEGRATED(GET_APIC_VERSION(v
)) ? GET_APIC_MAXLVT(v
) : 2;
263 #define APIC_DIVISOR 1
265 #define APIC_DIVISOR 16
269 * This function sets up the local APIC timer, with a timeout of
270 * 'clocks' APIC bus clock. During calibration we actually call
271 * this function twice on the boot CPU, once with a bogus timeout
272 * value, second time for real. The other (noncalibrating) CPUs
273 * call this function only once, with the real, calibrated value.
275 * We do reads before writes even if unnecessary, to get around the
276 * P5 APIC double write bug.
278 static void __setup_APIC_LVTT(unsigned int clocks
, int oneshot
, int irqen
)
280 unsigned int lvtt_value
, tmp_value
;
282 lvtt_value
= LOCAL_TIMER_VECTOR
;
284 lvtt_value
|= APIC_LVT_TIMER_PERIODIC
;
285 if (!lapic_is_integrated())
286 lvtt_value
|= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV
);
289 lvtt_value
|= APIC_LVT_MASKED
;
291 apic_write(APIC_LVTT
, lvtt_value
);
296 tmp_value
= apic_read(APIC_TDCR
);
297 apic_write(APIC_TDCR
,
298 (tmp_value
& ~(APIC_TDR_DIV_1
| APIC_TDR_DIV_TMBASE
)) |
302 apic_write(APIC_TMICT
, clocks
/ APIC_DIVISOR
);
306 * Setup extended LVT, AMD specific (K8, family 10h)
308 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
309 * MCE interrupts are supported. Thus MCE offset must be set to 0.
312 #define APIC_EILVT_LVTOFF_MCE 0
313 #define APIC_EILVT_LVTOFF_IBS 1
315 static void setup_APIC_eilvt(u8 lvt_off
, u8 vector
, u8 msg_type
, u8 mask
)
317 unsigned long reg
= (lvt_off
<< 4) + APIC_EILVT0
;
318 unsigned int v
= (mask
<< 16) | (msg_type
<< 8) | vector
;
323 u8
setup_APIC_eilvt_mce(u8 vector
, u8 msg_type
, u8 mask
)
325 setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE
, vector
, msg_type
, mask
);
326 return APIC_EILVT_LVTOFF_MCE
;
329 u8
setup_APIC_eilvt_ibs(u8 vector
, u8 msg_type
, u8 mask
)
331 setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS
, vector
, msg_type
, mask
);
332 return APIC_EILVT_LVTOFF_IBS
;
336 * Program the next event, relative to now
338 static int lapic_next_event(unsigned long delta
,
339 struct clock_event_device
*evt
)
341 apic_write(APIC_TMICT
, delta
);
346 * Setup the lapic timer in periodic or oneshot mode
348 static void lapic_timer_setup(enum clock_event_mode mode
,
349 struct clock_event_device
*evt
)
354 /* Lapic used as dummy for broadcast ? */
355 if (evt
->features
& CLOCK_EVT_FEAT_DUMMY
)
358 local_irq_save(flags
);
361 case CLOCK_EVT_MODE_PERIODIC
:
362 case CLOCK_EVT_MODE_ONESHOT
:
363 __setup_APIC_LVTT(calibration_result
,
364 mode
!= CLOCK_EVT_MODE_PERIODIC
, 1);
366 case CLOCK_EVT_MODE_UNUSED
:
367 case CLOCK_EVT_MODE_SHUTDOWN
:
368 v
= apic_read(APIC_LVTT
);
369 v
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
370 apic_write(APIC_LVTT
, v
);
372 case CLOCK_EVT_MODE_RESUME
:
373 /* Nothing to do here */
377 local_irq_restore(flags
);
381 * Local APIC timer broadcast function
383 static void lapic_timer_broadcast(cpumask_t mask
)
386 send_IPI_mask(mask
, LOCAL_TIMER_VECTOR
);
391 * Setup the local APIC timer for this CPU. Copy the initilized values
392 * of the boot CPU and register the clock event in the framework.
394 static void setup_APIC_timer(void)
396 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
398 memcpy(levt
, &lapic_clockevent
, sizeof(*levt
));
399 levt
->cpumask
= cpumask_of_cpu(smp_processor_id());
401 clockevents_register_device(levt
);
405 * In this function we calibrate APIC bus clocks to the external
406 * timer. Unfortunately we cannot use jiffies and the timer irq
407 * to calibrate, since some later bootup code depends on getting
408 * the first irq? Ugh.
410 * We want to do the calibration only once since we
411 * want to have local timer irqs syncron. CPUs connected
412 * by the same APIC bus have the very same bus frequency.
413 * And we want to have irqs off anyways, no accidental
417 #define TICK_COUNT 100000000
419 static int __init
calibrate_APIC_clock(void)
421 unsigned apic
, apic_start
;
422 unsigned long tsc
, tsc_start
;
428 * Put whatever arbitrary (but long enough) timeout
429 * value into the APIC clock, we just want to get the
430 * counter running for calibration.
432 * No interrupt enable !
434 __setup_APIC_LVTT(250000000, 0, 0);
436 apic_start
= apic_read(APIC_TMCCT
);
437 #ifdef CONFIG_X86_PM_TIMER
438 if (apic_calibrate_pmtmr
&& pmtmr_ioport
) {
439 pmtimer_wait(5000); /* 5ms wait */
440 apic
= apic_read(APIC_TMCCT
);
441 result
= (apic_start
- apic
) * 1000L / 5;
448 apic
= apic_read(APIC_TMCCT
);
450 } while ((tsc
- tsc_start
) < TICK_COUNT
&&
451 (apic_start
- apic
) < TICK_COUNT
);
453 result
= (apic_start
- apic
) * 1000L * tsc_khz
/
459 printk(KERN_DEBUG
"APIC timer calibration result %d\n", result
);
461 printk(KERN_INFO
"Detected %d.%03d MHz APIC timer.\n",
462 result
/ 1000 / 1000, result
/ 1000 % 1000);
464 /* Calculate the scaled math multiplication factor */
465 lapic_clockevent
.mult
= div_sc(result
, NSEC_PER_SEC
,
466 lapic_clockevent
.shift
);
467 lapic_clockevent
.max_delta_ns
=
468 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent
);
469 lapic_clockevent
.min_delta_ns
=
470 clockevent_delta2ns(0xF, &lapic_clockevent
);
472 calibration_result
= (result
* APIC_DIVISOR
) / HZ
;
475 * Do a sanity check on the APIC calibration result
477 if (calibration_result
< (1000000 / HZ
)) {
479 "APIC frequency too slow, disabling apic timer\n");
487 * Setup the boot APIC
489 * Calibrate and verify the result.
491 void __init
setup_boot_APIC_clock(void)
494 * The local apic timer can be disabled via the kernel
495 * commandline or from the CPU detection code. Register the lapic
496 * timer as a dummy clock event source on SMP systems, so the
497 * broadcast mechanism is used. On UP systems simply ignore it.
499 if (disable_apic_timer
) {
500 printk(KERN_INFO
"Disabling APIC timer\n");
501 /* No broadcast on UP ! */
502 if (num_possible_cpus() > 1) {
503 lapic_clockevent
.mult
= 1;
509 apic_printk(APIC_VERBOSE
, "Using local APIC timer interrupts.\n"
510 "calibrating APIC timer ...\n");
512 if (calibrate_APIC_clock()) {
513 /* No broadcast on UP ! */
514 if (num_possible_cpus() > 1)
520 * If nmi_watchdog is set to IO_APIC, we need the
521 * PIT/HPET going. Otherwise register lapic as a dummy
524 if (nmi_watchdog
!= NMI_IO_APIC
)
525 lapic_clockevent
.features
&= ~CLOCK_EVT_FEAT_DUMMY
;
527 printk(KERN_WARNING
"APIC timer registered as dummy,"
528 " due to nmi_watchdog=%d!\n", nmi_watchdog
);
530 /* Setup the lapic or request the broadcast */
534 void __cpuinit
setup_secondary_APIC_clock(void)
540 * The guts of the apic timer interrupt
542 static void local_apic_timer_interrupt(void)
544 int cpu
= smp_processor_id();
545 struct clock_event_device
*evt
= &per_cpu(lapic_events
, cpu
);
548 * Normally we should not be here till LAPIC has been initialized but
549 * in some cases like kdump, its possible that there is a pending LAPIC
550 * timer interrupt from previous kernel's context and is delivered in
551 * new kernel the moment interrupts are enabled.
553 * Interrupts are enabled early and LAPIC is setup much later, hence
554 * its possible that when we get here evt->event_handler is NULL.
555 * Check for event_handler being NULL and discard the interrupt as
558 if (!evt
->event_handler
) {
560 "Spurious LAPIC timer interrupt on cpu %d\n", cpu
);
562 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, evt
);
567 * the NMI deadlock-detector uses this.
570 add_pda(apic_timer_irqs
, 1);
572 per_cpu(irq_stat
, cpu
).apic_timer_irqs
++;
575 evt
->event_handler(evt
);
579 * Local APIC timer interrupt. This is the most natural way for doing
580 * local interrupts, but local timer interrupts can be emulated by
581 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
583 * [ if a single-CPU system runs an SMP kernel then we call the local
584 * interrupt as well. Thus we cannot inline the local irq ... ]
586 void smp_apic_timer_interrupt(struct pt_regs
*regs
)
588 struct pt_regs
*old_regs
= set_irq_regs(regs
);
591 * NOTE! We'd better ACK the irq immediately,
592 * because timer handling can be slow.
596 * update_process_times() expects us to have done irq_enter().
597 * Besides, if we don't timer interrupts ignore the global
598 * interrupt lock, which is the WrongThing (tm) to do.
602 local_apic_timer_interrupt();
605 set_irq_regs(old_regs
);
608 int setup_profiling_timer(unsigned int multiplier
)
615 * Local APIC start and shutdown
619 * clear_local_APIC - shutdown the local APIC
621 * This is called, when a CPU is disabled and before rebooting, so the state of
622 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
623 * leftovers during boot.
625 void clear_local_APIC(void)
630 /* APIC hasn't been mapped yet */
634 maxlvt
= lapic_get_maxlvt();
636 * Masking an LVT entry can trigger a local APIC error
637 * if the vector is zero. Mask LVTERR first to prevent this.
640 v
= ERROR_APIC_VECTOR
; /* any non-zero vector will do */
641 apic_write(APIC_LVTERR
, v
| APIC_LVT_MASKED
);
644 * Careful: we have to set masks only first to deassert
645 * any level-triggered sources.
647 v
= apic_read(APIC_LVTT
);
648 apic_write(APIC_LVTT
, v
| APIC_LVT_MASKED
);
649 v
= apic_read(APIC_LVT0
);
650 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
651 v
= apic_read(APIC_LVT1
);
652 apic_write(APIC_LVT1
, v
| APIC_LVT_MASKED
);
654 v
= apic_read(APIC_LVTPC
);
655 apic_write(APIC_LVTPC
, v
| APIC_LVT_MASKED
);
658 /* lets not touch this if we didn't frob it */
659 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(X86_MCE_INTEL)
661 v
= apic_read(APIC_LVTTHMR
);
662 apic_write(APIC_LVTTHMR
, v
| APIC_LVT_MASKED
);
666 * Clean APIC state for other OSs:
668 apic_write(APIC_LVTT
, APIC_LVT_MASKED
);
669 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
670 apic_write(APIC_LVT1
, APIC_LVT_MASKED
);
672 apic_write(APIC_LVTERR
, APIC_LVT_MASKED
);
674 apic_write(APIC_LVTPC
, APIC_LVT_MASKED
);
676 /* Integrated APIC (!82489DX) ? */
677 if (lapic_is_integrated()) {
679 /* Clear ESR due to Pentium errata 3AP and 11AP */
680 apic_write(APIC_ESR
, 0);
686 * disable_local_APIC - clear and disable the local APIC
688 void disable_local_APIC(void)
695 * Disable APIC (implies clearing of registers
698 value
= apic_read(APIC_SPIV
);
699 value
&= ~APIC_SPIV_APIC_ENABLED
;
700 apic_write(APIC_SPIV
, value
);
704 * When LAPIC was disabled by the BIOS and enabled by the kernel,
705 * restore the disabled state.
707 if (enabled_via_apicbase
) {
710 rdmsr(MSR_IA32_APICBASE
, l
, h
);
711 l
&= ~MSR_IA32_APICBASE_ENABLE
;
712 wrmsr(MSR_IA32_APICBASE
, l
, h
);
718 * If Linux enabled the LAPIC against the BIOS default disable it down before
719 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
720 * not power-off. Additionally clear all LVT entries before disable_local_APIC
721 * for the case where Linux didn't enable the LAPIC.
723 void lapic_shutdown(void)
730 local_irq_save(flags
);
733 if (!enabled_via_apicbase
)
737 disable_local_APIC();
740 local_irq_restore(flags
);
744 * This is to verify that we're looking at a real local APIC.
745 * Check these against your board if the CPUs aren't getting
746 * started for no apparent reason.
748 int __init
verify_local_APIC(void)
750 unsigned int reg0
, reg1
;
753 * The version register is read-only in a real APIC.
755 reg0
= apic_read(APIC_LVR
);
756 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg0
);
757 apic_write(APIC_LVR
, reg0
^ APIC_LVR_MASK
);
758 reg1
= apic_read(APIC_LVR
);
759 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg1
);
762 * The two version reads above should print the same
763 * numbers. If the second one is different, then we
764 * poke at a non-APIC.
770 * Check if the version looks reasonably.
772 reg1
= GET_APIC_VERSION(reg0
);
773 if (reg1
== 0x00 || reg1
== 0xff)
775 reg1
= lapic_get_maxlvt();
776 if (reg1
< 0x02 || reg1
== 0xff)
780 * The ID register is read/write in a real APIC.
782 reg0
= apic_read(APIC_ID
);
783 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg0
);
784 apic_write(APIC_ID
, reg0
^ APIC_ID_MASK
);
785 reg1
= apic_read(APIC_ID
);
786 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg1
);
787 apic_write(APIC_ID
, reg0
);
788 if (reg1
!= (reg0
^ APIC_ID_MASK
))
792 * The next two are just to see if we have sane values.
793 * They're only really relevant if we're in Virtual Wire
794 * compatibility mode, but most boxes are anymore.
796 reg0
= apic_read(APIC_LVT0
);
797 apic_printk(APIC_DEBUG
, "Getting LVT0: %x\n", reg0
);
798 reg1
= apic_read(APIC_LVT1
);
799 apic_printk(APIC_DEBUG
, "Getting LVT1: %x\n", reg1
);
805 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
807 void __init
sync_Arb_IDs(void)
810 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
813 if (modern_apic() || boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
)
819 apic_wait_icr_idle();
821 apic_printk(APIC_DEBUG
, "Synchronizing Arb IDs.\n");
822 apic_write(APIC_ICR
, APIC_DEST_ALLINC
|
823 APIC_INT_LEVELTRIG
| APIC_DM_INIT
);
827 * An initial setup of the virtual wire mode.
829 void __init
init_bsp_APIC(void)
834 * Don't do the setup now if we have a SMP BIOS as the
835 * through-I/O-APIC virtual wire mode might be active.
837 if (smp_found_config
|| !cpu_has_apic
)
841 * Do not trust the local APIC being empty at bootup.
848 value
= apic_read(APIC_SPIV
);
849 value
&= ~APIC_VECTOR_MASK
;
850 value
|= APIC_SPIV_APIC_ENABLED
;
853 /* This bit is reserved on P4/Xeon and should be cleared */
854 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
) &&
855 (boot_cpu_data
.x86
== 15))
856 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
859 value
|= APIC_SPIV_FOCUS_DISABLED
;
860 value
|= SPURIOUS_APIC_VECTOR
;
861 apic_write(APIC_SPIV
, value
);
864 * Set up the virtual wire mode.
866 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
868 if (!lapic_is_integrated()) /* 82489DX */
869 value
|= APIC_LVT_LEVEL_TRIGGER
;
870 apic_write(APIC_LVT1
, value
);
873 static void __cpuinit
lapic_setup_esr(void)
875 unsigned long oldvalue
, value
, maxlvt
;
876 if (lapic_is_integrated() && !esr_disable
) {
879 * Something untraceable is creating bad interrupts on
880 * secondary quads ... for the moment, just leave the
881 * ESR disabled - we can't do anything useful with the
882 * errors anyway - mbligh
884 printk(KERN_INFO
"Leaving ESR disabled.\n");
888 maxlvt
= lapic_get_maxlvt();
889 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
890 apic_write(APIC_ESR
, 0);
891 oldvalue
= apic_read(APIC_ESR
);
893 /* enables sending errors */
894 value
= ERROR_APIC_VECTOR
;
895 apic_write(APIC_LVTERR
, value
);
897 * spec says clear errors after enabling vector.
900 apic_write(APIC_ESR
, 0);
901 value
= apic_read(APIC_ESR
);
902 if (value
!= oldvalue
)
903 apic_printk(APIC_VERBOSE
, "ESR value before enabling "
904 "vector: 0x%08lx after: 0x%08lx\n",
907 printk(KERN_INFO
"No ESR for 82489DX.\n");
913 * setup_local_APIC - setup the local APIC
915 void __cpuinit
setup_local_APIC(void)
921 value
= apic_read(APIC_LVR
);
923 BUILD_BUG_ON((SPURIOUS_APIC_VECTOR
& 0x0f) != 0x0f);
926 * Double-check whether this APIC is really registered.
927 * This is meaningless in clustered apic mode, so we skip it.
929 if (!apic_id_registered())
933 * Intel recommends to set DFR, LDR and TPR before enabling
934 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
935 * document number 292116). So here it goes...
940 * Set Task Priority to 'accept all'. We never change this
943 value
= apic_read(APIC_TASKPRI
);
944 value
&= ~APIC_TPRI_MASK
;
945 apic_write(APIC_TASKPRI
, value
);
948 * After a crash, we no longer service the interrupts and a pending
949 * interrupt from previous kernel might still have ISR bit set.
951 * Most probably by now CPU has serviced that pending interrupt and
952 * it might not have done the ack_APIC_irq() because it thought,
953 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
954 * does not clear the ISR bit and cpu thinks it has already serivced
955 * the interrupt. Hence a vector might get locked. It was noticed
956 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
958 for (i
= APIC_ISR_NR
- 1; i
>= 0; i
--) {
959 value
= apic_read(APIC_ISR
+ i
*0x10);
960 for (j
= 31; j
>= 0; j
--) {
967 * Now that we are all set up, enable the APIC
969 value
= apic_read(APIC_SPIV
);
970 value
&= ~APIC_VECTOR_MASK
;
974 value
|= APIC_SPIV_APIC_ENABLED
;
976 /* We always use processor focus */
979 * Set spurious IRQ vector
981 value
|= SPURIOUS_APIC_VECTOR
;
982 apic_write(APIC_SPIV
, value
);
987 * set up through-local-APIC on the BP's LINT0. This is not
988 * strictly necessary in pure symmetric-IO mode, but sometimes
989 * we delegate interrupts to the 8259A.
992 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
994 value
= apic_read(APIC_LVT0
) & APIC_LVT_MASKED
;
995 if (!smp_processor_id() && !value
) {
996 value
= APIC_DM_EXTINT
;
997 apic_printk(APIC_VERBOSE
, "enabled ExtINT on CPU#%d\n",
1000 value
= APIC_DM_EXTINT
| APIC_LVT_MASKED
;
1001 apic_printk(APIC_VERBOSE
, "masked ExtINT on CPU#%d\n",
1002 smp_processor_id());
1004 apic_write(APIC_LVT0
, value
);
1007 * only the BP should see the LINT1 NMI signal, obviously.
1009 if (!smp_processor_id())
1010 value
= APIC_DM_NMI
;
1012 value
= APIC_DM_NMI
| APIC_LVT_MASKED
;
1013 apic_write(APIC_LVT1
, value
);
1017 void __cpuinit
end_local_APIC_setup(void)
1021 #ifdef CONFIG_X86_32
1024 /* Disable the local apic timer */
1025 value
= apic_read(APIC_LVTT
);
1026 value
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
1027 apic_write(APIC_LVTT
, value
);
1031 setup_apic_nmi_watchdog(NULL
);
1035 void check_x2apic(void)
1039 rdmsr(MSR_IA32_APICBASE
, msr
, msr2
);
1041 if (msr
& X2APIC_ENABLE
) {
1042 printk("x2apic enabled by BIOS, switching to x2apic ops\n");
1043 x2apic_preenabled
= x2apic
= 1;
1044 apic_ops
= &x2apic_ops
;
1048 void enable_x2apic(void)
1052 rdmsr(MSR_IA32_APICBASE
, msr
, msr2
);
1053 if (!(msr
& X2APIC_ENABLE
)) {
1054 printk("Enabling x2apic\n");
1055 wrmsr(MSR_IA32_APICBASE
, msr
| X2APIC_ENABLE
, 0);
1059 void enable_IR_x2apic(void)
1061 #ifdef CONFIG_INTR_REMAP
1063 unsigned long flags
;
1065 if (!cpu_has_x2apic
)
1068 if (!x2apic_preenabled
&& disable_x2apic
) {
1070 "Skipped enabling x2apic and Interrupt-remapping "
1071 "because of nox2apic\n");
1075 if (x2apic_preenabled
&& disable_x2apic
)
1076 panic("Bios already enabled x2apic, can't enforce nox2apic");
1078 if (!x2apic_preenabled
&& skip_ioapic_setup
) {
1080 "Skipped enabling x2apic and Interrupt-remapping "
1081 "because of skipping io-apic setup\n");
1085 ret
= dmar_table_init();
1088 "dmar_table_init() failed with %d:\n", ret
);
1090 if (x2apic_preenabled
)
1091 panic("x2apic enabled by bios. But IR enabling failed");
1094 "Not enabling x2apic,Intr-remapping\n");
1098 local_irq_save(flags
);
1100 save_mask_IO_APIC_setup();
1102 ret
= enable_intr_remapping(1);
1104 if (ret
&& x2apic_preenabled
) {
1105 local_irq_restore(flags
);
1106 panic("x2apic enabled by bios. But IR enabling failed");
1114 apic_ops
= &x2apic_ops
;
1120 * IR enabling failed
1122 restore_IO_APIC_setup();
1124 reinit_intr_remapped_IO_APIC(x2apic_preenabled
);
1127 local_irq_restore(flags
);
1130 if (!x2apic_preenabled
)
1132 "Enabled x2apic and interrupt-remapping\n");
1135 "Enabled Interrupt-remapping\n");
1138 "Failed to enable Interrupt-remapping and x2apic\n");
1140 if (!cpu_has_x2apic
)
1143 if (x2apic_preenabled
)
1144 panic("x2apic enabled prior OS handover,"
1145 " enable CONFIG_INTR_REMAP");
1147 printk(KERN_INFO
"Enable CONFIG_INTR_REMAP for enabling intr-remapping "
1155 * Detect and enable local APICs on non-SMP boards.
1156 * Original code written by Keir Fraser.
1157 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1158 * not correctly set up (usually the APIC timer won't work etc.)
1160 static int __init
detect_init_APIC(void)
1162 if (!cpu_has_apic
) {
1163 printk(KERN_INFO
"No local APIC present\n");
1167 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
1168 boot_cpu_physical_apicid
= 0;
1172 void __init
early_init_lapic_mapping(void)
1174 unsigned long phys_addr
;
1177 * If no local APIC can be found then go out
1178 * : it means there is no mpatable and MADT
1180 if (!smp_found_config
)
1183 phys_addr
= mp_lapic_addr
;
1185 set_fixmap_nocache(FIX_APIC_BASE
, phys_addr
);
1186 apic_printk(APIC_VERBOSE
, "mapped APIC to %16lx (%16lx)\n",
1187 APIC_BASE
, phys_addr
);
1190 * Fetch the APIC ID of the BSP in case we have a
1191 * default configuration (or the MP table is broken).
1193 boot_cpu_physical_apicid
= read_apic_id();
1197 * init_apic_mappings - initialize APIC mappings
1199 void __init
init_apic_mappings(void)
1202 boot_cpu_physical_apicid
= read_apic_id();
1207 * If no local APIC can be found then set up a fake all
1208 * zeroes page to simulate the local APIC and another
1209 * one for the IO-APIC.
1211 if (!smp_found_config
&& detect_init_APIC()) {
1212 apic_phys
= (unsigned long) alloc_bootmem_pages(PAGE_SIZE
);
1213 apic_phys
= __pa(apic_phys
);
1215 apic_phys
= mp_lapic_addr
;
1217 set_fixmap_nocache(FIX_APIC_BASE
, apic_phys
);
1218 apic_printk(APIC_VERBOSE
, "mapped APIC to %16lx (%16lx)\n",
1219 APIC_BASE
, apic_phys
);
1222 * Fetch the APIC ID of the BSP in case we have a
1223 * default configuration (or the MP table is broken).
1225 boot_cpu_physical_apicid
= read_apic_id();
1229 * This initializes the IO-APIC and APIC hardware if this is
1232 int apic_version
[MAX_APICS
];
1234 int __init
APIC_init_uniprocessor(void)
1237 printk(KERN_INFO
"Apic disabled\n");
1240 if (!cpu_has_apic
) {
1242 printk(KERN_INFO
"Apic disabled by BIOS\n");
1247 setup_apic_routing();
1249 verify_local_APIC();
1253 physid_set_mask_of_physid(boot_cpu_physical_apicid
, &phys_cpu_present_map
);
1254 apic_write(APIC_ID
, SET_APIC_ID(boot_cpu_physical_apicid
));
1259 * Now enable IO-APICs, actually call clear_IO_APIC
1260 * We need clear_IO_APIC before enabling vector on BP
1262 if (!skip_ioapic_setup
&& nr_ioapics
)
1265 if (!smp_found_config
|| skip_ioapic_setup
|| !nr_ioapics
)
1266 localise_nmi_watchdog();
1267 end_local_APIC_setup();
1269 if (smp_found_config
&& !skip_ioapic_setup
&& nr_ioapics
)
1273 setup_boot_APIC_clock();
1274 check_nmi_watchdog();
1279 * Local APIC interrupts
1283 * This interrupt should _never_ happen with our APIC/SMP architecture
1285 asmlinkage
void smp_spurious_interrupt(void)
1291 * Check if this really is a spurious interrupt and ACK it
1292 * if it is a vectored one. Just in case...
1293 * Spurious interrupts should not be ACKed.
1295 v
= apic_read(APIC_ISR
+ ((SPURIOUS_APIC_VECTOR
& ~0x1f) >> 1));
1296 if (v
& (1 << (SPURIOUS_APIC_VECTOR
& 0x1f)))
1299 add_pda(irq_spurious_count
, 1);
1304 * This interrupt should never happen with our APIC/SMP architecture
1306 asmlinkage
void smp_error_interrupt(void)
1312 /* First tickle the hardware, only then report what went on. -- REW */
1313 v
= apic_read(APIC_ESR
);
1314 apic_write(APIC_ESR
, 0);
1315 v1
= apic_read(APIC_ESR
);
1317 atomic_inc(&irq_err_count
);
1319 /* Here is what the APIC error bits mean:
1322 2: Send accept error
1323 3: Receive accept error
1325 5: Send illegal vector
1326 6: Received illegal vector
1327 7: Illegal register address
1329 printk(KERN_DEBUG
"APIC error on CPU%d: %02x(%02x)\n",
1330 smp_processor_id(), v
, v1
);
1335 * connect_bsp_APIC - attach the APIC to the interrupt system
1337 void __init
connect_bsp_APIC(void)
1339 #ifdef CONFIG_X86_32
1342 * Do not trust the local APIC being empty at bootup.
1346 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
1347 * local APIC to INT and NMI lines.
1349 apic_printk(APIC_VERBOSE
, "leaving PIC mode, "
1350 "enabling APIC mode.\n");
1359 * disconnect_bsp_APIC - detach the APIC from the interrupt system
1360 * @virt_wire_setup: indicates, whether virtual wire mode is selected
1362 * Virtual wire mode is necessary to deliver legacy interrupts even when the
1365 void disconnect_bsp_APIC(int virt_wire_setup
)
1369 #ifdef CONFIG_X86_32
1372 * Put the board back into PIC mode (has an effect only on
1373 * certain older boards). Note that APIC interrupts, including
1374 * IPIs, won't work beyond this point! The only exception are
1377 apic_printk(APIC_VERBOSE
, "disabling APIC mode, "
1378 "entering PIC mode.\n");
1385 /* Go back to Virtual Wire compatibility mode */
1387 /* For the spurious interrupt use vector F, and enable it */
1388 value
= apic_read(APIC_SPIV
);
1389 value
&= ~APIC_VECTOR_MASK
;
1390 value
|= APIC_SPIV_APIC_ENABLED
;
1392 apic_write(APIC_SPIV
, value
);
1394 if (!virt_wire_setup
) {
1396 * For LVT0 make it edge triggered, active high,
1397 * external and enabled
1399 value
= apic_read(APIC_LVT0
);
1400 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1401 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1402 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1403 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1404 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_EXTINT
);
1405 apic_write(APIC_LVT0
, value
);
1408 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
1412 * For LVT1 make it edge triggered, active high,
1415 value
= apic_read(APIC_LVT1
);
1416 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1417 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1418 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1419 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1420 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_NMI
);
1421 apic_write(APIC_LVT1
, value
);
1424 void __cpuinit
generic_processor_info(int apicid
, int version
)
1432 if (version
== 0x0) {
1433 printk(KERN_WARNING
"BIOS bug, APIC version is 0 for CPU#%d! "
1434 "fixing up to 0x10. (tell your hw vendor)\n",
1438 apic_version
[apicid
] = version
;
1440 if (num_processors
>= NR_CPUS
) {
1441 printk(KERN_WARNING
"WARNING: NR_CPUS limit of %i reached."
1442 " Processor ignored.\n", NR_CPUS
);
1447 cpus_complement(tmp_map
, cpu_present_map
);
1448 cpu
= first_cpu(tmp_map
);
1450 physid_set(apicid
, phys_cpu_present_map
);
1451 if (apicid
== boot_cpu_physical_apicid
) {
1453 * x86_bios_cpu_apicid is required to have processors listed
1454 * in same order as logical cpu numbers. Hence the first
1455 * entry is BSP, and so on.
1459 if (apicid
> max_physical_apicid
)
1460 max_physical_apicid
= apicid
;
1462 #ifdef CONFIG_X86_32
1464 * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y
1465 * but we need to work other dependencies like SMP_SUSPEND etc
1466 * before this can be done without some confusion.
1467 * if (CPU_HOTPLUG_ENABLED || num_processors > 8)
1468 * - Ashok Raj <ashok.raj@intel.com>
1470 if (max_physical_apicid
>= 8) {
1471 switch (boot_cpu_data
.x86_vendor
) {
1472 case X86_VENDOR_INTEL
:
1473 if (!APIC_XAPIC(version
)) {
1477 /* If P4 and above fall through */
1478 case X86_VENDOR_AMD
:
1484 #if defined(CONFIG_X86_SMP) || defined(CONFIG_X86_64)
1485 /* are we being called early in kernel startup? */
1486 if (early_per_cpu_ptr(x86_cpu_to_apicid
)) {
1487 u16
*cpu_to_apicid
= early_per_cpu_ptr(x86_cpu_to_apicid
);
1488 u16
*bios_cpu_apicid
= early_per_cpu_ptr(x86_bios_cpu_apicid
);
1490 cpu_to_apicid
[cpu
] = apicid
;
1491 bios_cpu_apicid
[cpu
] = apicid
;
1493 per_cpu(x86_cpu_to_apicid
, cpu
) = apicid
;
1494 per_cpu(x86_bios_cpu_apicid
, cpu
) = apicid
;
1498 cpu_set(cpu
, cpu_possible_map
);
1499 cpu_set(cpu
, cpu_present_map
);
1502 int hard_smp_processor_id(void)
1504 return read_apic_id();
1514 * 'active' is true if the local APIC was enabled by us and
1515 * not the BIOS; this signifies that we are also responsible
1516 * for disabling it before entering apm/acpi suspend
1519 /* r/w apic fields */
1520 unsigned int apic_id
;
1521 unsigned int apic_taskpri
;
1522 unsigned int apic_ldr
;
1523 unsigned int apic_dfr
;
1524 unsigned int apic_spiv
;
1525 unsigned int apic_lvtt
;
1526 unsigned int apic_lvtpc
;
1527 unsigned int apic_lvt0
;
1528 unsigned int apic_lvt1
;
1529 unsigned int apic_lvterr
;
1530 unsigned int apic_tmict
;
1531 unsigned int apic_tdcr
;
1532 unsigned int apic_thmr
;
1535 static int lapic_suspend(struct sys_device
*dev
, pm_message_t state
)
1537 unsigned long flags
;
1540 if (!apic_pm_state
.active
)
1543 maxlvt
= lapic_get_maxlvt();
1545 apic_pm_state
.apic_id
= apic_read(APIC_ID
);
1546 apic_pm_state
.apic_taskpri
= apic_read(APIC_TASKPRI
);
1547 apic_pm_state
.apic_ldr
= apic_read(APIC_LDR
);
1548 apic_pm_state
.apic_dfr
= apic_read(APIC_DFR
);
1549 apic_pm_state
.apic_spiv
= apic_read(APIC_SPIV
);
1550 apic_pm_state
.apic_lvtt
= apic_read(APIC_LVTT
);
1552 apic_pm_state
.apic_lvtpc
= apic_read(APIC_LVTPC
);
1553 apic_pm_state
.apic_lvt0
= apic_read(APIC_LVT0
);
1554 apic_pm_state
.apic_lvt1
= apic_read(APIC_LVT1
);
1555 apic_pm_state
.apic_lvterr
= apic_read(APIC_LVTERR
);
1556 apic_pm_state
.apic_tmict
= apic_read(APIC_TMICT
);
1557 apic_pm_state
.apic_tdcr
= apic_read(APIC_TDCR
);
1558 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
1560 apic_pm_state
.apic_thmr
= apic_read(APIC_LVTTHMR
);
1563 local_irq_save(flags
);
1564 disable_local_APIC();
1565 local_irq_restore(flags
);
1569 static int lapic_resume(struct sys_device
*dev
)
1572 unsigned long flags
;
1575 if (!apic_pm_state
.active
)
1578 maxlvt
= lapic_get_maxlvt();
1580 local_irq_save(flags
);
1582 #ifdef CONFIG_X86_64
1589 * Make sure the APICBASE points to the right address
1591 * FIXME! This will be wrong if we ever support suspend on
1592 * SMP! We'll need to do this as part of the CPU restore!
1594 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1595 l
&= ~MSR_IA32_APICBASE_BASE
;
1596 l
|= MSR_IA32_APICBASE_ENABLE
| mp_lapic_addr
;
1597 wrmsr(MSR_IA32_APICBASE
, l
, h
);
1600 apic_write(APIC_LVTERR
, ERROR_APIC_VECTOR
| APIC_LVT_MASKED
);
1601 apic_write(APIC_ID
, apic_pm_state
.apic_id
);
1602 apic_write(APIC_DFR
, apic_pm_state
.apic_dfr
);
1603 apic_write(APIC_LDR
, apic_pm_state
.apic_ldr
);
1604 apic_write(APIC_TASKPRI
, apic_pm_state
.apic_taskpri
);
1605 apic_write(APIC_SPIV
, apic_pm_state
.apic_spiv
);
1606 apic_write(APIC_LVT0
, apic_pm_state
.apic_lvt0
);
1607 apic_write(APIC_LVT1
, apic_pm_state
.apic_lvt1
);
1608 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
1610 apic_write(APIC_LVTTHMR
, apic_pm_state
.apic_thmr
);
1613 apic_write(APIC_LVTPC
, apic_pm_state
.apic_lvtpc
);
1614 apic_write(APIC_LVTT
, apic_pm_state
.apic_lvtt
);
1615 apic_write(APIC_TDCR
, apic_pm_state
.apic_tdcr
);
1616 apic_write(APIC_TMICT
, apic_pm_state
.apic_tmict
);
1617 apic_write(APIC_ESR
, 0);
1618 apic_read(APIC_ESR
);
1619 apic_write(APIC_LVTERR
, apic_pm_state
.apic_lvterr
);
1620 apic_write(APIC_ESR
, 0);
1621 apic_read(APIC_ESR
);
1623 local_irq_restore(flags
);
1629 * This device has no shutdown method - fully functioning local APICs
1630 * are needed on every CPU up until machine_halt/restart/poweroff.
1633 static struct sysdev_class lapic_sysclass
= {
1635 .resume
= lapic_resume
,
1636 .suspend
= lapic_suspend
,
1639 static struct sys_device device_lapic
= {
1641 .cls
= &lapic_sysclass
,
1644 static void __cpuinit
apic_pm_activate(void)
1646 apic_pm_state
.active
= 1;
1649 static int __init
init_lapic_sysfs(void)
1655 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
1657 error
= sysdev_class_register(&lapic_sysclass
);
1659 error
= sysdev_register(&device_lapic
);
1662 device_initcall(init_lapic_sysfs
);
1664 #else /* CONFIG_PM */
1666 static void apic_pm_activate(void) { }
1668 #endif /* CONFIG_PM */
1671 * apic_is_clustered_box() -- Check if we can expect good TSC
1673 * Thus far, the major user of this is IBM's Summit2 series:
1675 * Clustered boxes may have unsynced TSC problems if they are
1676 * multi-chassis. Use available data to take a good guess.
1677 * If in doubt, go HPET.
1679 __cpuinit
int apic_is_clustered_box(void)
1681 int i
, clusters
, zeros
;
1683 u16
*bios_cpu_apicid
;
1684 DECLARE_BITMAP(clustermap
, NUM_APIC_CLUSTERS
);
1687 * there is not this kind of box with AMD CPU yet.
1688 * Some AMD box with quadcore cpu and 8 sockets apicid
1689 * will be [4, 0x23] or [8, 0x27] could be thought to
1690 * vsmp box still need checking...
1692 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
) && !is_vsmp_box())
1695 bios_cpu_apicid
= early_per_cpu_ptr(x86_bios_cpu_apicid
);
1696 bitmap_zero(clustermap
, NUM_APIC_CLUSTERS
);
1698 for (i
= 0; i
< NR_CPUS
; i
++) {
1699 /* are we being called early in kernel startup? */
1700 if (bios_cpu_apicid
) {
1701 id
= bios_cpu_apicid
[i
];
1703 else if (i
< nr_cpu_ids
) {
1705 id
= per_cpu(x86_bios_cpu_apicid
, i
);
1712 if (id
!= BAD_APICID
)
1713 __set_bit(APIC_CLUSTERID(id
), clustermap
);
1716 /* Problem: Partially populated chassis may not have CPUs in some of
1717 * the APIC clusters they have been allocated. Only present CPUs have
1718 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap.
1719 * Since clusters are allocated sequentially, count zeros only if
1720 * they are bounded by ones.
1724 for (i
= 0; i
< NUM_APIC_CLUSTERS
; i
++) {
1725 if (test_bit(i
, clustermap
)) {
1726 clusters
+= 1 + zeros
;
1732 /* ScaleMP vSMPowered boxes have one cluster per board and TSCs are
1733 * not guaranteed to be synced between boards
1735 if (is_vsmp_box() && clusters
> 1)
1739 * If clusters > 2, then should be multi-chassis.
1740 * May have to revisit this when multi-core + hyperthreaded CPUs come
1741 * out, but AFAIK this will work even for them.
1743 return (clusters
> 2);
1746 static __init
int setup_nox2apic(char *str
)
1749 clear_cpu_cap(&boot_cpu_data
, X86_FEATURE_X2APIC
);
1752 early_param("nox2apic", setup_nox2apic
);
1756 * APIC command line parameters
1758 static int __init
setup_disableapic(char *arg
)
1761 setup_clear_cpu_cap(X86_FEATURE_APIC
);
1764 early_param("disableapic", setup_disableapic
);
1766 /* same as disableapic, for compatibility */
1767 static int __init
setup_nolapic(char *arg
)
1769 return setup_disableapic(arg
);
1771 early_param("nolapic", setup_nolapic
);
1773 static int __init
parse_lapic_timer_c2_ok(char *arg
)
1775 local_apic_timer_c2_ok
= 1;
1778 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok
);
1780 static int __init
parse_disable_apic_timer(char *arg
)
1782 disable_apic_timer
= 1;
1785 early_param("noapictimer", parse_disable_apic_timer
);
1787 static int __init
parse_nolapic_timer(char *arg
)
1789 disable_apic_timer
= 1;
1792 early_param("nolapic_timer", parse_nolapic_timer
);
1794 static __init
int setup_apicpmtimer(char *s
)
1796 apic_calibrate_pmtmr
= 1;
1800 __setup("apicpmtimer", setup_apicpmtimer
);
1802 static int __init
apic_set_verbosity(char *arg
)
1805 #ifdef CONFIG_X86_64
1806 skip_ioapic_setup
= 0;
1813 if (strcmp("debug", arg
) == 0)
1814 apic_verbosity
= APIC_DEBUG
;
1815 else if (strcmp("verbose", arg
) == 0)
1816 apic_verbosity
= APIC_VERBOSE
;
1818 printk(KERN_WARNING
"APIC Verbosity level %s not recognised"
1819 " use apic=verbose or apic=debug\n", arg
);
1825 early_param("apic", apic_set_verbosity
);
1827 static int __init
lapic_insert_resource(void)
1832 /* Put local APIC into the resource map. */
1833 lapic_resource
.start
= apic_phys
;
1834 lapic_resource
.end
= lapic_resource
.start
+ PAGE_SIZE
- 1;
1835 insert_resource(&iomem_resource
, &lapic_resource
);
1841 * need call insert after e820_reserve_resources()
1842 * that is using request_resource
1844 late_initcall(lapic_insert_resource
);