2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/bootmem.h>
22 #include <linux/interrupt.h>
23 #include <linux/mc146818rtc.h>
24 #include <linux/kernel_stat.h>
25 #include <linux/sysdev.h>
26 #include <linux/module.h>
27 #include <linux/ioport.h>
28 #include <linux/clockchips.h>
30 #include <asm/atomic.h>
33 #include <asm/mpspec.h>
34 #include <asm/pgalloc.h>
35 #include <asm/mach_apic.h>
38 #include <asm/proto.h>
39 #include <asm/timex.h>
44 int apic_calibrate_pmtmr __initdata
;
46 int disable_apic_timer __cpuinitdata
;
48 /* Local APIC timer works in C2? */
49 int local_apic_timer_c2_ok
;
50 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok
);
52 static struct resource
*ioapic_resources
;
53 static struct resource lapic_resource
= {
55 .flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
,
58 static unsigned int calibration_result
;
60 static int lapic_next_event(unsigned long delta
,
61 struct clock_event_device
*evt
);
62 static void lapic_timer_setup(enum clock_event_mode mode
,
63 struct clock_event_device
*evt
);
65 static void lapic_timer_broadcast(cpumask_t mask
);
67 static void __setup_APIC_LVTT(unsigned int clocks
, int oneshot
, int irqen
);
69 static struct clock_event_device lapic_clockevent
= {
71 .features
= CLOCK_EVT_FEAT_PERIODIC
| CLOCK_EVT_FEAT_ONESHOT
72 | CLOCK_EVT_FEAT_C3STOP
| CLOCK_EVT_FEAT_DUMMY
,
74 .set_mode
= lapic_timer_setup
,
75 .set_next_event
= lapic_next_event
,
76 .broadcast
= lapic_timer_broadcast
,
80 static DEFINE_PER_CPU(struct clock_event_device
, lapic_events
);
82 static int lapic_next_event(unsigned long delta
,
83 struct clock_event_device
*evt
)
85 apic_write(APIC_TMICT
, delta
);
89 static void lapic_timer_setup(enum clock_event_mode mode
,
90 struct clock_event_device
*evt
)
95 /* Lapic used as dummy for broadcast ? */
96 if (evt
->features
& CLOCK_EVT_FEAT_DUMMY
)
99 local_irq_save(flags
);
102 case CLOCK_EVT_MODE_PERIODIC
:
103 case CLOCK_EVT_MODE_ONESHOT
:
104 __setup_APIC_LVTT(calibration_result
,
105 mode
!= CLOCK_EVT_MODE_PERIODIC
, 1);
107 case CLOCK_EVT_MODE_UNUSED
:
108 case CLOCK_EVT_MODE_SHUTDOWN
:
109 v
= apic_read(APIC_LVTT
);
110 v
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
111 apic_write(APIC_LVTT
, v
);
113 case CLOCK_EVT_MODE_RESUME
:
114 /* Nothing to do here */
118 local_irq_restore(flags
);
122 * Local APIC timer broadcast function
124 static void lapic_timer_broadcast(cpumask_t mask
)
127 send_IPI_mask(mask
, LOCAL_TIMER_VECTOR
);
131 static void apic_pm_activate(void);
133 void apic_wait_icr_idle(void)
135 while (apic_read(APIC_ICR
) & APIC_ICR_BUSY
)
139 unsigned int safe_apic_wait_icr_idle(void)
141 unsigned int send_status
;
146 send_status
= apic_read(APIC_ICR
) & APIC_ICR_BUSY
;
150 } while (timeout
++ < 1000);
155 void enable_NMI_through_LVT0 (void * dummy
)
159 /* unmask and set to NMI */
161 apic_write(APIC_LVT0
, v
);
166 unsigned int v
, maxlvt
;
168 v
= apic_read(APIC_LVR
);
169 maxlvt
= GET_APIC_MAXLVT(v
);
174 * 'what should we do if we get a hw irq event on an illegal vector'.
175 * each architecture has to answer this themselves.
177 void ack_bad_irq(unsigned int irq
)
179 printk("unexpected IRQ trap at vector %02x\n", irq
);
181 * Currently unexpected vectors happen only on SMP and APIC.
182 * We _must_ ack these because every local APIC has only N
183 * irq slots per priority level, and a 'hanging, unacked' IRQ
184 * holds up an irq slot - in excessive cases (when multiple
185 * unexpected vectors occur) that might lock up the APIC
187 * But don't ack when the APIC is disabled. -AK
193 void clear_local_APIC(void)
198 maxlvt
= get_maxlvt();
201 * Masking an LVT entry can trigger a local APIC error
202 * if the vector is zero. Mask LVTERR first to prevent this.
205 v
= ERROR_APIC_VECTOR
; /* any non-zero vector will do */
206 apic_write(APIC_LVTERR
, v
| APIC_LVT_MASKED
);
209 * Careful: we have to set masks only first to deassert
210 * any level-triggered sources.
212 v
= apic_read(APIC_LVTT
);
213 apic_write(APIC_LVTT
, v
| APIC_LVT_MASKED
);
214 v
= apic_read(APIC_LVT0
);
215 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
216 v
= apic_read(APIC_LVT1
);
217 apic_write(APIC_LVT1
, v
| APIC_LVT_MASKED
);
219 v
= apic_read(APIC_LVTPC
);
220 apic_write(APIC_LVTPC
, v
| APIC_LVT_MASKED
);
224 * Clean APIC state for other OSs:
226 apic_write(APIC_LVTT
, APIC_LVT_MASKED
);
227 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
228 apic_write(APIC_LVT1
, APIC_LVT_MASKED
);
230 apic_write(APIC_LVTERR
, APIC_LVT_MASKED
);
232 apic_write(APIC_LVTPC
, APIC_LVT_MASKED
);
233 apic_write(APIC_ESR
, 0);
237 void disconnect_bsp_APIC(int virt_wire_setup
)
239 /* Go back to Virtual Wire compatibility mode */
242 /* For the spurious interrupt use vector F, and enable it */
243 value
= apic_read(APIC_SPIV
);
244 value
&= ~APIC_VECTOR_MASK
;
245 value
|= APIC_SPIV_APIC_ENABLED
;
247 apic_write(APIC_SPIV
, value
);
249 if (!virt_wire_setup
) {
250 /* For LVT0 make it edge triggered, active high, external and enabled */
251 value
= apic_read(APIC_LVT0
);
252 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
253 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
254 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
255 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
256 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_EXTINT
);
257 apic_write(APIC_LVT0
, value
);
260 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
263 /* For LVT1 make it edge triggered, active high, nmi and enabled */
264 value
= apic_read(APIC_LVT1
);
265 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
266 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
267 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
268 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
269 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_NMI
);
270 apic_write(APIC_LVT1
, value
);
273 void disable_local_APIC(void)
280 * Disable APIC (implies clearing of registers
283 value
= apic_read(APIC_SPIV
);
284 value
&= ~APIC_SPIV_APIC_ENABLED
;
285 apic_write(APIC_SPIV
, value
);
289 * This is to verify that we're looking at a real local APIC.
290 * Check these against your board if the CPUs aren't getting
291 * started for no apparent reason.
293 int __init
verify_local_APIC(void)
295 unsigned int reg0
, reg1
;
298 * The version register is read-only in a real APIC.
300 reg0
= apic_read(APIC_LVR
);
301 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg0
);
302 apic_write(APIC_LVR
, reg0
^ APIC_LVR_MASK
);
303 reg1
= apic_read(APIC_LVR
);
304 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg1
);
307 * The two version reads above should print the same
308 * numbers. If the second one is different, then we
309 * poke at a non-APIC.
315 * Check if the version looks reasonably.
317 reg1
= GET_APIC_VERSION(reg0
);
318 if (reg1
== 0x00 || reg1
== 0xff)
321 if (reg1
< 0x02 || reg1
== 0xff)
325 * The ID register is read/write in a real APIC.
327 reg0
= apic_read(APIC_ID
);
328 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg0
);
329 apic_write(APIC_ID
, reg0
^ APIC_ID_MASK
);
330 reg1
= apic_read(APIC_ID
);
331 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg1
);
332 apic_write(APIC_ID
, reg0
);
333 if (reg1
!= (reg0
^ APIC_ID_MASK
))
337 * The next two are just to see if we have sane values.
338 * They're only really relevant if we're in Virtual Wire
339 * compatibility mode, but most boxes are anymore.
341 reg0
= apic_read(APIC_LVT0
);
342 apic_printk(APIC_DEBUG
,"Getting LVT0: %x\n", reg0
);
343 reg1
= apic_read(APIC_LVT1
);
344 apic_printk(APIC_DEBUG
, "Getting LVT1: %x\n", reg1
);
349 void __init
sync_Arb_IDs(void)
351 /* Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 */
352 unsigned int ver
= GET_APIC_VERSION(apic_read(APIC_LVR
));
353 if (ver
>= 0x14) /* P4 or higher */
359 apic_wait_icr_idle();
361 apic_printk(APIC_DEBUG
, "Synchronizing Arb IDs.\n");
362 apic_write(APIC_ICR
, APIC_DEST_ALLINC
| APIC_INT_LEVELTRIG
367 * An initial setup of the virtual wire mode.
369 void __init
init_bsp_APIC(void)
374 * Don't do the setup now if we have a SMP BIOS as the
375 * through-I/O-APIC virtual wire mode might be active.
377 if (smp_found_config
|| !cpu_has_apic
)
380 value
= apic_read(APIC_LVR
);
383 * Do not trust the local APIC being empty at bootup.
390 value
= apic_read(APIC_SPIV
);
391 value
&= ~APIC_VECTOR_MASK
;
392 value
|= APIC_SPIV_APIC_ENABLED
;
393 value
|= APIC_SPIV_FOCUS_DISABLED
;
394 value
|= SPURIOUS_APIC_VECTOR
;
395 apic_write(APIC_SPIV
, value
);
398 * Set up the virtual wire mode.
400 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
402 apic_write(APIC_LVT1
, value
);
405 void __cpuinit
setup_local_APIC (void)
407 unsigned int value
, maxlvt
;
410 value
= apic_read(APIC_LVR
);
412 BUILD_BUG_ON((SPURIOUS_APIC_VECTOR
& 0x0f) != 0x0f);
415 * Double-check whether this APIC is really registered.
416 * This is meaningless in clustered apic mode, so we skip it.
418 if (!apic_id_registered())
422 * Intel recommends to set DFR, LDR and TPR before enabling
423 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
424 * document number 292116). So here it goes...
429 * Set Task Priority to 'accept all'. We never change this
432 value
= apic_read(APIC_TASKPRI
);
433 value
&= ~APIC_TPRI_MASK
;
434 apic_write(APIC_TASKPRI
, value
);
437 * After a crash, we no longer service the interrupts and a pending
438 * interrupt from previous kernel might still have ISR bit set.
440 * Most probably by now CPU has serviced that pending interrupt and
441 * it might not have done the ack_APIC_irq() because it thought,
442 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
443 * does not clear the ISR bit and cpu thinks it has already serivced
444 * the interrupt. Hence a vector might get locked. It was noticed
445 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
447 for (i
= APIC_ISR_NR
- 1; i
>= 0; i
--) {
448 value
= apic_read(APIC_ISR
+ i
*0x10);
449 for (j
= 31; j
>= 0; j
--) {
456 * Now that we are all set up, enable the APIC
458 value
= apic_read(APIC_SPIV
);
459 value
&= ~APIC_VECTOR_MASK
;
463 value
|= APIC_SPIV_APIC_ENABLED
;
465 /* We always use processor focus */
468 * Set spurious IRQ vector
470 value
|= SPURIOUS_APIC_VECTOR
;
471 apic_write(APIC_SPIV
, value
);
476 * set up through-local-APIC on the BP's LINT0. This is not
477 * strictly necessary in pure symmetric-IO mode, but sometimes
478 * we delegate interrupts to the 8259A.
481 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
483 value
= apic_read(APIC_LVT0
) & APIC_LVT_MASKED
;
484 if (!smp_processor_id() && !value
) {
485 value
= APIC_DM_EXTINT
;
486 apic_printk(APIC_VERBOSE
, "enabled ExtINT on CPU#%d\n", smp_processor_id());
488 value
= APIC_DM_EXTINT
| APIC_LVT_MASKED
;
489 apic_printk(APIC_VERBOSE
, "masked ExtINT on CPU#%d\n", smp_processor_id());
491 apic_write(APIC_LVT0
, value
);
494 * only the BP should see the LINT1 NMI signal, obviously.
496 if (!smp_processor_id())
499 value
= APIC_DM_NMI
| APIC_LVT_MASKED
;
500 apic_write(APIC_LVT1
, value
);
504 maxlvt
= get_maxlvt();
505 oldvalue
= apic_read(APIC_ESR
);
506 value
= ERROR_APIC_VECTOR
; // enables sending errors
507 apic_write(APIC_LVTERR
, value
);
509 * spec says clear errors after enabling vector.
512 apic_write(APIC_ESR
, 0);
513 value
= apic_read(APIC_ESR
);
514 if (value
!= oldvalue
)
515 apic_printk(APIC_VERBOSE
,
516 "ESR value after enabling vector: %08x, after %08x\n",
520 nmi_watchdog_default();
521 setup_apic_nmi_watchdog(NULL
);
528 /* 'active' is true if the local APIC was enabled by us and
529 not the BIOS; this signifies that we are also responsible
530 for disabling it before entering apm/acpi suspend */
532 /* r/w apic fields */
533 unsigned int apic_id
;
534 unsigned int apic_taskpri
;
535 unsigned int apic_ldr
;
536 unsigned int apic_dfr
;
537 unsigned int apic_spiv
;
538 unsigned int apic_lvtt
;
539 unsigned int apic_lvtpc
;
540 unsigned int apic_lvt0
;
541 unsigned int apic_lvt1
;
542 unsigned int apic_lvterr
;
543 unsigned int apic_tmict
;
544 unsigned int apic_tdcr
;
545 unsigned int apic_thmr
;
548 static int lapic_suspend(struct sys_device
*dev
, pm_message_t state
)
553 if (!apic_pm_state
.active
)
556 maxlvt
= get_maxlvt();
558 apic_pm_state
.apic_id
= apic_read(APIC_ID
);
559 apic_pm_state
.apic_taskpri
= apic_read(APIC_TASKPRI
);
560 apic_pm_state
.apic_ldr
= apic_read(APIC_LDR
);
561 apic_pm_state
.apic_dfr
= apic_read(APIC_DFR
);
562 apic_pm_state
.apic_spiv
= apic_read(APIC_SPIV
);
563 apic_pm_state
.apic_lvtt
= apic_read(APIC_LVTT
);
565 apic_pm_state
.apic_lvtpc
= apic_read(APIC_LVTPC
);
566 apic_pm_state
.apic_lvt0
= apic_read(APIC_LVT0
);
567 apic_pm_state
.apic_lvt1
= apic_read(APIC_LVT1
);
568 apic_pm_state
.apic_lvterr
= apic_read(APIC_LVTERR
);
569 apic_pm_state
.apic_tmict
= apic_read(APIC_TMICT
);
570 apic_pm_state
.apic_tdcr
= apic_read(APIC_TDCR
);
571 #ifdef CONFIG_X86_MCE_INTEL
573 apic_pm_state
.apic_thmr
= apic_read(APIC_LVTTHMR
);
575 local_irq_save(flags
);
576 disable_local_APIC();
577 local_irq_restore(flags
);
581 static int lapic_resume(struct sys_device
*dev
)
587 if (!apic_pm_state
.active
)
590 maxlvt
= get_maxlvt();
592 local_irq_save(flags
);
593 rdmsr(MSR_IA32_APICBASE
, l
, h
);
594 l
&= ~MSR_IA32_APICBASE_BASE
;
595 l
|= MSR_IA32_APICBASE_ENABLE
| mp_lapic_addr
;
596 wrmsr(MSR_IA32_APICBASE
, l
, h
);
597 apic_write(APIC_LVTERR
, ERROR_APIC_VECTOR
| APIC_LVT_MASKED
);
598 apic_write(APIC_ID
, apic_pm_state
.apic_id
);
599 apic_write(APIC_DFR
, apic_pm_state
.apic_dfr
);
600 apic_write(APIC_LDR
, apic_pm_state
.apic_ldr
);
601 apic_write(APIC_TASKPRI
, apic_pm_state
.apic_taskpri
);
602 apic_write(APIC_SPIV
, apic_pm_state
.apic_spiv
);
603 apic_write(APIC_LVT0
, apic_pm_state
.apic_lvt0
);
604 apic_write(APIC_LVT1
, apic_pm_state
.apic_lvt1
);
605 #ifdef CONFIG_X86_MCE_INTEL
607 apic_write(APIC_LVTTHMR
, apic_pm_state
.apic_thmr
);
610 apic_write(APIC_LVTPC
, apic_pm_state
.apic_lvtpc
);
611 apic_write(APIC_LVTT
, apic_pm_state
.apic_lvtt
);
612 apic_write(APIC_TDCR
, apic_pm_state
.apic_tdcr
);
613 apic_write(APIC_TMICT
, apic_pm_state
.apic_tmict
);
614 apic_write(APIC_ESR
, 0);
616 apic_write(APIC_LVTERR
, apic_pm_state
.apic_lvterr
);
617 apic_write(APIC_ESR
, 0);
619 local_irq_restore(flags
);
623 static struct sysdev_class lapic_sysclass
= {
624 set_kset_name("lapic"),
625 .resume
= lapic_resume
,
626 .suspend
= lapic_suspend
,
629 static struct sys_device device_lapic
= {
631 .cls
= &lapic_sysclass
,
634 static void __cpuinit
apic_pm_activate(void)
636 apic_pm_state
.active
= 1;
639 static int __init
init_lapic_sysfs(void)
644 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
645 error
= sysdev_class_register(&lapic_sysclass
);
647 error
= sysdev_register(&device_lapic
);
650 device_initcall(init_lapic_sysfs
);
652 #else /* CONFIG_PM */
654 static void apic_pm_activate(void) { }
656 #endif /* CONFIG_PM */
658 static int __init
apic_set_verbosity(char *str
)
661 skip_ioapic_setup
= 0;
665 if (strcmp("debug", str
) == 0)
666 apic_verbosity
= APIC_DEBUG
;
667 else if (strcmp("verbose", str
) == 0)
668 apic_verbosity
= APIC_VERBOSE
;
670 printk(KERN_WARNING
"APIC Verbosity level %s not recognised"
671 " use apic=verbose or apic=debug\n", str
);
677 early_param("apic", apic_set_verbosity
);
680 * Detect and enable local APICs on non-SMP boards.
681 * Original code written by Keir Fraser.
682 * On AMD64 we trust the BIOS - if it says no APIC it is likely
683 * not correctly set up (usually the APIC timer won't work etc.)
686 static int __init
detect_init_APIC (void)
689 printk(KERN_INFO
"No local APIC present\n");
693 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
698 #ifdef CONFIG_X86_IO_APIC
699 static struct resource
* __init
ioapic_setup_resources(void)
701 #define IOAPIC_RESOURCE_NAME_SIZE 11
703 struct resource
*res
;
710 n
= IOAPIC_RESOURCE_NAME_SIZE
+ sizeof(struct resource
);
713 mem
= alloc_bootmem(n
);
718 mem
+= sizeof(struct resource
) * nr_ioapics
;
720 for (i
= 0; i
< nr_ioapics
; i
++) {
722 res
[i
].flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
;
723 sprintf(mem
, "IOAPIC %u", i
);
724 mem
+= IOAPIC_RESOURCE_NAME_SIZE
;
728 ioapic_resources
= res
;
733 static int __init
ioapic_insert_resources(void)
736 struct resource
*r
= ioapic_resources
;
739 printk("IO APIC resources could be not be allocated.\n");
743 for (i
= 0; i
< nr_ioapics
; i
++) {
744 insert_resource(&iomem_resource
, r
);
751 /* Insert the IO APIC resources after PCI initialization has occured to handle
752 * IO APICS that are mapped in on a BAR in PCI space. */
753 late_initcall(ioapic_insert_resources
);
756 void __init
init_apic_mappings(void)
758 unsigned long apic_phys
;
761 * If no local APIC can be found then set up a fake all
762 * zeroes page to simulate the local APIC and another
763 * one for the IO-APIC.
765 if (!smp_found_config
&& detect_init_APIC()) {
766 apic_phys
= (unsigned long) alloc_bootmem_pages(PAGE_SIZE
);
767 apic_phys
= __pa(apic_phys
);
769 apic_phys
= mp_lapic_addr
;
771 set_fixmap_nocache(FIX_APIC_BASE
, apic_phys
);
772 apic_printk(APIC_VERBOSE
, "mapped APIC to %16lx (%16lx)\n",
773 APIC_BASE
, apic_phys
);
775 /* Put local APIC into the resource map. */
776 lapic_resource
.start
= apic_phys
;
777 lapic_resource
.end
= lapic_resource
.start
+ PAGE_SIZE
- 1;
778 insert_resource(&iomem_resource
, &lapic_resource
);
781 * Fetch the APIC ID of the BSP in case we have a
782 * default configuration (or the MP table is broken).
784 boot_cpu_id
= GET_APIC_ID(apic_read(APIC_ID
));
787 unsigned long ioapic_phys
, idx
= FIX_IO_APIC_BASE_0
;
789 struct resource
*ioapic_res
;
791 ioapic_res
= ioapic_setup_resources();
792 for (i
= 0; i
< nr_ioapics
; i
++) {
793 if (smp_found_config
) {
794 ioapic_phys
= mp_ioapics
[i
].mpc_apicaddr
;
796 ioapic_phys
= (unsigned long) alloc_bootmem_pages(PAGE_SIZE
);
797 ioapic_phys
= __pa(ioapic_phys
);
799 set_fixmap_nocache(idx
, ioapic_phys
);
800 apic_printk(APIC_VERBOSE
,"mapped IOAPIC to %016lx (%016lx)\n",
801 __fix_to_virt(idx
), ioapic_phys
);
804 if (ioapic_res
!= NULL
) {
805 ioapic_res
->start
= ioapic_phys
;
806 ioapic_res
->end
= ioapic_phys
+ (4 * 1024) - 1;
814 * This function sets up the local APIC timer, with a timeout of
815 * 'clocks' APIC bus clock. During calibration we actually call
816 * this function twice on the boot CPU, once with a bogus timeout
817 * value, second time for real. The other (noncalibrating) CPUs
818 * call this function only once, with the real, calibrated value.
820 * We do reads before writes even if unnecessary, to get around the
821 * P5 APIC double write bug.
824 static void __setup_APIC_LVTT(unsigned int clocks
, int oneshot
, int irqen
)
826 unsigned int lvtt_value
, tmp_value
;
828 lvtt_value
= LOCAL_TIMER_VECTOR
;
830 lvtt_value
|= APIC_LVT_TIMER_PERIODIC
;
832 lvtt_value
|= APIC_LVT_MASKED
;
834 apic_write(APIC_LVTT
, lvtt_value
);
839 tmp_value
= apic_read(APIC_TDCR
);
840 apic_write(APIC_TDCR
, (tmp_value
841 & ~(APIC_TDR_DIV_1
| APIC_TDR_DIV_TMBASE
))
845 apic_write(APIC_TMICT
, clocks
);
848 static void setup_APIC_timer(void)
850 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
852 memcpy(levt
, &lapic_clockevent
, sizeof(*levt
));
853 levt
->cpumask
= cpumask_of_cpu(smp_processor_id());
855 clockevents_register_device(levt
);
859 * In this function we calibrate APIC bus clocks to the external
860 * timer. Unfortunately we cannot use jiffies and the timer irq
861 * to calibrate, since some later bootup code depends on getting
862 * the first irq? Ugh.
864 * We want to do the calibration only once since we
865 * want to have local timer irqs syncron. CPUs connected
866 * by the same APIC bus have the very same bus frequency.
867 * And we want to have irqs off anyways, no accidental
871 #define TICK_COUNT 100000000
873 static void __init
calibrate_APIC_clock(void)
875 unsigned apic
, apic_start
;
876 unsigned long tsc
, tsc_start
;
882 * Put whatever arbitrary (but long enough) timeout
883 * value into the APIC clock, we just want to get the
884 * counter running for calibration.
886 * No interrupt enable !
888 __setup_APIC_LVTT(250000000, 0, 0);
890 apic_start
= apic_read(APIC_TMCCT
);
891 #ifdef CONFIG_X86_PM_TIMER
892 if (apic_calibrate_pmtmr
&& pmtmr_ioport
) {
893 pmtimer_wait(5000); /* 5ms wait */
894 apic
= apic_read(APIC_TMCCT
);
895 result
= (apic_start
- apic
) * 1000L / 5;
902 apic
= apic_read(APIC_TMCCT
);
904 } while ((tsc
- tsc_start
) < TICK_COUNT
&&
905 (apic_start
- apic
) < TICK_COUNT
);
907 result
= (apic_start
- apic
) * 1000L * tsc_khz
/
913 printk(KERN_DEBUG
"APIC timer calibration result %d\n", result
);
915 printk(KERN_INFO
"Detected %d.%03d MHz APIC timer.\n",
916 result
/ 1000 / 1000, result
/ 1000 % 1000);
918 /* Calculate the scaled math multiplication factor */
919 lapic_clockevent
.mult
= div_sc(result
, NSEC_PER_SEC
, 32);
920 lapic_clockevent
.max_delta_ns
=
921 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent
);
922 lapic_clockevent
.min_delta_ns
=
923 clockevent_delta2ns(0xF, &lapic_clockevent
);
925 calibration_result
= result
/ HZ
;
928 void __init
setup_boot_APIC_clock (void)
931 * The local apic timer can be disabled via the kernel commandline.
932 * Register the lapic timer as a dummy clock event source on SMP
933 * systems, so the broadcast mechanism is used. On UP systems simply
936 if (disable_apic_timer
) {
937 printk(KERN_INFO
"Disabling APIC timer\n");
938 /* No broadcast on UP ! */
939 if (num_possible_cpus() > 1)
944 printk(KERN_INFO
"Using local APIC timer interrupts.\n");
945 calibrate_APIC_clock();
948 * If nmi_watchdog is set to IO_APIC, we need the
949 * PIT/HPET going. Otherwise register lapic as a dummy
952 if (nmi_watchdog
!= NMI_IO_APIC
)
953 lapic_clockevent
.features
&= ~CLOCK_EVT_FEAT_DUMMY
;
955 printk(KERN_WARNING
"APIC timer registered as dummy,"
956 " due to nmi_watchdog=1!\n");
961 void __cpuinit
setup_secondary_APIC_clock(void)
966 int setup_profiling_timer(unsigned int multiplier
)
971 void setup_APIC_extended_lvt(unsigned char lvt_off
, unsigned char vector
,
972 unsigned char msg_type
, unsigned char mask
)
974 unsigned long reg
= (lvt_off
<< 4) + K8_APIC_EXT_LVT_BASE
;
975 unsigned int v
= (mask
<< 16) | (msg_type
<< 8) | vector
;
980 * Local timer interrupt handler. It does both profiling and
981 * process statistics/rescheduling.
983 * We do profiling in every local tick, statistics/rescheduling
984 * happen only every 'profiling multiplier' ticks. The default
985 * multiplier is 1 and it can be changed by writing the new multiplier
986 * value into /proc/profile.
989 void smp_local_timer_interrupt(void)
991 int cpu
= smp_processor_id();
992 struct clock_event_device
*evt
= &per_cpu(lapic_events
, cpu
);
995 * Normally we should not be here till LAPIC has been initialized but
996 * in some cases like kdump, its possible that there is a pending LAPIC
997 * timer interrupt from previous kernel's context and is delivered in
998 * new kernel the moment interrupts are enabled.
1000 * Interrupts are enabled early and LAPIC is setup much later, hence
1001 * its possible that when we get here evt->event_handler is NULL.
1002 * Check for event_handler being NULL and discard the interrupt as
1005 if (!evt
->event_handler
) {
1007 "Spurious LAPIC timer interrupt on cpu %d\n", cpu
);
1009 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, evt
);
1014 * the NMI deadlock-detector uses this.
1016 add_pda(apic_timer_irqs
, 1);
1018 evt
->event_handler(evt
);
1022 * Local APIC timer interrupt. This is the most natural way for doing
1023 * local interrupts, but local timer interrupts can be emulated by
1024 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
1026 * [ if a single-CPU system runs an SMP kernel then we call the local
1027 * interrupt as well. Thus we cannot inline the local irq ... ]
1029 void smp_apic_timer_interrupt(struct pt_regs
*regs
)
1031 struct pt_regs
*old_regs
= set_irq_regs(regs
);
1034 * NOTE! We'd better ACK the irq immediately,
1035 * because timer handling can be slow.
1039 * update_process_times() expects us to have done irq_enter().
1040 * Besides, if we don't timer interrupts ignore the global
1041 * interrupt lock, which is the WrongThing (tm) to do.
1045 smp_local_timer_interrupt();
1047 set_irq_regs(old_regs
);
1051 * apic_is_clustered_box() -- Check if we can expect good TSC
1053 * Thus far, the major user of this is IBM's Summit2 series:
1055 * Clustered boxes may have unsynced TSC problems if they are
1056 * multi-chassis. Use available data to take a good guess.
1057 * If in doubt, go HPET.
1059 __cpuinit
int apic_is_clustered_box(void)
1061 int i
, clusters
, zeros
;
1063 DECLARE_BITMAP(clustermap
, NUM_APIC_CLUSTERS
);
1065 bitmap_zero(clustermap
, NUM_APIC_CLUSTERS
);
1067 for (i
= 0; i
< NR_CPUS
; i
++) {
1068 id
= bios_cpu_apicid
[i
];
1069 if (id
!= BAD_APICID
)
1070 __set_bit(APIC_CLUSTERID(id
), clustermap
);
1073 /* Problem: Partially populated chassis may not have CPUs in some of
1074 * the APIC clusters they have been allocated. Only present CPUs have
1075 * bios_cpu_apicid entries, thus causing zeroes in the bitmap. Since
1076 * clusters are allocated sequentially, count zeros only if they are
1081 for (i
= 0; i
< NUM_APIC_CLUSTERS
; i
++) {
1082 if (test_bit(i
, clustermap
)) {
1083 clusters
+= 1 + zeros
;
1090 * If clusters > 2, then should be multi-chassis.
1091 * May have to revisit this when multi-core + hyperthreaded CPUs come
1092 * out, but AFAIK this will work even for them.
1094 return (clusters
> 2);
1098 * This interrupt should _never_ happen with our APIC/SMP architecture
1100 asmlinkage
void smp_spurious_interrupt(void)
1106 * Check if this really is a spurious interrupt and ACK it
1107 * if it is a vectored one. Just in case...
1108 * Spurious interrupts should not be ACKed.
1110 v
= apic_read(APIC_ISR
+ ((SPURIOUS_APIC_VECTOR
& ~0x1f) >> 1));
1111 if (v
& (1 << (SPURIOUS_APIC_VECTOR
& 0x1f)))
1118 * This interrupt should never happen with our APIC/SMP architecture
1121 asmlinkage
void smp_error_interrupt(void)
1127 /* First tickle the hardware, only then report what went on. -- REW */
1128 v
= apic_read(APIC_ESR
);
1129 apic_write(APIC_ESR
, 0);
1130 v1
= apic_read(APIC_ESR
);
1132 atomic_inc(&irq_err_count
);
1134 /* Here is what the APIC error bits mean:
1137 2: Send accept error
1138 3: Receive accept error
1140 5: Send illegal vector
1141 6: Received illegal vector
1142 7: Illegal register address
1144 printk (KERN_DEBUG
"APIC error on CPU%d: %02x(%02x)\n",
1145 smp_processor_id(), v
, v1
);
1152 * This initializes the IO-APIC and APIC hardware if this is
1155 int __init
APIC_init_uniprocessor (void)
1158 printk(KERN_INFO
"Apic disabled\n");
1161 if (!cpu_has_apic
) {
1163 printk(KERN_INFO
"Apic disabled by BIOS\n");
1167 verify_local_APIC();
1169 phys_cpu_present_map
= physid_mask_of_physid(boot_cpu_id
);
1170 apic_write(APIC_ID
, SET_APIC_ID(boot_cpu_id
));
1174 if (smp_found_config
&& !skip_ioapic_setup
&& nr_ioapics
)
1178 setup_boot_APIC_clock();
1179 check_nmi_watchdog();
1183 static __init
int setup_disableapic(char *str
)
1186 clear_bit(X86_FEATURE_APIC
, boot_cpu_data
.x86_capability
);
1189 early_param("disableapic", setup_disableapic
);
1191 /* same as disableapic, for compatibility */
1192 static __init
int setup_nolapic(char *str
)
1194 return setup_disableapic(str
);
1196 early_param("nolapic", setup_nolapic
);
1198 static int __init
parse_lapic_timer_c2_ok(char *arg
)
1200 local_apic_timer_c2_ok
= 1;
1203 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok
);
1205 static __init
int setup_noapictimer(char *str
)
1207 if (str
[0] != ' ' && str
[0] != 0)
1209 disable_apic_timer
= 1;
1212 __setup("noapictimer", setup_noapictimer
);
1214 static __init
int setup_apicpmtimer(char *s
)
1216 apic_calibrate_pmtmr
= 1;
1220 __setup("apicpmtimer", setup_apicpmtimer
);