2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/bootmem.h>
22 #include <linux/interrupt.h>
23 #include <linux/mc146818rtc.h>
24 #include <linux/kernel_stat.h>
25 #include <linux/sysdev.h>
26 #include <linux/ioport.h>
27 #include <linux/clockchips.h>
28 #include <linux/acpi_pmtmr.h>
29 #include <linux/module.h>
31 #include <asm/atomic.h>
34 #include <asm/mpspec.h>
36 #include <asm/pgalloc.h>
37 #include <asm/mach_apic.h>
40 #include <asm/proto.h>
41 #include <asm/timex.h>
46 int disable_apic_timer __cpuinitdata
;
47 static int apic_calibrate_pmtmr __initdata
;
50 /* Local APIC timer works in C2 */
51 int local_apic_timer_c2_ok
;
52 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok
);
55 * Debug level, exported for io_apic.c
59 static struct resource lapic_resource
= {
61 .flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
,
64 static unsigned int calibration_result
;
66 static int lapic_next_event(unsigned long delta
,
67 struct clock_event_device
*evt
);
68 static void lapic_timer_setup(enum clock_event_mode mode
,
69 struct clock_event_device
*evt
);
70 static void lapic_timer_broadcast(cpumask_t mask
);
71 static void apic_pm_activate(void);
73 static struct clock_event_device lapic_clockevent
= {
75 .features
= CLOCK_EVT_FEAT_PERIODIC
| CLOCK_EVT_FEAT_ONESHOT
76 | CLOCK_EVT_FEAT_C3STOP
| CLOCK_EVT_FEAT_DUMMY
,
78 .set_mode
= lapic_timer_setup
,
79 .set_next_event
= lapic_next_event
,
80 .broadcast
= lapic_timer_broadcast
,
84 static DEFINE_PER_CPU(struct clock_event_device
, lapic_events
);
86 static unsigned long apic_phys
;
89 * Get the LAPIC version
91 static inline int lapic_get_version(void)
93 return GET_APIC_VERSION(apic_read(APIC_LVR
));
97 * Check, if the APIC is integrated or a seperate chip
99 static inline int lapic_is_integrated(void)
105 * Check, whether this is a modern or a first generation APIC
107 static int modern_apic(void)
109 /* AMD systems use old APIC versions, so check the CPU */
110 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
&&
111 boot_cpu_data
.x86
>= 0xf)
113 return lapic_get_version() >= 0x14;
116 void apic_wait_icr_idle(void)
118 while (apic_read(APIC_ICR
) & APIC_ICR_BUSY
)
122 u32
safe_apic_wait_icr_idle(void)
129 send_status
= apic_read(APIC_ICR
) & APIC_ICR_BUSY
;
133 } while (timeout
++ < 1000);
139 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
141 void __cpuinit
enable_NMI_through_LVT0(void)
145 /* unmask and set to NMI */
147 apic_write(APIC_LVT0
, v
);
151 * lapic_get_maxlvt - get the maximum number of local vector table entries
153 int lapic_get_maxlvt(void)
155 unsigned int v
, maxlvt
;
157 v
= apic_read(APIC_LVR
);
158 maxlvt
= GET_APIC_MAXLVT(v
);
163 * This function sets up the local APIC timer, with a timeout of
164 * 'clocks' APIC bus clock. During calibration we actually call
165 * this function twice on the boot CPU, once with a bogus timeout
166 * value, second time for real. The other (noncalibrating) CPUs
167 * call this function only once, with the real, calibrated value.
169 * We do reads before writes even if unnecessary, to get around the
170 * P5 APIC double write bug.
173 static void __setup_APIC_LVTT(unsigned int clocks
, int oneshot
, int irqen
)
175 unsigned int lvtt_value
, tmp_value
;
177 lvtt_value
= LOCAL_TIMER_VECTOR
;
179 lvtt_value
|= APIC_LVT_TIMER_PERIODIC
;
181 lvtt_value
|= APIC_LVT_MASKED
;
183 apic_write(APIC_LVTT
, lvtt_value
);
188 tmp_value
= apic_read(APIC_TDCR
);
189 apic_write(APIC_TDCR
, (tmp_value
190 & ~(APIC_TDR_DIV_1
| APIC_TDR_DIV_TMBASE
))
194 apic_write(APIC_TMICT
, clocks
);
198 * Setup extended LVT, AMD specific (K8, family 10h)
200 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
201 * MCE interrupts are supported. Thus MCE offset must be set to 0.
204 #define APIC_EILVT_LVTOFF_MCE 0
205 #define APIC_EILVT_LVTOFF_IBS 1
207 static void setup_APIC_eilvt(u8 lvt_off
, u8 vector
, u8 msg_type
, u8 mask
)
209 unsigned long reg
= (lvt_off
<< 4) + APIC_EILVT0
;
210 unsigned int v
= (mask
<< 16) | (msg_type
<< 8) | vector
;
215 u8
setup_APIC_eilvt_mce(u8 vector
, u8 msg_type
, u8 mask
)
217 setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE
, vector
, msg_type
, mask
);
218 return APIC_EILVT_LVTOFF_MCE
;
221 u8
setup_APIC_eilvt_ibs(u8 vector
, u8 msg_type
, u8 mask
)
223 setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS
, vector
, msg_type
, mask
);
224 return APIC_EILVT_LVTOFF_IBS
;
228 * Program the next event, relative to now
230 static int lapic_next_event(unsigned long delta
,
231 struct clock_event_device
*evt
)
233 apic_write(APIC_TMICT
, delta
);
238 * Setup the lapic timer in periodic or oneshot mode
240 static void lapic_timer_setup(enum clock_event_mode mode
,
241 struct clock_event_device
*evt
)
246 /* Lapic used as dummy for broadcast ? */
247 if (evt
->features
& CLOCK_EVT_FEAT_DUMMY
)
250 local_irq_save(flags
);
253 case CLOCK_EVT_MODE_PERIODIC
:
254 case CLOCK_EVT_MODE_ONESHOT
:
255 __setup_APIC_LVTT(calibration_result
,
256 mode
!= CLOCK_EVT_MODE_PERIODIC
, 1);
258 case CLOCK_EVT_MODE_UNUSED
:
259 case CLOCK_EVT_MODE_SHUTDOWN
:
260 v
= apic_read(APIC_LVTT
);
261 v
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
262 apic_write(APIC_LVTT
, v
);
264 case CLOCK_EVT_MODE_RESUME
:
265 /* Nothing to do here */
269 local_irq_restore(flags
);
273 * Local APIC timer broadcast function
275 static void lapic_timer_broadcast(cpumask_t mask
)
278 send_IPI_mask(mask
, LOCAL_TIMER_VECTOR
);
283 * Setup the local APIC timer for this CPU. Copy the initilized values
284 * of the boot CPU and register the clock event in the framework.
286 static void setup_APIC_timer(void)
288 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
290 memcpy(levt
, &lapic_clockevent
, sizeof(*levt
));
291 levt
->cpumask
= cpumask_of_cpu(smp_processor_id());
293 clockevents_register_device(levt
);
297 * In this function we calibrate APIC bus clocks to the external
298 * timer. Unfortunately we cannot use jiffies and the timer irq
299 * to calibrate, since some later bootup code depends on getting
300 * the first irq? Ugh.
302 * We want to do the calibration only once since we
303 * want to have local timer irqs syncron. CPUs connected
304 * by the same APIC bus have the very same bus frequency.
305 * And we want to have irqs off anyways, no accidental
309 #define TICK_COUNT 100000000
311 static void __init
calibrate_APIC_clock(void)
313 unsigned apic
, apic_start
;
314 unsigned long tsc
, tsc_start
;
320 * Put whatever arbitrary (but long enough) timeout
321 * value into the APIC clock, we just want to get the
322 * counter running for calibration.
324 * No interrupt enable !
326 __setup_APIC_LVTT(250000000, 0, 0);
328 apic_start
= apic_read(APIC_TMCCT
);
329 #ifdef CONFIG_X86_PM_TIMER
330 if (apic_calibrate_pmtmr
&& pmtmr_ioport
) {
331 pmtimer_wait(5000); /* 5ms wait */
332 apic
= apic_read(APIC_TMCCT
);
333 result
= (apic_start
- apic
) * 1000L / 5;
340 apic
= apic_read(APIC_TMCCT
);
342 } while ((tsc
- tsc_start
) < TICK_COUNT
&&
343 (apic_start
- apic
) < TICK_COUNT
);
345 result
= (apic_start
- apic
) * 1000L * tsc_khz
/
351 printk(KERN_DEBUG
"APIC timer calibration result %d\n", result
);
353 printk(KERN_INFO
"Detected %d.%03d MHz APIC timer.\n",
354 result
/ 1000 / 1000, result
/ 1000 % 1000);
356 /* Calculate the scaled math multiplication factor */
357 lapic_clockevent
.mult
= div_sc(result
, NSEC_PER_SEC
, 32);
358 lapic_clockevent
.max_delta_ns
=
359 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent
);
360 lapic_clockevent
.min_delta_ns
=
361 clockevent_delta2ns(0xF, &lapic_clockevent
);
363 calibration_result
= result
/ HZ
;
367 * Setup the boot APIC
369 * Calibrate and verify the result.
371 void __init
setup_boot_APIC_clock(void)
374 * The local apic timer can be disabled via the kernel commandline.
375 * Register the lapic timer as a dummy clock event source on SMP
376 * systems, so the broadcast mechanism is used. On UP systems simply
379 if (disable_apic_timer
) {
380 printk(KERN_INFO
"Disabling APIC timer\n");
381 /* No broadcast on UP ! */
382 if (num_possible_cpus() > 1) {
383 lapic_clockevent
.mult
= 1;
389 printk(KERN_INFO
"Using local APIC timer interrupts.\n");
390 calibrate_APIC_clock();
393 * Do a sanity check on the APIC calibration result
395 if (calibration_result
< (1000000 / HZ
)) {
397 "APIC frequency too slow, disabling apic timer\n");
398 /* No broadcast on UP ! */
399 if (num_possible_cpus() > 1)
405 * If nmi_watchdog is set to IO_APIC, we need the
406 * PIT/HPET going. Otherwise register lapic as a dummy
409 if (nmi_watchdog
!= NMI_IO_APIC
)
410 lapic_clockevent
.features
&= ~CLOCK_EVT_FEAT_DUMMY
;
412 printk(KERN_WARNING
"APIC timer registered as dummy,"
413 " due to nmi_watchdog=1!\n");
419 * AMD C1E enabled CPUs have a real nasty problem: Some BIOSes set the
420 * C1E flag only in the secondary CPU, so when we detect the wreckage
421 * we already have enabled the boot CPU local apic timer. Check, if
422 * disable_apic_timer is set and the DUMMY flag is cleared. If yes,
423 * set the DUMMY flag again and force the broadcast mode in the
426 void __cpuinit
check_boot_apic_timer_broadcast(void)
428 if (!disable_apic_timer
||
429 (lapic_clockevent
.features
& CLOCK_EVT_FEAT_DUMMY
))
432 printk(KERN_INFO
"AMD C1E detected late. Force timer broadcast.\n");
433 lapic_clockevent
.features
|= CLOCK_EVT_FEAT_DUMMY
;
436 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE
,
437 &boot_cpu_physical_apicid
);
441 void __cpuinit
setup_secondary_APIC_clock(void)
443 check_boot_apic_timer_broadcast();
448 * The guts of the apic timer interrupt
450 static void local_apic_timer_interrupt(void)
452 int cpu
= smp_processor_id();
453 struct clock_event_device
*evt
= &per_cpu(lapic_events
, cpu
);
456 * Normally we should not be here till LAPIC has been initialized but
457 * in some cases like kdump, its possible that there is a pending LAPIC
458 * timer interrupt from previous kernel's context and is delivered in
459 * new kernel the moment interrupts are enabled.
461 * Interrupts are enabled early and LAPIC is setup much later, hence
462 * its possible that when we get here evt->event_handler is NULL.
463 * Check for event_handler being NULL and discard the interrupt as
466 if (!evt
->event_handler
) {
468 "Spurious LAPIC timer interrupt on cpu %d\n", cpu
);
470 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, evt
);
475 * the NMI deadlock-detector uses this.
477 add_pda(apic_timer_irqs
, 1);
479 evt
->event_handler(evt
);
483 * Local APIC timer interrupt. This is the most natural way for doing
484 * local interrupts, but local timer interrupts can be emulated by
485 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
487 * [ if a single-CPU system runs an SMP kernel then we call the local
488 * interrupt as well. Thus we cannot inline the local irq ... ]
490 void smp_apic_timer_interrupt(struct pt_regs
*regs
)
492 struct pt_regs
*old_regs
= set_irq_regs(regs
);
495 * NOTE! We'd better ACK the irq immediately,
496 * because timer handling can be slow.
500 * update_process_times() expects us to have done irq_enter().
501 * Besides, if we don't timer interrupts ignore the global
502 * interrupt lock, which is the WrongThing (tm) to do.
506 local_apic_timer_interrupt();
508 set_irq_regs(old_regs
);
511 int setup_profiling_timer(unsigned int multiplier
)
518 * Local APIC start and shutdown
522 * clear_local_APIC - shutdown the local APIC
524 * This is called, when a CPU is disabled and before rebooting, so the state of
525 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
526 * leftovers during boot.
528 void clear_local_APIC(void)
530 int maxlvt
= lapic_get_maxlvt();
533 /* APIC hasn't been mapped yet */
537 maxlvt
= lapic_get_maxlvt();
539 * Masking an LVT entry can trigger a local APIC error
540 * if the vector is zero. Mask LVTERR first to prevent this.
543 v
= ERROR_APIC_VECTOR
; /* any non-zero vector will do */
544 apic_write(APIC_LVTERR
, v
| APIC_LVT_MASKED
);
547 * Careful: we have to set masks only first to deassert
548 * any level-triggered sources.
550 v
= apic_read(APIC_LVTT
);
551 apic_write(APIC_LVTT
, v
| APIC_LVT_MASKED
);
552 v
= apic_read(APIC_LVT0
);
553 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
554 v
= apic_read(APIC_LVT1
);
555 apic_write(APIC_LVT1
, v
| APIC_LVT_MASKED
);
557 v
= apic_read(APIC_LVTPC
);
558 apic_write(APIC_LVTPC
, v
| APIC_LVT_MASKED
);
562 * Clean APIC state for other OSs:
564 apic_write(APIC_LVTT
, APIC_LVT_MASKED
);
565 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
566 apic_write(APIC_LVT1
, APIC_LVT_MASKED
);
568 apic_write(APIC_LVTERR
, APIC_LVT_MASKED
);
570 apic_write(APIC_LVTPC
, APIC_LVT_MASKED
);
571 apic_write(APIC_ESR
, 0);
576 * disable_local_APIC - clear and disable the local APIC
578 void disable_local_APIC(void)
585 * Disable APIC (implies clearing of registers
588 value
= apic_read(APIC_SPIV
);
589 value
&= ~APIC_SPIV_APIC_ENABLED
;
590 apic_write(APIC_SPIV
, value
);
593 void lapic_shutdown(void)
600 local_irq_save(flags
);
602 disable_local_APIC();
604 local_irq_restore(flags
);
608 * This is to verify that we're looking at a real local APIC.
609 * Check these against your board if the CPUs aren't getting
610 * started for no apparent reason.
612 int __init
verify_local_APIC(void)
614 unsigned int reg0
, reg1
;
617 * The version register is read-only in a real APIC.
619 reg0
= apic_read(APIC_LVR
);
620 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg0
);
621 apic_write(APIC_LVR
, reg0
^ APIC_LVR_MASK
);
622 reg1
= apic_read(APIC_LVR
);
623 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg1
);
626 * The two version reads above should print the same
627 * numbers. If the second one is different, then we
628 * poke at a non-APIC.
634 * Check if the version looks reasonably.
636 reg1
= GET_APIC_VERSION(reg0
);
637 if (reg1
== 0x00 || reg1
== 0xff)
639 reg1
= lapic_get_maxlvt();
640 if (reg1
< 0x02 || reg1
== 0xff)
644 * The ID register is read/write in a real APIC.
646 reg0
= apic_read(APIC_ID
);
647 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg0
);
648 apic_write(APIC_ID
, reg0
^ APIC_ID_MASK
);
649 reg1
= apic_read(APIC_ID
);
650 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg1
);
651 apic_write(APIC_ID
, reg0
);
652 if (reg1
!= (reg0
^ APIC_ID_MASK
))
656 * The next two are just to see if we have sane values.
657 * They're only really relevant if we're in Virtual Wire
658 * compatibility mode, but most boxes are anymore.
660 reg0
= apic_read(APIC_LVT0
);
661 apic_printk(APIC_DEBUG
, "Getting LVT0: %x\n", reg0
);
662 reg1
= apic_read(APIC_LVT1
);
663 apic_printk(APIC_DEBUG
, "Getting LVT1: %x\n", reg1
);
669 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
671 void __init
sync_Arb_IDs(void)
673 /* Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 */
680 apic_wait_icr_idle();
682 apic_printk(APIC_DEBUG
, "Synchronizing Arb IDs.\n");
683 apic_write(APIC_ICR
, APIC_DEST_ALLINC
| APIC_INT_LEVELTRIG
688 * An initial setup of the virtual wire mode.
690 void __init
init_bsp_APIC(void)
695 * Don't do the setup now if we have a SMP BIOS as the
696 * through-I/O-APIC virtual wire mode might be active.
698 if (smp_found_config
|| !cpu_has_apic
)
701 value
= apic_read(APIC_LVR
);
704 * Do not trust the local APIC being empty at bootup.
711 value
= apic_read(APIC_SPIV
);
712 value
&= ~APIC_VECTOR_MASK
;
713 value
|= APIC_SPIV_APIC_ENABLED
;
714 value
|= APIC_SPIV_FOCUS_DISABLED
;
715 value
|= SPURIOUS_APIC_VECTOR
;
716 apic_write(APIC_SPIV
, value
);
719 * Set up the virtual wire mode.
721 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
723 apic_write(APIC_LVT1
, value
);
727 * setup_local_APIC - setup the local APIC
729 void __cpuinit
setup_local_APIC(void)
734 value
= apic_read(APIC_LVR
);
736 BUILD_BUG_ON((SPURIOUS_APIC_VECTOR
& 0x0f) != 0x0f);
739 * Double-check whether this APIC is really registered.
740 * This is meaningless in clustered apic mode, so we skip it.
742 if (!apic_id_registered())
746 * Intel recommends to set DFR, LDR and TPR before enabling
747 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
748 * document number 292116). So here it goes...
753 * Set Task Priority to 'accept all'. We never change this
756 value
= apic_read(APIC_TASKPRI
);
757 value
&= ~APIC_TPRI_MASK
;
758 apic_write(APIC_TASKPRI
, value
);
761 * After a crash, we no longer service the interrupts and a pending
762 * interrupt from previous kernel might still have ISR bit set.
764 * Most probably by now CPU has serviced that pending interrupt and
765 * it might not have done the ack_APIC_irq() because it thought,
766 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
767 * does not clear the ISR bit and cpu thinks it has already serivced
768 * the interrupt. Hence a vector might get locked. It was noticed
769 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
771 for (i
= APIC_ISR_NR
- 1; i
>= 0; i
--) {
772 value
= apic_read(APIC_ISR
+ i
*0x10);
773 for (j
= 31; j
>= 0; j
--) {
780 * Now that we are all set up, enable the APIC
782 value
= apic_read(APIC_SPIV
);
783 value
&= ~APIC_VECTOR_MASK
;
787 value
|= APIC_SPIV_APIC_ENABLED
;
789 /* We always use processor focus */
792 * Set spurious IRQ vector
794 value
|= SPURIOUS_APIC_VECTOR
;
795 apic_write(APIC_SPIV
, value
);
800 * set up through-local-APIC on the BP's LINT0. This is not
801 * strictly necessary in pure symmetric-IO mode, but sometimes
802 * we delegate interrupts to the 8259A.
805 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
807 value
= apic_read(APIC_LVT0
) & APIC_LVT_MASKED
;
808 if (!smp_processor_id() && !value
) {
809 value
= APIC_DM_EXTINT
;
810 apic_printk(APIC_VERBOSE
, "enabled ExtINT on CPU#%d\n",
813 value
= APIC_DM_EXTINT
| APIC_LVT_MASKED
;
814 apic_printk(APIC_VERBOSE
, "masked ExtINT on CPU#%d\n",
817 apic_write(APIC_LVT0
, value
);
820 * only the BP should see the LINT1 NMI signal, obviously.
822 if (!smp_processor_id())
825 value
= APIC_DM_NMI
| APIC_LVT_MASKED
;
826 apic_write(APIC_LVT1
, value
);
829 void __cpuinit
lapic_setup_esr(void)
831 unsigned maxlvt
= lapic_get_maxlvt();
833 apic_write(APIC_LVTERR
, ERROR_APIC_VECTOR
);
835 * spec says clear errors after enabling vector.
838 apic_write(APIC_ESR
, 0);
841 void __cpuinit
end_local_APIC_setup(void)
844 nmi_watchdog_default();
845 setup_apic_nmi_watchdog(NULL
);
850 * Detect and enable local APICs on non-SMP boards.
851 * Original code written by Keir Fraser.
852 * On AMD64 we trust the BIOS - if it says no APIC it is likely
853 * not correctly set up (usually the APIC timer won't work etc.)
855 static int __init
detect_init_APIC(void)
858 printk(KERN_INFO
"No local APIC present\n");
862 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
863 boot_cpu_physical_apicid
= 0;
867 void __init
early_init_lapic_mapping(void)
869 unsigned long apic_phys
;
872 * If no local APIC can be found then go out
873 * : it means there is no mpatable and MADT
875 if (!smp_found_config
)
878 apic_phys
= mp_lapic_addr
;
880 set_fixmap_nocache(FIX_APIC_BASE
, apic_phys
);
881 apic_printk(APIC_VERBOSE
, "mapped APIC to %16lx (%16lx)\n",
882 APIC_BASE
, apic_phys
);
885 * Fetch the APIC ID of the BSP in case we have a
886 * default configuration (or the MP table is broken).
888 boot_cpu_physical_apicid
= GET_APIC_ID(apic_read(APIC_ID
));
892 * init_apic_mappings - initialize APIC mappings
894 void __init
init_apic_mappings(void)
897 * If no local APIC can be found then set up a fake all
898 * zeroes page to simulate the local APIC and another
899 * one for the IO-APIC.
901 if (!smp_found_config
&& detect_init_APIC()) {
902 apic_phys
= (unsigned long) alloc_bootmem_pages(PAGE_SIZE
);
903 apic_phys
= __pa(apic_phys
);
905 apic_phys
= mp_lapic_addr
;
907 set_fixmap_nocache(FIX_APIC_BASE
, apic_phys
);
908 apic_printk(APIC_VERBOSE
, "mapped APIC to %16lx (%16lx)\n",
909 APIC_BASE
, apic_phys
);
912 * Fetch the APIC ID of the BSP in case we have a
913 * default configuration (or the MP table is broken).
915 boot_cpu_physical_apicid
= GET_APIC_ID(apic_read(APIC_ID
));
919 * This initializes the IO-APIC and APIC hardware if this is
922 int __init
APIC_init_uniprocessor(void)
925 printk(KERN_INFO
"Apic disabled\n");
930 printk(KERN_INFO
"Apic disabled by BIOS\n");
936 phys_cpu_present_map
= physid_mask_of_physid(boot_cpu_physical_apicid
);
937 apic_write(APIC_ID
, SET_APIC_ID(boot_cpu_physical_apicid
));
942 * Now enable IO-APICs, actually call clear_IO_APIC
943 * We need clear_IO_APIC before enabling vector on BP
945 if (!skip_ioapic_setup
&& nr_ioapics
)
948 end_local_APIC_setup();
950 if (smp_found_config
&& !skip_ioapic_setup
&& nr_ioapics
)
954 setup_boot_APIC_clock();
955 check_nmi_watchdog();
960 * Local APIC interrupts
964 * This interrupt should _never_ happen with our APIC/SMP architecture
966 asmlinkage
void smp_spurious_interrupt(void)
972 * Check if this really is a spurious interrupt and ACK it
973 * if it is a vectored one. Just in case...
974 * Spurious interrupts should not be ACKed.
976 v
= apic_read(APIC_ISR
+ ((SPURIOUS_APIC_VECTOR
& ~0x1f) >> 1));
977 if (v
& (1 << (SPURIOUS_APIC_VECTOR
& 0x1f)))
980 add_pda(irq_spurious_count
, 1);
985 * This interrupt should never happen with our APIC/SMP architecture
987 asmlinkage
void smp_error_interrupt(void)
993 /* First tickle the hardware, only then report what went on. -- REW */
994 v
= apic_read(APIC_ESR
);
995 apic_write(APIC_ESR
, 0);
996 v1
= apic_read(APIC_ESR
);
998 atomic_inc(&irq_err_count
);
1000 /* Here is what the APIC error bits mean:
1003 2: Send accept error
1004 3: Receive accept error
1006 5: Send illegal vector
1007 6: Received illegal vector
1008 7: Illegal register address
1010 printk(KERN_DEBUG
"APIC error on CPU%d: %02x(%02x)\n",
1011 smp_processor_id(), v
, v1
);
1015 void disconnect_bsp_APIC(int virt_wire_setup
)
1017 /* Go back to Virtual Wire compatibility mode */
1018 unsigned long value
;
1020 /* For the spurious interrupt use vector F, and enable it */
1021 value
= apic_read(APIC_SPIV
);
1022 value
&= ~APIC_VECTOR_MASK
;
1023 value
|= APIC_SPIV_APIC_ENABLED
;
1025 apic_write(APIC_SPIV
, value
);
1027 if (!virt_wire_setup
) {
1029 * For LVT0 make it edge triggered, active high,
1030 * external and enabled
1032 value
= apic_read(APIC_LVT0
);
1033 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1034 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1035 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1036 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1037 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_EXTINT
);
1038 apic_write(APIC_LVT0
, value
);
1041 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
1044 /* For LVT1 make it edge triggered, active high, nmi and enabled */
1045 value
= apic_read(APIC_LVT1
);
1046 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1047 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1048 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1049 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1050 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_NMI
);
1051 apic_write(APIC_LVT1
, value
);
1060 /* 'active' is true if the local APIC was enabled by us and
1061 not the BIOS; this signifies that we are also responsible
1062 for disabling it before entering apm/acpi suspend */
1064 /* r/w apic fields */
1065 unsigned int apic_id
;
1066 unsigned int apic_taskpri
;
1067 unsigned int apic_ldr
;
1068 unsigned int apic_dfr
;
1069 unsigned int apic_spiv
;
1070 unsigned int apic_lvtt
;
1071 unsigned int apic_lvtpc
;
1072 unsigned int apic_lvt0
;
1073 unsigned int apic_lvt1
;
1074 unsigned int apic_lvterr
;
1075 unsigned int apic_tmict
;
1076 unsigned int apic_tdcr
;
1077 unsigned int apic_thmr
;
1080 static int lapic_suspend(struct sys_device
*dev
, pm_message_t state
)
1082 unsigned long flags
;
1085 if (!apic_pm_state
.active
)
1088 maxlvt
= lapic_get_maxlvt();
1090 apic_pm_state
.apic_id
= apic_read(APIC_ID
);
1091 apic_pm_state
.apic_taskpri
= apic_read(APIC_TASKPRI
);
1092 apic_pm_state
.apic_ldr
= apic_read(APIC_LDR
);
1093 apic_pm_state
.apic_dfr
= apic_read(APIC_DFR
);
1094 apic_pm_state
.apic_spiv
= apic_read(APIC_SPIV
);
1095 apic_pm_state
.apic_lvtt
= apic_read(APIC_LVTT
);
1097 apic_pm_state
.apic_lvtpc
= apic_read(APIC_LVTPC
);
1098 apic_pm_state
.apic_lvt0
= apic_read(APIC_LVT0
);
1099 apic_pm_state
.apic_lvt1
= apic_read(APIC_LVT1
);
1100 apic_pm_state
.apic_lvterr
= apic_read(APIC_LVTERR
);
1101 apic_pm_state
.apic_tmict
= apic_read(APIC_TMICT
);
1102 apic_pm_state
.apic_tdcr
= apic_read(APIC_TDCR
);
1103 #ifdef CONFIG_X86_MCE_INTEL
1105 apic_pm_state
.apic_thmr
= apic_read(APIC_LVTTHMR
);
1107 local_irq_save(flags
);
1108 disable_local_APIC();
1109 local_irq_restore(flags
);
1113 static int lapic_resume(struct sys_device
*dev
)
1116 unsigned long flags
;
1119 if (!apic_pm_state
.active
)
1122 maxlvt
= lapic_get_maxlvt();
1124 local_irq_save(flags
);
1125 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1126 l
&= ~MSR_IA32_APICBASE_BASE
;
1127 l
|= MSR_IA32_APICBASE_ENABLE
| mp_lapic_addr
;
1128 wrmsr(MSR_IA32_APICBASE
, l
, h
);
1129 apic_write(APIC_LVTERR
, ERROR_APIC_VECTOR
| APIC_LVT_MASKED
);
1130 apic_write(APIC_ID
, apic_pm_state
.apic_id
);
1131 apic_write(APIC_DFR
, apic_pm_state
.apic_dfr
);
1132 apic_write(APIC_LDR
, apic_pm_state
.apic_ldr
);
1133 apic_write(APIC_TASKPRI
, apic_pm_state
.apic_taskpri
);
1134 apic_write(APIC_SPIV
, apic_pm_state
.apic_spiv
);
1135 apic_write(APIC_LVT0
, apic_pm_state
.apic_lvt0
);
1136 apic_write(APIC_LVT1
, apic_pm_state
.apic_lvt1
);
1137 #ifdef CONFIG_X86_MCE_INTEL
1139 apic_write(APIC_LVTTHMR
, apic_pm_state
.apic_thmr
);
1142 apic_write(APIC_LVTPC
, apic_pm_state
.apic_lvtpc
);
1143 apic_write(APIC_LVTT
, apic_pm_state
.apic_lvtt
);
1144 apic_write(APIC_TDCR
, apic_pm_state
.apic_tdcr
);
1145 apic_write(APIC_TMICT
, apic_pm_state
.apic_tmict
);
1146 apic_write(APIC_ESR
, 0);
1147 apic_read(APIC_ESR
);
1148 apic_write(APIC_LVTERR
, apic_pm_state
.apic_lvterr
);
1149 apic_write(APIC_ESR
, 0);
1150 apic_read(APIC_ESR
);
1151 local_irq_restore(flags
);
1155 static struct sysdev_class lapic_sysclass
= {
1157 .resume
= lapic_resume
,
1158 .suspend
= lapic_suspend
,
1161 static struct sys_device device_lapic
= {
1163 .cls
= &lapic_sysclass
,
1166 static void __cpuinit
apic_pm_activate(void)
1168 apic_pm_state
.active
= 1;
1171 static int __init
init_lapic_sysfs(void)
1177 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
1179 error
= sysdev_class_register(&lapic_sysclass
);
1181 error
= sysdev_register(&device_lapic
);
1184 device_initcall(init_lapic_sysfs
);
1186 #else /* CONFIG_PM */
1188 static void apic_pm_activate(void) { }
1190 #endif /* CONFIG_PM */
1193 * apic_is_clustered_box() -- Check if we can expect good TSC
1195 * Thus far, the major user of this is IBM's Summit2 series:
1197 * Clustered boxes may have unsynced TSC problems if they are
1198 * multi-chassis. Use available data to take a good guess.
1199 * If in doubt, go HPET.
1201 __cpuinit
int apic_is_clustered_box(void)
1203 int i
, clusters
, zeros
;
1205 u16
*bios_cpu_apicid
;
1206 DECLARE_BITMAP(clustermap
, NUM_APIC_CLUSTERS
);
1209 * there is not this kind of box with AMD CPU yet.
1210 * Some AMD box with quadcore cpu and 8 sockets apicid
1211 * will be [4, 0x23] or [8, 0x27] could be thought to
1212 * vsmp box still need checking...
1214 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
) && !is_vsmp_box())
1217 bios_cpu_apicid
= x86_bios_cpu_apicid_early_ptr
;
1218 bitmap_zero(clustermap
, NUM_APIC_CLUSTERS
);
1220 for (i
= 0; i
< NR_CPUS
; i
++) {
1221 /* are we being called early in kernel startup? */
1222 if (bios_cpu_apicid
) {
1223 id
= bios_cpu_apicid
[i
];
1225 else if (i
< nr_cpu_ids
) {
1227 id
= per_cpu(x86_bios_cpu_apicid
, i
);
1234 if (id
!= BAD_APICID
)
1235 __set_bit(APIC_CLUSTERID(id
), clustermap
);
1238 /* Problem: Partially populated chassis may not have CPUs in some of
1239 * the APIC clusters they have been allocated. Only present CPUs have
1240 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap.
1241 * Since clusters are allocated sequentially, count zeros only if
1242 * they are bounded by ones.
1246 for (i
= 0; i
< NUM_APIC_CLUSTERS
; i
++) {
1247 if (test_bit(i
, clustermap
)) {
1248 clusters
+= 1 + zeros
;
1254 /* ScaleMP vSMPowered boxes have one cluster per board and TSCs are
1255 * not guaranteed to be synced between boards
1257 if (is_vsmp_box() && clusters
> 1)
1261 * If clusters > 2, then should be multi-chassis.
1262 * May have to revisit this when multi-core + hyperthreaded CPUs come
1263 * out, but AFAIK this will work even for them.
1265 return (clusters
> 2);
1269 * APIC command line parameters
1271 static int __init
apic_set_verbosity(char *str
)
1274 skip_ioapic_setup
= 0;
1278 if (strcmp("debug", str
) == 0)
1279 apic_verbosity
= APIC_DEBUG
;
1280 else if (strcmp("verbose", str
) == 0)
1281 apic_verbosity
= APIC_VERBOSE
;
1283 printk(KERN_WARNING
"APIC Verbosity level %s not recognised"
1284 " use apic=verbose or apic=debug\n", str
);
1290 early_param("apic", apic_set_verbosity
);
1292 static __init
int setup_disableapic(char *str
)
1295 clear_cpu_cap(&boot_cpu_data
, X86_FEATURE_APIC
);
1298 early_param("disableapic", setup_disableapic
);
1300 /* same as disableapic, for compatibility */
1301 static __init
int setup_nolapic(char *str
)
1303 return setup_disableapic(str
);
1305 early_param("nolapic", setup_nolapic
);
1307 static int __init
parse_lapic_timer_c2_ok(char *arg
)
1309 local_apic_timer_c2_ok
= 1;
1312 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok
);
1314 static __init
int setup_noapictimer(char *str
)
1316 if (str
[0] != ' ' && str
[0] != 0)
1318 disable_apic_timer
= 1;
1321 __setup("noapictimer", setup_noapictimer
);
1323 static __init
int setup_apicpmtimer(char *s
)
1325 apic_calibrate_pmtmr
= 1;
1329 __setup("apicpmtimer", setup_apicpmtimer
);
1331 static int __init
lapic_insert_resource(void)
1336 /* Put local APIC into the resource map. */
1337 lapic_resource
.start
= apic_phys
;
1338 lapic_resource
.end
= lapic_resource
.start
+ PAGE_SIZE
- 1;
1339 insert_resource(&iomem_resource
, &lapic_resource
);
1345 * need call insert after e820_reserve_resources()
1346 * that is using request_resource
1348 late_initcall(lapic_insert_resource
);