arch/x86/kernel/cpu/amd.c

   1 #include <linux/init.h>
   2 #include <linux/bitops.h>
   3 #include <linux/mm.h>
   4 #include <asm/io.h>
   5 #include <asm/processor.h>
   6 #include <asm/apic.h>
   7
   8 #include <mach_apic.h>
   9 #include "cpu.h"
  10
  11 /*
  12  *      B step AMD K6 before B 9730xxxx have hardware bugs that can cause
  13  *      misexecution of code under Linux. Owners of such processors should
  14  *      contact AMD for precise details and a CPU swap.
  15  *
  16  *      See     http://www.multimania.com/poulot/k6bug.html
  17  *              http://www.amd.com/K6/k6docs/revgd.html
  18  *
  19  *      The following test is erm.. interesting. AMD neglected to up
  20  *      the chip setting when fixing the bug but they also tweaked some
  21  *      performance at the same time..
  22  */
  23
  24 extern void vide(void);
  25 __asm__(".align 4\nvide: ret");
  26
  27 #ifdef CONFIG_X86_LOCAL_APIC
  28 #define CPUID_PROCESSOR_SIGNATURE       1
  29 #define CPUID_XFAM              0x0ff00000
  30 #define CPUID_XFAM_K8           0x00000000
  31 #define CPUID_XFAM_10H          0x00100000
  32 #define CPUID_XFAM_11H          0x00200000
  33 #define CPUID_XMOD              0x000f0000
  34 #define CPUID_XMOD_REV_F        0x00040000
  35
  36 /* AMD systems with C1E don't have a working lAPIC timer. Check for that. */
  37 static __cpuinit int amd_apic_timer_broken(void)
  38 {
  39         u32 lo, hi;
  40         u32 eax = cpuid_eax(CPUID_PROCESSOR_SIGNATURE);
  41         switch (eax & CPUID_XFAM) {
  42         case CPUID_XFAM_K8:
  43                 if ((eax & CPUID_XMOD) < CPUID_XMOD_REV_F)
  44                         break;
  45         case CPUID_XFAM_10H:
  46         case CPUID_XFAM_11H:
  47                 rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
  48                 if (lo & K8_INTP_C1E_ACTIVE_MASK) {
  49                         if (smp_processor_id() != boot_cpu_physical_apicid)
  50                                 printk(KERN_INFO "AMD C1E detected late. "
  51                                        "        Force timer broadcast.\n");
  52                         return 1;
  53                 }
  54                 break;
  55         default:
  56                 /* err on the side of caution */
  57                 return 1;
  58         }
  59         return 0;
  60 }
  61 #endif
  62
  63 int force_mwait __cpuinitdata;
  64
  65 static void __cpuinit early_init_amd(struct cpuinfo_x86 *c)
  66 {
  67         if (cpuid_eax(0x80000000) >= 0x80000007) {
  68                 c->x86_power = cpuid_edx(0x80000007);
  69                 if (c->x86_power & (1<<8))
  70                         set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
  71         }
  72 }
  73
  74 static void __cpuinit init_amd(struct cpuinfo_x86 *c)
  75 {
  76         u32 l, h;
  77         int mbytes = num_physpages >> (20-PAGE_SHIFT);
  78         int r;
  79
  80 #ifdef CONFIG_SMP
  81         unsigned long long value;
  82
  83         /*
  84          * Disable TLB flush filter by setting HWCR.FFDIS on K8
  85          * bit 6 of msr C001_0015
  86          *
  87          * Errata 63 for SH-B3 steppings
  88          * Errata 122 for all steppings (F+ have it disabled by default)
  89          */
  90         if (c->x86 == 15) {
  91                 rdmsrl(MSR_K7_HWCR, value);
  92                 value |= 1 << 6;
  93                 wrmsrl(MSR_K7_HWCR, value);
  94         }
  95 #endif
  96
  97         early_init_amd(c);
  98
  99         /*
 100          *      FIXME: We should handle the K5 here. Set up the write
 101          *      range and also turn on MSR 83 bits 4 and 31 (write alloc,
 102          *      no bus pipeline)
 103          */
 104
 105         /*
 106          * Bit 31 in normal CPUID used for nonstandard 3DNow ID;
 107          * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
 108          */
 109         clear_cpu_cap(c, 0*32+31);
 110
 111         r = get_model_name(c);
 112
 113         switch (c->x86) {
 114         case 4:
 115                 /*
 116                  * General Systems BIOSen alias the cpu frequency registers
 117                  * of the Elan at 0x000df000. Unfortuantly, one of the Linux
 118                  * drivers subsequently pokes it, and changes the CPU speed.
 119                  * Workaround : Remove the unneeded alias.
 120                  */
 121 #define CBAR            (0xfffc) /* Configuration Base Address  (32-bit) */
 122 #define CBAR_ENB        (0x80000000)
 123 #define CBAR_KEY        (0X000000CB)
 124                         if (c->x86_model == 9 || c->x86_model == 10) {
 125                                 if (inl (CBAR) & CBAR_ENB)
 126                                         outl (0 | CBAR_KEY, CBAR);
 127                         }
 128                         break;
 129         case 5:
 130                         if (c->x86_model < 6) {
 131                                 /* Based on AMD doc 20734R - June 2000 */
 132                                 if (c->x86_model == 0) {
 133                                         clear_cpu_cap(c, X86_FEATURE_APIC);
 134                                         set_cpu_cap(c, X86_FEATURE_PGE);
 135                                 }
 136                                 break;
 137                         }
 138
 139                         if (c->x86_model == 6 && c->x86_mask == 1) {
 140                                 const int K6_BUG_LOOP = 1000000;
 141                                 int n;
 142                                 void (*f_vide)(void);
 143                                 unsigned long d, d2;
 144
 145                                 printk(KERN_INFO "AMD K6 stepping B detected - ");
 146
 147                                 /*
 148                                  * It looks like AMD fixed the 2.6.2 bug and improved indirect
 149                                  * calls at the same time.
 150                                  */
 151
 152                                 n = K6_BUG_LOOP;
 153                                 f_vide = vide;
 154                                 rdtscl(d);
 155                                 while (n--)
 156                                         f_vide();
 157                                 rdtscl(d2);
 158                                 d = d2-d;
 159
 160                                 if (d > 20*K6_BUG_LOOP)
 161                                         printk("system stability may be impaired when more than 32 MB are used.\n");
 162                                 else
 163                                         printk("probably OK (after B9730xxxx).\n");
 164                                 printk(KERN_INFO "Please see http://membres.lycos.fr/poulot/k6bug.html\n");
 165                         }
 166
 167                         /* K6 with old style WHCR */
 168                         if (c->x86_model < 8 ||
 169                            (c->x86_model == 8 && c->x86_mask < 8)) {
 170                                 /* We can only write allocate on the low 508Mb */
 171                                 if (mbytes > 508)
 172                                         mbytes = 508;
 173
 174                                 rdmsr(MSR_K6_WHCR, l, h);
 175                                 if ((l&0x0000FFFF) == 0) {
 176                                         unsigned long flags;
 177                                         l = (1<<0)|((mbytes/4)<<1);
 178                                         local_irq_save(flags);
 179                                         wbinvd();
 180                                         wrmsr(MSR_K6_WHCR, l, h);
 181                                         local_irq_restore(flags);
 182                                         printk(KERN_INFO "Enabling old style K6 write allocation for %d Mb\n",
 183                                                 mbytes);
 184                                 }
 185                                 break;
 186                         }
 187
 188                         if ((c->x86_model == 8 && c->x86_mask > 7) ||
 189                              c->x86_model == 9 || c->x86_model == 13) {
 190                                 /* The more serious chips .. */
 191
 192                                 if (mbytes > 4092)
 193                                         mbytes = 4092;
 194
 195                                 rdmsr(MSR_K6_WHCR, l, h);
 196                                 if ((l&0xFFFF0000) == 0) {
 197                                         unsigned long flags;
 198                                         l = ((mbytes>>2)<<22)|(1<<16);
 199                                         local_irq_save(flags);
 200                                         wbinvd();
 201                                         wrmsr(MSR_K6_WHCR, l, h);
 202                                         local_irq_restore(flags);
 203                                         printk(KERN_INFO "Enabling new style K6 write allocation for %d Mb\n",
 204                                                 mbytes);
 205                                 }
 206
 207                                 /*  Set MTRR capability flag if appropriate */
 208                                 if (c->x86_model == 13 || c->x86_model == 9 ||
 209                                    (c->x86_model == 8 && c->x86_mask >= 8))
 210                                         set_cpu_cap(c, X86_FEATURE_K6_MTRR);
 211                                 break;
 212                         }
 213
 214                         if (c->x86_model == 10) {
 215                                 /* AMD Geode LX is model 10 */
 216                                 /* placeholder for any needed mods */
 217                                 break;
 218                         }
 219                         break;
 220         case 6: /* An Athlon/Duron */
 221
 222                         /*
 223                          * Bit 15 of Athlon specific MSR 15, needs to be 0
 224                          * to enable SSE on Palomino/Morgan/Barton CPU's.
 225                          * If the BIOS didn't enable it already, enable it here.
 226                          */
 227                         if (c->x86_model >= 6 && c->x86_model <= 10) {
 228                                 if (!cpu_has(c, X86_FEATURE_XMM)) {
 229                                         printk(KERN_INFO "Enabling disabled K7/SSE Support.\n");
 230                                         rdmsr(MSR_K7_HWCR, l, h);
 231                                         l &= ~0x00008000;
 232                                         wrmsr(MSR_K7_HWCR, l, h);
 233                                         set_cpu_cap(c, X86_FEATURE_XMM);
 234                                 }
 235                         }
 236
 237                         /*
 238                          * It's been determined by AMD that Athlons since model 8 stepping 1
 239                          * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx
 240                          * As per AMD technical note 27212 0.2
 241                          */
 242                         if ((c->x86_model == 8 && c->x86_mask >= 1) || (c->x86_model > 8)) {
 243                                 rdmsr(MSR_K7_CLK_CTL, l, h);
 244                                 if ((l & 0xfff00000) != 0x20000000) {
 245                                         printk ("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n", l,
 246                                                 ((l & 0x000fffff)|0x20000000));
 247                                         wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h);
 248                                 }
 249                         }
 250                         break;
 251         }
 252
 253         switch (c->x86) {
 254         case 15:
 255         /* Use K8 tuning for Fam10h and Fam11h */
 256         case 0x10:
 257         case 0x11:
 258                 set_cpu_cap(c, X86_FEATURE_K8);
 259                 break;
 260         case 6:
 261                 set_cpu_cap(c, X86_FEATURE_K7);
 262                 break;
 263         }
 264         if (c->x86 >= 6)
 265                 set_cpu_cap(c, X86_FEATURE_FXSAVE_LEAK);
 266
 267         display_cacheinfo(c);
 268
 269         if (cpuid_eax(0x80000000) >= 0x80000008)
 270                 c->x86_max_cores = (cpuid_ecx(0x80000008) & 0xff) + 1;
 271
 272 #ifdef CONFIG_X86_HT
 273         /*
 274          * On a AMD multi core setup the lower bits of the APIC id
 275          * distinguish the cores.
 276          */
 277         if (c->x86_max_cores > 1) {
 278                 int cpu = smp_processor_id();
 279                 unsigned bits = (cpuid_ecx(0x80000008) >> 12) & 0xf;
 280
 281                 if (bits == 0) {
 282                         while ((1 << bits) < c->x86_max_cores)
 283                                 bits++;
 284                 }
 285                 c->cpu_core_id = c->phys_proc_id & ((1<<bits)-1);
 286                 c->phys_proc_id >>= bits;
 287                 printk(KERN_INFO "CPU %d(%d) -> Core %d\n",
 288                        cpu, c->x86_max_cores, c->cpu_core_id);
 289         }
 290 #endif
 291
 292         if (cpuid_eax(0x80000000) >= 0x80000006) {
 293                 if ((c->x86 == 0x10) && (cpuid_edx(0x80000006) & 0xf000))
 294                         num_cache_leaves = 4;
 295                 else
 296                         num_cache_leaves = 3;
 297         }
 298
 299 #ifdef CONFIG_X86_LOCAL_APIC
 300         if (amd_apic_timer_broken())
 301                 local_apic_timer_disabled = 1;
 302 #endif
 303
 304         /* K6s reports MCEs but don't actually have all the MSRs */
 305         if (c->x86 < 6)
 306                 clear_cpu_cap(c, X86_FEATURE_MCE);
 307
 308         if (cpu_has_xmm2)
 309                 set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);
 310
 311         if (c->x86 == 0x10)
 312                 amd_enable_pci_ext_cfg(c);
 313 }
 314
 315 static unsigned int __cpuinit amd_size_cache(struct cpuinfo_x86 *c, unsigned int size)
 316 {
 317         /* AMD errata T13 (order #21922) */
 318         if ((c->x86 == 6)) {
 319                 if (c->x86_model == 3 && c->x86_mask == 0)      /* Duron Rev A0 */
 320                         size = 64;
 321                 if (c->x86_model == 4 &&
 322                     (c->x86_mask == 0 || c->x86_mask == 1))     /* Tbird rev A1/A2 */
 323                         size = 256;
 324         }
 325         return size;
 326 }
 327
 328 static struct cpu_dev amd_cpu_dev __cpuinitdata = {
 329         .c_vendor       = "AMD",
 330         .c_ident        = { "AuthenticAMD" },
 331         .c_models = {
 332                 { .vendor = X86_VENDOR_AMD, .family = 4, .model_names =
 333                   {
 334                           [3] = "486 DX/2",
 335                           [7] = "486 DX/2-WB",
 336                           [8] = "486 DX/4",
 337                           [9] = "486 DX/4-WB",
 338                           [14] = "Am5x86-WT",
 339                           [15] = "Am5x86-WB"
 340                   }
 341                 },
 342         },
 343         .c_early_init   = early_init_amd,
 344         .c_init         = init_amd,
 345         .c_size_cache   = amd_size_cache,
 346 };
 347
 348 cpu_vendor_dev_register(X86_VENDOR_AMD, &amd_cpu_dev);