1 #include <linux/export.h>
2 #include <linux/init.h>
3 #include <linux/bitops.h>
8 #include <linux/sched.h>
9 #include <asm/processor.h>
12 #include <asm/pci-direct.h>
15 # include <asm/numa_64.h>
16 # include <asm/mmconfig.h>
17 # include <asm/cacheflush.h>
24 * B step AMD K6 before B 9730xxxx have hardware bugs that can cause
25 * misexecution of code under Linux. Owners of such processors should
26 * contact AMD for precise details and a CPU swap.
28 * See http://www.multimania.com/poulot/k6bug.html
29 * and section 2.6.2 of "AMD-K6 Processor Revision Guide - Model 6"
30 * (Publication # 21266 Issue Date: August 1998)
32 * The following test is erm.. interesting. AMD neglected to up
33 * the chip setting when fixing the bug but they also tweaked some
34 * performance at the same time..
37 extern void vide(void);
38 __asm__(".align 4\nvide: ret");
40 static void __cpuinit
init_amd_k5(struct cpuinfo_x86
*c
)
43 * General Systems BIOSen alias the cpu frequency registers
44 * of the Elan at 0x000df000. Unfortuantly, one of the Linux
45 * drivers subsequently pokes it, and changes the CPU speed.
46 * Workaround : Remove the unneeded alias.
48 #define CBAR (0xfffc) /* Configuration Base Address (32-bit) */
49 #define CBAR_ENB (0x80000000)
50 #define CBAR_KEY (0X000000CB)
51 if (c
->x86_model
== 9 || c
->x86_model
== 10) {
52 if (inl(CBAR
) & CBAR_ENB
)
53 outl(0 | CBAR_KEY
, CBAR
);
58 static void __cpuinit
init_amd_k6(struct cpuinfo_x86
*c
)
61 int mbytes
= num_physpages
>> (20-PAGE_SHIFT
);
63 if (c
->x86_model
< 6) {
64 /* Based on AMD doc 20734R - June 2000 */
65 if (c
->x86_model
== 0) {
66 clear_cpu_cap(c
, X86_FEATURE_APIC
);
67 set_cpu_cap(c
, X86_FEATURE_PGE
);
72 if (c
->x86_model
== 6 && c
->x86_mask
== 1) {
73 const int K6_BUG_LOOP
= 1000000;
78 printk(KERN_INFO
"AMD K6 stepping B detected - ");
81 * It looks like AMD fixed the 2.6.2 bug and improved indirect
82 * calls at the same time.
93 if (d
> 20*K6_BUG_LOOP
)
95 "system stability may be impaired when more than 32 MB are used.\n");
97 printk(KERN_CONT
"probably OK (after B9730xxxx).\n");
100 /* K6 with old style WHCR */
101 if (c
->x86_model
< 8 ||
102 (c
->x86_model
== 8 && c
->x86_mask
< 8)) {
103 /* We can only write allocate on the low 508Mb */
107 rdmsr(MSR_K6_WHCR
, l
, h
);
108 if ((l
&0x0000FFFF) == 0) {
110 l
= (1<<0)|((mbytes
/4)<<1);
111 local_irq_save(flags
);
113 wrmsr(MSR_K6_WHCR
, l
, h
);
114 local_irq_restore(flags
);
115 printk(KERN_INFO
"Enabling old style K6 write allocation for %d Mb\n",
121 if ((c
->x86_model
== 8 && c
->x86_mask
> 7) ||
122 c
->x86_model
== 9 || c
->x86_model
== 13) {
123 /* The more serious chips .. */
128 rdmsr(MSR_K6_WHCR
, l
, h
);
129 if ((l
&0xFFFF0000) == 0) {
131 l
= ((mbytes
>>2)<<22)|(1<<16);
132 local_irq_save(flags
);
134 wrmsr(MSR_K6_WHCR
, l
, h
);
135 local_irq_restore(flags
);
136 printk(KERN_INFO
"Enabling new style K6 write allocation for %d Mb\n",
143 if (c
->x86_model
== 10) {
144 /* AMD Geode LX is model 10 */
145 /* placeholder for any needed mods */
150 static void __cpuinit
amd_k7_smp_check(struct cpuinfo_x86
*c
)
152 /* calling is from identify_secondary_cpu() ? */
157 * Certain Athlons might work (for various values of 'work') in SMP
158 * but they are not certified as MP capable.
160 /* Athlon 660/661 is valid. */
161 if ((c
->x86_model
== 6) && ((c
->x86_mask
== 0) ||
165 /* Duron 670 is valid */
166 if ((c
->x86_model
== 7) && (c
->x86_mask
== 0))
170 * Athlon 662, Duron 671, and Athlon >model 7 have capability
171 * bit. It's worth noting that the A5 stepping (662) of some
172 * Athlon XP's have the MP bit set.
173 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for
176 if (((c
->x86_model
== 6) && (c
->x86_mask
>= 2)) ||
177 ((c
->x86_model
== 7) && (c
->x86_mask
>= 1)) ||
182 /* If we get here, not a certified SMP capable AMD system. */
185 * Don't taint if we are running SMP kernel on a single non-MP
188 WARN_ONCE(1, "WARNING: This combination of AMD"
189 " processors is not suitable for SMP.\n");
190 if (!test_taint(TAINT_UNSAFE_SMP
))
191 add_taint(TAINT_UNSAFE_SMP
);
197 static void __cpuinit
init_amd_k7(struct cpuinfo_x86
*c
)
202 * Bit 15 of Athlon specific MSR 15, needs to be 0
203 * to enable SSE on Palomino/Morgan/Barton CPU's.
204 * If the BIOS didn't enable it already, enable it here.
206 if (c
->x86_model
>= 6 && c
->x86_model
<= 10) {
207 if (!cpu_has(c
, X86_FEATURE_XMM
)) {
208 printk(KERN_INFO
"Enabling disabled K7/SSE Support.\n");
209 rdmsr(MSR_K7_HWCR
, l
, h
);
211 wrmsr(MSR_K7_HWCR
, l
, h
);
212 set_cpu_cap(c
, X86_FEATURE_XMM
);
217 * It's been determined by AMD that Athlons since model 8 stepping 1
218 * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx
219 * As per AMD technical note 27212 0.2
221 if ((c
->x86_model
== 8 && c
->x86_mask
>= 1) || (c
->x86_model
> 8)) {
222 rdmsr(MSR_K7_CLK_CTL
, l
, h
);
223 if ((l
& 0xfff00000) != 0x20000000) {
225 "CPU: CLK_CTL MSR was %x. Reprogramming to %x\n",
226 l
, ((l
& 0x000fffff)|0x20000000));
227 wrmsr(MSR_K7_CLK_CTL
, (l
& 0x000fffff)|0x20000000, h
);
231 set_cpu_cap(c
, X86_FEATURE_K7
);
239 * To workaround broken NUMA config. Read the comment in
240 * srat_detect_node().
242 static int __cpuinit
nearby_node(int apicid
)
246 for (i
= apicid
- 1; i
>= 0; i
--) {
247 node
= __apicid_to_node
[i
];
248 if (node
!= NUMA_NO_NODE
&& node_online(node
))
251 for (i
= apicid
+ 1; i
< MAX_LOCAL_APIC
; i
++) {
252 node
= __apicid_to_node
[i
];
253 if (node
!= NUMA_NO_NODE
&& node_online(node
))
256 return first_node(node_online_map
); /* Shouldn't happen */
261 * Fixup core topology information for
262 * (1) AMD multi-node processors
263 * Assumption: Number of cores in each internal node is the same.
264 * (2) AMD processors supporting compute units
267 static void __cpuinit
amd_get_topology(struct cpuinfo_x86
*c
)
269 u32 nodes
, cores_per_cu
= 1;
271 int cpu
= smp_processor_id();
273 /* get information required for multi-node processors */
274 if (cpu_has(c
, X86_FEATURE_TOPOEXT
)) {
275 u32 eax
, ebx
, ecx
, edx
;
277 cpuid(0x8000001e, &eax
, &ebx
, &ecx
, &edx
);
278 nodes
= ((ecx
>> 8) & 7) + 1;
281 /* get compute unit information */
282 smp_num_siblings
= ((ebx
>> 8) & 3) + 1;
283 c
->compute_unit_id
= ebx
& 0xff;
284 cores_per_cu
+= ((ebx
>> 8) & 3);
285 } else if (cpu_has(c
, X86_FEATURE_NODEID_MSR
)) {
288 rdmsrl(MSR_FAM10H_NODE_ID
, value
);
289 nodes
= ((value
>> 3) & 7) + 1;
294 /* fixup multi-node processor information */
299 set_cpu_cap(c
, X86_FEATURE_AMD_DCM
);
300 cores_per_node
= c
->x86_max_cores
/ nodes
;
301 cus_per_node
= cores_per_node
/ cores_per_cu
;
303 /* store NodeID, use llc_shared_map to store sibling info */
304 per_cpu(cpu_llc_id
, cpu
) = node_id
;
306 /* core id has to be in the [0 .. cores_per_node - 1] range */
307 c
->cpu_core_id
%= cores_per_node
;
308 c
->compute_unit_id
%= cus_per_node
;
314 * On a AMD dual core setup the lower bits of the APIC id distingush the cores.
315 * Assumes number of cores is a power of two.
317 static void __cpuinit
amd_detect_cmp(struct cpuinfo_x86
*c
)
321 int cpu
= smp_processor_id();
323 bits
= c
->x86_coreid_bits
;
324 /* Low order bits define the core id (index of core in socket) */
325 c
->cpu_core_id
= c
->initial_apicid
& ((1 << bits
)-1);
326 /* Convert the initial APIC ID into the socket ID */
327 c
->phys_proc_id
= c
->initial_apicid
>> bits
;
328 /* use socket ID also for last level cache */
329 per_cpu(cpu_llc_id
, cpu
) = c
->phys_proc_id
;
334 int amd_get_nb_id(int cpu
)
338 id
= per_cpu(cpu_llc_id
, cpu
);
342 EXPORT_SYMBOL_GPL(amd_get_nb_id
);
344 static void __cpuinit
srat_detect_node(struct cpuinfo_x86
*c
)
347 int cpu
= smp_processor_id();
349 unsigned apicid
= c
->apicid
;
351 node
= numa_cpu_node(cpu
);
352 if (node
== NUMA_NO_NODE
)
353 node
= per_cpu(cpu_llc_id
, cpu
);
356 * On multi-fabric platform (e.g. Numascale NumaChip) a
357 * platform-specific handler needs to be called to fixup some
360 if (x86_cpuinit
.fixup_cpu_id
)
361 x86_cpuinit
.fixup_cpu_id(c
, node
);
363 if (!node_online(node
)) {
365 * Two possibilities here:
367 * - The CPU is missing memory and no node was created. In
368 * that case try picking one from a nearby CPU.
370 * - The APIC IDs differ from the HyperTransport node IDs
371 * which the K8 northbridge parsing fills in. Assume
372 * they are all increased by a constant offset, but in
373 * the same order as the HT nodeids. If that doesn't
374 * result in a usable node fall back to the path for the
377 * This workaround operates directly on the mapping between
378 * APIC ID and NUMA node, assuming certain relationship
379 * between APIC ID, HT node ID and NUMA topology. As going
380 * through CPU mapping may alter the outcome, directly
381 * access __apicid_to_node[].
383 int ht_nodeid
= c
->initial_apicid
;
385 if (ht_nodeid
>= 0 &&
386 __apicid_to_node
[ht_nodeid
] != NUMA_NO_NODE
)
387 node
= __apicid_to_node
[ht_nodeid
];
388 /* Pick a nearby node */
389 if (!node_online(node
))
390 node
= nearby_node(apicid
);
392 numa_set_node(cpu
, node
);
396 static void __cpuinit
early_init_amd_mc(struct cpuinfo_x86
*c
)
401 /* Multi core CPU? */
402 if (c
->extended_cpuid_level
< 0x80000008)
405 ecx
= cpuid_ecx(0x80000008);
407 c
->x86_max_cores
= (ecx
& 0xff) + 1;
409 /* CPU telling us the core id bits shift? */
410 bits
= (ecx
>> 12) & 0xF;
412 /* Otherwise recompute */
414 while ((1 << bits
) < c
->x86_max_cores
)
418 c
->x86_coreid_bits
= bits
;
422 static void __cpuinit
bsp_init_amd(struct cpuinfo_x86
*c
)
424 if (cpu_has(c
, X86_FEATURE_CONSTANT_TSC
)) {
427 (c
->x86
== 0x10 && c
->x86_model
>= 0x2)) {
430 rdmsrl(MSR_K7_HWCR
, val
);
431 if (!(val
& BIT(24)))
432 printk(KERN_WARNING FW_BUG
"TSC doesn't count "
433 "with P0 frequency!\n");
437 if (c
->x86
== 0x15) {
438 unsigned long upperbit
;
441 cpuid
= cpuid_edx(0x80000005);
442 assoc
= cpuid
>> 16 & 0xff;
443 upperbit
= ((cpuid
>> 24) << 10) / assoc
;
445 va_align
.mask
= (upperbit
- 1) & PAGE_MASK
;
446 va_align
.flags
= ALIGN_VA_32
| ALIGN_VA_64
;
450 static void __cpuinit
early_init_amd(struct cpuinfo_x86
*c
)
452 early_init_amd_mc(c
);
455 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
456 * with P/T states and does not stop in deep C-states
458 if (c
->x86_power
& (1 << 8)) {
459 set_cpu_cap(c
, X86_FEATURE_CONSTANT_TSC
);
460 set_cpu_cap(c
, X86_FEATURE_NONSTOP_TSC
);
461 if (!check_tsc_unstable())
462 sched_clock_stable
= 1;
466 set_cpu_cap(c
, X86_FEATURE_SYSCALL32
);
468 /* Set MTRR capability flag if appropriate */
470 if (c
->x86_model
== 13 || c
->x86_model
== 9 ||
471 (c
->x86_model
== 8 && c
->x86_mask
>= 8))
472 set_cpu_cap(c
, X86_FEATURE_K6_MTRR
);
474 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PCI)
475 /* check CPU config space for extended APIC ID */
476 if (cpu_has_apic
&& c
->x86
>= 0xf) {
478 val
= read_pci_config(0, 24, 0, 0x68);
479 if ((val
& ((1 << 17) | (1 << 18))) == ((1 << 17) | (1 << 18)))
480 set_cpu_cap(c
, X86_FEATURE_EXTD_APICID
);
485 static void __cpuinit
init_amd(struct cpuinfo_x86
*c
)
490 unsigned long long value
;
493 * Disable TLB flush filter by setting HWCR.FFDIS on K8
494 * bit 6 of msr C001_0015
496 * Errata 63 for SH-B3 steppings
497 * Errata 122 for all steppings (F+ have it disabled by default)
500 rdmsrl(MSR_K7_HWCR
, value
);
502 wrmsrl(MSR_K7_HWCR
, value
);
509 * Bit 31 in normal CPUID used for nonstandard 3DNow ID;
510 * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
512 clear_cpu_cap(c
, 0*32+31);
515 /* On C+ stepping K8 rep microcode works well for copy/memset */
519 level
= cpuid_eax(1);
520 if ((level
>= 0x0f48 && level
< 0x0f50) || level
>= 0x0f58)
521 set_cpu_cap(c
, X86_FEATURE_REP_GOOD
);
524 * Some BIOSes incorrectly force this feature, but only K8
525 * revision D (model = 0x14) and later actually support it.
526 * (AMD Erratum #110, docId: 25759).
528 if (c
->x86_model
< 0x14 && cpu_has(c
, X86_FEATURE_LAHF_LM
)) {
531 clear_cpu_cap(c
, X86_FEATURE_LAHF_LM
);
532 if (!rdmsrl_amd_safe(0xc001100d, &val
)) {
533 val
&= ~(1ULL << 32);
534 wrmsrl_amd_safe(0xc001100d, val
);
540 set_cpu_cap(c
, X86_FEATURE_REP_GOOD
);
542 /* get apicid instead of initial apic id from cpuid */
543 c
->apicid
= hard_smp_processor_id();
547 * FIXME: We should handle the K5 here. Set up the write
548 * range and also turn on MSR 83 bits 4 and 31 (write alloc,
559 case 6: /* An Athlon/Duron */
564 /* K6s reports MCEs but don't actually have all the MSRs */
566 clear_cpu_cap(c
, X86_FEATURE_MCE
);
569 /* Enable workaround for FXSAVE leak */
571 set_cpu_cap(c
, X86_FEATURE_FXSAVE_LEAK
);
573 if (!c
->x86_model_id
[0]) {
576 /* Should distinguish Models here, but this is only
577 a fallback anyways. */
578 strcpy(c
->x86_model_id
, "Hammer");
583 /* re-enable TopologyExtensions if switched off by BIOS */
584 if ((c
->x86
== 0x15) &&
585 (c
->x86_model
>= 0x10) && (c
->x86_model
<= 0x1f) &&
586 !cpu_has(c
, X86_FEATURE_TOPOEXT
)) {
589 if (!rdmsrl_amd_safe(0xc0011005, &val
)) {
591 wrmsrl_amd_safe(0xc0011005, val
);
592 rdmsrl(0xc0011005, val
);
593 if (val
& (1ULL << 54)) {
594 set_cpu_cap(c
, X86_FEATURE_TOPOEXT
);
595 printk(KERN_INFO FW_INFO
"CPU: Re-enabling "
596 "disabled Topology Extensions Support\n");
601 cpu_detect_cache_sizes(c
);
603 /* Multi core CPU? */
604 if (c
->extended_cpuid_level
>= 0x80000008) {
613 if (c
->extended_cpuid_level
>= 0x80000006) {
614 if (cpuid_edx(0x80000006) & 0xf000)
615 num_cache_leaves
= 4;
617 num_cache_leaves
= 3;
621 set_cpu_cap(c
, X86_FEATURE_K8
);
624 /* MFENCE stops RDTSC speculation */
625 set_cpu_cap(c
, X86_FEATURE_MFENCE_RDTSC
);
629 if (c
->x86
== 0x10) {
630 /* do this for boot cpu */
631 if (c
== &boot_cpu_data
)
632 check_enable_amd_mmconf_dmi();
634 fam10h_check_enable_mmcfg();
637 if (c
== &boot_cpu_data
&& c
->x86
>= 0xf) {
638 unsigned long long tseg
;
641 * Split up direct mapping around the TSEG SMM area.
642 * Don't do it for gbpages because there seems very little
643 * benefit in doing so.
645 if (!rdmsrl_safe(MSR_K8_TSEG_ADDR
, &tseg
)) {
646 printk(KERN_DEBUG
"tseg: %010llx\n", tseg
);
647 if ((tseg
>>PMD_SHIFT
) <
648 (max_low_pfn_mapped
>>(PMD_SHIFT
-PAGE_SHIFT
)) ||
650 (max_pfn_mapped
>>(PMD_SHIFT
-PAGE_SHIFT
)) &&
651 (tseg
>>PMD_SHIFT
) >= (1ULL<<(32 - PMD_SHIFT
))))
652 set_memory_4k((unsigned long)__va(tseg
), 1);
658 * Family 0x12 and above processors have APIC timer
659 * running in deep C states.
662 set_cpu_cap(c
, X86_FEATURE_ARAT
);
665 * Disable GART TLB Walk Errors on Fam10h. We do this here
666 * because this is always needed when GART is enabled, even in a
667 * kernel which has no MCE support built in.
669 if (c
->x86
== 0x10) {
671 * BIOS should disable GartTlbWlk Errors themself. If
672 * it doesn't do it here as suggested by the BKDG.
674 * Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=33012
679 err
= rdmsrl_safe(MSR_AMD64_MCx_MASK(4), &mask
);
682 checking_wrmsrl(MSR_AMD64_MCx_MASK(4), mask
);
686 rdmsr_safe(MSR_AMD64_PATCH_LEVEL
, &c
->microcode
, &dummy
);
690 static unsigned int __cpuinit
amd_size_cache(struct cpuinfo_x86
*c
,
693 /* AMD errata T13 (order #21922) */
696 if (c
->x86_model
== 3 && c
->x86_mask
== 0)
698 /* Tbird rev A1/A2 */
699 if (c
->x86_model
== 4 &&
700 (c
->x86_mask
== 0 || c
->x86_mask
== 1))
707 static const struct cpu_dev __cpuinitconst amd_cpu_dev
= {
709 .c_ident
= { "AuthenticAMD" },
712 { .vendor
= X86_VENDOR_AMD
, .family
= 4, .model_names
=
723 .c_size_cache
= amd_size_cache
,
725 .c_early_init
= early_init_amd
,
726 .c_bsp_init
= bsp_init_amd
,
728 .c_x86_vendor
= X86_VENDOR_AMD
,
731 cpu_dev_register(amd_cpu_dev
);
734 * AMD errata checking
736 * Errata are defined as arrays of ints using the AMD_LEGACY_ERRATUM() or
737 * AMD_OSVW_ERRATUM() macros. The latter is intended for newer errata that
738 * have an OSVW id assigned, which it takes as first argument. Both take a
739 * variable number of family-specific model-stepping ranges created by
740 * AMD_MODEL_RANGE(). Each erratum also has to be declared as extern const
741 * int[] in arch/x86/include/asm/processor.h.
745 * const int amd_erratum_319[] =
746 * AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0x4, 0x2),
747 * AMD_MODEL_RANGE(0x10, 0x8, 0x0, 0x8, 0x0),
748 * AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0));
751 const int amd_erratum_400
[] =
752 AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf),
753 AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf));
754 EXPORT_SYMBOL_GPL(amd_erratum_400
);
756 const int amd_erratum_383
[] =
757 AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf));
758 EXPORT_SYMBOL_GPL(amd_erratum_383
);
760 bool cpu_has_amd_erratum(const int *erratum
)
762 struct cpuinfo_x86
*cpu
= __this_cpu_ptr(&cpu_info
);
763 int osvw_id
= *erratum
++;
768 * If called early enough that current_cpu_data hasn't been initialized
769 * yet, fall back to boot_cpu_data.
772 cpu
= &boot_cpu_data
;
774 if (cpu
->x86_vendor
!= X86_VENDOR_AMD
)
777 if (osvw_id
>= 0 && osvw_id
< 65536 &&
778 cpu_has(cpu
, X86_FEATURE_OSVW
)) {
781 rdmsrl(MSR_AMD64_OSVW_ID_LENGTH
, osvw_len
);
782 if (osvw_id
< osvw_len
) {
785 rdmsrl(MSR_AMD64_OSVW_STATUS
+ (osvw_id
>> 6),
787 return osvw_bits
& (1ULL << (osvw_id
& 0x3f));
791 /* OSVW unavailable or ID unknown, match family-model-stepping range */
792 ms
= (cpu
->x86_model
<< 4) | cpu
->x86_mask
;
793 while ((range
= *erratum
++))
794 if ((cpu
->x86
== AMD_MODEL_RANGE_FAMILY(range
)) &&
795 (ms
>= AMD_MODEL_RANGE_START(range
)) &&
796 (ms
<= AMD_MODEL_RANGE_END(range
)))
802 EXPORT_SYMBOL_GPL(cpu_has_amd_erratum
);