1 #include <linux/init.h>
2 #include <linux/kernel.h>
3 #include <linux/sched.h>
4 #include <linux/string.h>
5 #include <linux/bootmem.h>
6 #include <linux/bitops.h>
7 #include <linux/module.h>
8 #include <linux/kgdb.h>
9 #include <linux/topology.h>
10 #include <linux/delay.h>
11 #include <linux/smp.h>
12 #include <linux/percpu.h>
16 #include <asm/linkage.h>
17 #include <asm/mmu_context.h>
23 #ifdef CONFIG_X86_LOCAL_APIC
24 #include <asm/mpspec.h>
26 #include <mach_apic.h>
27 #include <asm/genapic.h>
31 #include <asm/pgtable.h>
32 #include <asm/processor.h>
34 #include <asm/atomic.h>
35 #include <asm/proto.h>
36 #include <asm/sections.h>
37 #include <asm/setup.h>
41 static struct cpu_dev
*this_cpu __cpuinitdata
;
44 /* We need valid kernel segments for data and code in long mode too
45 * IRET will check the segment types kkeil 2000/10/28
46 * Also sysret mandates a special GDT layout
48 /* The TLS descriptors are currently at a different place compared to i386.
49 Hopefully nobody expects them at a fixed place (Wine?) */
50 DEFINE_PER_CPU(struct gdt_page
, gdt_page
) = { .gdt
= {
51 [GDT_ENTRY_KERNEL32_CS
] = { { { 0x0000ffff, 0x00cf9b00 } } },
52 [GDT_ENTRY_KERNEL_CS
] = { { { 0x0000ffff, 0x00af9b00 } } },
53 [GDT_ENTRY_KERNEL_DS
] = { { { 0x0000ffff, 0x00cf9300 } } },
54 [GDT_ENTRY_DEFAULT_USER32_CS
] = { { { 0x0000ffff, 0x00cffb00 } } },
55 [GDT_ENTRY_DEFAULT_USER_DS
] = { { { 0x0000ffff, 0x00cff300 } } },
56 [GDT_ENTRY_DEFAULT_USER_CS
] = { { { 0x0000ffff, 0x00affb00 } } },
59 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page
, gdt_page
) = { .gdt
= {
60 [GDT_ENTRY_KERNEL_CS
] = { { { 0x0000ffff, 0x00cf9a00 } } },
61 [GDT_ENTRY_KERNEL_DS
] = { { { 0x0000ffff, 0x00cf9200 } } },
62 [GDT_ENTRY_DEFAULT_USER_CS
] = { { { 0x0000ffff, 0x00cffa00 } } },
63 [GDT_ENTRY_DEFAULT_USER_DS
] = { { { 0x0000ffff, 0x00cff200 } } },
65 * Segments used for calling PnP BIOS have byte granularity.
66 * They code segments and data segments have fixed 64k limits,
67 * the transfer segment sizes are set at run time.
70 [GDT_ENTRY_PNPBIOS_CS32
] = { { { 0x0000ffff, 0x00409a00 } } },
72 [GDT_ENTRY_PNPBIOS_CS16
] = { { { 0x0000ffff, 0x00009a00 } } },
74 [GDT_ENTRY_PNPBIOS_DS
] = { { { 0x0000ffff, 0x00009200 } } },
76 [GDT_ENTRY_PNPBIOS_TS1
] = { { { 0x00000000, 0x00009200 } } },
78 [GDT_ENTRY_PNPBIOS_TS2
] = { { { 0x00000000, 0x00009200 } } },
80 * The APM segments have byte granularity and their bases
81 * are set at run time. All have 64k limits.
84 [GDT_ENTRY_APMBIOS_BASE
] = { { { 0x0000ffff, 0x00409a00 } } },
86 [GDT_ENTRY_APMBIOS_BASE
+1] = { { { 0x0000ffff, 0x00009a00 } } },
88 [GDT_ENTRY_APMBIOS_BASE
+2] = { { { 0x0000ffff, 0x00409200 } } },
90 [GDT_ENTRY_ESPFIX_SS
] = { { { 0x00000000, 0x00c09200 } } },
91 [GDT_ENTRY_PERCPU
] = { { { 0x00000000, 0x00000000 } } },
94 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page
);
97 static int cachesize_override __cpuinitdata
= -1;
98 static int disable_x86_serial_nr __cpuinitdata
= 1;
100 static int __init
cachesize_setup(char *str
)
102 get_option(&str
, &cachesize_override
);
105 __setup("cachesize=", cachesize_setup
);
107 static int __init
x86_fxsr_setup(char *s
)
109 setup_clear_cpu_cap(X86_FEATURE_FXSR
);
110 setup_clear_cpu_cap(X86_FEATURE_XMM
);
113 __setup("nofxsr", x86_fxsr_setup
);
115 static int __init
x86_sep_setup(char *s
)
117 setup_clear_cpu_cap(X86_FEATURE_SEP
);
120 __setup("nosep", x86_sep_setup
);
122 /* Standard macro to see if a specific flag is changeable */
123 static inline int flag_is_changeable_p(u32 flag
)
137 : "=&r" (f1
), "=&r" (f2
)
140 return ((f1
^f2
) & flag
) != 0;
143 /* Probe for the CPUID instruction */
144 static int __cpuinit
have_cpuid_p(void)
146 return flag_is_changeable_p(X86_EFLAGS_ID
);
149 static void __cpuinit
squash_the_stupid_serial_number(struct cpuinfo_x86
*c
)
151 if (cpu_has(c
, X86_FEATURE_PN
) && disable_x86_serial_nr
) {
152 /* Disable processor serial number */
153 unsigned long lo
, hi
;
154 rdmsr(MSR_IA32_BBL_CR_CTL
, lo
, hi
);
156 wrmsr(MSR_IA32_BBL_CR_CTL
, lo
, hi
);
157 printk(KERN_NOTICE
"CPU serial number disabled.\n");
158 clear_cpu_cap(c
, X86_FEATURE_PN
);
160 /* Disabling the serial number may affect the cpuid level */
161 c
->cpuid_level
= cpuid_eax(0);
165 static int __init
x86_serial_nr_setup(char *s
)
167 disable_x86_serial_nr
= 0;
170 __setup("serialnumber", x86_serial_nr_setup
);
172 static inline int flag_is_changeable_p(u32 flag
)
176 /* Probe for the CPUID instruction */
177 static inline int have_cpuid_p(void)
181 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86
*c
)
187 * Naming convention should be: <Name> [(<Codename>)]
188 * This table only is used unless init_<vendor>() below doesn't set it;
189 * in particular, if CPUID levels 0x80000002..4 are supported, this isn't used
193 /* Look up CPU names by table lookup. */
194 static char __cpuinit
*table_lookup_model(struct cpuinfo_x86
*c
)
196 struct cpu_model_info
*info
;
198 if (c
->x86_model
>= 16)
199 return NULL
; /* Range check */
204 info
= this_cpu
->c_models
;
206 while (info
&& info
->family
) {
207 if (info
->family
== c
->x86
)
208 return info
->model_names
[c
->x86_model
];
211 return NULL
; /* Not found */
214 __u32 cleared_cpu_caps
[NCAPINTS
] __cpuinitdata
;
216 /* Current gdt points %fs at the "master" per-cpu area: after this,
217 * it's on the real one. */
218 void switch_to_new_gdt(void)
220 struct desc_ptr gdt_descr
;
222 gdt_descr
.address
= (long)get_cpu_gdt_table(smp_processor_id());
223 gdt_descr
.size
= GDT_SIZE
- 1;
224 load_gdt(&gdt_descr
);
226 asm("mov %0, %%fs" : : "r" (__KERNEL_PERCPU
) : "memory");
230 static struct cpu_dev
*cpu_devs
[X86_VENDOR_NUM
] = {};
232 static void __cpuinit
default_init(struct cpuinfo_x86
*c
)
235 display_cacheinfo(c
);
237 /* Not much we can do here... */
238 /* Check if at least it has cpuid */
239 if (c
->cpuid_level
== -1) {
240 /* No cpuid. It must be an ancient CPU */
242 strcpy(c
->x86_model_id
, "486");
243 else if (c
->x86
== 3)
244 strcpy(c
->x86_model_id
, "386");
249 static struct cpu_dev __cpuinitdata default_cpu
= {
250 .c_init
= default_init
,
251 .c_vendor
= "Unknown",
252 .c_x86_vendor
= X86_VENDOR_UNKNOWN
,
255 int __cpuinit
get_model_name(struct cpuinfo_x86
*c
)
260 if (c
->extended_cpuid_level
< 0x80000004)
263 v
= (unsigned int *) c
->x86_model_id
;
264 cpuid(0x80000002, &v
[0], &v
[1], &v
[2], &v
[3]);
265 cpuid(0x80000003, &v
[4], &v
[5], &v
[6], &v
[7]);
266 cpuid(0x80000004, &v
[8], &v
[9], &v
[10], &v
[11]);
267 c
->x86_model_id
[48] = 0;
269 /* Intel chips right-justify this string for some dumb reason;
270 undo that brain damage */
271 p
= q
= &c
->x86_model_id
[0];
277 while (q
<= &c
->x86_model_id
[48])
278 *q
++ = '\0'; /* Zero-pad the rest */
284 void __cpuinit
display_cacheinfo(struct cpuinfo_x86
*c
)
286 unsigned int n
, dummy
, ebx
, ecx
, edx
, l2size
;
288 n
= c
->extended_cpuid_level
;
290 if (n
>= 0x80000005) {
291 cpuid(0x80000005, &dummy
, &ebx
, &ecx
, &edx
);
292 printk(KERN_INFO
"CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
293 edx
>>24, edx
&0xFF, ecx
>>24, ecx
&0xFF);
294 c
->x86_cache_size
= (ecx
>>24) + (edx
>>24);
296 /* On K8 L1 TLB is inclusive, so don't count it */
301 if (n
< 0x80000006) /* Some chips just has a large L1. */
304 cpuid(0x80000006, &dummy
, &ebx
, &ecx
, &edx
);
308 c
->x86_tlbsize
+= ((ebx
>> 16) & 0xfff) + (ebx
& 0xfff);
310 /* do processor-specific cache resizing */
311 if (this_cpu
->c_size_cache
)
312 l2size
= this_cpu
->c_size_cache(c
, l2size
);
314 /* Allow user to override all this if necessary. */
315 if (cachesize_override
!= -1)
316 l2size
= cachesize_override
;
319 return; /* Again, no L2 cache is possible */
322 c
->x86_cache_size
= l2size
;
324 printk(KERN_INFO
"CPU: L2 Cache: %dK (%d bytes/line)\n",
328 void __cpuinit
detect_ht(struct cpuinfo_x86
*c
)
331 u32 eax
, ebx
, ecx
, edx
;
332 int index_msb
, core_bits
;
334 if (!cpu_has(c
, X86_FEATURE_HT
))
337 if (cpu_has(c
, X86_FEATURE_CMP_LEGACY
))
340 if (cpu_has(c
, X86_FEATURE_XTOPOLOGY
))
343 cpuid(1, &eax
, &ebx
, &ecx
, &edx
);
345 smp_num_siblings
= (ebx
& 0xff0000) >> 16;
347 if (smp_num_siblings
== 1) {
348 printk(KERN_INFO
"CPU: Hyper-Threading is disabled\n");
349 } else if (smp_num_siblings
> 1) {
351 if (smp_num_siblings
> NR_CPUS
) {
352 printk(KERN_WARNING
"CPU: Unsupported number of siblings %d",
354 smp_num_siblings
= 1;
358 index_msb
= get_count_order(smp_num_siblings
);
360 c
->phys_proc_id
= phys_pkg_id(index_msb
);
362 c
->phys_proc_id
= phys_pkg_id(c
->initial_apicid
, index_msb
);
365 smp_num_siblings
= smp_num_siblings
/ c
->x86_max_cores
;
367 index_msb
= get_count_order(smp_num_siblings
);
369 core_bits
= get_count_order(c
->x86_max_cores
);
372 c
->cpu_core_id
= phys_pkg_id(index_msb
) &
373 ((1 << core_bits
) - 1);
375 c
->cpu_core_id
= phys_pkg_id(c
->initial_apicid
, index_msb
) &
376 ((1 << core_bits
) - 1);
381 if ((c
->x86_max_cores
* smp_num_siblings
) > 1) {
382 printk(KERN_INFO
"CPU: Physical Processor ID: %d\n",
384 printk(KERN_INFO
"CPU: Processor Core ID: %d\n",
390 static void __cpuinit
get_cpu_vendor(struct cpuinfo_x86
*c
)
392 char *v
= c
->x86_vendor_id
;
396 for (i
= 0; i
< X86_VENDOR_NUM
; i
++) {
400 if (!strcmp(v
, cpu_devs
[i
]->c_ident
[0]) ||
401 (cpu_devs
[i
]->c_ident
[1] &&
402 !strcmp(v
, cpu_devs
[i
]->c_ident
[1]))) {
403 this_cpu
= cpu_devs
[i
];
404 c
->x86_vendor
= this_cpu
->c_x86_vendor
;
411 printk(KERN_ERR
"CPU: Vendor unknown, using generic init.\n");
412 printk(KERN_ERR
"CPU: Your system may be unstable.\n");
415 c
->x86_vendor
= X86_VENDOR_UNKNOWN
;
416 this_cpu
= &default_cpu
;
419 void __cpuinit
cpu_detect(struct cpuinfo_x86
*c
)
421 /* Get vendor name */
422 cpuid(0x00000000, (unsigned int *)&c
->cpuid_level
,
423 (unsigned int *)&c
->x86_vendor_id
[0],
424 (unsigned int *)&c
->x86_vendor_id
[8],
425 (unsigned int *)&c
->x86_vendor_id
[4]);
428 /* Intel-defined flags: level 0x00000001 */
429 if (c
->cpuid_level
>= 0x00000001) {
430 u32 junk
, tfms
, cap0
, misc
;
431 cpuid(0x00000001, &tfms
, &misc
, &junk
, &cap0
);
432 c
->x86
= (tfms
>> 8) & 0xf;
433 c
->x86_model
= (tfms
>> 4) & 0xf;
434 c
->x86_mask
= tfms
& 0xf;
436 c
->x86
+= (tfms
>> 20) & 0xff;
438 c
->x86_model
+= ((tfms
>> 16) & 0xf) << 4;
439 if (cap0
& (1<<19)) {
440 c
->x86_clflush_size
= ((misc
>> 8) & 0xff) * 8;
441 c
->x86_cache_alignment
= c
->x86_clflush_size
;
446 static void __cpuinit
get_cpu_cap(struct cpuinfo_x86
*c
)
451 /* Intel-defined flags: level 0x00000001 */
452 if (c
->cpuid_level
>= 0x00000001) {
453 u32 capability
, excap
;
454 cpuid(0x00000001, &tfms
, &ebx
, &excap
, &capability
);
455 c
->x86_capability
[0] = capability
;
456 c
->x86_capability
[4] = excap
;
459 /* AMD-defined flags: level 0x80000001 */
460 xlvl
= cpuid_eax(0x80000000);
461 c
->extended_cpuid_level
= xlvl
;
462 if ((xlvl
& 0xffff0000) == 0x80000000) {
463 if (xlvl
>= 0x80000001) {
464 c
->x86_capability
[1] = cpuid_edx(0x80000001);
465 c
->x86_capability
[6] = cpuid_ecx(0x80000001);
470 /* Transmeta-defined flags: level 0x80860001 */
471 xlvl
= cpuid_eax(0x80860000);
472 if ((xlvl
& 0xffff0000) == 0x80860000) {
473 /* Don't set x86_cpuid_level here for now to not confuse. */
474 if (xlvl
>= 0x80860001)
475 c
->x86_capability
[2] = cpuid_edx(0x80860001);
478 if (c
->extended_cpuid_level
>= 0x80000007)
479 c
->x86_power
= cpuid_edx(0x80000007);
481 if (c
->extended_cpuid_level
>= 0x80000008) {
482 u32 eax
= cpuid_eax(0x80000008);
484 c
->x86_virt_bits
= (eax
>> 8) & 0xff;
485 c
->x86_phys_bits
= eax
& 0xff;
490 * Do minimum CPU detection early.
491 * Fields really needed: vendor, cpuid_level, family, model, mask,
493 * The others are not touched to avoid unwanted side effects.
495 * WARNING: this function is only called on the BP. Don't add code here
496 * that is supposed to run on all CPUs.
498 static void __init
early_identify_cpu(struct cpuinfo_x86
*c
)
501 c
->x86_clflush_size
= 64;
503 c
->x86_clflush_size
= 32;
505 c
->x86_cache_alignment
= c
->x86_clflush_size
;
510 memset(&c
->x86_capability
, 0, sizeof c
->x86_capability
);
512 c
->extended_cpuid_level
= 0;
520 if (this_cpu
->c_early_init
)
521 this_cpu
->c_early_init(c
);
523 validate_pat_support(c
);
526 void __init
early_cpu_init(void)
528 struct cpu_dev
**cdev
;
531 printk("KERNEL supported cpus:\n");
532 for (cdev
= __x86_cpu_dev_start
; cdev
< __x86_cpu_dev_end
; cdev
++) {
533 struct cpu_dev
*cpudev
= *cdev
;
536 if (count
>= X86_VENDOR_NUM
)
538 cpu_devs
[count
] = cpudev
;
541 for (j
= 0; j
< 2; j
++) {
542 if (!cpudev
->c_ident
[j
])
544 printk(" %s %s\n", cpudev
->c_vendor
,
549 early_identify_cpu(&boot_cpu_data
);
553 * The NOPL instruction is supposed to exist on all CPUs with
554 * family >= 6, unfortunately, that's not true in practice because
555 * of early VIA chips and (more importantly) broken virtualizers that
556 * are not easy to detect. Hence, probe for it based on first
559 * Note: no 64-bit chip is known to lack these, but put the code here
560 * for consistency with 32 bits, and to make it utterly trivial to
561 * diagnose the problem should it ever surface.
563 static void __cpuinit
detect_nopl(struct cpuinfo_x86
*c
)
565 const u32 nopl_signature
= 0x888c53b1; /* Random number */
566 u32 has_nopl
= nopl_signature
;
568 clear_cpu_cap(c
, X86_FEATURE_NOPL
);
571 "1: .byte 0x0f,0x1f,0xc0\n" /* nopl %eax */
573 " .section .fixup,\"ax\"\n"
580 if (has_nopl
== nopl_signature
)
581 set_cpu_cap(c
, X86_FEATURE_NOPL
);
585 static void __cpuinit
generic_identify(struct cpuinfo_x86
*c
)
590 c
->extended_cpuid_level
= 0;
598 if (c
->cpuid_level
>= 0x00000001) {
599 c
->initial_apicid
= (cpuid_ebx(1) >> 24) & 0xFF;
601 # ifdef CONFIG_X86_HT
602 c
->apicid
= phys_pkg_id(c
->initial_apicid
, 0);
604 c
->apicid
= c
->initial_apicid
;
609 c
->phys_proc_id
= c
->initial_apicid
;
613 if (c
->extended_cpuid_level
>= 0x80000004)
614 get_model_name(c
); /* Default name */
616 init_scattered_cpuid_features(c
);
621 * This does the hard work of actually picking apart the CPU stuff...
623 static void __cpuinit
identify_cpu(struct cpuinfo_x86
*c
)
627 c
->loops_per_jiffy
= loops_per_jiffy
;
628 c
->x86_cache_size
= -1;
629 c
->x86_vendor
= X86_VENDOR_UNKNOWN
;
630 c
->x86_model
= c
->x86_mask
= 0; /* So far unknown... */
631 c
->x86_vendor_id
[0] = '\0'; /* Unset */
632 c
->x86_model_id
[0] = '\0'; /* Unset */
633 c
->x86_max_cores
= 1;
635 c
->x86_coreid_bits
= 0;
636 c
->x86_clflush_size
= 64;
638 c
->cpuid_level
= -1; /* CPUID not detected */
639 c
->x86_clflush_size
= 32;
641 c
->x86_cache_alignment
= c
->x86_clflush_size
;
642 memset(&c
->x86_capability
, 0, sizeof c
->x86_capability
);
644 if (!have_cpuid_p()) {
646 * First of all, decide if this is a 486 or higher
647 * It's a 486 if we can modify the AC flag
649 if (flag_is_changeable_p(X86_EFLAGS_AC
))
657 if (this_cpu
->c_identify
)
658 this_cpu
->c_identify(c
);
661 c
->apicid
= phys_pkg_id(0);
665 * Vendor-specific initialization. In this section we
666 * canonicalize the feature flags, meaning if there are
667 * features a certain CPU supports which CPUID doesn't
668 * tell us, CPUID claiming incorrect flags, or other bugs,
669 * we handle them here.
671 * At the end of this section, c->x86_capability better
672 * indicate the features this CPU genuinely supports!
674 if (this_cpu
->c_init
)
677 /* Disable the PN if appropriate */
678 squash_the_stupid_serial_number(c
);
681 * The vendor-specific functions might have changed features. Now
682 * we do "generic changes."
685 /* If the model name is still unset, do table lookup. */
686 if (!c
->x86_model_id
[0]) {
688 p
= table_lookup_model(c
);
690 strcpy(c
->x86_model_id
, p
);
693 sprintf(c
->x86_model_id
, "%02x/%02x",
694 c
->x86
, c
->x86_model
);
702 * On SMP, boot_cpu_data holds the common feature set between
703 * all CPUs; so make sure that we indicate which features are
704 * common between the CPUs. The first time this routine gets
705 * executed, c == &boot_cpu_data.
707 if (c
!= &boot_cpu_data
) {
708 /* AND the already accumulated flags with these */
709 for (i
= 0; i
< NCAPINTS
; i
++)
710 boot_cpu_data
.x86_capability
[i
] &= c
->x86_capability
[i
];
713 /* Clear all flags overriden by options */
714 for (i
= 0; i
< NCAPINTS
; i
++)
715 c
->x86_capability
[i
] &= ~cleared_cpu_caps
[i
];
717 #ifdef CONFIG_X86_MCE
718 /* Init Machine Check Exception if available. */
722 select_idle_routine(c
);
724 #if defined(CONFIG_NUMA) && defined(CONFIG_X86_64)
725 numa_add_cpu(smp_processor_id());
729 void __init
identify_boot_cpu(void)
731 identify_cpu(&boot_cpu_data
);
738 void __cpuinit
identify_secondary_cpu(struct cpuinfo_x86
*c
)
740 BUG_ON(c
== &boot_cpu_data
);
753 static struct msr_range msr_range_array
[] __cpuinitdata
= {
754 { 0x00000000, 0x00000418},
755 { 0xc0000000, 0xc000040b},
756 { 0xc0010000, 0xc0010142},
757 { 0xc0011000, 0xc001103b},
760 static void __cpuinit
print_cpu_msr(void)
765 unsigned index_min
, index_max
;
767 for (i
= 0; i
< ARRAY_SIZE(msr_range_array
); i
++) {
768 index_min
= msr_range_array
[i
].min
;
769 index_max
= msr_range_array
[i
].max
;
770 for (index
= index_min
; index
< index_max
; index
++) {
771 if (rdmsrl_amd_safe(index
, &val
))
773 printk(KERN_INFO
" MSR%08x: %016llx\n", index
, val
);
778 static int show_msr __cpuinitdata
;
779 static __init
int setup_show_msr(char *arg
)
783 get_option(&arg
, &num
);
789 __setup("show_msr=", setup_show_msr
);
791 static __init
int setup_noclflush(char *arg
)
793 setup_clear_cpu_cap(X86_FEATURE_CLFLSH
);
796 __setup("noclflush", setup_noclflush
);
798 void __cpuinit
print_cpu_info(struct cpuinfo_x86
*c
)
802 if (c
->x86_vendor
< X86_VENDOR_NUM
)
803 vendor
= this_cpu
->c_vendor
;
804 else if (c
->cpuid_level
>= 0)
805 vendor
= c
->x86_vendor_id
;
807 if (vendor
&& strncmp(c
->x86_model_id
, vendor
, strlen(vendor
)))
808 printk(KERN_CONT
"%s ", vendor
);
810 if (c
->x86_model_id
[0])
811 printk(KERN_CONT
"%s", c
->x86_model_id
);
813 printk(KERN_CONT
"%d86", c
->x86
);
815 if (c
->x86_mask
|| c
->cpuid_level
>= 0)
816 printk(KERN_CONT
" stepping %02x\n", c
->x86_mask
);
818 printk(KERN_CONT
"\n");
821 if (c
->cpu_index
< show_msr
)
829 static __init
int setup_disablecpuid(char *arg
)
832 if (get_option(&arg
, &bit
) && bit
< NCAPINTS
*32)
833 setup_clear_cpu_cap(bit
);
838 __setup("clearcpuid=", setup_disablecpuid
);
840 cpumask_t cpu_initialized __cpuinitdata
= CPU_MASK_NONE
;
843 struct x8664_pda
**_cpu_pda __read_mostly
;
844 EXPORT_SYMBOL(_cpu_pda
);
846 struct desc_ptr idt_descr
= { 256 * 16 - 1, (unsigned long) idt_table
};
848 char boot_cpu_stack
[IRQSTACKSIZE
] __page_aligned_bss
;
850 void pda_init(int cpu
)
852 struct x8664_pda
*pda
= cpu_pda(cpu
);
854 /* Setup up data that may be needed in __get_free_pages early */
857 /* Memory clobbers used to order PDA accessed */
859 wrmsrl(MSR_GS_BASE
, pda
);
862 pda
->cpunumber
= cpu
;
864 pda
->kernelstack
= (unsigned long)stack_thread_info() -
865 PDA_STACKOFFSET
+ THREAD_SIZE
;
866 pda
->active_mm
= &init_mm
;
870 /* others are initialized in smpboot.c */
871 pda
->pcurrent
= &init_task
;
872 pda
->irqstackptr
= boot_cpu_stack
;
873 pda
->irqstackptr
+= IRQSTACKSIZE
- 64;
875 if (!pda
->irqstackptr
) {
876 pda
->irqstackptr
= (char *)
877 __get_free_pages(GFP_ATOMIC
, IRQSTACK_ORDER
);
878 if (!pda
->irqstackptr
)
879 panic("cannot allocate irqstack for cpu %d",
881 pda
->irqstackptr
+= IRQSTACKSIZE
- 64;
884 if (pda
->nodenumber
== 0 && cpu_to_node(cpu
) != NUMA_NO_NODE
)
885 pda
->nodenumber
= cpu_to_node(cpu
);
889 char boot_exception_stacks
[(N_EXCEPTION_STACKS
- 1) * EXCEPTION_STKSZ
+
890 DEBUG_STKSZ
] __page_aligned_bss
;
892 extern asmlinkage
void ignore_sysret(void);
894 /* May not be marked __init: used by software suspend */
895 void syscall_init(void)
898 * LSTAR and STAR live in a bit strange symbiosis.
899 * They both write to the same internal register. STAR allows to
900 * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip.
902 wrmsrl(MSR_STAR
, ((u64
)__USER32_CS
)<<48 | ((u64
)__KERNEL_CS
)<<32);
903 wrmsrl(MSR_LSTAR
, system_call
);
904 wrmsrl(MSR_CSTAR
, ignore_sysret
);
906 #ifdef CONFIG_IA32_EMULATION
907 syscall32_cpu_init();
910 /* Flags to clear on syscall */
911 wrmsrl(MSR_SYSCALL_MASK
,
912 X86_EFLAGS_TF
|X86_EFLAGS_DF
|X86_EFLAGS_IF
|X86_EFLAGS_IOPL
);
915 unsigned long kernel_eflags
;
918 * Copies of the original ist values from the tss are only accessed during
919 * debugging, no special alignment required.
921 DEFINE_PER_CPU(struct orig_ist
, orig_ist
);
925 /* Make sure %fs is initialized properly in idle threads */
926 struct pt_regs
* __cpuinit
idle_regs(struct pt_regs
*regs
)
928 memset(regs
, 0, sizeof(struct pt_regs
));
929 regs
->fs
= __KERNEL_PERCPU
;
935 * cpu_init() initializes state that is per-CPU. Some data is already
936 * initialized (naturally) in the bootstrap process, such as the GDT
937 * and IDT. We reload them nevertheless, this function acts as a
938 * 'CPU state barrier', nothing should get across.
939 * A lot of state is already set up in PDA init for 64 bit
942 void __cpuinit
cpu_init(void)
944 int cpu
= stack_smp_processor_id();
945 struct tss_struct
*t
= &per_cpu(init_tss
, cpu
);
946 struct orig_ist
*orig_ist
= &per_cpu(orig_ist
, cpu
);
948 char *estacks
= NULL
;
949 struct task_struct
*me
;
952 /* CPU 0 is initialised in head64.c */
956 estacks
= boot_exception_stacks
;
960 if (cpu_test_and_set(cpu
, cpu_initialized
))
961 panic("CPU#%d already initialized!\n", cpu
);
963 printk(KERN_INFO
"Initializing CPU#%d\n", cpu
);
965 clear_in_cr4(X86_CR4_VME
|X86_CR4_PVI
|X86_CR4_TSD
|X86_CR4_DE
);
968 * Initialize the per-CPU GDT with the boot GDT,
969 * and set up the GDT descriptor:
973 load_idt((const struct desc_ptr
*)&idt_descr
);
975 memset(me
->thread
.tls_array
, 0, GDT_ENTRY_TLS_ENTRIES
* 8);
978 wrmsrl(MSR_FS_BASE
, 0);
979 wrmsrl(MSR_KERNEL_GS_BASE
, 0);
983 if (cpu
!= 0 && x2apic
)
987 * set up and load the per-CPU TSS
989 if (!orig_ist
->ist
[0]) {
990 static const unsigned int order
[N_EXCEPTION_STACKS
] = {
991 [0 ... N_EXCEPTION_STACKS
- 1] = EXCEPTION_STACK_ORDER
,
992 [DEBUG_STACK
- 1] = DEBUG_STACK_ORDER
994 for (v
= 0; v
< N_EXCEPTION_STACKS
; v
++) {
996 estacks
= (char *)__get_free_pages(GFP_ATOMIC
, order
[v
]);
998 panic("Cannot allocate exception "
999 "stack %ld %d\n", v
, cpu
);
1001 estacks
+= PAGE_SIZE
<< order
[v
];
1002 orig_ist
->ist
[v
] = t
->x86_tss
.ist
[v
] =
1003 (unsigned long)estacks
;
1007 t
->x86_tss
.io_bitmap_base
= offsetof(struct tss_struct
, io_bitmap
);
1009 * <= is required because the CPU will access up to
1010 * 8 bits beyond the end of the IO permission bitmap.
1012 for (i
= 0; i
<= IO_BITMAP_LONGS
; i
++)
1013 t
->io_bitmap
[i
] = ~0UL;
1015 atomic_inc(&init_mm
.mm_count
);
1016 me
->active_mm
= &init_mm
;
1019 enter_lazy_tlb(&init_mm
, me
);
1021 load_sp0(t
, ¤t
->thread
);
1022 set_tss_desc(cpu
, t
);
1024 load_LDT(&init_mm
.context
);
1028 * If the kgdb is connected no debug regs should be altered. This
1029 * is only applicable when KGDB and a KGDB I/O module are built
1030 * into the kernel and you are using early debugging with
1031 * kgdbwait. KGDB will control the kernel HW breakpoint registers.
1033 if (kgdb_connected
&& arch_kgdb_ops
.correct_hw_break
)
1034 arch_kgdb_ops
.correct_hw_break();
1038 * Clear all 6 debug registers:
1041 set_debugreg(0UL, 0);
1042 set_debugreg(0UL, 1);
1043 set_debugreg(0UL, 2);
1044 set_debugreg(0UL, 3);
1045 set_debugreg(0UL, 6);
1046 set_debugreg(0UL, 7);
1048 /* If the kgdb is connected no debug regs should be altered. */
1054 raw_local_save_flags(kernel_eflags
);
1062 void __cpuinit
cpu_init(void)
1064 int cpu
= smp_processor_id();
1065 struct task_struct
*curr
= current
;
1066 struct tss_struct
*t
= &per_cpu(init_tss
, cpu
);
1067 struct thread_struct
*thread
= &curr
->thread
;
1069 if (cpu_test_and_set(cpu
, cpu_initialized
)) {
1070 printk(KERN_WARNING
"CPU#%d already initialized!\n", cpu
);
1071 for (;;) local_irq_enable();
1074 printk(KERN_INFO
"Initializing CPU#%d\n", cpu
);
1076 if (cpu_has_vme
|| cpu_has_tsc
|| cpu_has_de
)
1077 clear_in_cr4(X86_CR4_VME
|X86_CR4_PVI
|X86_CR4_TSD
|X86_CR4_DE
);
1079 load_idt(&idt_descr
);
1080 switch_to_new_gdt();
1083 * Set up and load the per-CPU TSS and LDT
1085 atomic_inc(&init_mm
.mm_count
);
1086 curr
->active_mm
= &init_mm
;
1089 enter_lazy_tlb(&init_mm
, curr
);
1091 load_sp0(t
, thread
);
1092 set_tss_desc(cpu
, t
);
1094 load_LDT(&init_mm
.context
);
1096 #ifdef CONFIG_DOUBLEFAULT
1097 /* Set up doublefault TSS pointer in the GDT */
1098 __set_tss_desc(cpu
, GDT_ENTRY_DOUBLEFAULT_TSS
, &doublefault_tss
);
1102 asm volatile ("mov %0, %%gs" : : "r" (0));
1104 /* Clear all 6 debug registers: */
1113 * Force FPU initialization:
1116 current_thread_info()->status
= TS_XSAVE
;
1118 current_thread_info()->status
= 0;
1120 mxcsr_feature_mask_init();
1123 * Boot processor to setup the FP and extended state context info.
1125 if (!smp_processor_id())
1126 init_thread_xstate();
1131 #ifdef CONFIG_HOTPLUG_CPU
1132 void __cpuinit
cpu_uninit(void)
1134 int cpu
= raw_smp_processor_id();
1135 cpu_clear(cpu
, cpu_initialized
);
1137 /* lazy TLB state */
1138 per_cpu(cpu_tlbstate
, cpu
).state
= 0;
1139 per_cpu(cpu_tlbstate
, cpu
).active_mm
= &init_mm
;