1 #include <linux/bootmem.h>
2 #include <linux/linkage.h>
3 #include <linux/bitops.h>
4 #include <linux/kernel.h>
5 #include <linux/module.h>
6 #include <linux/percpu.h>
7 #include <linux/string.h>
8 #include <linux/delay.h>
9 #include <linux/sched.h>
10 #include <linux/init.h>
11 #include <linux/kgdb.h>
12 #include <linux/smp.h>
15 #include <asm/stackprotector.h>
16 #include <asm/perf_event.h>
17 #include <asm/mmu_context.h>
18 #include <asm/archrandom.h>
19 #include <asm/hypervisor.h>
20 #include <asm/processor.h>
21 #include <asm/debugreg.h>
22 #include <asm/sections.h>
23 #include <asm/vsyscall.h>
24 #include <linux/topology.h>
25 #include <linux/cpumask.h>
26 #include <asm/pgtable.h>
27 #include <linux/atomic.h>
28 #include <asm/proto.h>
29 #include <asm/setup.h>
33 #include <asm/fpu-internal.h>
35 #include <linux/numa.h>
41 #include <asm/microcode.h>
42 #include <asm/microcode_intel.h>
44 #ifdef CONFIG_X86_LOCAL_APIC
45 #include <asm/uv/uv.h>
50 /* all of these masks are initialized in setup_cpu_local_masks() */
51 cpumask_var_t cpu_initialized_mask
;
52 cpumask_var_t cpu_callout_mask
;
53 cpumask_var_t cpu_callin_mask
;
55 /* representing cpus for which sibling maps can be computed */
56 cpumask_var_t cpu_sibling_setup_mask
;
58 /* correctly size the local cpu masks */
59 void __init
setup_cpu_local_masks(void)
61 alloc_bootmem_cpumask_var(&cpu_initialized_mask
);
62 alloc_bootmem_cpumask_var(&cpu_callin_mask
);
63 alloc_bootmem_cpumask_var(&cpu_callout_mask
);
64 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask
);
67 static void default_init(struct cpuinfo_x86
*c
)
70 cpu_detect_cache_sizes(c
);
72 /* Not much we can do here... */
73 /* Check if at least it has cpuid */
74 if (c
->cpuid_level
== -1) {
75 /* No cpuid. It must be an ancient CPU */
77 strcpy(c
->x86_model_id
, "486");
79 strcpy(c
->x86_model_id
, "386");
84 static const struct cpu_dev default_cpu
= {
85 .c_init
= default_init
,
86 .c_vendor
= "Unknown",
87 .c_x86_vendor
= X86_VENDOR_UNKNOWN
,
90 static const struct cpu_dev
*this_cpu
= &default_cpu
;
92 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page
, gdt_page
) = { .gdt
= {
95 * We need valid kernel segments for data and code in long mode too
96 * IRET will check the segment types kkeil 2000/10/28
97 * Also sysret mandates a special GDT layout
99 * TLS descriptors are currently at a different place compared to i386.
100 * Hopefully nobody expects them at a fixed place (Wine?)
102 [GDT_ENTRY_KERNEL32_CS
] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff),
103 [GDT_ENTRY_KERNEL_CS
] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff),
104 [GDT_ENTRY_KERNEL_DS
] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff),
105 [GDT_ENTRY_DEFAULT_USER32_CS
] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff),
106 [GDT_ENTRY_DEFAULT_USER_DS
] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff),
107 [GDT_ENTRY_DEFAULT_USER_CS
] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff),
109 [GDT_ENTRY_KERNEL_CS
] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff),
110 [GDT_ENTRY_KERNEL_DS
] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
111 [GDT_ENTRY_DEFAULT_USER_CS
] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff),
112 [GDT_ENTRY_DEFAULT_USER_DS
] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff),
114 * Segments used for calling PnP BIOS have byte granularity.
115 * They code segments and data segments have fixed 64k limits,
116 * the transfer segment sizes are set at run time.
119 [GDT_ENTRY_PNPBIOS_CS32
] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
121 [GDT_ENTRY_PNPBIOS_CS16
] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
123 [GDT_ENTRY_PNPBIOS_DS
] = GDT_ENTRY_INIT(0x0092, 0, 0xffff),
125 [GDT_ENTRY_PNPBIOS_TS1
] = GDT_ENTRY_INIT(0x0092, 0, 0),
127 [GDT_ENTRY_PNPBIOS_TS2
] = GDT_ENTRY_INIT(0x0092, 0, 0),
129 * The APM segments have byte granularity and their bases
130 * are set at run time. All have 64k limits.
133 [GDT_ENTRY_APMBIOS_BASE
] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
135 [GDT_ENTRY_APMBIOS_BASE
+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
137 [GDT_ENTRY_APMBIOS_BASE
+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff),
139 [GDT_ENTRY_ESPFIX_SS
] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
140 [GDT_ENTRY_PERCPU
] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
141 GDT_STACK_CANARY_INIT
144 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page
);
146 static int __init
x86_xsave_setup(char *s
)
148 setup_clear_cpu_cap(X86_FEATURE_XSAVE
);
149 setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT
);
150 setup_clear_cpu_cap(X86_FEATURE_AVX
);
151 setup_clear_cpu_cap(X86_FEATURE_AVX2
);
154 __setup("noxsave", x86_xsave_setup
);
156 static int __init
x86_xsaveopt_setup(char *s
)
158 setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT
);
161 __setup("noxsaveopt", x86_xsaveopt_setup
);
164 static int cachesize_override
= -1;
165 static int disable_x86_serial_nr
= 1;
167 static int __init
cachesize_setup(char *str
)
169 get_option(&str
, &cachesize_override
);
172 __setup("cachesize=", cachesize_setup
);
174 static int __init
x86_fxsr_setup(char *s
)
176 setup_clear_cpu_cap(X86_FEATURE_FXSR
);
177 setup_clear_cpu_cap(X86_FEATURE_XMM
);
180 __setup("nofxsr", x86_fxsr_setup
);
182 static int __init
x86_sep_setup(char *s
)
184 setup_clear_cpu_cap(X86_FEATURE_SEP
);
187 __setup("nosep", x86_sep_setup
);
189 /* Standard macro to see if a specific flag is changeable */
190 static inline int flag_is_changeable_p(u32 flag
)
195 * Cyrix and IDT cpus allow disabling of CPUID
196 * so the code below may return different results
197 * when it is executed before and after enabling
198 * the CPUID. Add "volatile" to not allow gcc to
199 * optimize the subsequent calls to this function.
201 asm volatile ("pushfl \n\t"
212 : "=&r" (f1
), "=&r" (f2
)
215 return ((f1
^f2
) & flag
) != 0;
218 /* Probe for the CPUID instruction */
219 int have_cpuid_p(void)
221 return flag_is_changeable_p(X86_EFLAGS_ID
);
224 static void squash_the_stupid_serial_number(struct cpuinfo_x86
*c
)
226 unsigned long lo
, hi
;
228 if (!cpu_has(c
, X86_FEATURE_PN
) || !disable_x86_serial_nr
)
231 /* Disable processor serial number: */
233 rdmsr(MSR_IA32_BBL_CR_CTL
, lo
, hi
);
235 wrmsr(MSR_IA32_BBL_CR_CTL
, lo
, hi
);
237 printk(KERN_NOTICE
"CPU serial number disabled.\n");
238 clear_cpu_cap(c
, X86_FEATURE_PN
);
240 /* Disabling the serial number may affect the cpuid level */
241 c
->cpuid_level
= cpuid_eax(0);
244 static int __init
x86_serial_nr_setup(char *s
)
246 disable_x86_serial_nr
= 0;
249 __setup("serialnumber", x86_serial_nr_setup
);
251 static inline int flag_is_changeable_p(u32 flag
)
255 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86
*c
)
260 static __init
int setup_disable_smep(char *arg
)
262 setup_clear_cpu_cap(X86_FEATURE_SMEP
);
265 __setup("nosmep", setup_disable_smep
);
267 static __always_inline
void setup_smep(struct cpuinfo_x86
*c
)
269 if (cpu_has(c
, X86_FEATURE_SMEP
))
270 set_in_cr4(X86_CR4_SMEP
);
273 static __init
int setup_disable_smap(char *arg
)
275 setup_clear_cpu_cap(X86_FEATURE_SMAP
);
278 __setup("nosmap", setup_disable_smap
);
280 static __always_inline
void setup_smap(struct cpuinfo_x86
*c
)
282 unsigned long eflags
;
284 /* This should have been cleared long ago */
285 raw_local_save_flags(eflags
);
286 BUG_ON(eflags
& X86_EFLAGS_AC
);
288 if (cpu_has(c
, X86_FEATURE_SMAP
)) {
289 #ifdef CONFIG_X86_SMAP
290 set_in_cr4(X86_CR4_SMAP
);
292 clear_in_cr4(X86_CR4_SMAP
);
298 * Some CPU features depend on higher CPUID levels, which may not always
299 * be available due to CPUID level capping or broken virtualization
300 * software. Add those features to this table to auto-disable them.
302 struct cpuid_dependent_feature
{
307 static const struct cpuid_dependent_feature
308 cpuid_dependent_features
[] = {
309 { X86_FEATURE_MWAIT
, 0x00000005 },
310 { X86_FEATURE_DCA
, 0x00000009 },
311 { X86_FEATURE_XSAVE
, 0x0000000d },
315 static void filter_cpuid_features(struct cpuinfo_x86
*c
, bool warn
)
317 const struct cpuid_dependent_feature
*df
;
319 for (df
= cpuid_dependent_features
; df
->feature
; df
++) {
321 if (!cpu_has(c
, df
->feature
))
324 * Note: cpuid_level is set to -1 if unavailable, but
325 * extended_extended_level is set to 0 if unavailable
326 * and the legitimate extended levels are all negative
327 * when signed; hence the weird messing around with
330 if (!((s32
)df
->level
< 0 ?
331 (u32
)df
->level
> (u32
)c
->extended_cpuid_level
:
332 (s32
)df
->level
> (s32
)c
->cpuid_level
))
335 clear_cpu_cap(c
, df
->feature
);
340 "CPU: CPU feature %s disabled, no CPUID level 0x%x\n",
341 x86_cap_flags
[df
->feature
], df
->level
);
346 * Naming convention should be: <Name> [(<Codename>)]
347 * This table only is used unless init_<vendor>() below doesn't set it;
348 * in particular, if CPUID levels 0x80000002..4 are supported, this
352 /* Look up CPU names by table lookup. */
353 static const char *table_lookup_model(struct cpuinfo_x86
*c
)
356 const struct legacy_cpu_model_info
*info
;
358 if (c
->x86_model
>= 16)
359 return NULL
; /* Range check */
364 info
= this_cpu
->legacy_models
;
366 while (info
->family
) {
367 if (info
->family
== c
->x86
)
368 return info
->model_names
[c
->x86_model
];
372 return NULL
; /* Not found */
375 __u32 cpu_caps_cleared
[NCAPINTS
];
376 __u32 cpu_caps_set
[NCAPINTS
];
378 void load_percpu_segment(int cpu
)
381 loadsegment(fs
, __KERNEL_PERCPU
);
384 wrmsrl(MSR_GS_BASE
, (unsigned long)per_cpu(irq_stack_union
.gs_base
, cpu
));
386 load_stack_canary_segment();
390 * Current gdt points %fs at the "master" per-cpu area: after this,
391 * it's on the real one.
393 void switch_to_new_gdt(int cpu
)
395 struct desc_ptr gdt_descr
;
397 gdt_descr
.address
= (long)get_cpu_gdt_table(cpu
);
398 gdt_descr
.size
= GDT_SIZE
- 1;
399 load_gdt(&gdt_descr
);
400 /* Reload the per-cpu base */
402 load_percpu_segment(cpu
);
405 static const struct cpu_dev
*cpu_devs
[X86_VENDOR_NUM
] = {};
407 static void get_model_name(struct cpuinfo_x86
*c
)
412 if (c
->extended_cpuid_level
< 0x80000004)
415 v
= (unsigned int *)c
->x86_model_id
;
416 cpuid(0x80000002, &v
[0], &v
[1], &v
[2], &v
[3]);
417 cpuid(0x80000003, &v
[4], &v
[5], &v
[6], &v
[7]);
418 cpuid(0x80000004, &v
[8], &v
[9], &v
[10], &v
[11]);
419 c
->x86_model_id
[48] = 0;
422 * Intel chips right-justify this string for some dumb reason;
423 * undo that brain damage:
425 p
= q
= &c
->x86_model_id
[0];
431 while (q
<= &c
->x86_model_id
[48])
432 *q
++ = '\0'; /* Zero-pad the rest */
436 void cpu_detect_cache_sizes(struct cpuinfo_x86
*c
)
438 unsigned int n
, dummy
, ebx
, ecx
, edx
, l2size
;
440 n
= c
->extended_cpuid_level
;
442 if (n
>= 0x80000005) {
443 cpuid(0x80000005, &dummy
, &ebx
, &ecx
, &edx
);
444 c
->x86_cache_size
= (ecx
>>24) + (edx
>>24);
446 /* On K8 L1 TLB is inclusive, so don't count it */
451 if (n
< 0x80000006) /* Some chips just has a large L1. */
454 cpuid(0x80000006, &dummy
, &ebx
, &ecx
, &edx
);
458 c
->x86_tlbsize
+= ((ebx
>> 16) & 0xfff) + (ebx
& 0xfff);
460 /* do processor-specific cache resizing */
461 if (this_cpu
->legacy_cache_size
)
462 l2size
= this_cpu
->legacy_cache_size(c
, l2size
);
464 /* Allow user to override all this if necessary. */
465 if (cachesize_override
!= -1)
466 l2size
= cachesize_override
;
469 return; /* Again, no L2 cache is possible */
472 c
->x86_cache_size
= l2size
;
475 u16 __read_mostly tlb_lli_4k
[NR_INFO
];
476 u16 __read_mostly tlb_lli_2m
[NR_INFO
];
477 u16 __read_mostly tlb_lli_4m
[NR_INFO
];
478 u16 __read_mostly tlb_lld_4k
[NR_INFO
];
479 u16 __read_mostly tlb_lld_2m
[NR_INFO
];
480 u16 __read_mostly tlb_lld_4m
[NR_INFO
];
481 u16 __read_mostly tlb_lld_1g
[NR_INFO
];
484 * tlb_flushall_shift shows the balance point in replacing cr3 write
485 * with multiple 'invlpg'. It will do this replacement when
486 * flush_tlb_lines <= active_lines/2^tlb_flushall_shift.
487 * If tlb_flushall_shift is -1, means the replacement will be disabled.
489 s8 __read_mostly tlb_flushall_shift
= -1;
491 void cpu_detect_tlb(struct cpuinfo_x86
*c
)
493 if (this_cpu
->c_detect_tlb
)
494 this_cpu
->c_detect_tlb(c
);
496 printk(KERN_INFO
"Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n"
497 "Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n"
498 "tlb_flushall_shift: %d\n",
499 tlb_lli_4k
[ENTRIES
], tlb_lli_2m
[ENTRIES
],
500 tlb_lli_4m
[ENTRIES
], tlb_lld_4k
[ENTRIES
],
501 tlb_lld_2m
[ENTRIES
], tlb_lld_4m
[ENTRIES
],
502 tlb_lld_1g
[ENTRIES
], tlb_flushall_shift
);
505 void detect_ht(struct cpuinfo_x86
*c
)
508 u32 eax
, ebx
, ecx
, edx
;
509 int index_msb
, core_bits
;
512 if (!cpu_has(c
, X86_FEATURE_HT
))
515 if (cpu_has(c
, X86_FEATURE_CMP_LEGACY
))
518 if (cpu_has(c
, X86_FEATURE_XTOPOLOGY
))
521 cpuid(1, &eax
, &ebx
, &ecx
, &edx
);
523 smp_num_siblings
= (ebx
& 0xff0000) >> 16;
525 if (smp_num_siblings
== 1) {
526 printk_once(KERN_INFO
"CPU0: Hyper-Threading is disabled\n");
530 if (smp_num_siblings
<= 1)
533 index_msb
= get_count_order(smp_num_siblings
);
534 c
->phys_proc_id
= apic
->phys_pkg_id(c
->initial_apicid
, index_msb
);
536 smp_num_siblings
= smp_num_siblings
/ c
->x86_max_cores
;
538 index_msb
= get_count_order(smp_num_siblings
);
540 core_bits
= get_count_order(c
->x86_max_cores
);
542 c
->cpu_core_id
= apic
->phys_pkg_id(c
->initial_apicid
, index_msb
) &
543 ((1 << core_bits
) - 1);
546 if (!printed
&& (c
->x86_max_cores
* smp_num_siblings
) > 1) {
547 printk(KERN_INFO
"CPU: Physical Processor ID: %d\n",
549 printk(KERN_INFO
"CPU: Processor Core ID: %d\n",
556 static void get_cpu_vendor(struct cpuinfo_x86
*c
)
558 char *v
= c
->x86_vendor_id
;
561 for (i
= 0; i
< X86_VENDOR_NUM
; i
++) {
565 if (!strcmp(v
, cpu_devs
[i
]->c_ident
[0]) ||
566 (cpu_devs
[i
]->c_ident
[1] &&
567 !strcmp(v
, cpu_devs
[i
]->c_ident
[1]))) {
569 this_cpu
= cpu_devs
[i
];
570 c
->x86_vendor
= this_cpu
->c_x86_vendor
;
576 "CPU: vendor_id '%s' unknown, using generic init.\n" \
577 "CPU: Your system may be unstable.\n", v
);
579 c
->x86_vendor
= X86_VENDOR_UNKNOWN
;
580 this_cpu
= &default_cpu
;
583 void cpu_detect(struct cpuinfo_x86
*c
)
585 /* Get vendor name */
586 cpuid(0x00000000, (unsigned int *)&c
->cpuid_level
,
587 (unsigned int *)&c
->x86_vendor_id
[0],
588 (unsigned int *)&c
->x86_vendor_id
[8],
589 (unsigned int *)&c
->x86_vendor_id
[4]);
592 /* Intel-defined flags: level 0x00000001 */
593 if (c
->cpuid_level
>= 0x00000001) {
594 u32 junk
, tfms
, cap0
, misc
;
596 cpuid(0x00000001, &tfms
, &misc
, &junk
, &cap0
);
597 c
->x86
= (tfms
>> 8) & 0xf;
598 c
->x86_model
= (tfms
>> 4) & 0xf;
599 c
->x86_mask
= tfms
& 0xf;
602 c
->x86
+= (tfms
>> 20) & 0xff;
604 c
->x86_model
+= ((tfms
>> 16) & 0xf) << 4;
606 if (cap0
& (1<<19)) {
607 c
->x86_clflush_size
= ((misc
>> 8) & 0xff) * 8;
608 c
->x86_cache_alignment
= c
->x86_clflush_size
;
613 void get_cpu_cap(struct cpuinfo_x86
*c
)
618 /* Intel-defined flags: level 0x00000001 */
619 if (c
->cpuid_level
>= 0x00000001) {
620 u32 capability
, excap
;
622 cpuid(0x00000001, &tfms
, &ebx
, &excap
, &capability
);
623 c
->x86_capability
[0] = capability
;
624 c
->x86_capability
[4] = excap
;
627 /* Additional Intel-defined flags: level 0x00000007 */
628 if (c
->cpuid_level
>= 0x00000007) {
629 u32 eax
, ebx
, ecx
, edx
;
631 cpuid_count(0x00000007, 0, &eax
, &ebx
, &ecx
, &edx
);
633 c
->x86_capability
[9] = ebx
;
636 /* AMD-defined flags: level 0x80000001 */
637 xlvl
= cpuid_eax(0x80000000);
638 c
->extended_cpuid_level
= xlvl
;
640 if ((xlvl
& 0xffff0000) == 0x80000000) {
641 if (xlvl
>= 0x80000001) {
642 c
->x86_capability
[1] = cpuid_edx(0x80000001);
643 c
->x86_capability
[6] = cpuid_ecx(0x80000001);
647 if (c
->extended_cpuid_level
>= 0x80000008) {
648 u32 eax
= cpuid_eax(0x80000008);
650 c
->x86_virt_bits
= (eax
>> 8) & 0xff;
651 c
->x86_phys_bits
= eax
& 0xff;
654 else if (cpu_has(c
, X86_FEATURE_PAE
) || cpu_has(c
, X86_FEATURE_PSE36
))
655 c
->x86_phys_bits
= 36;
658 if (c
->extended_cpuid_level
>= 0x80000007)
659 c
->x86_power
= cpuid_edx(0x80000007);
661 init_scattered_cpuid_features(c
);
664 static void identify_cpu_without_cpuid(struct cpuinfo_x86
*c
)
670 * First of all, decide if this is a 486 or higher
671 * It's a 486 if we can modify the AC flag
673 if (flag_is_changeable_p(X86_EFLAGS_AC
))
678 for (i
= 0; i
< X86_VENDOR_NUM
; i
++)
679 if (cpu_devs
[i
] && cpu_devs
[i
]->c_identify
) {
680 c
->x86_vendor_id
[0] = 0;
681 cpu_devs
[i
]->c_identify(c
);
682 if (c
->x86_vendor_id
[0]) {
691 * Do minimum CPU detection early.
692 * Fields really needed: vendor, cpuid_level, family, model, mask,
694 * The others are not touched to avoid unwanted side effects.
696 * WARNING: this function is only called on the BP. Don't add code here
697 * that is supposed to run on all CPUs.
699 static void __init
early_identify_cpu(struct cpuinfo_x86
*c
)
702 c
->x86_clflush_size
= 64;
703 c
->x86_phys_bits
= 36;
704 c
->x86_virt_bits
= 48;
706 c
->x86_clflush_size
= 32;
707 c
->x86_phys_bits
= 32;
708 c
->x86_virt_bits
= 32;
710 c
->x86_cache_alignment
= c
->x86_clflush_size
;
712 memset(&c
->x86_capability
, 0, sizeof c
->x86_capability
);
713 c
->extended_cpuid_level
= 0;
716 identify_cpu_without_cpuid(c
);
718 /* cyrix could have cpuid enabled via c_identify()*/
727 if (this_cpu
->c_early_init
)
728 this_cpu
->c_early_init(c
);
731 filter_cpuid_features(c
, false);
733 if (this_cpu
->c_bsp_init
)
734 this_cpu
->c_bsp_init(c
);
736 setup_force_cpu_cap(X86_FEATURE_ALWAYS
);
739 void __init
early_cpu_init(void)
741 const struct cpu_dev
*const *cdev
;
744 #ifdef CONFIG_PROCESSOR_SELECT
745 printk(KERN_INFO
"KERNEL supported cpus:\n");
748 for (cdev
= __x86_cpu_dev_start
; cdev
< __x86_cpu_dev_end
; cdev
++) {
749 const struct cpu_dev
*cpudev
= *cdev
;
751 if (count
>= X86_VENDOR_NUM
)
753 cpu_devs
[count
] = cpudev
;
756 #ifdef CONFIG_PROCESSOR_SELECT
760 for (j
= 0; j
< 2; j
++) {
761 if (!cpudev
->c_ident
[j
])
763 printk(KERN_INFO
" %s %s\n", cpudev
->c_vendor
,
769 early_identify_cpu(&boot_cpu_data
);
773 * The NOPL instruction is supposed to exist on all CPUs of family >= 6;
774 * unfortunately, that's not true in practice because of early VIA
775 * chips and (more importantly) broken virtualizers that are not easy
776 * to detect. In the latter case it doesn't even *fail* reliably, so
777 * probing for it doesn't even work. Disable it completely on 32-bit
778 * unless we can find a reliable way to detect all the broken cases.
779 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has().
781 static void detect_nopl(struct cpuinfo_x86
*c
)
784 clear_cpu_cap(c
, X86_FEATURE_NOPL
);
786 set_cpu_cap(c
, X86_FEATURE_NOPL
);
790 static void generic_identify(struct cpuinfo_x86
*c
)
792 c
->extended_cpuid_level
= 0;
795 identify_cpu_without_cpuid(c
);
797 /* cyrix could have cpuid enabled via c_identify()*/
807 if (c
->cpuid_level
>= 0x00000001) {
808 c
->initial_apicid
= (cpuid_ebx(1) >> 24) & 0xFF;
810 # ifdef CONFIG_X86_HT
811 c
->apicid
= apic
->phys_pkg_id(c
->initial_apicid
, 0);
813 c
->apicid
= c
->initial_apicid
;
816 c
->phys_proc_id
= c
->initial_apicid
;
819 get_model_name(c
); /* Default name */
825 * This does the hard work of actually picking apart the CPU stuff...
827 static void identify_cpu(struct cpuinfo_x86
*c
)
831 c
->loops_per_jiffy
= loops_per_jiffy
;
832 c
->x86_cache_size
= -1;
833 c
->x86_vendor
= X86_VENDOR_UNKNOWN
;
834 c
->x86_model
= c
->x86_mask
= 0; /* So far unknown... */
835 c
->x86_vendor_id
[0] = '\0'; /* Unset */
836 c
->x86_model_id
[0] = '\0'; /* Unset */
837 c
->x86_max_cores
= 1;
838 c
->x86_coreid_bits
= 0;
840 c
->x86_clflush_size
= 64;
841 c
->x86_phys_bits
= 36;
842 c
->x86_virt_bits
= 48;
844 c
->cpuid_level
= -1; /* CPUID not detected */
845 c
->x86_clflush_size
= 32;
846 c
->x86_phys_bits
= 32;
847 c
->x86_virt_bits
= 32;
849 c
->x86_cache_alignment
= c
->x86_clflush_size
;
850 memset(&c
->x86_capability
, 0, sizeof c
->x86_capability
);
854 if (this_cpu
->c_identify
)
855 this_cpu
->c_identify(c
);
857 /* Clear/Set all flags overriden by options, after probe */
858 for (i
= 0; i
< NCAPINTS
; i
++) {
859 c
->x86_capability
[i
] &= ~cpu_caps_cleared
[i
];
860 c
->x86_capability
[i
] |= cpu_caps_set
[i
];
864 c
->apicid
= apic
->phys_pkg_id(c
->initial_apicid
, 0);
868 * Vendor-specific initialization. In this section we
869 * canonicalize the feature flags, meaning if there are
870 * features a certain CPU supports which CPUID doesn't
871 * tell us, CPUID claiming incorrect flags, or other bugs,
872 * we handle them here.
874 * At the end of this section, c->x86_capability better
875 * indicate the features this CPU genuinely supports!
877 if (this_cpu
->c_init
)
880 /* Disable the PN if appropriate */
881 squash_the_stupid_serial_number(c
);
883 /* Set up SMEP/SMAP */
888 * The vendor-specific functions might have changed features.
889 * Now we do "generic changes."
892 /* Filter out anything that depends on CPUID levels we don't have */
893 filter_cpuid_features(c
, true);
895 /* If the model name is still unset, do table lookup. */
896 if (!c
->x86_model_id
[0]) {
898 p
= table_lookup_model(c
);
900 strcpy(c
->x86_model_id
, p
);
903 sprintf(c
->x86_model_id
, "%02x/%02x",
904 c
->x86
, c
->x86_model
);
915 * Clear/Set all flags overriden by options, need do it
916 * before following smp all cpus cap AND.
918 for (i
= 0; i
< NCAPINTS
; i
++) {
919 c
->x86_capability
[i
] &= ~cpu_caps_cleared
[i
];
920 c
->x86_capability
[i
] |= cpu_caps_set
[i
];
924 * On SMP, boot_cpu_data holds the common feature set between
925 * all CPUs; so make sure that we indicate which features are
926 * common between the CPUs. The first time this routine gets
927 * executed, c == &boot_cpu_data.
929 if (c
!= &boot_cpu_data
) {
930 /* AND the already accumulated flags with these */
931 for (i
= 0; i
< NCAPINTS
; i
++)
932 boot_cpu_data
.x86_capability
[i
] &= c
->x86_capability
[i
];
934 /* OR, i.e. replicate the bug flags */
935 for (i
= NCAPINTS
; i
< NCAPINTS
+ NBUGINTS
; i
++)
936 c
->x86_capability
[i
] |= boot_cpu_data
.x86_capability
[i
];
939 /* Init Machine Check Exception if available. */
942 select_idle_routine(c
);
945 numa_add_cpu(smp_processor_id());
950 static void vgetcpu_set_mode(void)
952 if (cpu_has(&boot_cpu_data
, X86_FEATURE_RDTSCP
))
953 vgetcpu_mode
= VGETCPU_RDTSCP
;
955 vgetcpu_mode
= VGETCPU_LSL
;
958 /* May not be __init: called during resume */
959 static void syscall32_cpu_init(void)
961 /* Load these always in case some future AMD CPU supports
962 SYSENTER from compat mode too. */
963 wrmsrl_safe(MSR_IA32_SYSENTER_CS
, (u64
)__KERNEL_CS
);
964 wrmsrl_safe(MSR_IA32_SYSENTER_ESP
, 0ULL);
965 wrmsrl_safe(MSR_IA32_SYSENTER_EIP
, (u64
)ia32_sysenter_target
);
967 wrmsrl(MSR_CSTAR
, ia32_cstar_target
);
972 void enable_sep_cpu(void)
975 struct tss_struct
*tss
= &per_cpu(init_tss
, cpu
);
977 if (!boot_cpu_has(X86_FEATURE_SEP
)) {
982 tss
->x86_tss
.ss1
= __KERNEL_CS
;
983 tss
->x86_tss
.sp1
= sizeof(struct tss_struct
) + (unsigned long) tss
;
984 wrmsr(MSR_IA32_SYSENTER_CS
, __KERNEL_CS
, 0);
985 wrmsr(MSR_IA32_SYSENTER_ESP
, tss
->x86_tss
.sp1
, 0);
986 wrmsr(MSR_IA32_SYSENTER_EIP
, (unsigned long) ia32_sysenter_target
, 0);
991 void __init
identify_boot_cpu(void)
993 identify_cpu(&boot_cpu_data
);
994 init_amd_e400_c1e_mask();
1001 cpu_detect_tlb(&boot_cpu_data
);
1004 void identify_secondary_cpu(struct cpuinfo_x86
*c
)
1006 BUG_ON(c
== &boot_cpu_data
);
1008 #ifdef CONFIG_X86_32
1019 static const struct msr_range msr_range_array
[] = {
1020 { 0x00000000, 0x00000418},
1021 { 0xc0000000, 0xc000040b},
1022 { 0xc0010000, 0xc0010142},
1023 { 0xc0011000, 0xc001103b},
1026 static void __print_cpu_msr(void)
1028 unsigned index_min
, index_max
;
1033 for (i
= 0; i
< ARRAY_SIZE(msr_range_array
); i
++) {
1034 index_min
= msr_range_array
[i
].min
;
1035 index_max
= msr_range_array
[i
].max
;
1037 for (index
= index_min
; index
< index_max
; index
++) {
1038 if (rdmsrl_safe(index
, &val
))
1040 printk(KERN_INFO
" MSR%08x: %016llx\n", index
, val
);
1045 static int show_msr
;
1047 static __init
int setup_show_msr(char *arg
)
1051 get_option(&arg
, &num
);
1057 __setup("show_msr=", setup_show_msr
);
1059 static __init
int setup_noclflush(char *arg
)
1061 setup_clear_cpu_cap(X86_FEATURE_CLFLUSH
);
1062 setup_clear_cpu_cap(X86_FEATURE_CLFLUSHOPT
);
1065 __setup("noclflush", setup_noclflush
);
1067 void print_cpu_info(struct cpuinfo_x86
*c
)
1069 const char *vendor
= NULL
;
1071 if (c
->x86_vendor
< X86_VENDOR_NUM
) {
1072 vendor
= this_cpu
->c_vendor
;
1074 if (c
->cpuid_level
>= 0)
1075 vendor
= c
->x86_vendor_id
;
1078 if (vendor
&& !strstr(c
->x86_model_id
, vendor
))
1079 printk(KERN_CONT
"%s ", vendor
);
1081 if (c
->x86_model_id
[0])
1082 printk(KERN_CONT
"%s", strim(c
->x86_model_id
));
1084 printk(KERN_CONT
"%d86", c
->x86
);
1086 printk(KERN_CONT
" (fam: %02x, model: %02x", c
->x86
, c
->x86_model
);
1088 if (c
->x86_mask
|| c
->cpuid_level
>= 0)
1089 printk(KERN_CONT
", stepping: %02x)\n", c
->x86_mask
);
1091 printk(KERN_CONT
")\n");
1096 void print_cpu_msr(struct cpuinfo_x86
*c
)
1098 if (c
->cpu_index
< show_msr
)
1102 static __init
int setup_disablecpuid(char *arg
)
1106 if (get_option(&arg
, &bit
) && bit
< NCAPINTS
*32)
1107 setup_clear_cpu_cap(bit
);
1113 __setup("clearcpuid=", setup_disablecpuid
);
1115 DEFINE_PER_CPU(unsigned long, kernel_stack
) =
1116 (unsigned long)&init_thread_union
- KERNEL_STACK_OFFSET
+ THREAD_SIZE
;
1117 EXPORT_PER_CPU_SYMBOL(kernel_stack
);
1119 #ifdef CONFIG_X86_64
1120 struct desc_ptr idt_descr
= { NR_VECTORS
* 16 - 1, (unsigned long) idt_table
};
1121 struct desc_ptr debug_idt_descr
= { NR_VECTORS
* 16 - 1,
1122 (unsigned long) debug_idt_table
};
1124 DEFINE_PER_CPU_FIRST(union irq_stack_union
,
1125 irq_stack_union
) __aligned(PAGE_SIZE
) __visible
;
1128 * The following four percpu variables are hot. Align current_task to
1129 * cacheline size such that all four fall in the same cacheline.
1131 DEFINE_PER_CPU(struct task_struct
*, current_task
) ____cacheline_aligned
=
1133 EXPORT_PER_CPU_SYMBOL(current_task
);
1135 DEFINE_PER_CPU(char *, irq_stack_ptr
) =
1136 init_per_cpu_var(irq_stack_union
.irq_stack
) + IRQ_STACK_SIZE
- 64;
1138 DEFINE_PER_CPU(unsigned int, irq_count
) __visible
= -1;
1140 DEFINE_PER_CPU(int, __preempt_count
) = INIT_PREEMPT_COUNT
;
1141 EXPORT_PER_CPU_SYMBOL(__preempt_count
);
1143 DEFINE_PER_CPU(struct task_struct
*, fpu_owner_task
);
1146 * Special IST stacks which the CPU switches to when it calls
1147 * an IST-marked descriptor entry. Up to 7 stacks (hardware
1148 * limit), all of them are 4K, except the debug stack which
1151 static const unsigned int exception_stack_sizes
[N_EXCEPTION_STACKS
] = {
1152 [0 ... N_EXCEPTION_STACKS
- 1] = EXCEPTION_STKSZ
,
1153 [DEBUG_STACK
- 1] = DEBUG_STKSZ
1156 static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks
1157 [(N_EXCEPTION_STACKS
- 1) * EXCEPTION_STKSZ
+ DEBUG_STKSZ
]);
1159 /* May not be marked __init: used by software suspend */
1160 void syscall_init(void)
1163 * LSTAR and STAR live in a bit strange symbiosis.
1164 * They both write to the same internal register. STAR allows to
1165 * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip.
1167 wrmsrl(MSR_STAR
, ((u64
)__USER32_CS
)<<48 | ((u64
)__KERNEL_CS
)<<32);
1168 wrmsrl(MSR_LSTAR
, system_call
);
1169 wrmsrl(MSR_CSTAR
, ignore_sysret
);
1171 #ifdef CONFIG_IA32_EMULATION
1172 syscall32_cpu_init();
1175 /* Flags to clear on syscall */
1176 wrmsrl(MSR_SYSCALL_MASK
,
1177 X86_EFLAGS_TF
|X86_EFLAGS_DF
|X86_EFLAGS_IF
|
1178 X86_EFLAGS_IOPL
|X86_EFLAGS_AC
);
1182 * Copies of the original ist values from the tss are only accessed during
1183 * debugging, no special alignment required.
1185 DEFINE_PER_CPU(struct orig_ist
, orig_ist
);
1187 static DEFINE_PER_CPU(unsigned long, debug_stack_addr
);
1188 DEFINE_PER_CPU(int, debug_stack_usage
);
1190 int is_debug_stack(unsigned long addr
)
1192 return __get_cpu_var(debug_stack_usage
) ||
1193 (addr
<= __get_cpu_var(debug_stack_addr
) &&
1194 addr
> (__get_cpu_var(debug_stack_addr
) - DEBUG_STKSZ
));
1197 DEFINE_PER_CPU(u32
, debug_idt_ctr
);
1199 void debug_stack_set_zero(void)
1201 this_cpu_inc(debug_idt_ctr
);
1205 void debug_stack_reset(void)
1207 if (WARN_ON(!this_cpu_read(debug_idt_ctr
)))
1209 if (this_cpu_dec_return(debug_idt_ctr
) == 0)
1213 #else /* CONFIG_X86_64 */
1215 DEFINE_PER_CPU(struct task_struct
*, current_task
) = &init_task
;
1216 EXPORT_PER_CPU_SYMBOL(current_task
);
1217 DEFINE_PER_CPU(int, __preempt_count
) = INIT_PREEMPT_COUNT
;
1218 EXPORT_PER_CPU_SYMBOL(__preempt_count
);
1219 DEFINE_PER_CPU(struct task_struct
*, fpu_owner_task
);
1221 #ifdef CONFIG_CC_STACKPROTECTOR
1222 DEFINE_PER_CPU_ALIGNED(struct stack_canary
, stack_canary
);
1225 #endif /* CONFIG_X86_64 */
1228 * Clear all 6 debug registers:
1230 static void clear_all_debug_regs(void)
1234 for (i
= 0; i
< 8; i
++) {
1235 /* Ignore db4, db5 */
1236 if ((i
== 4) || (i
== 5))
1245 * Restore debug regs if using kgdbwait and you have a kernel debugger
1246 * connection established.
1248 static void dbg_restore_debug_regs(void)
1250 if (unlikely(kgdb_connected
&& arch_kgdb_ops
.correct_hw_break
))
1251 arch_kgdb_ops
.correct_hw_break();
1253 #else /* ! CONFIG_KGDB */
1254 #define dbg_restore_debug_regs()
1255 #endif /* ! CONFIG_KGDB */
1258 * cpu_init() initializes state that is per-CPU. Some data is already
1259 * initialized (naturally) in the bootstrap process, such as the GDT
1260 * and IDT. We reload them nevertheless, this function acts as a
1261 * 'CPU state barrier', nothing should get across.
1262 * A lot of state is already set up in PDA init for 64 bit
1264 #ifdef CONFIG_X86_64
1268 struct orig_ist
*oist
;
1269 struct task_struct
*me
;
1270 struct tss_struct
*t
;
1276 * Load microcode on this cpu if a valid microcode is available.
1277 * This is early microcode loading procedure.
1281 cpu
= stack_smp_processor_id();
1282 t
= &per_cpu(init_tss
, cpu
);
1283 oist
= &per_cpu(orig_ist
, cpu
);
1286 if (this_cpu_read(numa_node
) == 0 &&
1287 early_cpu_to_node(cpu
) != NUMA_NO_NODE
)
1288 set_numa_node(early_cpu_to_node(cpu
));
1293 if (cpumask_test_and_set_cpu(cpu
, cpu_initialized_mask
))
1294 panic("CPU#%d already initialized!\n", cpu
);
1296 pr_debug("Initializing CPU#%d\n", cpu
);
1298 clear_in_cr4(X86_CR4_VME
|X86_CR4_PVI
|X86_CR4_TSD
|X86_CR4_DE
);
1301 * Initialize the per-CPU GDT with the boot GDT,
1302 * and set up the GDT descriptor:
1305 switch_to_new_gdt(cpu
);
1310 memset(me
->thread
.tls_array
, 0, GDT_ENTRY_TLS_ENTRIES
* 8);
1313 wrmsrl(MSR_FS_BASE
, 0);
1314 wrmsrl(MSR_KERNEL_GS_BASE
, 0);
1321 * set up and load the per-CPU TSS
1323 if (!oist
->ist
[0]) {
1324 char *estacks
= per_cpu(exception_stacks
, cpu
);
1326 for (v
= 0; v
< N_EXCEPTION_STACKS
; v
++) {
1327 estacks
+= exception_stack_sizes
[v
];
1328 oist
->ist
[v
] = t
->x86_tss
.ist
[v
] =
1329 (unsigned long)estacks
;
1330 if (v
== DEBUG_STACK
-1)
1331 per_cpu(debug_stack_addr
, cpu
) = (unsigned long)estacks
;
1335 t
->x86_tss
.io_bitmap_base
= offsetof(struct tss_struct
, io_bitmap
);
1338 * <= is required because the CPU will access up to
1339 * 8 bits beyond the end of the IO permission bitmap.
1341 for (i
= 0; i
<= IO_BITMAP_LONGS
; i
++)
1342 t
->io_bitmap
[i
] = ~0UL;
1344 atomic_inc(&init_mm
.mm_count
);
1345 me
->active_mm
= &init_mm
;
1347 enter_lazy_tlb(&init_mm
, me
);
1349 load_sp0(t
, ¤t
->thread
);
1350 set_tss_desc(cpu
, t
);
1352 load_LDT(&init_mm
.context
);
1354 clear_all_debug_regs();
1355 dbg_restore_debug_regs();
1367 int cpu
= smp_processor_id();
1368 struct task_struct
*curr
= current
;
1369 struct tss_struct
*t
= &per_cpu(init_tss
, cpu
);
1370 struct thread_struct
*thread
= &curr
->thread
;
1372 show_ucode_info_early();
1374 if (cpumask_test_and_set_cpu(cpu
, cpu_initialized_mask
)) {
1375 printk(KERN_WARNING
"CPU#%d already initialized!\n", cpu
);
1380 printk(KERN_INFO
"Initializing CPU#%d\n", cpu
);
1382 if (cpu_has_vme
|| cpu_has_tsc
|| cpu_has_de
)
1383 clear_in_cr4(X86_CR4_VME
|X86_CR4_PVI
|X86_CR4_TSD
|X86_CR4_DE
);
1386 switch_to_new_gdt(cpu
);
1389 * Set up and load the per-CPU TSS and LDT
1391 atomic_inc(&init_mm
.mm_count
);
1392 curr
->active_mm
= &init_mm
;
1394 enter_lazy_tlb(&init_mm
, curr
);
1396 load_sp0(t
, thread
);
1397 set_tss_desc(cpu
, t
);
1399 load_LDT(&init_mm
.context
);
1401 t
->x86_tss
.io_bitmap_base
= offsetof(struct tss_struct
, io_bitmap
);
1403 #ifdef CONFIG_DOUBLEFAULT
1404 /* Set up doublefault TSS pointer in the GDT */
1405 __set_tss_desc(cpu
, GDT_ENTRY_DOUBLEFAULT_TSS
, &doublefault_tss
);
1408 clear_all_debug_regs();
1409 dbg_restore_debug_regs();
1415 #ifdef CONFIG_X86_DEBUG_STATIC_CPU_HAS
1416 void warn_pre_alternatives(void)
1418 WARN(1, "You're using static_cpu_has before alternatives have run!\n");
1420 EXPORT_SYMBOL_GPL(warn_pre_alternatives
);
1423 inline bool __static_cpu_has_safe(u16 bit
)
1425 return boot_cpu_has(bit
);
1427 EXPORT_SYMBOL_GPL(__static_cpu_has_safe
);