1 #include <linux/bootmem.h>
2 #include <linux/linkage.h>
3 #include <linux/bitops.h>
4 #include <linux/kernel.h>
5 #include <linux/module.h>
6 #include <linux/percpu.h>
7 #include <linux/string.h>
8 #include <linux/ctype.h>
9 #include <linux/delay.h>
10 #include <linux/sched.h>
11 #include <linux/init.h>
12 #include <linux/kprobes.h>
13 #include <linux/kgdb.h>
14 #include <linux/smp.h>
16 #include <linux/syscore_ops.h>
18 #include <asm/stackprotector.h>
19 #include <asm/perf_event.h>
20 #include <asm/mmu_context.h>
21 #include <asm/archrandom.h>
22 #include <asm/hypervisor.h>
23 #include <asm/processor.h>
24 #include <asm/tlbflush.h>
25 #include <asm/debugreg.h>
26 #include <asm/sections.h>
27 #include <asm/vsyscall.h>
28 #include <linux/topology.h>
29 #include <linux/cpumask.h>
30 #include <asm/pgtable.h>
31 #include <linux/atomic.h>
32 #include <asm/proto.h>
33 #include <asm/setup.h>
36 #include <asm/fpu/internal.h>
38 #include <linux/numa.h>
44 #include <asm/microcode.h>
45 #include <asm/microcode_intel.h>
47 #ifdef CONFIG_X86_LOCAL_APIC
48 #include <asm/uv/uv.h>
53 /* all of these masks are initialized in setup_cpu_local_masks() */
54 cpumask_var_t cpu_initialized_mask
;
55 cpumask_var_t cpu_callout_mask
;
56 cpumask_var_t cpu_callin_mask
;
58 /* representing cpus for which sibling maps can be computed */
59 cpumask_var_t cpu_sibling_setup_mask
;
61 /* correctly size the local cpu masks */
62 void __init
setup_cpu_local_masks(void)
64 alloc_bootmem_cpumask_var(&cpu_initialized_mask
);
65 alloc_bootmem_cpumask_var(&cpu_callin_mask
);
66 alloc_bootmem_cpumask_var(&cpu_callout_mask
);
67 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask
);
70 static void default_init(struct cpuinfo_x86
*c
)
73 cpu_detect_cache_sizes(c
);
75 /* Not much we can do here... */
76 /* Check if at least it has cpuid */
77 if (c
->cpuid_level
== -1) {
78 /* No cpuid. It must be an ancient CPU */
80 strcpy(c
->x86_model_id
, "486");
82 strcpy(c
->x86_model_id
, "386");
87 static const struct cpu_dev default_cpu
= {
88 .c_init
= default_init
,
89 .c_vendor
= "Unknown",
90 .c_x86_vendor
= X86_VENDOR_UNKNOWN
,
93 static const struct cpu_dev
*this_cpu
= &default_cpu
;
95 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page
, gdt_page
) = { .gdt
= {
98 * We need valid kernel segments for data and code in long mode too
99 * IRET will check the segment types kkeil 2000/10/28
100 * Also sysret mandates a special GDT layout
102 * TLS descriptors are currently at a different place compared to i386.
103 * Hopefully nobody expects them at a fixed place (Wine?)
105 [GDT_ENTRY_KERNEL32_CS
] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff),
106 [GDT_ENTRY_KERNEL_CS
] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff),
107 [GDT_ENTRY_KERNEL_DS
] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff),
108 [GDT_ENTRY_DEFAULT_USER32_CS
] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff),
109 [GDT_ENTRY_DEFAULT_USER_DS
] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff),
110 [GDT_ENTRY_DEFAULT_USER_CS
] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff),
112 [GDT_ENTRY_KERNEL_CS
] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff),
113 [GDT_ENTRY_KERNEL_DS
] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
114 [GDT_ENTRY_DEFAULT_USER_CS
] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff),
115 [GDT_ENTRY_DEFAULT_USER_DS
] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff),
117 * Segments used for calling PnP BIOS have byte granularity.
118 * They code segments and data segments have fixed 64k limits,
119 * the transfer segment sizes are set at run time.
122 [GDT_ENTRY_PNPBIOS_CS32
] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
124 [GDT_ENTRY_PNPBIOS_CS16
] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
126 [GDT_ENTRY_PNPBIOS_DS
] = GDT_ENTRY_INIT(0x0092, 0, 0xffff),
128 [GDT_ENTRY_PNPBIOS_TS1
] = GDT_ENTRY_INIT(0x0092, 0, 0),
130 [GDT_ENTRY_PNPBIOS_TS2
] = GDT_ENTRY_INIT(0x0092, 0, 0),
132 * The APM segments have byte granularity and their bases
133 * are set at run time. All have 64k limits.
136 [GDT_ENTRY_APMBIOS_BASE
] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
138 [GDT_ENTRY_APMBIOS_BASE
+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
140 [GDT_ENTRY_APMBIOS_BASE
+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff),
142 [GDT_ENTRY_ESPFIX_SS
] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
143 [GDT_ENTRY_PERCPU
] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
144 GDT_STACK_CANARY_INIT
147 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page
);
149 static int __init
x86_mpx_setup(char *s
)
151 /* require an exact match without trailing characters */
155 /* do not emit a message if the feature is not present */
156 if (!boot_cpu_has(X86_FEATURE_MPX
))
159 setup_clear_cpu_cap(X86_FEATURE_MPX
);
160 pr_info("nompx: Intel Memory Protection Extensions (MPX) disabled\n");
163 __setup("nompx", x86_mpx_setup
);
166 static int cachesize_override
= -1;
167 static int disable_x86_serial_nr
= 1;
169 static int __init
cachesize_setup(char *str
)
171 get_option(&str
, &cachesize_override
);
174 __setup("cachesize=", cachesize_setup
);
176 static int __init
x86_sep_setup(char *s
)
178 setup_clear_cpu_cap(X86_FEATURE_SEP
);
181 __setup("nosep", x86_sep_setup
);
183 /* Standard macro to see if a specific flag is changeable */
184 static inline int flag_is_changeable_p(u32 flag
)
189 * Cyrix and IDT cpus allow disabling of CPUID
190 * so the code below may return different results
191 * when it is executed before and after enabling
192 * the CPUID. Add "volatile" to not allow gcc to
193 * optimize the subsequent calls to this function.
195 asm volatile ("pushfl \n\t"
206 : "=&r" (f1
), "=&r" (f2
)
209 return ((f1
^f2
) & flag
) != 0;
212 /* Probe for the CPUID instruction */
213 int have_cpuid_p(void)
215 return flag_is_changeable_p(X86_EFLAGS_ID
);
218 static void squash_the_stupid_serial_number(struct cpuinfo_x86
*c
)
220 unsigned long lo
, hi
;
222 if (!cpu_has(c
, X86_FEATURE_PN
) || !disable_x86_serial_nr
)
225 /* Disable processor serial number: */
227 rdmsr(MSR_IA32_BBL_CR_CTL
, lo
, hi
);
229 wrmsr(MSR_IA32_BBL_CR_CTL
, lo
, hi
);
231 pr_notice("CPU serial number disabled.\n");
232 clear_cpu_cap(c
, X86_FEATURE_PN
);
234 /* Disabling the serial number may affect the cpuid level */
235 c
->cpuid_level
= cpuid_eax(0);
238 static int __init
x86_serial_nr_setup(char *s
)
240 disable_x86_serial_nr
= 0;
243 __setup("serialnumber", x86_serial_nr_setup
);
245 static inline int flag_is_changeable_p(u32 flag
)
249 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86
*c
)
254 static __init
int setup_disable_smep(char *arg
)
256 setup_clear_cpu_cap(X86_FEATURE_SMEP
);
259 __setup("nosmep", setup_disable_smep
);
261 static __always_inline
void setup_smep(struct cpuinfo_x86
*c
)
263 if (cpu_has(c
, X86_FEATURE_SMEP
))
264 cr4_set_bits(X86_CR4_SMEP
);
267 static __init
int setup_disable_smap(char *arg
)
269 setup_clear_cpu_cap(X86_FEATURE_SMAP
);
272 __setup("nosmap", setup_disable_smap
);
274 static __always_inline
void setup_smap(struct cpuinfo_x86
*c
)
276 unsigned long eflags
= native_save_fl();
278 /* This should have been cleared long ago */
279 BUG_ON(eflags
& X86_EFLAGS_AC
);
281 if (cpu_has(c
, X86_FEATURE_SMAP
)) {
282 #ifdef CONFIG_X86_SMAP
283 cr4_set_bits(X86_CR4_SMAP
);
285 cr4_clear_bits(X86_CR4_SMAP
);
291 * Some CPU features depend on higher CPUID levels, which may not always
292 * be available due to CPUID level capping or broken virtualization
293 * software. Add those features to this table to auto-disable them.
295 struct cpuid_dependent_feature
{
300 static const struct cpuid_dependent_feature
301 cpuid_dependent_features
[] = {
302 { X86_FEATURE_MWAIT
, 0x00000005 },
303 { X86_FEATURE_DCA
, 0x00000009 },
304 { X86_FEATURE_XSAVE
, 0x0000000d },
308 static void filter_cpuid_features(struct cpuinfo_x86
*c
, bool warn
)
310 const struct cpuid_dependent_feature
*df
;
312 for (df
= cpuid_dependent_features
; df
->feature
; df
++) {
314 if (!cpu_has(c
, df
->feature
))
317 * Note: cpuid_level is set to -1 if unavailable, but
318 * extended_extended_level is set to 0 if unavailable
319 * and the legitimate extended levels are all negative
320 * when signed; hence the weird messing around with
323 if (!((s32
)df
->level
< 0 ?
324 (u32
)df
->level
> (u32
)c
->extended_cpuid_level
:
325 (s32
)df
->level
> (s32
)c
->cpuid_level
))
328 clear_cpu_cap(c
, df
->feature
);
332 pr_warn("CPU: CPU feature " X86_CAP_FMT
" disabled, no CPUID level 0x%x\n",
333 x86_cap_flag(df
->feature
), df
->level
);
338 * Naming convention should be: <Name> [(<Codename>)]
339 * This table only is used unless init_<vendor>() below doesn't set it;
340 * in particular, if CPUID levels 0x80000002..4 are supported, this
344 /* Look up CPU names by table lookup. */
345 static const char *table_lookup_model(struct cpuinfo_x86
*c
)
348 const struct legacy_cpu_model_info
*info
;
350 if (c
->x86_model
>= 16)
351 return NULL
; /* Range check */
356 info
= this_cpu
->legacy_models
;
358 while (info
->family
) {
359 if (info
->family
== c
->x86
)
360 return info
->model_names
[c
->x86_model
];
364 return NULL
; /* Not found */
367 __u32 cpu_caps_cleared
[NCAPINTS
];
368 __u32 cpu_caps_set
[NCAPINTS
];
370 void load_percpu_segment(int cpu
)
373 loadsegment(fs
, __KERNEL_PERCPU
);
376 wrmsrl(MSR_GS_BASE
, (unsigned long)per_cpu(irq_stack_union
.gs_base
, cpu
));
378 load_stack_canary_segment();
382 * Current gdt points %fs at the "master" per-cpu area: after this,
383 * it's on the real one.
385 void switch_to_new_gdt(int cpu
)
387 struct desc_ptr gdt_descr
;
389 gdt_descr
.address
= (long)get_cpu_gdt_table(cpu
);
390 gdt_descr
.size
= GDT_SIZE
- 1;
391 load_gdt(&gdt_descr
);
392 /* Reload the per-cpu base */
394 load_percpu_segment(cpu
);
397 static const struct cpu_dev
*cpu_devs
[X86_VENDOR_NUM
] = {};
399 static void get_model_name(struct cpuinfo_x86
*c
)
404 if (c
->extended_cpuid_level
< 0x80000004)
407 v
= (unsigned int *)c
->x86_model_id
;
408 cpuid(0x80000002, &v
[0], &v
[1], &v
[2], &v
[3]);
409 cpuid(0x80000003, &v
[4], &v
[5], &v
[6], &v
[7]);
410 cpuid(0x80000004, &v
[8], &v
[9], &v
[10], &v
[11]);
411 c
->x86_model_id
[48] = 0;
413 /* Trim whitespace */
414 p
= q
= s
= &c
->x86_model_id
[0];
420 /* Note the last non-whitespace index */
430 void cpu_detect_cache_sizes(struct cpuinfo_x86
*c
)
432 unsigned int n
, dummy
, ebx
, ecx
, edx
, l2size
;
434 n
= c
->extended_cpuid_level
;
436 if (n
>= 0x80000005) {
437 cpuid(0x80000005, &dummy
, &ebx
, &ecx
, &edx
);
438 c
->x86_cache_size
= (ecx
>>24) + (edx
>>24);
440 /* On K8 L1 TLB is inclusive, so don't count it */
445 if (n
< 0x80000006) /* Some chips just has a large L1. */
448 cpuid(0x80000006, &dummy
, &ebx
, &ecx
, &edx
);
452 c
->x86_tlbsize
+= ((ebx
>> 16) & 0xfff) + (ebx
& 0xfff);
454 /* do processor-specific cache resizing */
455 if (this_cpu
->legacy_cache_size
)
456 l2size
= this_cpu
->legacy_cache_size(c
, l2size
);
458 /* Allow user to override all this if necessary. */
459 if (cachesize_override
!= -1)
460 l2size
= cachesize_override
;
463 return; /* Again, no L2 cache is possible */
466 c
->x86_cache_size
= l2size
;
469 u16 __read_mostly tlb_lli_4k
[NR_INFO
];
470 u16 __read_mostly tlb_lli_2m
[NR_INFO
];
471 u16 __read_mostly tlb_lli_4m
[NR_INFO
];
472 u16 __read_mostly tlb_lld_4k
[NR_INFO
];
473 u16 __read_mostly tlb_lld_2m
[NR_INFO
];
474 u16 __read_mostly tlb_lld_4m
[NR_INFO
];
475 u16 __read_mostly tlb_lld_1g
[NR_INFO
];
477 static void cpu_detect_tlb(struct cpuinfo_x86
*c
)
479 if (this_cpu
->c_detect_tlb
)
480 this_cpu
->c_detect_tlb(c
);
482 pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n",
483 tlb_lli_4k
[ENTRIES
], tlb_lli_2m
[ENTRIES
],
484 tlb_lli_4m
[ENTRIES
]);
486 pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n",
487 tlb_lld_4k
[ENTRIES
], tlb_lld_2m
[ENTRIES
],
488 tlb_lld_4m
[ENTRIES
], tlb_lld_1g
[ENTRIES
]);
491 void detect_ht(struct cpuinfo_x86
*c
)
494 u32 eax
, ebx
, ecx
, edx
;
495 int index_msb
, core_bits
;
498 if (!cpu_has(c
, X86_FEATURE_HT
))
501 if (cpu_has(c
, X86_FEATURE_CMP_LEGACY
))
504 if (cpu_has(c
, X86_FEATURE_XTOPOLOGY
))
507 cpuid(1, &eax
, &ebx
, &ecx
, &edx
);
509 smp_num_siblings
= (ebx
& 0xff0000) >> 16;
511 if (smp_num_siblings
== 1) {
512 pr_info_once("CPU0: Hyper-Threading is disabled\n");
516 if (smp_num_siblings
<= 1)
519 index_msb
= get_count_order(smp_num_siblings
);
520 c
->phys_proc_id
= apic
->phys_pkg_id(c
->initial_apicid
, index_msb
);
522 smp_num_siblings
= smp_num_siblings
/ c
->x86_max_cores
;
524 index_msb
= get_count_order(smp_num_siblings
);
526 core_bits
= get_count_order(c
->x86_max_cores
);
528 c
->cpu_core_id
= apic
->phys_pkg_id(c
->initial_apicid
, index_msb
) &
529 ((1 << core_bits
) - 1);
532 if (!printed
&& (c
->x86_max_cores
* smp_num_siblings
) > 1) {
533 pr_info("CPU: Physical Processor ID: %d\n",
535 pr_info("CPU: Processor Core ID: %d\n",
542 static void get_cpu_vendor(struct cpuinfo_x86
*c
)
544 char *v
= c
->x86_vendor_id
;
547 for (i
= 0; i
< X86_VENDOR_NUM
; i
++) {
551 if (!strcmp(v
, cpu_devs
[i
]->c_ident
[0]) ||
552 (cpu_devs
[i
]->c_ident
[1] &&
553 !strcmp(v
, cpu_devs
[i
]->c_ident
[1]))) {
555 this_cpu
= cpu_devs
[i
];
556 c
->x86_vendor
= this_cpu
->c_x86_vendor
;
561 pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \
562 "CPU: Your system may be unstable.\n", v
);
564 c
->x86_vendor
= X86_VENDOR_UNKNOWN
;
565 this_cpu
= &default_cpu
;
568 void cpu_detect(struct cpuinfo_x86
*c
)
570 /* Get vendor name */
571 cpuid(0x00000000, (unsigned int *)&c
->cpuid_level
,
572 (unsigned int *)&c
->x86_vendor_id
[0],
573 (unsigned int *)&c
->x86_vendor_id
[8],
574 (unsigned int *)&c
->x86_vendor_id
[4]);
577 /* Intel-defined flags: level 0x00000001 */
578 if (c
->cpuid_level
>= 0x00000001) {
579 u32 junk
, tfms
, cap0
, misc
;
581 cpuid(0x00000001, &tfms
, &misc
, &junk
, &cap0
);
582 c
->x86
= x86_family(tfms
);
583 c
->x86_model
= x86_model(tfms
);
584 c
->x86_mask
= x86_stepping(tfms
);
586 if (cap0
& (1<<19)) {
587 c
->x86_clflush_size
= ((misc
>> 8) & 0xff) * 8;
588 c
->x86_cache_alignment
= c
->x86_clflush_size
;
593 void get_cpu_cap(struct cpuinfo_x86
*c
)
595 u32 eax
, ebx
, ecx
, edx
;
597 /* Intel-defined flags: level 0x00000001 */
598 if (c
->cpuid_level
>= 0x00000001) {
599 cpuid(0x00000001, &eax
, &ebx
, &ecx
, &edx
);
601 c
->x86_capability
[CPUID_1_ECX
] = ecx
;
602 c
->x86_capability
[CPUID_1_EDX
] = edx
;
605 /* Additional Intel-defined flags: level 0x00000007 */
606 if (c
->cpuid_level
>= 0x00000007) {
607 cpuid_count(0x00000007, 0, &eax
, &ebx
, &ecx
, &edx
);
609 c
->x86_capability
[CPUID_7_0_EBX
] = ebx
;
611 c
->x86_capability
[CPUID_6_EAX
] = cpuid_eax(0x00000006);
614 /* Extended state features: level 0x0000000d */
615 if (c
->cpuid_level
>= 0x0000000d) {
616 cpuid_count(0x0000000d, 1, &eax
, &ebx
, &ecx
, &edx
);
618 c
->x86_capability
[CPUID_D_1_EAX
] = eax
;
621 /* Additional Intel-defined flags: level 0x0000000F */
622 if (c
->cpuid_level
>= 0x0000000F) {
624 /* QoS sub-leaf, EAX=0Fh, ECX=0 */
625 cpuid_count(0x0000000F, 0, &eax
, &ebx
, &ecx
, &edx
);
626 c
->x86_capability
[CPUID_F_0_EDX
] = edx
;
628 if (cpu_has(c
, X86_FEATURE_CQM_LLC
)) {
629 /* will be overridden if occupancy monitoring exists */
630 c
->x86_cache_max_rmid
= ebx
;
632 /* QoS sub-leaf, EAX=0Fh, ECX=1 */
633 cpuid_count(0x0000000F, 1, &eax
, &ebx
, &ecx
, &edx
);
634 c
->x86_capability
[CPUID_F_1_EDX
] = edx
;
636 if (cpu_has(c
, X86_FEATURE_CQM_OCCUP_LLC
)) {
637 c
->x86_cache_max_rmid
= ecx
;
638 c
->x86_cache_occ_scale
= ebx
;
641 c
->x86_cache_max_rmid
= -1;
642 c
->x86_cache_occ_scale
= -1;
646 /* AMD-defined flags: level 0x80000001 */
647 eax
= cpuid_eax(0x80000000);
648 c
->extended_cpuid_level
= eax
;
650 if ((eax
& 0xffff0000) == 0x80000000) {
651 if (eax
>= 0x80000001) {
652 cpuid(0x80000001, &eax
, &ebx
, &ecx
, &edx
);
654 c
->x86_capability
[CPUID_8000_0001_ECX
] = ecx
;
655 c
->x86_capability
[CPUID_8000_0001_EDX
] = edx
;
659 if (c
->extended_cpuid_level
>= 0x80000008) {
660 cpuid(0x80000008, &eax
, &ebx
, &ecx
, &edx
);
662 c
->x86_virt_bits
= (eax
>> 8) & 0xff;
663 c
->x86_phys_bits
= eax
& 0xff;
664 c
->x86_capability
[CPUID_8000_0008_EBX
] = ebx
;
667 else if (cpu_has(c
, X86_FEATURE_PAE
) || cpu_has(c
, X86_FEATURE_PSE36
))
668 c
->x86_phys_bits
= 36;
671 if (c
->extended_cpuid_level
>= 0x80000007)
672 c
->x86_power
= cpuid_edx(0x80000007);
674 if (c
->extended_cpuid_level
>= 0x8000000a)
675 c
->x86_capability
[CPUID_8000_000A_EDX
] = cpuid_edx(0x8000000a);
677 init_scattered_cpuid_features(c
);
680 static void identify_cpu_without_cpuid(struct cpuinfo_x86
*c
)
686 * First of all, decide if this is a 486 or higher
687 * It's a 486 if we can modify the AC flag
689 if (flag_is_changeable_p(X86_EFLAGS_AC
))
694 for (i
= 0; i
< X86_VENDOR_NUM
; i
++)
695 if (cpu_devs
[i
] && cpu_devs
[i
]->c_identify
) {
696 c
->x86_vendor_id
[0] = 0;
697 cpu_devs
[i
]->c_identify(c
);
698 if (c
->x86_vendor_id
[0]) {
707 * Do minimum CPU detection early.
708 * Fields really needed: vendor, cpuid_level, family, model, mask,
710 * The others are not touched to avoid unwanted side effects.
712 * WARNING: this function is only called on the BP. Don't add code here
713 * that is supposed to run on all CPUs.
715 static void __init
early_identify_cpu(struct cpuinfo_x86
*c
)
718 c
->x86_clflush_size
= 64;
719 c
->x86_phys_bits
= 36;
720 c
->x86_virt_bits
= 48;
722 c
->x86_clflush_size
= 32;
723 c
->x86_phys_bits
= 32;
724 c
->x86_virt_bits
= 32;
726 c
->x86_cache_alignment
= c
->x86_clflush_size
;
728 memset(&c
->x86_capability
, 0, sizeof c
->x86_capability
);
729 c
->extended_cpuid_level
= 0;
732 identify_cpu_without_cpuid(c
);
734 /* cyrix could have cpuid enabled via c_identify()*/
742 if (this_cpu
->c_early_init
)
743 this_cpu
->c_early_init(c
);
746 filter_cpuid_features(c
, false);
748 if (this_cpu
->c_bsp_init
)
749 this_cpu
->c_bsp_init(c
);
751 setup_force_cpu_cap(X86_FEATURE_ALWAYS
);
755 void __init
early_cpu_init(void)
757 const struct cpu_dev
*const *cdev
;
760 #ifdef CONFIG_PROCESSOR_SELECT
761 pr_info("KERNEL supported cpus:\n");
764 for (cdev
= __x86_cpu_dev_start
; cdev
< __x86_cpu_dev_end
; cdev
++) {
765 const struct cpu_dev
*cpudev
= *cdev
;
767 if (count
>= X86_VENDOR_NUM
)
769 cpu_devs
[count
] = cpudev
;
772 #ifdef CONFIG_PROCESSOR_SELECT
776 for (j
= 0; j
< 2; j
++) {
777 if (!cpudev
->c_ident
[j
])
779 pr_info(" %s %s\n", cpudev
->c_vendor
,
785 early_identify_cpu(&boot_cpu_data
);
789 * The NOPL instruction is supposed to exist on all CPUs of family >= 6;
790 * unfortunately, that's not true in practice because of early VIA
791 * chips and (more importantly) broken virtualizers that are not easy
792 * to detect. In the latter case it doesn't even *fail* reliably, so
793 * probing for it doesn't even work. Disable it completely on 32-bit
794 * unless we can find a reliable way to detect all the broken cases.
795 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has().
797 static void detect_nopl(struct cpuinfo_x86
*c
)
800 clear_cpu_cap(c
, X86_FEATURE_NOPL
);
802 set_cpu_cap(c
, X86_FEATURE_NOPL
);
806 static void generic_identify(struct cpuinfo_x86
*c
)
808 c
->extended_cpuid_level
= 0;
811 identify_cpu_without_cpuid(c
);
813 /* cyrix could have cpuid enabled via c_identify()*/
823 if (c
->cpuid_level
>= 0x00000001) {
824 c
->initial_apicid
= (cpuid_ebx(1) >> 24) & 0xFF;
827 c
->apicid
= apic
->phys_pkg_id(c
->initial_apicid
, 0);
829 c
->apicid
= c
->initial_apicid
;
832 c
->phys_proc_id
= c
->initial_apicid
;
835 get_model_name(c
); /* Default name */
840 static void x86_init_cache_qos(struct cpuinfo_x86
*c
)
843 * The heavy lifting of max_rmid and cache_occ_scale are handled
844 * in get_cpu_cap(). Here we just set the max_rmid for the boot_cpu
845 * in case CQM bits really aren't there in this CPU.
847 if (c
!= &boot_cpu_data
) {
848 boot_cpu_data
.x86_cache_max_rmid
=
849 min(boot_cpu_data
.x86_cache_max_rmid
,
850 c
->x86_cache_max_rmid
);
855 * This does the hard work of actually picking apart the CPU stuff...
857 static void identify_cpu(struct cpuinfo_x86
*c
)
861 c
->loops_per_jiffy
= loops_per_jiffy
;
862 c
->x86_cache_size
= -1;
863 c
->x86_vendor
= X86_VENDOR_UNKNOWN
;
864 c
->x86_model
= c
->x86_mask
= 0; /* So far unknown... */
865 c
->x86_vendor_id
[0] = '\0'; /* Unset */
866 c
->x86_model_id
[0] = '\0'; /* Unset */
867 c
->x86_max_cores
= 1;
868 c
->x86_coreid_bits
= 0;
870 c
->x86_clflush_size
= 64;
871 c
->x86_phys_bits
= 36;
872 c
->x86_virt_bits
= 48;
874 c
->cpuid_level
= -1; /* CPUID not detected */
875 c
->x86_clflush_size
= 32;
876 c
->x86_phys_bits
= 32;
877 c
->x86_virt_bits
= 32;
879 c
->x86_cache_alignment
= c
->x86_clflush_size
;
880 memset(&c
->x86_capability
, 0, sizeof c
->x86_capability
);
884 if (this_cpu
->c_identify
)
885 this_cpu
->c_identify(c
);
887 /* Clear/Set all flags overriden by options, after probe */
888 for (i
= 0; i
< NCAPINTS
; i
++) {
889 c
->x86_capability
[i
] &= ~cpu_caps_cleared
[i
];
890 c
->x86_capability
[i
] |= cpu_caps_set
[i
];
894 c
->apicid
= apic
->phys_pkg_id(c
->initial_apicid
, 0);
898 * Vendor-specific initialization. In this section we
899 * canonicalize the feature flags, meaning if there are
900 * features a certain CPU supports which CPUID doesn't
901 * tell us, CPUID claiming incorrect flags, or other bugs,
902 * we handle them here.
904 * At the end of this section, c->x86_capability better
905 * indicate the features this CPU genuinely supports!
907 if (this_cpu
->c_init
)
910 /* Disable the PN if appropriate */
911 squash_the_stupid_serial_number(c
);
913 /* Set up SMEP/SMAP */
918 * The vendor-specific functions might have changed features.
919 * Now we do "generic changes."
922 /* Filter out anything that depends on CPUID levels we don't have */
923 filter_cpuid_features(c
, true);
925 /* If the model name is still unset, do table lookup. */
926 if (!c
->x86_model_id
[0]) {
928 p
= table_lookup_model(c
);
930 strcpy(c
->x86_model_id
, p
);
933 sprintf(c
->x86_model_id
, "%02x/%02x",
934 c
->x86
, c
->x86_model
);
943 x86_init_cache_qos(c
);
946 * Clear/Set all flags overriden by options, need do it
947 * before following smp all cpus cap AND.
949 for (i
= 0; i
< NCAPINTS
; i
++) {
950 c
->x86_capability
[i
] &= ~cpu_caps_cleared
[i
];
951 c
->x86_capability
[i
] |= cpu_caps_set
[i
];
955 * On SMP, boot_cpu_data holds the common feature set between
956 * all CPUs; so make sure that we indicate which features are
957 * common between the CPUs. The first time this routine gets
958 * executed, c == &boot_cpu_data.
960 if (c
!= &boot_cpu_data
) {
961 /* AND the already accumulated flags with these */
962 for (i
= 0; i
< NCAPINTS
; i
++)
963 boot_cpu_data
.x86_capability
[i
] &= c
->x86_capability
[i
];
965 /* OR, i.e. replicate the bug flags */
966 for (i
= NCAPINTS
; i
< NCAPINTS
+ NBUGINTS
; i
++)
967 c
->x86_capability
[i
] |= boot_cpu_data
.x86_capability
[i
];
970 /* Init Machine Check Exception if available. */
973 select_idle_routine(c
);
976 numa_add_cpu(smp_processor_id());
981 * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions
985 void enable_sep_cpu(void)
987 struct tss_struct
*tss
;
991 tss
= &per_cpu(cpu_tss
, cpu
);
993 if (!boot_cpu_has(X86_FEATURE_SEP
))
997 * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field --
998 * see the big comment in struct x86_hw_tss's definition.
1001 tss
->x86_tss
.ss1
= __KERNEL_CS
;
1002 wrmsr(MSR_IA32_SYSENTER_CS
, tss
->x86_tss
.ss1
, 0);
1004 wrmsr(MSR_IA32_SYSENTER_ESP
,
1005 (unsigned long)tss
+ offsetofend(struct tss_struct
, SYSENTER_stack
),
1008 wrmsr(MSR_IA32_SYSENTER_EIP
, (unsigned long)entry_SYSENTER_32
, 0);
1015 void __init
identify_boot_cpu(void)
1017 identify_cpu(&boot_cpu_data
);
1018 init_amd_e400_c1e_mask();
1019 #ifdef CONFIG_X86_32
1023 cpu_detect_tlb(&boot_cpu_data
);
1026 void identify_secondary_cpu(struct cpuinfo_x86
*c
)
1028 BUG_ON(c
== &boot_cpu_data
);
1030 #ifdef CONFIG_X86_32
1041 static const struct msr_range msr_range_array
[] = {
1042 { 0x00000000, 0x00000418},
1043 { 0xc0000000, 0xc000040b},
1044 { 0xc0010000, 0xc0010142},
1045 { 0xc0011000, 0xc001103b},
1048 static void __print_cpu_msr(void)
1050 unsigned index_min
, index_max
;
1055 for (i
= 0; i
< ARRAY_SIZE(msr_range_array
); i
++) {
1056 index_min
= msr_range_array
[i
].min
;
1057 index_max
= msr_range_array
[i
].max
;
1059 for (index
= index_min
; index
< index_max
; index
++) {
1060 if (rdmsrl_safe(index
, &val
))
1062 pr_info(" MSR%08x: %016llx\n", index
, val
);
1067 static int show_msr
;
1069 static __init
int setup_show_msr(char *arg
)
1073 get_option(&arg
, &num
);
1079 __setup("show_msr=", setup_show_msr
);
1081 static __init
int setup_noclflush(char *arg
)
1083 setup_clear_cpu_cap(X86_FEATURE_CLFLUSH
);
1084 setup_clear_cpu_cap(X86_FEATURE_CLFLUSHOPT
);
1087 __setup("noclflush", setup_noclflush
);
1089 void print_cpu_info(struct cpuinfo_x86
*c
)
1091 const char *vendor
= NULL
;
1093 if (c
->x86_vendor
< X86_VENDOR_NUM
) {
1094 vendor
= this_cpu
->c_vendor
;
1096 if (c
->cpuid_level
>= 0)
1097 vendor
= c
->x86_vendor_id
;
1100 if (vendor
&& !strstr(c
->x86_model_id
, vendor
))
1101 pr_cont("%s ", vendor
);
1103 if (c
->x86_model_id
[0])
1104 pr_cont("%s", c
->x86_model_id
);
1106 pr_cont("%d86", c
->x86
);
1108 pr_cont(" (family: 0x%x, model: 0x%x", c
->x86
, c
->x86_model
);
1110 if (c
->x86_mask
|| c
->cpuid_level
>= 0)
1111 pr_cont(", stepping: 0x%x)\n", c
->x86_mask
);
1118 void print_cpu_msr(struct cpuinfo_x86
*c
)
1120 if (c
->cpu_index
< show_msr
)
1124 static __init
int setup_disablecpuid(char *arg
)
1128 if (get_option(&arg
, &bit
) && bit
< NCAPINTS
*32)
1129 setup_clear_cpu_cap(bit
);
1135 __setup("clearcpuid=", setup_disablecpuid
);
1137 #ifdef CONFIG_X86_64
1138 struct desc_ptr idt_descr
= { NR_VECTORS
* 16 - 1, (unsigned long) idt_table
};
1139 struct desc_ptr debug_idt_descr
= { NR_VECTORS
* 16 - 1,
1140 (unsigned long) debug_idt_table
};
1142 DEFINE_PER_CPU_FIRST(union irq_stack_union
,
1143 irq_stack_union
) __aligned(PAGE_SIZE
) __visible
;
1146 * The following percpu variables are hot. Align current_task to
1147 * cacheline size such that they fall in the same cacheline.
1149 DEFINE_PER_CPU(struct task_struct
*, current_task
) ____cacheline_aligned
=
1151 EXPORT_PER_CPU_SYMBOL(current_task
);
1153 DEFINE_PER_CPU(char *, irq_stack_ptr
) =
1154 init_per_cpu_var(irq_stack_union
.irq_stack
) + IRQ_STACK_SIZE
- 64;
1156 DEFINE_PER_CPU(unsigned int, irq_count
) __visible
= -1;
1158 DEFINE_PER_CPU(int, __preempt_count
) = INIT_PREEMPT_COUNT
;
1159 EXPORT_PER_CPU_SYMBOL(__preempt_count
);
1162 * Special IST stacks which the CPU switches to when it calls
1163 * an IST-marked descriptor entry. Up to 7 stacks (hardware
1164 * limit), all of them are 4K, except the debug stack which
1167 static const unsigned int exception_stack_sizes
[N_EXCEPTION_STACKS
] = {
1168 [0 ... N_EXCEPTION_STACKS
- 1] = EXCEPTION_STKSZ
,
1169 [DEBUG_STACK
- 1] = DEBUG_STKSZ
1172 static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks
1173 [(N_EXCEPTION_STACKS
- 1) * EXCEPTION_STKSZ
+ DEBUG_STKSZ
]);
1175 /* May not be marked __init: used by software suspend */
1176 void syscall_init(void)
1179 * LSTAR and STAR live in a bit strange symbiosis.
1180 * They both write to the same internal register. STAR allows to
1181 * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip.
1183 wrmsr(MSR_STAR
, 0, (__USER32_CS
<< 16) | __KERNEL_CS
);
1184 wrmsrl(MSR_LSTAR
, (unsigned long)entry_SYSCALL_64
);
1186 #ifdef CONFIG_IA32_EMULATION
1187 wrmsrl(MSR_CSTAR
, (unsigned long)entry_SYSCALL_compat
);
1189 * This only works on Intel CPUs.
1190 * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP.
1191 * This does not cause SYSENTER to jump to the wrong location, because
1192 * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit).
1194 wrmsrl_safe(MSR_IA32_SYSENTER_CS
, (u64
)__KERNEL_CS
);
1195 wrmsrl_safe(MSR_IA32_SYSENTER_ESP
, 0ULL);
1196 wrmsrl_safe(MSR_IA32_SYSENTER_EIP
, (u64
)entry_SYSENTER_compat
);
1198 wrmsrl(MSR_CSTAR
, (unsigned long)ignore_sysret
);
1199 wrmsrl_safe(MSR_IA32_SYSENTER_CS
, (u64
)GDT_ENTRY_INVALID_SEG
);
1200 wrmsrl_safe(MSR_IA32_SYSENTER_ESP
, 0ULL);
1201 wrmsrl_safe(MSR_IA32_SYSENTER_EIP
, 0ULL);
1204 /* Flags to clear on syscall */
1205 wrmsrl(MSR_SYSCALL_MASK
,
1206 X86_EFLAGS_TF
|X86_EFLAGS_DF
|X86_EFLAGS_IF
|
1207 X86_EFLAGS_IOPL
|X86_EFLAGS_AC
|X86_EFLAGS_NT
);
1211 * Copies of the original ist values from the tss are only accessed during
1212 * debugging, no special alignment required.
1214 DEFINE_PER_CPU(struct orig_ist
, orig_ist
);
1216 static DEFINE_PER_CPU(unsigned long, debug_stack_addr
);
1217 DEFINE_PER_CPU(int, debug_stack_usage
);
1219 int is_debug_stack(unsigned long addr
)
1221 return __this_cpu_read(debug_stack_usage
) ||
1222 (addr
<= __this_cpu_read(debug_stack_addr
) &&
1223 addr
> (__this_cpu_read(debug_stack_addr
) - DEBUG_STKSZ
));
1225 NOKPROBE_SYMBOL(is_debug_stack
);
1227 DEFINE_PER_CPU(u32
, debug_idt_ctr
);
1229 void debug_stack_set_zero(void)
1231 this_cpu_inc(debug_idt_ctr
);
1234 NOKPROBE_SYMBOL(debug_stack_set_zero
);
1236 void debug_stack_reset(void)
1238 if (WARN_ON(!this_cpu_read(debug_idt_ctr
)))
1240 if (this_cpu_dec_return(debug_idt_ctr
) == 0)
1243 NOKPROBE_SYMBOL(debug_stack_reset
);
1245 #else /* CONFIG_X86_64 */
1247 DEFINE_PER_CPU(struct task_struct
*, current_task
) = &init_task
;
1248 EXPORT_PER_CPU_SYMBOL(current_task
);
1249 DEFINE_PER_CPU(int, __preempt_count
) = INIT_PREEMPT_COUNT
;
1250 EXPORT_PER_CPU_SYMBOL(__preempt_count
);
1253 * On x86_32, vm86 modifies tss.sp0, so sp0 isn't a reliable way to find
1254 * the top of the kernel stack. Use an extra percpu variable to track the
1255 * top of the kernel stack directly.
1257 DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack
) =
1258 (unsigned long)&init_thread_union
+ THREAD_SIZE
;
1259 EXPORT_PER_CPU_SYMBOL(cpu_current_top_of_stack
);
1261 #ifdef CONFIG_CC_STACKPROTECTOR
1262 DEFINE_PER_CPU_ALIGNED(struct stack_canary
, stack_canary
);
1265 #endif /* CONFIG_X86_64 */
1268 * Clear all 6 debug registers:
1270 static void clear_all_debug_regs(void)
1274 for (i
= 0; i
< 8; i
++) {
1275 /* Ignore db4, db5 */
1276 if ((i
== 4) || (i
== 5))
1285 * Restore debug regs if using kgdbwait and you have a kernel debugger
1286 * connection established.
1288 static void dbg_restore_debug_regs(void)
1290 if (unlikely(kgdb_connected
&& arch_kgdb_ops
.correct_hw_break
))
1291 arch_kgdb_ops
.correct_hw_break();
1293 #else /* ! CONFIG_KGDB */
1294 #define dbg_restore_debug_regs()
1295 #endif /* ! CONFIG_KGDB */
1297 static void wait_for_master_cpu(int cpu
)
1301 * wait for ACK from master CPU before continuing
1302 * with AP initialization
1304 WARN_ON(cpumask_test_and_set_cpu(cpu
, cpu_initialized_mask
));
1305 while (!cpumask_test_cpu(cpu
, cpu_callout_mask
))
1311 * cpu_init() initializes state that is per-CPU. Some data is already
1312 * initialized (naturally) in the bootstrap process, such as the GDT
1313 * and IDT. We reload them nevertheless, this function acts as a
1314 * 'CPU state barrier', nothing should get across.
1315 * A lot of state is already set up in PDA init for 64 bit
1317 #ifdef CONFIG_X86_64
1321 struct orig_ist
*oist
;
1322 struct task_struct
*me
;
1323 struct tss_struct
*t
;
1325 int cpu
= stack_smp_processor_id();
1328 wait_for_master_cpu(cpu
);
1331 * Initialize the CR4 shadow before doing anything that could
1337 * Load microcode on this cpu if a valid microcode is available.
1338 * This is early microcode loading procedure.
1342 t
= &per_cpu(cpu_tss
, cpu
);
1343 oist
= &per_cpu(orig_ist
, cpu
);
1346 if (this_cpu_read(numa_node
) == 0 &&
1347 early_cpu_to_node(cpu
) != NUMA_NO_NODE
)
1348 set_numa_node(early_cpu_to_node(cpu
));
1353 pr_debug("Initializing CPU#%d\n", cpu
);
1355 cr4_clear_bits(X86_CR4_VME
|X86_CR4_PVI
|X86_CR4_TSD
|X86_CR4_DE
);
1358 * Initialize the per-CPU GDT with the boot GDT,
1359 * and set up the GDT descriptor:
1362 switch_to_new_gdt(cpu
);
1367 memset(me
->thread
.tls_array
, 0, GDT_ENTRY_TLS_ENTRIES
* 8);
1370 wrmsrl(MSR_FS_BASE
, 0);
1371 wrmsrl(MSR_KERNEL_GS_BASE
, 0);
1378 * set up and load the per-CPU TSS
1380 if (!oist
->ist
[0]) {
1381 char *estacks
= per_cpu(exception_stacks
, cpu
);
1383 for (v
= 0; v
< N_EXCEPTION_STACKS
; v
++) {
1384 estacks
+= exception_stack_sizes
[v
];
1385 oist
->ist
[v
] = t
->x86_tss
.ist
[v
] =
1386 (unsigned long)estacks
;
1387 if (v
== DEBUG_STACK
-1)
1388 per_cpu(debug_stack_addr
, cpu
) = (unsigned long)estacks
;
1392 t
->x86_tss
.io_bitmap_base
= offsetof(struct tss_struct
, io_bitmap
);
1395 * <= is required because the CPU will access up to
1396 * 8 bits beyond the end of the IO permission bitmap.
1398 for (i
= 0; i
<= IO_BITMAP_LONGS
; i
++)
1399 t
->io_bitmap
[i
] = ~0UL;
1401 atomic_inc(&init_mm
.mm_count
);
1402 me
->active_mm
= &init_mm
;
1404 enter_lazy_tlb(&init_mm
, me
);
1406 load_sp0(t
, ¤t
->thread
);
1407 set_tss_desc(cpu
, t
);
1409 load_mm_ldt(&init_mm
);
1411 clear_all_debug_regs();
1412 dbg_restore_debug_regs();
1424 int cpu
= smp_processor_id();
1425 struct task_struct
*curr
= current
;
1426 struct tss_struct
*t
= &per_cpu(cpu_tss
, cpu
);
1427 struct thread_struct
*thread
= &curr
->thread
;
1429 wait_for_master_cpu(cpu
);
1432 * Initialize the CR4 shadow before doing anything that could
1437 show_ucode_info_early();
1439 pr_info("Initializing CPU#%d\n", cpu
);
1441 if (cpu_feature_enabled(X86_FEATURE_VME
) ||
1443 boot_cpu_has(X86_FEATURE_DE
))
1444 cr4_clear_bits(X86_CR4_VME
|X86_CR4_PVI
|X86_CR4_TSD
|X86_CR4_DE
);
1447 switch_to_new_gdt(cpu
);
1450 * Set up and load the per-CPU TSS and LDT
1452 atomic_inc(&init_mm
.mm_count
);
1453 curr
->active_mm
= &init_mm
;
1455 enter_lazy_tlb(&init_mm
, curr
);
1457 load_sp0(t
, thread
);
1458 set_tss_desc(cpu
, t
);
1460 load_mm_ldt(&init_mm
);
1462 t
->x86_tss
.io_bitmap_base
= offsetof(struct tss_struct
, io_bitmap
);
1464 #ifdef CONFIG_DOUBLEFAULT
1465 /* Set up doublefault TSS pointer in the GDT */
1466 __set_tss_desc(cpu
, GDT_ENTRY_DOUBLEFAULT_TSS
, &doublefault_tss
);
1469 clear_all_debug_regs();
1470 dbg_restore_debug_regs();
1476 #ifdef CONFIG_X86_DEBUG_STATIC_CPU_HAS
1477 void warn_pre_alternatives(void)
1479 WARN(1, "You're using static_cpu_has before alternatives have run!\n");
1481 EXPORT_SYMBOL_GPL(warn_pre_alternatives
);
1484 inline bool __static_cpu_has_safe(u16 bit
)
1486 return boot_cpu_has(bit
);
1488 EXPORT_SYMBOL_GPL(__static_cpu_has_safe
);
1490 static void bsp_resume(void)
1492 if (this_cpu
->c_bsp_resume
)
1493 this_cpu
->c_bsp_resume(&boot_cpu_data
);
1496 static struct syscore_ops cpu_syscore_ops
= {
1497 .resume
= bsp_resume
,
1500 static int __init
init_cpu_syscore(void)
1502 register_syscore_ops(&cpu_syscore_ops
);
1505 core_initcall(init_cpu_syscore
);