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69507ae8a65b3507d780d619bc131bb51b3ff426
[deliverable/linux.git] / arch / x86 / kernel / cpu / common.c
1 #include <linux/init.h>
2 #include <linux/string.h>
3 #include <linux/delay.h>
4 #include <linux/smp.h>
5 #include <linux/module.h>
6 #include <linux/percpu.h>
7 #include <linux/bootmem.h>
8 #include <asm/semaphore.h>
9 #include <asm/processor.h>
10 #include <asm/i387.h>
11 #include <asm/msr.h>
12 #include <asm/io.h>
13 #include <asm/mmu_context.h>
14 #include <asm/mtrr.h>
15 #include <asm/mce.h>
16 #ifdef CONFIG_X86_LOCAL_APIC
17 #include <asm/mpspec.h>
18 #include <asm/apic.h>
19 #include <mach_apic.h>
20 #endif
21
22 #include "cpu.h"
23
24 DEFINE_PER_CPU(struct gdt_page, gdt_page) = { .gdt = {
25 [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00cf9a00 } } },
26 [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9200 } } },
27 [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00cffa00 } } },
28 [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff200 } } },
29 /*
30 * Segments used for calling PnP BIOS have byte granularity.
31 * They code segments and data segments have fixed 64k limits,
32 * the transfer segment sizes are set at run time.
33 */
34 /* 32-bit code */
35 [GDT_ENTRY_PNPBIOS_CS32] = { { { 0x0000ffff, 0x00409a00 } } },
36 /* 16-bit code */
37 [GDT_ENTRY_PNPBIOS_CS16] = { { { 0x0000ffff, 0x00009a00 } } },
38 /* 16-bit data */
39 [GDT_ENTRY_PNPBIOS_DS] = { { { 0x0000ffff, 0x00009200 } } },
40 /* 16-bit data */
41 [GDT_ENTRY_PNPBIOS_TS1] = { { { 0x00000000, 0x00009200 } } },
42 /* 16-bit data */
43 [GDT_ENTRY_PNPBIOS_TS2] = { { { 0x00000000, 0x00009200 } } },
44 /*
45 * The APM segments have byte granularity and their bases
46 * are set at run time. All have 64k limits.
47 */
48 /* 32-bit code */
49 [GDT_ENTRY_APMBIOS_BASE] = { { { 0x0000ffff, 0x00409a00 } } },
50 /* 16-bit code */
51 [GDT_ENTRY_APMBIOS_BASE+1] = { { { 0x0000ffff, 0x00009a00 } } },
52 /* data */
53 [GDT_ENTRY_APMBIOS_BASE+2] = { { { 0x0000ffff, 0x00409200 } } },
54
55 [GDT_ENTRY_ESPFIX_SS] = { { { 0x00000000, 0x00c09200 } } },
56 [GDT_ENTRY_PERCPU] = { { { 0x00000000, 0x00000000 } } },
57 } };
58 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page);
59
60 static int cachesize_override __cpuinitdata = -1;
61 static int disable_x86_fxsr __cpuinitdata;
62 static int disable_x86_serial_nr __cpuinitdata = 1;
63 static int disable_x86_sep __cpuinitdata;
64
65 struct cpu_dev * cpu_devs[X86_VENDOR_NUM] = {};
66
67 extern int disable_pse;
68
69 static void __cpuinit default_init(struct cpuinfo_x86 * c)
70 {
71 /* Not much we can do here... */
72 /* Check if at least it has cpuid */
73 if (c->cpuid_level == -1) {
74 /* No cpuid. It must be an ancient CPU */
75 if (c->x86 == 4)
76 strcpy(c->x86_model_id, "486");
77 else if (c->x86 == 3)
78 strcpy(c->x86_model_id, "386");
79 }
80 }
81
82 static struct cpu_dev __cpuinitdata default_cpu = {
83 .c_init = default_init,
84 .c_vendor = "Unknown",
85 };
86 static struct cpu_dev * this_cpu __cpuinitdata = &default_cpu;
87
88 static int __init cachesize_setup(char *str)
89 {
90 get_option (&str, &cachesize_override);
91 return 1;
92 }
93 __setup("cachesize=", cachesize_setup);
94
95 int __cpuinit get_model_name(struct cpuinfo_x86 *c)
96 {
97 unsigned int *v;
98 char *p, *q;
99
100 if (cpuid_eax(0x80000000) < 0x80000004)
101 return 0;
102
103 v = (unsigned int *) c->x86_model_id;
104 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
105 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
106 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
107 c->x86_model_id[48] = 0;
108
109 /* Intel chips right-justify this string for some dumb reason;
110 undo that brain damage */
111 p = q = &c->x86_model_id[0];
112 while ( *p == ' ' )
113 p++;
114 if ( p != q ) {
115 while ( *p )
116 *q++ = *p++;
117 while ( q <= &c->x86_model_id[48] )
118 *q++ = '\0'; /* Zero-pad the rest */
119 }
120
121 return 1;
122 }
123
124
125 void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
126 {
127 unsigned int n, dummy, ecx, edx, l2size;
128
129 n = cpuid_eax(0x80000000);
130
131 if (n >= 0x80000005) {
132 cpuid(0x80000005, &dummy, &dummy, &ecx, &edx);
133 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
134 edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
135 c->x86_cache_size=(ecx>>24)+(edx>>24);
136 }
137
138 if (n < 0x80000006) /* Some chips just has a large L1. */
139 return;
140
141 ecx = cpuid_ecx(0x80000006);
142 l2size = ecx >> 16;
143
144 /* do processor-specific cache resizing */
145 if (this_cpu->c_size_cache)
146 l2size = this_cpu->c_size_cache(c,l2size);
147
148 /* Allow user to override all this if necessary. */
149 if (cachesize_override != -1)
150 l2size = cachesize_override;
151
152 if ( l2size == 0 )
153 return; /* Again, no L2 cache is possible */
154
155 c->x86_cache_size = l2size;
156
157 printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
158 l2size, ecx & 0xFF);
159 }
160
161 /* Naming convention should be: <Name> [(<Codename>)] */
162 /* This table only is used unless init_<vendor>() below doesn't set it; */
163 /* in particular, if CPUID levels 0x80000002..4 are supported, this isn't used */
164
165 /* Look up CPU names by table lookup. */
166 static char __cpuinit *table_lookup_model(struct cpuinfo_x86 *c)
167 {
168 struct cpu_model_info *info;
169
170 if ( c->x86_model >= 16 )
171 return NULL; /* Range check */
172
173 if (!this_cpu)
174 return NULL;
175
176 info = this_cpu->c_models;
177
178 while (info && info->family) {
179 if (info->family == c->x86)
180 return info->model_names[c->x86_model];
181 info++;
182 }
183 return NULL; /* Not found */
184 }
185
186
187 static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c, int early)
188 {
189 char *v = c->x86_vendor_id;
190 int i;
191 static int printed;
192
193 for (i = 0; i < X86_VENDOR_NUM; i++) {
194 if (cpu_devs[i]) {
195 if (!strcmp(v,cpu_devs[i]->c_ident[0]) ||
196 (cpu_devs[i]->c_ident[1] &&
197 !strcmp(v,cpu_devs[i]->c_ident[1]))) {
198 c->x86_vendor = i;
199 if (!early)
200 this_cpu = cpu_devs[i];
201 return;
202 }
203 }
204 }
205 if (!printed) {
206 printed++;
207 printk(KERN_ERR "CPU: Vendor unknown, using generic init.\n");
208 printk(KERN_ERR "CPU: Your system may be unstable.\n");
209 }
210 c->x86_vendor = X86_VENDOR_UNKNOWN;
211 this_cpu = &default_cpu;
212 }
213
214
215 static int __init x86_fxsr_setup(char * s)
216 {
217 /* Tell all the other CPUs to not use it... */
218 disable_x86_fxsr = 1;
219
220 /*
221 * ... and clear the bits early in the boot_cpu_data
222 * so that the bootup process doesn't try to do this
223 * either.
224 */
225 clear_bit(X86_FEATURE_FXSR, boot_cpu_data.x86_capability);
226 clear_bit(X86_FEATURE_XMM, boot_cpu_data.x86_capability);
227 return 1;
228 }
229 __setup("nofxsr", x86_fxsr_setup);
230
231
232 static int __init x86_sep_setup(char * s)
233 {
234 disable_x86_sep = 1;
235 return 1;
236 }
237 __setup("nosep", x86_sep_setup);
238
239
240 /* Standard macro to see if a specific flag is changeable */
241 static inline int flag_is_changeable_p(u32 flag)
242 {
243 u32 f1, f2;
244
245 asm("pushfl\n\t"
246 "pushfl\n\t"
247 "popl %0\n\t"
248 "movl %0,%1\n\t"
249 "xorl %2,%0\n\t"
250 "pushl %0\n\t"
251 "popfl\n\t"
252 "pushfl\n\t"
253 "popl %0\n\t"
254 "popfl\n\t"
255 : "=&r" (f1), "=&r" (f2)
256 : "ir" (flag));
257
258 return ((f1^f2) & flag) != 0;
259 }
260
261
262 /* Probe for the CPUID instruction */
263 static int __cpuinit have_cpuid_p(void)
264 {
265 return flag_is_changeable_p(X86_EFLAGS_ID);
266 }
267
268 void __init cpu_detect(struct cpuinfo_x86 *c)
269 {
270 /* Get vendor name */
271 cpuid(0x00000000, &c->cpuid_level,
272 (int *)&c->x86_vendor_id[0],
273 (int *)&c->x86_vendor_id[8],
274 (int *)&c->x86_vendor_id[4]);
275
276 c->x86 = 4;
277 if (c->cpuid_level >= 0x00000001) {
278 u32 junk, tfms, cap0, misc;
279 cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
280 c->x86 = (tfms >> 8) & 15;
281 c->x86_model = (tfms >> 4) & 15;
282 if (c->x86 == 0xf)
283 c->x86 += (tfms >> 20) & 0xff;
284 if (c->x86 >= 0x6)
285 c->x86_model += ((tfms >> 16) & 0xF) << 4;
286 c->x86_mask = tfms & 15;
287 if (cap0 & (1<<19))
288 c->x86_cache_alignment = ((misc >> 8) & 0xff) * 8;
289 }
290 }
291
292 /* Do minimum CPU detection early.
293 Fields really needed: vendor, cpuid_level, family, model, mask, cache alignment.
294 The others are not touched to avoid unwanted side effects.
295
296 WARNING: this function is only called on the BP. Don't add code here
297 that is supposed to run on all CPUs. */
298 static void __init early_cpu_detect(void)
299 {
300 struct cpuinfo_x86 *c = &boot_cpu_data;
301
302 c->x86_cache_alignment = 32;
303
304 if (!have_cpuid_p())
305 return;
306
307 cpu_detect(c);
308
309 get_cpu_vendor(c, 1);
310 }
311
312 static void __cpuinit generic_identify(struct cpuinfo_x86 * c)
313 {
314 u32 tfms, xlvl;
315 int ebx;
316
317 if (have_cpuid_p()) {
318 /* Get vendor name */
319 cpuid(0x00000000, &c->cpuid_level,
320 (int *)&c->x86_vendor_id[0],
321 (int *)&c->x86_vendor_id[8],
322 (int *)&c->x86_vendor_id[4]);
323
324 get_cpu_vendor(c, 0);
325 /* Initialize the standard set of capabilities */
326 /* Note that the vendor-specific code below might override */
327
328 /* Intel-defined flags: level 0x00000001 */
329 if ( c->cpuid_level >= 0x00000001 ) {
330 u32 capability, excap;
331 cpuid(0x00000001, &tfms, &ebx, &excap, &capability);
332 c->x86_capability[0] = capability;
333 c->x86_capability[4] = excap;
334 c->x86 = (tfms >> 8) & 15;
335 c->x86_model = (tfms >> 4) & 15;
336 if (c->x86 == 0xf)
337 c->x86 += (tfms >> 20) & 0xff;
338 if (c->x86 >= 0x6)
339 c->x86_model += ((tfms >> 16) & 0xF) << 4;
340 c->x86_mask = tfms & 15;
341 #ifdef CONFIG_X86_HT
342 c->apicid = phys_pkg_id((ebx >> 24) & 0xFF, 0);
343 #else
344 c->apicid = (ebx >> 24) & 0xFF;
345 #endif
346 if (c->x86_capability[0] & (1<<19))
347 c->x86_clflush_size = ((ebx >> 8) & 0xff) * 8;
348 } else {
349 /* Have CPUID level 0 only - unheard of */
350 c->x86 = 4;
351 }
352
353 /* AMD-defined flags: level 0x80000001 */
354 xlvl = cpuid_eax(0x80000000);
355 if ( (xlvl & 0xffff0000) == 0x80000000 ) {
356 if ( xlvl >= 0x80000001 ) {
357 c->x86_capability[1] = cpuid_edx(0x80000001);
358 c->x86_capability[6] = cpuid_ecx(0x80000001);
359 }
360 if ( xlvl >= 0x80000004 )
361 get_model_name(c); /* Default name */
362 }
363
364 init_scattered_cpuid_features(c);
365 }
366
367 early_intel_workaround(c);
368
369 #ifdef CONFIG_X86_HT
370 c->phys_proc_id = (cpuid_ebx(1) >> 24) & 0xff;
371 #endif
372 }
373
374 static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
375 {
376 if (cpu_has(c, X86_FEATURE_PN) && disable_x86_serial_nr ) {
377 /* Disable processor serial number */
378 unsigned long lo,hi;
379 rdmsr(MSR_IA32_BBL_CR_CTL,lo,hi);
380 lo |= 0x200000;
381 wrmsr(MSR_IA32_BBL_CR_CTL,lo,hi);
382 printk(KERN_NOTICE "CPU serial number disabled.\n");
383 clear_bit(X86_FEATURE_PN, c->x86_capability);
384
385 /* Disabling the serial number may affect the cpuid level */
386 c->cpuid_level = cpuid_eax(0);
387 }
388 }
389
390 static int __init x86_serial_nr_setup(char *s)
391 {
392 disable_x86_serial_nr = 0;
393 return 1;
394 }
395 __setup("serialnumber", x86_serial_nr_setup);
396
397
398
399 /*
400 * This does the hard work of actually picking apart the CPU stuff...
401 */
402 static void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
403 {
404 int i;
405
406 c->loops_per_jiffy = loops_per_jiffy;
407 c->x86_cache_size = -1;
408 c->x86_vendor = X86_VENDOR_UNKNOWN;
409 c->cpuid_level = -1; /* CPUID not detected */
410 c->x86_model = c->x86_mask = 0; /* So far unknown... */
411 c->x86_vendor_id[0] = '\0'; /* Unset */
412 c->x86_model_id[0] = '\0'; /* Unset */
413 c->x86_max_cores = 1;
414 c->x86_clflush_size = 32;
415 memset(&c->x86_capability, 0, sizeof c->x86_capability);
416
417 if (!have_cpuid_p()) {
418 /* First of all, decide if this is a 486 or higher */
419 /* It's a 486 if we can modify the AC flag */
420 if ( flag_is_changeable_p(X86_EFLAGS_AC) )
421 c->x86 = 4;
422 else
423 c->x86 = 3;
424 }
425
426 generic_identify(c);
427
428 printk(KERN_DEBUG "CPU: After generic identify, caps:");
429 for (i = 0; i < NCAPINTS; i++)
430 printk(" %08lx", c->x86_capability[i]);
431 printk("\n");
432
433 if (this_cpu->c_identify) {
434 this_cpu->c_identify(c);
435
436 printk(KERN_DEBUG "CPU: After vendor identify, caps:");
437 for (i = 0; i < NCAPINTS; i++)
438 printk(" %08lx", c->x86_capability[i]);
439 printk("\n");
440 }
441
442 /*
443 * Vendor-specific initialization. In this section we
444 * canonicalize the feature flags, meaning if there are
445 * features a certain CPU supports which CPUID doesn't
446 * tell us, CPUID claiming incorrect flags, or other bugs,
447 * we handle them here.
448 *
449 * At the end of this section, c->x86_capability better
450 * indicate the features this CPU genuinely supports!
451 */
452 if (this_cpu->c_init)
453 this_cpu->c_init(c);
454
455 /* Disable the PN if appropriate */
456 squash_the_stupid_serial_number(c);
457
458 /*
459 * The vendor-specific functions might have changed features. Now
460 * we do "generic changes."
461 */
462
463 /* TSC disabled? */
464 if ( tsc_disable )
465 clear_bit(X86_FEATURE_TSC, c->x86_capability);
466
467 /* FXSR disabled? */
468 if (disable_x86_fxsr) {
469 clear_bit(X86_FEATURE_FXSR, c->x86_capability);
470 clear_bit(X86_FEATURE_XMM, c->x86_capability);
471 }
472
473 /* SEP disabled? */
474 if (disable_x86_sep)
475 clear_bit(X86_FEATURE_SEP, c->x86_capability);
476
477 if (disable_pse)
478 clear_bit(X86_FEATURE_PSE, c->x86_capability);
479
480 /* If the model name is still unset, do table lookup. */
481 if ( !c->x86_model_id[0] ) {
482 char *p;
483 p = table_lookup_model(c);
484 if ( p )
485 strcpy(c->x86_model_id, p);
486 else
487 /* Last resort... */
488 sprintf(c->x86_model_id, "%02x/%02x",
489 c->x86, c->x86_model);
490 }
491
492 /* Now the feature flags better reflect actual CPU features! */
493
494 printk(KERN_DEBUG "CPU: After all inits, caps:");
495 for (i = 0; i < NCAPINTS; i++)
496 printk(" %08lx", c->x86_capability[i]);
497 printk("\n");
498
499 /*
500 * On SMP, boot_cpu_data holds the common feature set between
501 * all CPUs; so make sure that we indicate which features are
502 * common between the CPUs. The first time this routine gets
503 * executed, c == &boot_cpu_data.
504 */
505 if ( c != &boot_cpu_data ) {
506 /* AND the already accumulated flags with these */
507 for ( i = 0 ; i < NCAPINTS ; i++ )
508 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
509 }
510
511 /* Init Machine Check Exception if available. */
512 mcheck_init(c);
513 }
514
515 void __init identify_boot_cpu(void)
516 {
517 identify_cpu(&boot_cpu_data);
518 sysenter_setup();
519 enable_sep_cpu();
520 mtrr_bp_init();
521 }
522
523 void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c)
524 {
525 BUG_ON(c == &boot_cpu_data);
526 identify_cpu(c);
527 enable_sep_cpu();
528 mtrr_ap_init();
529 }
530
531 #ifdef CONFIG_X86_HT
532 void __cpuinit detect_ht(struct cpuinfo_x86 *c)
533 {
534 u32 eax, ebx, ecx, edx;
535 int index_msb, core_bits;
536
537 cpuid(1, &eax, &ebx, &ecx, &edx);
538
539 if (!cpu_has(c, X86_FEATURE_HT) || cpu_has(c, X86_FEATURE_CMP_LEGACY))
540 return;
541
542 smp_num_siblings = (ebx & 0xff0000) >> 16;
543
544 if (smp_num_siblings == 1) {
545 printk(KERN_INFO "CPU: Hyper-Threading is disabled\n");
546 } else if (smp_num_siblings > 1 ) {
547
548 if (smp_num_siblings > NR_CPUS) {
549 printk(KERN_WARNING "CPU: Unsupported number of the "
550 "siblings %d", smp_num_siblings);
551 smp_num_siblings = 1;
552 return;
553 }
554
555 index_msb = get_count_order(smp_num_siblings);
556 c->phys_proc_id = phys_pkg_id((ebx >> 24) & 0xFF, index_msb);
557
558 printk(KERN_INFO "CPU: Physical Processor ID: %d\n",
559 c->phys_proc_id);
560
561 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
562
563 index_msb = get_count_order(smp_num_siblings) ;
564
565 core_bits = get_count_order(c->x86_max_cores);
566
567 c->cpu_core_id = phys_pkg_id((ebx >> 24) & 0xFF, index_msb) &
568 ((1 << core_bits) - 1);
569
570 if (c->x86_max_cores > 1)
571 printk(KERN_INFO "CPU: Processor Core ID: %d\n",
572 c->cpu_core_id);
573 }
574 }
575 #endif
576
577 void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
578 {
579 char *vendor = NULL;
580
581 if (c->x86_vendor < X86_VENDOR_NUM)
582 vendor = this_cpu->c_vendor;
583 else if (c->cpuid_level >= 0)
584 vendor = c->x86_vendor_id;
585
586 if (vendor && strncmp(c->x86_model_id, vendor, strlen(vendor)))
587 printk("%s ", vendor);
588
589 if (!c->x86_model_id[0])
590 printk("%d86", c->x86);
591 else
592 printk("%s", c->x86_model_id);
593
594 if (c->x86_mask || c->cpuid_level >= 0)
595 printk(" stepping %02x\n", c->x86_mask);
596 else
597 printk("\n");
598 }
599
600 cpumask_t cpu_initialized __cpuinitdata = CPU_MASK_NONE;
601
602 /* This is hacky. :)
603 * We're emulating future behavior.
604 * In the future, the cpu-specific init functions will be called implicitly
605 * via the magic of initcalls.
606 * They will insert themselves into the cpu_devs structure.
607 * Then, when cpu_init() is called, we can just iterate over that array.
608 */
609
610 extern int intel_cpu_init(void);
611 extern int cyrix_init_cpu(void);
612 extern int nsc_init_cpu(void);
613 extern int amd_init_cpu(void);
614 extern int centaur_init_cpu(void);
615 extern int transmeta_init_cpu(void);
616 extern int nexgen_init_cpu(void);
617 extern int umc_init_cpu(void);
618
619 void __init early_cpu_init(void)
620 {
621 intel_cpu_init();
622 cyrix_init_cpu();
623 nsc_init_cpu();
624 amd_init_cpu();
625 centaur_init_cpu();
626 transmeta_init_cpu();
627 nexgen_init_cpu();
628 umc_init_cpu();
629 early_cpu_detect();
630
631 #ifdef CONFIG_DEBUG_PAGEALLOC
632 /* pse is not compatible with on-the-fly unmapping,
633 * disable it even if the cpus claim to support it.
634 */
635 clear_bit(X86_FEATURE_PSE, boot_cpu_data.x86_capability);
636 disable_pse = 1;
637 #endif
638 }
639
640 /* Make sure %fs is initialized properly in idle threads */
641 struct pt_regs * __devinit idle_regs(struct pt_regs *regs)
642 {
643 memset(regs, 0, sizeof(struct pt_regs));
644 regs->fs = __KERNEL_PERCPU;
645 return regs;
646 }
647
648 /* Current gdt points %fs at the "master" per-cpu area: after this,
649 * it's on the real one. */
650 void switch_to_new_gdt(void)
651 {
652 struct desc_ptr gdt_descr;
653
654 gdt_descr.address = (long)get_cpu_gdt_table(smp_processor_id());
655 gdt_descr.size = GDT_SIZE - 1;
656 load_gdt(&gdt_descr);
657 asm("mov %0, %%fs" : : "r" (__KERNEL_PERCPU) : "memory");
658 }
659
660 /*
661 * cpu_init() initializes state that is per-CPU. Some data is already
662 * initialized (naturally) in the bootstrap process, such as the GDT
663 * and IDT. We reload them nevertheless, this function acts as a
664 * 'CPU state barrier', nothing should get across.
665 */
666 void __cpuinit cpu_init(void)
667 {
668 int cpu = smp_processor_id();
669 struct task_struct *curr = current;
670 struct tss_struct * t = &per_cpu(init_tss, cpu);
671 struct thread_struct *thread = &curr->thread;
672
673 if (cpu_test_and_set(cpu, cpu_initialized)) {
674 printk(KERN_WARNING "CPU#%d already initialized!\n", cpu);
675 for (;;) local_irq_enable();
676 }
677
678 printk(KERN_INFO "Initializing CPU#%d\n", cpu);
679
680 if (cpu_has_vme || cpu_has_tsc || cpu_has_de)
681 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
682 if (tsc_disable && cpu_has_tsc) {
683 printk(KERN_NOTICE "Disabling TSC...\n");
684 /**** FIX-HPA: DOES THIS REALLY BELONG HERE? ****/
685 clear_bit(X86_FEATURE_TSC, boot_cpu_data.x86_capability);
686 set_in_cr4(X86_CR4_TSD);
687 }
688
689 load_idt(&idt_descr);
690 switch_to_new_gdt();
691
692 /*
693 * Set up and load the per-CPU TSS and LDT
694 */
695 atomic_inc(&init_mm.mm_count);
696 curr->active_mm = &init_mm;
697 if (curr->mm)
698 BUG();
699 enter_lazy_tlb(&init_mm, curr);
700
701 load_sp0(t, thread);
702 set_tss_desc(cpu,t);
703 load_TR_desc();
704 load_LDT(&init_mm.context);
705
706 #ifdef CONFIG_DOUBLEFAULT
707 /* Set up doublefault TSS pointer in the GDT */
708 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss);
709 #endif
710
711 /* Clear %gs. */
712 asm volatile ("mov %0, %%gs" : : "r" (0));
713
714 /* Clear all 6 debug registers: */
715 set_debugreg(0, 0);
716 set_debugreg(0, 1);
717 set_debugreg(0, 2);
718 set_debugreg(0, 3);
719 set_debugreg(0, 6);
720 set_debugreg(0, 7);
721
722 /*
723 * Force FPU initialization:
724 */
725 current_thread_info()->status = 0;
726 clear_used_math();
727 mxcsr_feature_mask_init();
728 }
729
730 #ifdef CONFIG_HOTPLUG_CPU
731 void __cpuinit cpu_uninit(void)
732 {
733 int cpu = raw_smp_processor_id();
734 cpu_clear(cpu, cpu_initialized);
735
736 /* lazy TLB state */
737 per_cpu(cpu_tlbstate, cpu).state = 0;
738 per_cpu(cpu_tlbstate, cpu).active_mm = &init_mm;
739 }
740 #endif
Linux kernel - Deliverables
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