1 #include <linux/bootmem.h>
2 #include <linux/linkage.h>
3 #include <linux/bitops.h>
4 #include <linux/kernel.h>
5 #include <linux/module.h>
6 #include <linux/percpu.h>
7 #include <linux/string.h>
8 #include <linux/ctype.h>
9 #include <linux/delay.h>
10 #include <linux/sched.h>
11 #include <linux/init.h>
12 #include <linux/kprobes.h>
13 #include <linux/kgdb.h>
14 #include <linux/smp.h>
16 #include <linux/syscore_ops.h>
18 #include <asm/stackprotector.h>
19 #include <asm/perf_event.h>
20 #include <asm/mmu_context.h>
21 #include <asm/archrandom.h>
22 #include <asm/hypervisor.h>
23 #include <asm/processor.h>
24 #include <asm/tlbflush.h>
25 #include <asm/debugreg.h>
26 #include <asm/sections.h>
27 #include <asm/vsyscall.h>
28 #include <linux/topology.h>
29 #include <linux/cpumask.h>
30 #include <asm/pgtable.h>
31 #include <linux/atomic.h>
32 #include <asm/proto.h>
33 #include <asm/setup.h>
36 #include <asm/fpu/internal.h>
38 #include <linux/numa.h>
45 #include <asm/microcode.h>
46 #include <asm/microcode_intel.h>
48 #ifdef CONFIG_X86_LOCAL_APIC
49 #include <asm/uv/uv.h>
54 /* all of these masks are initialized in setup_cpu_local_masks() */
55 cpumask_var_t cpu_initialized_mask
;
56 cpumask_var_t cpu_callout_mask
;
57 cpumask_var_t cpu_callin_mask
;
59 /* representing cpus for which sibling maps can be computed */
60 cpumask_var_t cpu_sibling_setup_mask
;
62 /* correctly size the local cpu masks */
63 void __init
setup_cpu_local_masks(void)
65 alloc_bootmem_cpumask_var(&cpu_initialized_mask
);
66 alloc_bootmem_cpumask_var(&cpu_callin_mask
);
67 alloc_bootmem_cpumask_var(&cpu_callout_mask
);
68 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask
);
71 static void default_init(struct cpuinfo_x86
*c
)
74 cpu_detect_cache_sizes(c
);
76 /* Not much we can do here... */
77 /* Check if at least it has cpuid */
78 if (c
->cpuid_level
== -1) {
79 /* No cpuid. It must be an ancient CPU */
81 strcpy(c
->x86_model_id
, "486");
83 strcpy(c
->x86_model_id
, "386");
88 static const struct cpu_dev default_cpu
= {
89 .c_init
= default_init
,
90 .c_vendor
= "Unknown",
91 .c_x86_vendor
= X86_VENDOR_UNKNOWN
,
94 static const struct cpu_dev
*this_cpu
= &default_cpu
;
96 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page
, gdt_page
) = { .gdt
= {
99 * We need valid kernel segments for data and code in long mode too
100 * IRET will check the segment types kkeil 2000/10/28
101 * Also sysret mandates a special GDT layout
103 * TLS descriptors are currently at a different place compared to i386.
104 * Hopefully nobody expects them at a fixed place (Wine?)
106 [GDT_ENTRY_KERNEL32_CS
] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff),
107 [GDT_ENTRY_KERNEL_CS
] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff),
108 [GDT_ENTRY_KERNEL_DS
] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff),
109 [GDT_ENTRY_DEFAULT_USER32_CS
] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff),
110 [GDT_ENTRY_DEFAULT_USER_DS
] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff),
111 [GDT_ENTRY_DEFAULT_USER_CS
] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff),
113 [GDT_ENTRY_KERNEL_CS
] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff),
114 [GDT_ENTRY_KERNEL_DS
] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
115 [GDT_ENTRY_DEFAULT_USER_CS
] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff),
116 [GDT_ENTRY_DEFAULT_USER_DS
] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff),
118 * Segments used for calling PnP BIOS have byte granularity.
119 * They code segments and data segments have fixed 64k limits,
120 * the transfer segment sizes are set at run time.
123 [GDT_ENTRY_PNPBIOS_CS32
] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
125 [GDT_ENTRY_PNPBIOS_CS16
] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
127 [GDT_ENTRY_PNPBIOS_DS
] = GDT_ENTRY_INIT(0x0092, 0, 0xffff),
129 [GDT_ENTRY_PNPBIOS_TS1
] = GDT_ENTRY_INIT(0x0092, 0, 0),
131 [GDT_ENTRY_PNPBIOS_TS2
] = GDT_ENTRY_INIT(0x0092, 0, 0),
133 * The APM segments have byte granularity and their bases
134 * are set at run time. All have 64k limits.
137 [GDT_ENTRY_APMBIOS_BASE
] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
139 [GDT_ENTRY_APMBIOS_BASE
+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
141 [GDT_ENTRY_APMBIOS_BASE
+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff),
143 [GDT_ENTRY_ESPFIX_SS
] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
144 [GDT_ENTRY_PERCPU
] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
145 GDT_STACK_CANARY_INIT
148 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page
);
150 static int __init
x86_mpx_setup(char *s
)
152 /* require an exact match without trailing characters */
156 /* do not emit a message if the feature is not present */
157 if (!boot_cpu_has(X86_FEATURE_MPX
))
160 setup_clear_cpu_cap(X86_FEATURE_MPX
);
161 pr_info("nompx: Intel Memory Protection Extensions (MPX) disabled\n");
164 __setup("nompx", x86_mpx_setup
);
166 static int __init
x86_noinvpcid_setup(char *s
)
168 /* noinvpcid doesn't accept parameters */
172 /* do not emit a message if the feature is not present */
173 if (!boot_cpu_has(X86_FEATURE_INVPCID
))
176 setup_clear_cpu_cap(X86_FEATURE_INVPCID
);
177 pr_info("noinvpcid: INVPCID feature disabled\n");
180 early_param("noinvpcid", x86_noinvpcid_setup
);
183 static int cachesize_override
= -1;
184 static int disable_x86_serial_nr
= 1;
186 static int __init
cachesize_setup(char *str
)
188 get_option(&str
, &cachesize_override
);
191 __setup("cachesize=", cachesize_setup
);
193 static int __init
x86_sep_setup(char *s
)
195 setup_clear_cpu_cap(X86_FEATURE_SEP
);
198 __setup("nosep", x86_sep_setup
);
200 /* Standard macro to see if a specific flag is changeable */
201 static inline int flag_is_changeable_p(u32 flag
)
206 * Cyrix and IDT cpus allow disabling of CPUID
207 * so the code below may return different results
208 * when it is executed before and after enabling
209 * the CPUID. Add "volatile" to not allow gcc to
210 * optimize the subsequent calls to this function.
212 asm volatile ("pushfl \n\t"
223 : "=&r" (f1
), "=&r" (f2
)
226 return ((f1
^f2
) & flag
) != 0;
229 /* Probe for the CPUID instruction */
230 int have_cpuid_p(void)
232 return flag_is_changeable_p(X86_EFLAGS_ID
);
235 static void squash_the_stupid_serial_number(struct cpuinfo_x86
*c
)
237 unsigned long lo
, hi
;
239 if (!cpu_has(c
, X86_FEATURE_PN
) || !disable_x86_serial_nr
)
242 /* Disable processor serial number: */
244 rdmsr(MSR_IA32_BBL_CR_CTL
, lo
, hi
);
246 wrmsr(MSR_IA32_BBL_CR_CTL
, lo
, hi
);
248 pr_notice("CPU serial number disabled.\n");
249 clear_cpu_cap(c
, X86_FEATURE_PN
);
251 /* Disabling the serial number may affect the cpuid level */
252 c
->cpuid_level
= cpuid_eax(0);
255 static int __init
x86_serial_nr_setup(char *s
)
257 disable_x86_serial_nr
= 0;
260 __setup("serialnumber", x86_serial_nr_setup
);
262 static inline int flag_is_changeable_p(u32 flag
)
266 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86
*c
)
271 static __init
int setup_disable_smep(char *arg
)
273 setup_clear_cpu_cap(X86_FEATURE_SMEP
);
274 /* Check for things that depend on SMEP being enabled: */
275 check_mpx_erratum(&boot_cpu_data
);
278 __setup("nosmep", setup_disable_smep
);
280 static __always_inline
void setup_smep(struct cpuinfo_x86
*c
)
282 if (cpu_has(c
, X86_FEATURE_SMEP
))
283 cr4_set_bits(X86_CR4_SMEP
);
286 static __init
int setup_disable_smap(char *arg
)
288 setup_clear_cpu_cap(X86_FEATURE_SMAP
);
291 __setup("nosmap", setup_disable_smap
);
293 static __always_inline
void setup_smap(struct cpuinfo_x86
*c
)
295 unsigned long eflags
= native_save_fl();
297 /* This should have been cleared long ago */
298 BUG_ON(eflags
& X86_EFLAGS_AC
);
300 if (cpu_has(c
, X86_FEATURE_SMAP
)) {
301 #ifdef CONFIG_X86_SMAP
302 cr4_set_bits(X86_CR4_SMAP
);
304 cr4_clear_bits(X86_CR4_SMAP
);
310 * Protection Keys are not available in 32-bit mode.
312 static bool pku_disabled
;
314 static __always_inline
void setup_pku(struct cpuinfo_x86
*c
)
316 /* check the boot processor, plus compile options for PKU: */
317 if (!cpu_feature_enabled(X86_FEATURE_PKU
))
319 /* checks the actual processor's cpuid bits: */
320 if (!cpu_has(c
, X86_FEATURE_PKU
))
325 cr4_set_bits(X86_CR4_PKE
);
327 * Seting X86_CR4_PKE will cause the X86_FEATURE_OSPKE
328 * cpuid bit to be set. We need to ensure that we
329 * update that bit in this CPU's "cpu_info".
334 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS
335 static __init
int setup_disable_pku(char *arg
)
338 * Do not clear the X86_FEATURE_PKU bit. All of the
339 * runtime checks are against OSPKE so clearing the
342 * This way, we will see "pku" in cpuinfo, but not
343 * "ospke", which is exactly what we want. It shows
344 * that the CPU has PKU, but the OS has not enabled it.
345 * This happens to be exactly how a system would look
346 * if we disabled the config option.
348 pr_info("x86: 'nopku' specified, disabling Memory Protection Keys\n");
352 __setup("nopku", setup_disable_pku
);
353 #endif /* CONFIG_X86_64 */
356 * Some CPU features depend on higher CPUID levels, which may not always
357 * be available due to CPUID level capping or broken virtualization
358 * software. Add those features to this table to auto-disable them.
360 struct cpuid_dependent_feature
{
365 static const struct cpuid_dependent_feature
366 cpuid_dependent_features
[] = {
367 { X86_FEATURE_MWAIT
, 0x00000005 },
368 { X86_FEATURE_DCA
, 0x00000009 },
369 { X86_FEATURE_XSAVE
, 0x0000000d },
373 static void filter_cpuid_features(struct cpuinfo_x86
*c
, bool warn
)
375 const struct cpuid_dependent_feature
*df
;
377 for (df
= cpuid_dependent_features
; df
->feature
; df
++) {
379 if (!cpu_has(c
, df
->feature
))
382 * Note: cpuid_level is set to -1 if unavailable, but
383 * extended_extended_level is set to 0 if unavailable
384 * and the legitimate extended levels are all negative
385 * when signed; hence the weird messing around with
388 if (!((s32
)df
->level
< 0 ?
389 (u32
)df
->level
> (u32
)c
->extended_cpuid_level
:
390 (s32
)df
->level
> (s32
)c
->cpuid_level
))
393 clear_cpu_cap(c
, df
->feature
);
397 pr_warn("CPU: CPU feature " X86_CAP_FMT
" disabled, no CPUID level 0x%x\n",
398 x86_cap_flag(df
->feature
), df
->level
);
403 * Naming convention should be: <Name> [(<Codename>)]
404 * This table only is used unless init_<vendor>() below doesn't set it;
405 * in particular, if CPUID levels 0x80000002..4 are supported, this
409 /* Look up CPU names by table lookup. */
410 static const char *table_lookup_model(struct cpuinfo_x86
*c
)
413 const struct legacy_cpu_model_info
*info
;
415 if (c
->x86_model
>= 16)
416 return NULL
; /* Range check */
421 info
= this_cpu
->legacy_models
;
423 while (info
->family
) {
424 if (info
->family
== c
->x86
)
425 return info
->model_names
[c
->x86_model
];
429 return NULL
; /* Not found */
432 __u32 cpu_caps_cleared
[NCAPINTS
];
433 __u32 cpu_caps_set
[NCAPINTS
];
435 void load_percpu_segment(int cpu
)
438 loadsegment(fs
, __KERNEL_PERCPU
);
440 __loadsegment_simple(gs
, 0);
441 wrmsrl(MSR_GS_BASE
, (unsigned long)per_cpu(irq_stack_union
.gs_base
, cpu
));
443 load_stack_canary_segment();
447 * Current gdt points %fs at the "master" per-cpu area: after this,
448 * it's on the real one.
450 void switch_to_new_gdt(int cpu
)
452 struct desc_ptr gdt_descr
;
454 gdt_descr
.address
= (long)get_cpu_gdt_table(cpu
);
455 gdt_descr
.size
= GDT_SIZE
- 1;
456 load_gdt(&gdt_descr
);
457 /* Reload the per-cpu base */
459 load_percpu_segment(cpu
);
462 static const struct cpu_dev
*cpu_devs
[X86_VENDOR_NUM
] = {};
464 static void get_model_name(struct cpuinfo_x86
*c
)
469 if (c
->extended_cpuid_level
< 0x80000004)
472 v
= (unsigned int *)c
->x86_model_id
;
473 cpuid(0x80000002, &v
[0], &v
[1], &v
[2], &v
[3]);
474 cpuid(0x80000003, &v
[4], &v
[5], &v
[6], &v
[7]);
475 cpuid(0x80000004, &v
[8], &v
[9], &v
[10], &v
[11]);
476 c
->x86_model_id
[48] = 0;
478 /* Trim whitespace */
479 p
= q
= s
= &c
->x86_model_id
[0];
485 /* Note the last non-whitespace index */
495 void cpu_detect_cache_sizes(struct cpuinfo_x86
*c
)
497 unsigned int n
, dummy
, ebx
, ecx
, edx
, l2size
;
499 n
= c
->extended_cpuid_level
;
501 if (n
>= 0x80000005) {
502 cpuid(0x80000005, &dummy
, &ebx
, &ecx
, &edx
);
503 c
->x86_cache_size
= (ecx
>>24) + (edx
>>24);
505 /* On K8 L1 TLB is inclusive, so don't count it */
510 if (n
< 0x80000006) /* Some chips just has a large L1. */
513 cpuid(0x80000006, &dummy
, &ebx
, &ecx
, &edx
);
517 c
->x86_tlbsize
+= ((ebx
>> 16) & 0xfff) + (ebx
& 0xfff);
519 /* do processor-specific cache resizing */
520 if (this_cpu
->legacy_cache_size
)
521 l2size
= this_cpu
->legacy_cache_size(c
, l2size
);
523 /* Allow user to override all this if necessary. */
524 if (cachesize_override
!= -1)
525 l2size
= cachesize_override
;
528 return; /* Again, no L2 cache is possible */
531 c
->x86_cache_size
= l2size
;
534 u16 __read_mostly tlb_lli_4k
[NR_INFO
];
535 u16 __read_mostly tlb_lli_2m
[NR_INFO
];
536 u16 __read_mostly tlb_lli_4m
[NR_INFO
];
537 u16 __read_mostly tlb_lld_4k
[NR_INFO
];
538 u16 __read_mostly tlb_lld_2m
[NR_INFO
];
539 u16 __read_mostly tlb_lld_4m
[NR_INFO
];
540 u16 __read_mostly tlb_lld_1g
[NR_INFO
];
542 static void cpu_detect_tlb(struct cpuinfo_x86
*c
)
544 if (this_cpu
->c_detect_tlb
)
545 this_cpu
->c_detect_tlb(c
);
547 pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n",
548 tlb_lli_4k
[ENTRIES
], tlb_lli_2m
[ENTRIES
],
549 tlb_lli_4m
[ENTRIES
]);
551 pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n",
552 tlb_lld_4k
[ENTRIES
], tlb_lld_2m
[ENTRIES
],
553 tlb_lld_4m
[ENTRIES
], tlb_lld_1g
[ENTRIES
]);
556 void detect_ht(struct cpuinfo_x86
*c
)
559 u32 eax
, ebx
, ecx
, edx
;
560 int index_msb
, core_bits
;
563 if (!cpu_has(c
, X86_FEATURE_HT
))
566 if (cpu_has(c
, X86_FEATURE_CMP_LEGACY
))
569 if (cpu_has(c
, X86_FEATURE_XTOPOLOGY
))
572 cpuid(1, &eax
, &ebx
, &ecx
, &edx
);
574 smp_num_siblings
= (ebx
& 0xff0000) >> 16;
576 if (smp_num_siblings
== 1) {
577 pr_info_once("CPU0: Hyper-Threading is disabled\n");
581 if (smp_num_siblings
<= 1)
584 index_msb
= get_count_order(smp_num_siblings
);
585 c
->phys_proc_id
= apic
->phys_pkg_id(c
->initial_apicid
, index_msb
);
587 smp_num_siblings
= smp_num_siblings
/ c
->x86_max_cores
;
589 index_msb
= get_count_order(smp_num_siblings
);
591 core_bits
= get_count_order(c
->x86_max_cores
);
593 c
->cpu_core_id
= apic
->phys_pkg_id(c
->initial_apicid
, index_msb
) &
594 ((1 << core_bits
) - 1);
597 if (!printed
&& (c
->x86_max_cores
* smp_num_siblings
) > 1) {
598 pr_info("CPU: Physical Processor ID: %d\n",
600 pr_info("CPU: Processor Core ID: %d\n",
607 static void get_cpu_vendor(struct cpuinfo_x86
*c
)
609 char *v
= c
->x86_vendor_id
;
612 for (i
= 0; i
< X86_VENDOR_NUM
; i
++) {
616 if (!strcmp(v
, cpu_devs
[i
]->c_ident
[0]) ||
617 (cpu_devs
[i
]->c_ident
[1] &&
618 !strcmp(v
, cpu_devs
[i
]->c_ident
[1]))) {
620 this_cpu
= cpu_devs
[i
];
621 c
->x86_vendor
= this_cpu
->c_x86_vendor
;
626 pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \
627 "CPU: Your system may be unstable.\n", v
);
629 c
->x86_vendor
= X86_VENDOR_UNKNOWN
;
630 this_cpu
= &default_cpu
;
633 void cpu_detect(struct cpuinfo_x86
*c
)
635 /* Get vendor name */
636 cpuid(0x00000000, (unsigned int *)&c
->cpuid_level
,
637 (unsigned int *)&c
->x86_vendor_id
[0],
638 (unsigned int *)&c
->x86_vendor_id
[8],
639 (unsigned int *)&c
->x86_vendor_id
[4]);
642 /* Intel-defined flags: level 0x00000001 */
643 if (c
->cpuid_level
>= 0x00000001) {
644 u32 junk
, tfms
, cap0
, misc
;
646 cpuid(0x00000001, &tfms
, &misc
, &junk
, &cap0
);
647 c
->x86
= x86_family(tfms
);
648 c
->x86_model
= x86_model(tfms
);
649 c
->x86_mask
= x86_stepping(tfms
);
651 if (cap0
& (1<<19)) {
652 c
->x86_clflush_size
= ((misc
>> 8) & 0xff) * 8;
653 c
->x86_cache_alignment
= c
->x86_clflush_size
;
658 void get_cpu_cap(struct cpuinfo_x86
*c
)
660 u32 eax
, ebx
, ecx
, edx
;
662 /* Intel-defined flags: level 0x00000001 */
663 if (c
->cpuid_level
>= 0x00000001) {
664 cpuid(0x00000001, &eax
, &ebx
, &ecx
, &edx
);
666 c
->x86_capability
[CPUID_1_ECX
] = ecx
;
667 c
->x86_capability
[CPUID_1_EDX
] = edx
;
670 /* Additional Intel-defined flags: level 0x00000007 */
671 if (c
->cpuid_level
>= 0x00000007) {
672 cpuid_count(0x00000007, 0, &eax
, &ebx
, &ecx
, &edx
);
674 c
->x86_capability
[CPUID_7_0_EBX
] = ebx
;
676 c
->x86_capability
[CPUID_6_EAX
] = cpuid_eax(0x00000006);
677 c
->x86_capability
[CPUID_7_ECX
] = ecx
;
680 /* Extended state features: level 0x0000000d */
681 if (c
->cpuid_level
>= 0x0000000d) {
682 cpuid_count(0x0000000d, 1, &eax
, &ebx
, &ecx
, &edx
);
684 c
->x86_capability
[CPUID_D_1_EAX
] = eax
;
687 /* Additional Intel-defined flags: level 0x0000000F */
688 if (c
->cpuid_level
>= 0x0000000F) {
690 /* QoS sub-leaf, EAX=0Fh, ECX=0 */
691 cpuid_count(0x0000000F, 0, &eax
, &ebx
, &ecx
, &edx
);
692 c
->x86_capability
[CPUID_F_0_EDX
] = edx
;
694 if (cpu_has(c
, X86_FEATURE_CQM_LLC
)) {
695 /* will be overridden if occupancy monitoring exists */
696 c
->x86_cache_max_rmid
= ebx
;
698 /* QoS sub-leaf, EAX=0Fh, ECX=1 */
699 cpuid_count(0x0000000F, 1, &eax
, &ebx
, &ecx
, &edx
);
700 c
->x86_capability
[CPUID_F_1_EDX
] = edx
;
702 if ((cpu_has(c
, X86_FEATURE_CQM_OCCUP_LLC
)) ||
703 ((cpu_has(c
, X86_FEATURE_CQM_MBM_TOTAL
)) ||
704 (cpu_has(c
, X86_FEATURE_CQM_MBM_LOCAL
)))) {
705 c
->x86_cache_max_rmid
= ecx
;
706 c
->x86_cache_occ_scale
= ebx
;
709 c
->x86_cache_max_rmid
= -1;
710 c
->x86_cache_occ_scale
= -1;
714 /* AMD-defined flags: level 0x80000001 */
715 eax
= cpuid_eax(0x80000000);
716 c
->extended_cpuid_level
= eax
;
718 if ((eax
& 0xffff0000) == 0x80000000) {
719 if (eax
>= 0x80000001) {
720 cpuid(0x80000001, &eax
, &ebx
, &ecx
, &edx
);
722 c
->x86_capability
[CPUID_8000_0001_ECX
] = ecx
;
723 c
->x86_capability
[CPUID_8000_0001_EDX
] = edx
;
727 if (c
->extended_cpuid_level
>= 0x80000007) {
728 cpuid(0x80000007, &eax
, &ebx
, &ecx
, &edx
);
730 c
->x86_capability
[CPUID_8000_0007_EBX
] = ebx
;
734 if (c
->extended_cpuid_level
>= 0x80000008) {
735 cpuid(0x80000008, &eax
, &ebx
, &ecx
, &edx
);
737 c
->x86_virt_bits
= (eax
>> 8) & 0xff;
738 c
->x86_phys_bits
= eax
& 0xff;
739 c
->x86_capability
[CPUID_8000_0008_EBX
] = ebx
;
742 else if (cpu_has(c
, X86_FEATURE_PAE
) || cpu_has(c
, X86_FEATURE_PSE36
))
743 c
->x86_phys_bits
= 36;
746 if (c
->extended_cpuid_level
>= 0x8000000a)
747 c
->x86_capability
[CPUID_8000_000A_EDX
] = cpuid_edx(0x8000000a);
749 init_scattered_cpuid_features(c
);
752 static void identify_cpu_without_cpuid(struct cpuinfo_x86
*c
)
758 * First of all, decide if this is a 486 or higher
759 * It's a 486 if we can modify the AC flag
761 if (flag_is_changeable_p(X86_EFLAGS_AC
))
766 for (i
= 0; i
< X86_VENDOR_NUM
; i
++)
767 if (cpu_devs
[i
] && cpu_devs
[i
]->c_identify
) {
768 c
->x86_vendor_id
[0] = 0;
769 cpu_devs
[i
]->c_identify(c
);
770 if (c
->x86_vendor_id
[0]) {
779 * Do minimum CPU detection early.
780 * Fields really needed: vendor, cpuid_level, family, model, mask,
782 * The others are not touched to avoid unwanted side effects.
784 * WARNING: this function is only called on the BP. Don't add code here
785 * that is supposed to run on all CPUs.
787 static void __init
early_identify_cpu(struct cpuinfo_x86
*c
)
790 c
->x86_clflush_size
= 64;
791 c
->x86_phys_bits
= 36;
792 c
->x86_virt_bits
= 48;
794 c
->x86_clflush_size
= 32;
795 c
->x86_phys_bits
= 32;
796 c
->x86_virt_bits
= 32;
798 c
->x86_cache_alignment
= c
->x86_clflush_size
;
800 memset(&c
->x86_capability
, 0, sizeof c
->x86_capability
);
801 c
->extended_cpuid_level
= 0;
804 identify_cpu_without_cpuid(c
);
806 /* cyrix could have cpuid enabled via c_identify()*/
814 if (this_cpu
->c_early_init
)
815 this_cpu
->c_early_init(c
);
818 filter_cpuid_features(c
, false);
820 if (this_cpu
->c_bsp_init
)
821 this_cpu
->c_bsp_init(c
);
823 setup_force_cpu_cap(X86_FEATURE_ALWAYS
);
827 void __init
early_cpu_init(void)
829 const struct cpu_dev
*const *cdev
;
832 #ifdef CONFIG_PROCESSOR_SELECT
833 pr_info("KERNEL supported cpus:\n");
836 for (cdev
= __x86_cpu_dev_start
; cdev
< __x86_cpu_dev_end
; cdev
++) {
837 const struct cpu_dev
*cpudev
= *cdev
;
839 if (count
>= X86_VENDOR_NUM
)
841 cpu_devs
[count
] = cpudev
;
844 #ifdef CONFIG_PROCESSOR_SELECT
848 for (j
= 0; j
< 2; j
++) {
849 if (!cpudev
->c_ident
[j
])
851 pr_info(" %s %s\n", cpudev
->c_vendor
,
857 early_identify_cpu(&boot_cpu_data
);
861 * The NOPL instruction is supposed to exist on all CPUs of family >= 6;
862 * unfortunately, that's not true in practice because of early VIA
863 * chips and (more importantly) broken virtualizers that are not easy
864 * to detect. In the latter case it doesn't even *fail* reliably, so
865 * probing for it doesn't even work. Disable it completely on 32-bit
866 * unless we can find a reliable way to detect all the broken cases.
867 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has().
869 static void detect_nopl(struct cpuinfo_x86
*c
)
872 clear_cpu_cap(c
, X86_FEATURE_NOPL
);
874 set_cpu_cap(c
, X86_FEATURE_NOPL
);
878 static void detect_null_seg_behavior(struct cpuinfo_x86
*c
)
882 * Empirically, writing zero to a segment selector on AMD does
883 * not clear the base, whereas writing zero to a segment
884 * selector on Intel does clear the base. Intel's behavior
885 * allows slightly faster context switches in the common case
886 * where GS is unused by the prev and next threads.
888 * Since neither vendor documents this anywhere that I can see,
889 * detect it directly instead of hardcoding the choice by
892 * I've designated AMD's behavior as the "bug" because it's
893 * counterintuitive and less friendly.
896 unsigned long old_base
, tmp
;
897 rdmsrl(MSR_FS_BASE
, old_base
);
898 wrmsrl(MSR_FS_BASE
, 1);
900 rdmsrl(MSR_FS_BASE
, tmp
);
902 set_cpu_bug(c
, X86_BUG_NULL_SEG
);
903 wrmsrl(MSR_FS_BASE
, old_base
);
907 static void generic_identify(struct cpuinfo_x86
*c
)
909 c
->extended_cpuid_level
= 0;
912 identify_cpu_without_cpuid(c
);
914 /* cyrix could have cpuid enabled via c_identify()*/
924 if (c
->cpuid_level
>= 0x00000001) {
925 c
->initial_apicid
= (cpuid_ebx(1) >> 24) & 0xFF;
928 c
->apicid
= apic
->phys_pkg_id(c
->initial_apicid
, 0);
930 c
->apicid
= c
->initial_apicid
;
933 c
->phys_proc_id
= c
->initial_apicid
;
936 get_model_name(c
); /* Default name */
940 detect_null_seg_behavior(c
);
943 * ESPFIX is a strange bug. All real CPUs have it. Paravirt
944 * systems that run Linux at CPL > 0 may or may not have the
945 * issue, but, even if they have the issue, there's absolutely
946 * nothing we can do about it because we can't use the real IRET
949 * NB: For the time being, only 32-bit kernels support
950 * X86_BUG_ESPFIX as such. 64-bit kernels directly choose
951 * whether to apply espfix using paravirt hooks. If any
952 * non-paravirt system ever shows up that does *not* have the
953 * ESPFIX issue, we can change this.
956 # ifdef CONFIG_PARAVIRT
958 extern void native_iret(void);
959 if (pv_cpu_ops
.iret
== native_iret
)
960 set_cpu_bug(c
, X86_BUG_ESPFIX
);
963 set_cpu_bug(c
, X86_BUG_ESPFIX
);
968 static void x86_init_cache_qos(struct cpuinfo_x86
*c
)
971 * The heavy lifting of max_rmid and cache_occ_scale are handled
972 * in get_cpu_cap(). Here we just set the max_rmid for the boot_cpu
973 * in case CQM bits really aren't there in this CPU.
975 if (c
!= &boot_cpu_data
) {
976 boot_cpu_data
.x86_cache_max_rmid
=
977 min(boot_cpu_data
.x86_cache_max_rmid
,
978 c
->x86_cache_max_rmid
);
983 * This does the hard work of actually picking apart the CPU stuff...
985 static void identify_cpu(struct cpuinfo_x86
*c
)
989 c
->loops_per_jiffy
= loops_per_jiffy
;
990 c
->x86_cache_size
= -1;
991 c
->x86_vendor
= X86_VENDOR_UNKNOWN
;
992 c
->x86_model
= c
->x86_mask
= 0; /* So far unknown... */
993 c
->x86_vendor_id
[0] = '\0'; /* Unset */
994 c
->x86_model_id
[0] = '\0'; /* Unset */
995 c
->x86_max_cores
= 1;
996 c
->x86_coreid_bits
= 0;
998 c
->x86_clflush_size
= 64;
999 c
->x86_phys_bits
= 36;
1000 c
->x86_virt_bits
= 48;
1002 c
->cpuid_level
= -1; /* CPUID not detected */
1003 c
->x86_clflush_size
= 32;
1004 c
->x86_phys_bits
= 32;
1005 c
->x86_virt_bits
= 32;
1007 c
->x86_cache_alignment
= c
->x86_clflush_size
;
1008 memset(&c
->x86_capability
, 0, sizeof c
->x86_capability
);
1010 generic_identify(c
);
1012 if (this_cpu
->c_identify
)
1013 this_cpu
->c_identify(c
);
1015 /* Clear/Set all flags overridden by options, after probe */
1016 for (i
= 0; i
< NCAPINTS
; i
++) {
1017 c
->x86_capability
[i
] &= ~cpu_caps_cleared
[i
];
1018 c
->x86_capability
[i
] |= cpu_caps_set
[i
];
1021 #ifdef CONFIG_X86_64
1022 c
->apicid
= apic
->phys_pkg_id(c
->initial_apicid
, 0);
1026 * Vendor-specific initialization. In this section we
1027 * canonicalize the feature flags, meaning if there are
1028 * features a certain CPU supports which CPUID doesn't
1029 * tell us, CPUID claiming incorrect flags, or other bugs,
1030 * we handle them here.
1032 * At the end of this section, c->x86_capability better
1033 * indicate the features this CPU genuinely supports!
1035 if (this_cpu
->c_init
)
1036 this_cpu
->c_init(c
);
1038 /* Disable the PN if appropriate */
1039 squash_the_stupid_serial_number(c
);
1041 /* Set up SMEP/SMAP */
1046 * The vendor-specific functions might have changed features.
1047 * Now we do "generic changes."
1050 /* Filter out anything that depends on CPUID levels we don't have */
1051 filter_cpuid_features(c
, true);
1053 /* If the model name is still unset, do table lookup. */
1054 if (!c
->x86_model_id
[0]) {
1056 p
= table_lookup_model(c
);
1058 strcpy(c
->x86_model_id
, p
);
1060 /* Last resort... */
1061 sprintf(c
->x86_model_id
, "%02x/%02x",
1062 c
->x86
, c
->x86_model
);
1065 #ifdef CONFIG_X86_64
1071 x86_init_cache_qos(c
);
1075 * Clear/Set all flags overridden by options, need do it
1076 * before following smp all cpus cap AND.
1078 for (i
= 0; i
< NCAPINTS
; i
++) {
1079 c
->x86_capability
[i
] &= ~cpu_caps_cleared
[i
];
1080 c
->x86_capability
[i
] |= cpu_caps_set
[i
];
1084 * On SMP, boot_cpu_data holds the common feature set between
1085 * all CPUs; so make sure that we indicate which features are
1086 * common between the CPUs. The first time this routine gets
1087 * executed, c == &boot_cpu_data.
1089 if (c
!= &boot_cpu_data
) {
1090 /* AND the already accumulated flags with these */
1091 for (i
= 0; i
< NCAPINTS
; i
++)
1092 boot_cpu_data
.x86_capability
[i
] &= c
->x86_capability
[i
];
1094 /* OR, i.e. replicate the bug flags */
1095 for (i
= NCAPINTS
; i
< NCAPINTS
+ NBUGINTS
; i
++)
1096 c
->x86_capability
[i
] |= boot_cpu_data
.x86_capability
[i
];
1099 /* Init Machine Check Exception if available. */
1102 select_idle_routine(c
);
1105 numa_add_cpu(smp_processor_id());
1107 /* The boot/hotplug time assigment got cleared, restore it */
1108 c
->logical_proc_id
= topology_phys_to_logical_pkg(c
->phys_proc_id
);
1112 * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions
1113 * on 32-bit kernels:
1115 #ifdef CONFIG_X86_32
1116 void enable_sep_cpu(void)
1118 struct tss_struct
*tss
;
1121 if (!boot_cpu_has(X86_FEATURE_SEP
))
1125 tss
= &per_cpu(cpu_tss
, cpu
);
1128 * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field --
1129 * see the big comment in struct x86_hw_tss's definition.
1132 tss
->x86_tss
.ss1
= __KERNEL_CS
;
1133 wrmsr(MSR_IA32_SYSENTER_CS
, tss
->x86_tss
.ss1
, 0);
1135 wrmsr(MSR_IA32_SYSENTER_ESP
,
1136 (unsigned long)tss
+ offsetofend(struct tss_struct
, SYSENTER_stack
),
1139 wrmsr(MSR_IA32_SYSENTER_EIP
, (unsigned long)entry_SYSENTER_32
, 0);
1145 void __init
identify_boot_cpu(void)
1147 identify_cpu(&boot_cpu_data
);
1148 init_amd_e400_c1e_mask();
1149 #ifdef CONFIG_X86_32
1153 cpu_detect_tlb(&boot_cpu_data
);
1156 void identify_secondary_cpu(struct cpuinfo_x86
*c
)
1158 BUG_ON(c
== &boot_cpu_data
);
1160 #ifdef CONFIG_X86_32
1171 static const struct msr_range msr_range_array
[] = {
1172 { 0x00000000, 0x00000418},
1173 { 0xc0000000, 0xc000040b},
1174 { 0xc0010000, 0xc0010142},
1175 { 0xc0011000, 0xc001103b},
1178 static void __print_cpu_msr(void)
1180 unsigned index_min
, index_max
;
1185 for (i
= 0; i
< ARRAY_SIZE(msr_range_array
); i
++) {
1186 index_min
= msr_range_array
[i
].min
;
1187 index_max
= msr_range_array
[i
].max
;
1189 for (index
= index_min
; index
< index_max
; index
++) {
1190 if (rdmsrl_safe(index
, &val
))
1192 pr_info(" MSR%08x: %016llx\n", index
, val
);
1197 static int show_msr
;
1199 static __init
int setup_show_msr(char *arg
)
1203 get_option(&arg
, &num
);
1209 __setup("show_msr=", setup_show_msr
);
1211 static __init
int setup_noclflush(char *arg
)
1213 setup_clear_cpu_cap(X86_FEATURE_CLFLUSH
);
1214 setup_clear_cpu_cap(X86_FEATURE_CLFLUSHOPT
);
1217 __setup("noclflush", setup_noclflush
);
1219 void print_cpu_info(struct cpuinfo_x86
*c
)
1221 const char *vendor
= NULL
;
1223 if (c
->x86_vendor
< X86_VENDOR_NUM
) {
1224 vendor
= this_cpu
->c_vendor
;
1226 if (c
->cpuid_level
>= 0)
1227 vendor
= c
->x86_vendor_id
;
1230 if (vendor
&& !strstr(c
->x86_model_id
, vendor
))
1231 pr_cont("%s ", vendor
);
1233 if (c
->x86_model_id
[0])
1234 pr_cont("%s", c
->x86_model_id
);
1236 pr_cont("%d86", c
->x86
);
1238 pr_cont(" (family: 0x%x, model: 0x%x", c
->x86
, c
->x86_model
);
1240 if (c
->x86_mask
|| c
->cpuid_level
>= 0)
1241 pr_cont(", stepping: 0x%x)\n", c
->x86_mask
);
1248 void print_cpu_msr(struct cpuinfo_x86
*c
)
1250 if (c
->cpu_index
< show_msr
)
1254 static __init
int setup_disablecpuid(char *arg
)
1258 if (get_option(&arg
, &bit
) && bit
< NCAPINTS
*32)
1259 setup_clear_cpu_cap(bit
);
1265 __setup("clearcpuid=", setup_disablecpuid
);
1267 #ifdef CONFIG_X86_64
1268 struct desc_ptr idt_descr
= { NR_VECTORS
* 16 - 1, (unsigned long) idt_table
};
1269 struct desc_ptr debug_idt_descr
= { NR_VECTORS
* 16 - 1,
1270 (unsigned long) debug_idt_table
};
1272 DEFINE_PER_CPU_FIRST(union irq_stack_union
,
1273 irq_stack_union
) __aligned(PAGE_SIZE
) __visible
;
1276 * The following percpu variables are hot. Align current_task to
1277 * cacheline size such that they fall in the same cacheline.
1279 DEFINE_PER_CPU(struct task_struct
*, current_task
) ____cacheline_aligned
=
1281 EXPORT_PER_CPU_SYMBOL(current_task
);
1283 DEFINE_PER_CPU(char *, irq_stack_ptr
) =
1284 init_per_cpu_var(irq_stack_union
.irq_stack
) + IRQ_STACK_SIZE
- 64;
1286 DEFINE_PER_CPU(unsigned int, irq_count
) __visible
= -1;
1288 DEFINE_PER_CPU(int, __preempt_count
) = INIT_PREEMPT_COUNT
;
1289 EXPORT_PER_CPU_SYMBOL(__preempt_count
);
1292 * Special IST stacks which the CPU switches to when it calls
1293 * an IST-marked descriptor entry. Up to 7 stacks (hardware
1294 * limit), all of them are 4K, except the debug stack which
1297 static const unsigned int exception_stack_sizes
[N_EXCEPTION_STACKS
] = {
1298 [0 ... N_EXCEPTION_STACKS
- 1] = EXCEPTION_STKSZ
,
1299 [DEBUG_STACK
- 1] = DEBUG_STKSZ
1302 static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks
1303 [(N_EXCEPTION_STACKS
- 1) * EXCEPTION_STKSZ
+ DEBUG_STKSZ
]);
1305 /* May not be marked __init: used by software suspend */
1306 void syscall_init(void)
1309 * LSTAR and STAR live in a bit strange symbiosis.
1310 * They both write to the same internal register. STAR allows to
1311 * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip.
1313 wrmsr(MSR_STAR
, 0, (__USER32_CS
<< 16) | __KERNEL_CS
);
1314 wrmsrl(MSR_LSTAR
, (unsigned long)entry_SYSCALL_64
);
1316 #ifdef CONFIG_IA32_EMULATION
1317 wrmsrl(MSR_CSTAR
, (unsigned long)entry_SYSCALL_compat
);
1319 * This only works on Intel CPUs.
1320 * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP.
1321 * This does not cause SYSENTER to jump to the wrong location, because
1322 * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit).
1324 wrmsrl_safe(MSR_IA32_SYSENTER_CS
, (u64
)__KERNEL_CS
);
1325 wrmsrl_safe(MSR_IA32_SYSENTER_ESP
, 0ULL);
1326 wrmsrl_safe(MSR_IA32_SYSENTER_EIP
, (u64
)entry_SYSENTER_compat
);
1328 wrmsrl(MSR_CSTAR
, (unsigned long)ignore_sysret
);
1329 wrmsrl_safe(MSR_IA32_SYSENTER_CS
, (u64
)GDT_ENTRY_INVALID_SEG
);
1330 wrmsrl_safe(MSR_IA32_SYSENTER_ESP
, 0ULL);
1331 wrmsrl_safe(MSR_IA32_SYSENTER_EIP
, 0ULL);
1334 /* Flags to clear on syscall */
1335 wrmsrl(MSR_SYSCALL_MASK
,
1336 X86_EFLAGS_TF
|X86_EFLAGS_DF
|X86_EFLAGS_IF
|
1337 X86_EFLAGS_IOPL
|X86_EFLAGS_AC
|X86_EFLAGS_NT
);
1341 * Copies of the original ist values from the tss are only accessed during
1342 * debugging, no special alignment required.
1344 DEFINE_PER_CPU(struct orig_ist
, orig_ist
);
1346 static DEFINE_PER_CPU(unsigned long, debug_stack_addr
);
1347 DEFINE_PER_CPU(int, debug_stack_usage
);
1349 int is_debug_stack(unsigned long addr
)
1351 return __this_cpu_read(debug_stack_usage
) ||
1352 (addr
<= __this_cpu_read(debug_stack_addr
) &&
1353 addr
> (__this_cpu_read(debug_stack_addr
) - DEBUG_STKSZ
));
1355 NOKPROBE_SYMBOL(is_debug_stack
);
1357 DEFINE_PER_CPU(u32
, debug_idt_ctr
);
1359 void debug_stack_set_zero(void)
1361 this_cpu_inc(debug_idt_ctr
);
1364 NOKPROBE_SYMBOL(debug_stack_set_zero
);
1366 void debug_stack_reset(void)
1368 if (WARN_ON(!this_cpu_read(debug_idt_ctr
)))
1370 if (this_cpu_dec_return(debug_idt_ctr
) == 0)
1373 NOKPROBE_SYMBOL(debug_stack_reset
);
1375 #else /* CONFIG_X86_64 */
1377 DEFINE_PER_CPU(struct task_struct
*, current_task
) = &init_task
;
1378 EXPORT_PER_CPU_SYMBOL(current_task
);
1379 DEFINE_PER_CPU(int, __preempt_count
) = INIT_PREEMPT_COUNT
;
1380 EXPORT_PER_CPU_SYMBOL(__preempt_count
);
1383 * On x86_32, vm86 modifies tss.sp0, so sp0 isn't a reliable way to find
1384 * the top of the kernel stack. Use an extra percpu variable to track the
1385 * top of the kernel stack directly.
1387 DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack
) =
1388 (unsigned long)&init_thread_union
+ THREAD_SIZE
;
1389 EXPORT_PER_CPU_SYMBOL(cpu_current_top_of_stack
);
1391 #ifdef CONFIG_CC_STACKPROTECTOR
1392 DEFINE_PER_CPU_ALIGNED(struct stack_canary
, stack_canary
);
1395 #endif /* CONFIG_X86_64 */
1398 * Clear all 6 debug registers:
1400 static void clear_all_debug_regs(void)
1404 for (i
= 0; i
< 8; i
++) {
1405 /* Ignore db4, db5 */
1406 if ((i
== 4) || (i
== 5))
1415 * Restore debug regs if using kgdbwait and you have a kernel debugger
1416 * connection established.
1418 static void dbg_restore_debug_regs(void)
1420 if (unlikely(kgdb_connected
&& arch_kgdb_ops
.correct_hw_break
))
1421 arch_kgdb_ops
.correct_hw_break();
1423 #else /* ! CONFIG_KGDB */
1424 #define dbg_restore_debug_regs()
1425 #endif /* ! CONFIG_KGDB */
1427 static void wait_for_master_cpu(int cpu
)
1431 * wait for ACK from master CPU before continuing
1432 * with AP initialization
1434 WARN_ON(cpumask_test_and_set_cpu(cpu
, cpu_initialized_mask
));
1435 while (!cpumask_test_cpu(cpu
, cpu_callout_mask
))
1441 * cpu_init() initializes state that is per-CPU. Some data is already
1442 * initialized (naturally) in the bootstrap process, such as the GDT
1443 * and IDT. We reload them nevertheless, this function acts as a
1444 * 'CPU state barrier', nothing should get across.
1445 * A lot of state is already set up in PDA init for 64 bit
1447 #ifdef CONFIG_X86_64
1451 struct orig_ist
*oist
;
1452 struct task_struct
*me
;
1453 struct tss_struct
*t
;
1455 int cpu
= raw_smp_processor_id();
1458 wait_for_master_cpu(cpu
);
1461 * Initialize the CR4 shadow before doing anything that could
1467 * Load microcode on this cpu if a valid microcode is available.
1468 * This is early microcode loading procedure.
1472 t
= &per_cpu(cpu_tss
, cpu
);
1473 oist
= &per_cpu(orig_ist
, cpu
);
1476 if (this_cpu_read(numa_node
) == 0 &&
1477 early_cpu_to_node(cpu
) != NUMA_NO_NODE
)
1478 set_numa_node(early_cpu_to_node(cpu
));
1483 pr_debug("Initializing CPU#%d\n", cpu
);
1485 cr4_clear_bits(X86_CR4_VME
|X86_CR4_PVI
|X86_CR4_TSD
|X86_CR4_DE
);
1488 * Initialize the per-CPU GDT with the boot GDT,
1489 * and set up the GDT descriptor:
1492 switch_to_new_gdt(cpu
);
1497 memset(me
->thread
.tls_array
, 0, GDT_ENTRY_TLS_ENTRIES
* 8);
1500 wrmsrl(MSR_FS_BASE
, 0);
1501 wrmsrl(MSR_KERNEL_GS_BASE
, 0);
1508 * set up and load the per-CPU TSS
1510 if (!oist
->ist
[0]) {
1511 char *estacks
= per_cpu(exception_stacks
, cpu
);
1513 for (v
= 0; v
< N_EXCEPTION_STACKS
; v
++) {
1514 estacks
+= exception_stack_sizes
[v
];
1515 oist
->ist
[v
] = t
->x86_tss
.ist
[v
] =
1516 (unsigned long)estacks
;
1517 if (v
== DEBUG_STACK
-1)
1518 per_cpu(debug_stack_addr
, cpu
) = (unsigned long)estacks
;
1522 t
->x86_tss
.io_bitmap_base
= offsetof(struct tss_struct
, io_bitmap
);
1525 * <= is required because the CPU will access up to
1526 * 8 bits beyond the end of the IO permission bitmap.
1528 for (i
= 0; i
<= IO_BITMAP_LONGS
; i
++)
1529 t
->io_bitmap
[i
] = ~0UL;
1531 atomic_inc(&init_mm
.mm_count
);
1532 me
->active_mm
= &init_mm
;
1534 enter_lazy_tlb(&init_mm
, me
);
1536 load_sp0(t
, ¤t
->thread
);
1537 set_tss_desc(cpu
, t
);
1539 load_mm_ldt(&init_mm
);
1541 clear_all_debug_regs();
1542 dbg_restore_debug_regs();
1554 int cpu
= smp_processor_id();
1555 struct task_struct
*curr
= current
;
1556 struct tss_struct
*t
= &per_cpu(cpu_tss
, cpu
);
1557 struct thread_struct
*thread
= &curr
->thread
;
1559 wait_for_master_cpu(cpu
);
1562 * Initialize the CR4 shadow before doing anything that could
1567 show_ucode_info_early();
1569 pr_info("Initializing CPU#%d\n", cpu
);
1571 if (cpu_feature_enabled(X86_FEATURE_VME
) ||
1572 boot_cpu_has(X86_FEATURE_TSC
) ||
1573 boot_cpu_has(X86_FEATURE_DE
))
1574 cr4_clear_bits(X86_CR4_VME
|X86_CR4_PVI
|X86_CR4_TSD
|X86_CR4_DE
);
1577 switch_to_new_gdt(cpu
);
1580 * Set up and load the per-CPU TSS and LDT
1582 atomic_inc(&init_mm
.mm_count
);
1583 curr
->active_mm
= &init_mm
;
1585 enter_lazy_tlb(&init_mm
, curr
);
1587 load_sp0(t
, thread
);
1588 set_tss_desc(cpu
, t
);
1590 load_mm_ldt(&init_mm
);
1592 t
->x86_tss
.io_bitmap_base
= offsetof(struct tss_struct
, io_bitmap
);
1594 #ifdef CONFIG_DOUBLEFAULT
1595 /* Set up doublefault TSS pointer in the GDT */
1596 __set_tss_desc(cpu
, GDT_ENTRY_DOUBLEFAULT_TSS
, &doublefault_tss
);
1599 clear_all_debug_regs();
1600 dbg_restore_debug_regs();
1606 static void bsp_resume(void)
1608 if (this_cpu
->c_bsp_resume
)
1609 this_cpu
->c_bsp_resume(&boot_cpu_data
);
1612 static struct syscore_ops cpu_syscore_ops
= {
1613 .resume
= bsp_resume
,
1616 static int __init
init_cpu_syscore(void)
1618 register_syscore_ops(&cpu_syscore_ops
);
1621 core_initcall(init_cpu_syscore
);