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[deliverable/linux.git] / arch / x86 / kernel / cpu / common_64.c
1 #include <linux/init.h>
2 #include <linux/kernel.h>
3 #include <linux/sched.h>
4 #include <linux/string.h>
5 #include <linux/bootmem.h>
6 #include <linux/bitops.h>
7 #include <linux/module.h>
8 #include <linux/kgdb.h>
9 #include <linux/topology.h>
10 #include <linux/delay.h>
11 #include <linux/smp.h>
12 #include <linux/percpu.h>
13 #include <asm/i387.h>
14 #include <asm/msr.h>
15 #include <asm/io.h>
16 #include <asm/linkage.h>
17 #include <asm/mmu_context.h>
18 #include <asm/mtrr.h>
19 #include <asm/mce.h>
20 #include <asm/pat.h>
21 #include <asm/asm.h>
22 #include <asm/numa.h>
23 #ifdef CONFIG_X86_LOCAL_APIC
24 #include <asm/mpspec.h>
25 #include <asm/apic.h>
26 #include <mach_apic.h>
27 #include <asm/genapic.h>
28 #endif
29 #include <asm/pda.h>
30 #include <asm/pgtable.h>
31 #include <asm/processor.h>
32 #include <asm/desc.h>
33 #include <asm/atomic.h>
34 #include <asm/proto.h>
35 #include <asm/sections.h>
36 #include <asm/setup.h>
37
38 #include "cpu.h"
39
40 static struct cpu_dev *this_cpu __cpuinitdata;
41
42 #ifdef CONFIG_X86_64
43 /* We need valid kernel segments for data and code in long mode too
44 * IRET will check the segment types kkeil 2000/10/28
45 * Also sysret mandates a special GDT layout
46 */
47 /* The TLS descriptors are currently at a different place compared to i386.
48 Hopefully nobody expects them at a fixed place (Wine?) */
49 DEFINE_PER_CPU(struct gdt_page, gdt_page) = { .gdt = {
50 [GDT_ENTRY_KERNEL32_CS] = { { { 0x0000ffff, 0x00cf9b00 } } },
51 [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00af9b00 } } },
52 [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9300 } } },
53 [GDT_ENTRY_DEFAULT_USER32_CS] = { { { 0x0000ffff, 0x00cffb00 } } },
54 [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff300 } } },
55 [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00affb00 } } },
56 } };
57 #else
58 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = {
59 [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00cf9a00 } } },
60 [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9200 } } },
61 [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00cffa00 } } },
62 [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff200 } } },
63 /*
64 * Segments used for calling PnP BIOS have byte granularity.
65 * They code segments and data segments have fixed 64k limits,
66 * the transfer segment sizes are set at run time.
67 */
68 /* 32-bit code */
69 [GDT_ENTRY_PNPBIOS_CS32] = { { { 0x0000ffff, 0x00409a00 } } },
70 /* 16-bit code */
71 [GDT_ENTRY_PNPBIOS_CS16] = { { { 0x0000ffff, 0x00009a00 } } },
72 /* 16-bit data */
73 [GDT_ENTRY_PNPBIOS_DS] = { { { 0x0000ffff, 0x00009200 } } },
74 /* 16-bit data */
75 [GDT_ENTRY_PNPBIOS_TS1] = { { { 0x00000000, 0x00009200 } } },
76 /* 16-bit data */
77 [GDT_ENTRY_PNPBIOS_TS2] = { { { 0x00000000, 0x00009200 } } },
78 /*
79 * The APM segments have byte granularity and their bases
80 * are set at run time. All have 64k limits.
81 */
82 /* 32-bit code */
83 [GDT_ENTRY_APMBIOS_BASE] = { { { 0x0000ffff, 0x00409a00 } } },
84 /* 16-bit code */
85 [GDT_ENTRY_APMBIOS_BASE+1] = { { { 0x0000ffff, 0x00009a00 } } },
86 /* data */
87 [GDT_ENTRY_APMBIOS_BASE+2] = { { { 0x0000ffff, 0x00409200 } } },
88
89 [GDT_ENTRY_ESPFIX_SS] = { { { 0x00000000, 0x00c09200 } } },
90 [GDT_ENTRY_PERCPU] = { { { 0x00000000, 0x00000000 } } },
91 } };
92 #endif
93 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page);
94
95 #ifdef CONFIG_X86_32
96 static int cachesize_override __cpuinitdata = -1;
97 static int disable_x86_serial_nr __cpuinitdata = 1;
98
99 static int __init cachesize_setup(char *str)
100 {
101 get_option(&str, &cachesize_override);
102 return 1;
103 }
104 __setup("cachesize=", cachesize_setup);
105
106 /*
107 * Naming convention should be: <Name> [(<Codename>)]
108 * This table only is used unless init_<vendor>() below doesn't set it;
109 * in particular, if CPUID levels 0x80000002..4 are supported, this isn't used
110 *
111 */
112
113 /* Look up CPU names by table lookup. */
114 static char __cpuinit *table_lookup_model(struct cpuinfo_x86 *c)
115 {
116 struct cpu_model_info *info;
117
118 if (c->x86_model >= 16)
119 return NULL; /* Range check */
120
121 if (!this_cpu)
122 return NULL;
123
124 info = this_cpu->c_models;
125
126 while (info && info->family) {
127 if (info->family == c->x86)
128 return info->model_names[c->x86_model];
129 info++;
130 }
131 return NULL; /* Not found */
132 }
133
134 static int __init x86_fxsr_setup(char *s)
135 {
136 setup_clear_cpu_cap(X86_FEATURE_FXSR);
137 setup_clear_cpu_cap(X86_FEATURE_XMM);
138 return 1;
139 }
140 __setup("nofxsr", x86_fxsr_setup);
141
142 static int __init x86_sep_setup(char *s)
143 {
144 setup_clear_cpu_cap(X86_FEATURE_SEP);
145 return 1;
146 }
147 __setup("nosep", x86_sep_setup);
148
149 /* Standard macro to see if a specific flag is changeable */
150 static inline int flag_is_changeable_p(u32 flag)
151 {
152 u32 f1, f2;
153
154 asm("pushfl\n\t"
155 "pushfl\n\t"
156 "popl %0\n\t"
157 "movl %0,%1\n\t"
158 "xorl %2,%0\n\t"
159 "pushl %0\n\t"
160 "popfl\n\t"
161 "pushfl\n\t"
162 "popl %0\n\t"
163 "popfl\n\t"
164 : "=&r" (f1), "=&r" (f2)
165 : "ir" (flag));
166
167 return ((f1^f2) & flag) != 0;
168 }
169
170 /* Probe for the CPUID instruction */
171 static int __cpuinit have_cpuid_p(void)
172 {
173 return flag_is_changeable_p(X86_EFLAGS_ID);
174 }
175
176 static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
177 {
178 if (cpu_has(c, X86_FEATURE_PN) && disable_x86_serial_nr) {
179 /* Disable processor serial number */
180 unsigned long lo, hi;
181 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
182 lo |= 0x200000;
183 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
184 printk(KERN_NOTICE "CPU serial number disabled.\n");
185 clear_cpu_cap(c, X86_FEATURE_PN);
186
187 /* Disabling the serial number may affect the cpuid level */
188 c->cpuid_level = cpuid_eax(0);
189 }
190 }
191
192 static int __init x86_serial_nr_setup(char *s)
193 {
194 disable_x86_serial_nr = 0;
195 return 1;
196 }
197 __setup("serialnumber", x86_serial_nr_setup);
198 #else
199 /* Probe for the CPUID instruction */
200 static inline int have_cpuid_p(void)
201 {
202 return 1;
203 }
204 #endif
205
206 __u32 cleared_cpu_caps[NCAPINTS] __cpuinitdata;
207
208 /* Current gdt points %fs at the "master" per-cpu area: after this,
209 * it's on the real one. */
210 void switch_to_new_gdt(void)
211 {
212 struct desc_ptr gdt_descr;
213
214 gdt_descr.address = (long)get_cpu_gdt_table(smp_processor_id());
215 gdt_descr.size = GDT_SIZE - 1;
216 load_gdt(&gdt_descr);
217 #ifdef CONFIG_X86_32
218 asm("mov %0, %%fs" : : "r" (__KERNEL_PERCPU) : "memory");
219 #endif
220 }
221
222 static struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {};
223
224 static void __cpuinit default_init(struct cpuinfo_x86 *c)
225 {
226 #ifdef CONFIG_X86_64
227 display_cacheinfo(c);
228 #else
229 /* Not much we can do here... */
230 /* Check if at least it has cpuid */
231 if (c->cpuid_level == -1) {
232 /* No cpuid. It must be an ancient CPU */
233 if (c->x86 == 4)
234 strcpy(c->x86_model_id, "486");
235 else if (c->x86 == 3)
236 strcpy(c->x86_model_id, "386");
237 }
238 #endif
239 }
240
241 static struct cpu_dev __cpuinitdata default_cpu = {
242 .c_init = default_init,
243 .c_vendor = "Unknown",
244 .c_x86_vendor = X86_VENDOR_UNKNOWN,
245 };
246
247 int __cpuinit get_model_name(struct cpuinfo_x86 *c)
248 {
249 unsigned int *v;
250 char *p, *q;
251
252 if (c->extended_cpuid_level < 0x80000004)
253 return 0;
254
255 v = (unsigned int *) c->x86_model_id;
256 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
257 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
258 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
259 c->x86_model_id[48] = 0;
260
261 /* Intel chips right-justify this string for some dumb reason;
262 undo that brain damage */
263 p = q = &c->x86_model_id[0];
264 while (*p == ' ')
265 p++;
266 if (p != q) {
267 while (*p)
268 *q++ = *p++;
269 while (q <= &c->x86_model_id[48])
270 *q++ = '\0'; /* Zero-pad the rest */
271 }
272
273 return 1;
274 }
275
276
277 void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
278 {
279 unsigned int n, dummy, ebx, ecx, edx, l2size;
280
281 n = c->extended_cpuid_level;
282
283 if (n >= 0x80000005) {
284 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
285 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
286 edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
287 c->x86_cache_size = (ecx>>24) + (edx>>24);
288 #ifdef CONFIG_X86_64
289 /* On K8 L1 TLB is inclusive, so don't count it */
290 c->x86_tlbsize = 0;
291 #endif
292 }
293
294 if (n < 0x80000006) /* Some chips just has a large L1. */
295 return;
296
297 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
298 l2size = ecx >> 16;
299
300 #ifdef CONFIG_X86_64
301 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
302 #else
303
304 /* do processor-specific cache resizing */
305 if (this_cpu->c_size_cache)
306 l2size = this_cpu->c_size_cache(c, l2size);
307
308 /* Allow user to override all this if necessary. */
309 if (cachesize_override != -1)
310 l2size = cachesize_override;
311
312 if (l2size == 0)
313 return; /* Again, no L2 cache is possible */
314 #endif
315
316 c->x86_cache_size = l2size;
317
318 printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
319 l2size, ecx & 0xFF);
320 }
321
322 void __cpuinit detect_ht(struct cpuinfo_x86 *c)
323 {
324 #ifdef CONFIG_X86_HT
325 u32 eax, ebx, ecx, edx;
326 int index_msb, core_bits;
327
328 if (!cpu_has(c, X86_FEATURE_HT))
329 return;
330 if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
331 goto out;
332
333 if (cpu_has(c, X86_FEATURE_XTOPOLOGY))
334 return;
335
336 cpuid(1, &eax, &ebx, &ecx, &edx);
337
338 smp_num_siblings = (ebx & 0xff0000) >> 16;
339
340 if (smp_num_siblings == 1) {
341 printk(KERN_INFO "CPU: Hyper-Threading is disabled\n");
342 } else if (smp_num_siblings > 1) {
343
344 if (smp_num_siblings > NR_CPUS) {
345 printk(KERN_WARNING "CPU: Unsupported number of siblings %d",
346 smp_num_siblings);
347 smp_num_siblings = 1;
348 return;
349 }
350
351 index_msb = get_count_order(smp_num_siblings);
352 #ifdef CONFIG_X86_64
353 c->phys_proc_id = phys_pkg_id(index_msb);
354 #else
355 c->phys_proc_id = phys_pkg_id(c->initial_apicid, index_msb);
356 #endif
357
358 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
359
360 index_msb = get_count_order(smp_num_siblings);
361
362 core_bits = get_count_order(c->x86_max_cores);
363
364 #ifdef CONFIG_X86_64
365 c->cpu_core_id = phys_pkg_id(index_msb) &
366 ((1 << core_bits) - 1);
367 #else
368 c->cpu_core_id = phys_pkg_id(c->initial_apicid, index_msb) &
369 ((1 << core_bits) - 1);
370 #endif
371 }
372
373 out:
374 if ((c->x86_max_cores * smp_num_siblings) > 1) {
375 printk(KERN_INFO "CPU: Physical Processor ID: %d\n",
376 c->phys_proc_id);
377 printk(KERN_INFO "CPU: Processor Core ID: %d\n",
378 c->cpu_core_id);
379 }
380 #endif
381 }
382
383 static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
384 {
385 char *v = c->x86_vendor_id;
386 int i;
387 static int printed;
388
389 for (i = 0; i < X86_VENDOR_NUM; i++) {
390 if (!cpu_devs[i])
391 break;
392
393 if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||
394 (cpu_devs[i]->c_ident[1] &&
395 !strcmp(v, cpu_devs[i]->c_ident[1]))) {
396 this_cpu = cpu_devs[i];
397 c->x86_vendor = this_cpu->c_x86_vendor;
398 return;
399 }
400 }
401
402 if (!printed) {
403 printed++;
404 printk(KERN_ERR "CPU: Vendor unknown, using generic init.\n");
405 printk(KERN_ERR "CPU: Your system may be unstable.\n");
406 }
407
408 c->x86_vendor = X86_VENDOR_UNKNOWN;
409 this_cpu = &default_cpu;
410 }
411
412 void __cpuinit cpu_detect(struct cpuinfo_x86 *c)
413 {
414 /* Get vendor name */
415 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
416 (unsigned int *)&c->x86_vendor_id[0],
417 (unsigned int *)&c->x86_vendor_id[8],
418 (unsigned int *)&c->x86_vendor_id[4]);
419
420 c->x86 = 4;
421 /* Intel-defined flags: level 0x00000001 */
422 if (c->cpuid_level >= 0x00000001) {
423 u32 junk, tfms, cap0, misc;
424 cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
425 c->x86 = (tfms >> 8) & 0xf;
426 c->x86_model = (tfms >> 4) & 0xf;
427 c->x86_mask = tfms & 0xf;
428 if (c->x86 == 0xf)
429 c->x86 += (tfms >> 20) & 0xff;
430 if (c->x86 >= 0x6)
431 c->x86_model += ((tfms >> 16) & 0xf) << 4;
432 if (cap0 & (1<<19)) {
433 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
434 c->x86_cache_alignment = c->x86_clflush_size;
435 }
436 }
437 }
438
439
440 static void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c)
441 {
442 u32 tfms, xlvl;
443 u32 ebx;
444
445 /* Intel-defined flags: level 0x00000001 */
446 if (c->cpuid_level >= 0x00000001) {
447 u32 capability, excap;
448
449 cpuid(0x00000001, &tfms, &ebx, &excap, &capability);
450 c->x86_capability[0] = capability;
451 c->x86_capability[4] = excap;
452 }
453
454 /* AMD-defined flags: level 0x80000001 */
455 xlvl = cpuid_eax(0x80000000);
456 c->extended_cpuid_level = xlvl;
457 if ((xlvl & 0xffff0000) == 0x80000000) {
458 if (xlvl >= 0x80000001) {
459 c->x86_capability[1] = cpuid_edx(0x80000001);
460 c->x86_capability[6] = cpuid_ecx(0x80000001);
461 }
462 }
463
464 #ifdef CONFIG_X86_64
465 /* Transmeta-defined flags: level 0x80860001 */
466 xlvl = cpuid_eax(0x80860000);
467 if ((xlvl & 0xffff0000) == 0x80860000) {
468 /* Don't set x86_cpuid_level here for now to not confuse. */
469 if (xlvl >= 0x80860001)
470 c->x86_capability[2] = cpuid_edx(0x80860001);
471 }
472
473 if (c->extended_cpuid_level >= 0x80000007)
474 c->x86_power = cpuid_edx(0x80000007);
475
476 if (c->extended_cpuid_level >= 0x80000008) {
477 u32 eax = cpuid_eax(0x80000008);
478
479 c->x86_virt_bits = (eax >> 8) & 0xff;
480 c->x86_phys_bits = eax & 0xff;
481 }
482 #endif
483 }
484
485 /*
486 * Do minimum CPU detection early.
487 * Fields really needed: vendor, cpuid_level, family, model, mask,
488 * cache alignment.
489 * The others are not touched to avoid unwanted side effects.
490 *
491 * WARNING: this function is only called on the BP. Don't add code here
492 * that is supposed to run on all CPUs.
493 */
494 static void __init early_identify_cpu(struct cpuinfo_x86 *c)
495 {
496
497 #ifdef CONFIG_X86_64
498 c->x86_clflush_size = 64;
499 #else
500 c->x86_clflush_size = 32;
501 #endif
502 c->x86_cache_alignment = c->x86_clflush_size;
503
504 if (!have_cpuid_p())
505 return;
506
507 memset(&c->x86_capability, 0, sizeof c->x86_capability);
508
509 c->extended_cpuid_level = 0;
510
511 cpu_detect(c);
512
513 get_cpu_vendor(c);
514
515 get_cpu_cap(c);
516
517 if (this_cpu->c_early_init)
518 this_cpu->c_early_init(c);
519
520 validate_pat_support(c);
521 }
522
523 void __init early_cpu_init(void)
524 {
525 struct cpu_dev **cdev;
526 int count = 0;
527
528 printk("KERNEL supported cpus:\n");
529 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) {
530 struct cpu_dev *cpudev = *cdev;
531 unsigned int j;
532
533 if (count >= X86_VENDOR_NUM)
534 break;
535 cpu_devs[count] = cpudev;
536 count++;
537
538 for (j = 0; j < 2; j++) {
539 if (!cpudev->c_ident[j])
540 continue;
541 printk(" %s %s\n", cpudev->c_vendor,
542 cpudev->c_ident[j]);
543 }
544 }
545
546 early_identify_cpu(&boot_cpu_data);
547 }
548
549 /*
550 * The NOPL instruction is supposed to exist on all CPUs with
551 * family >= 6, unfortunately, that's not true in practice because
552 * of early VIA chips and (more importantly) broken virtualizers that
553 * are not easy to detect. Hence, probe for it based on first
554 * principles.
555 *
556 * Note: no 64-bit chip is known to lack these, but put the code here
557 * for consistency with 32 bits, and to make it utterly trivial to
558 * diagnose the problem should it ever surface.
559 */
560 static void __cpuinit detect_nopl(struct cpuinfo_x86 *c)
561 {
562 const u32 nopl_signature = 0x888c53b1; /* Random number */
563 u32 has_nopl = nopl_signature;
564
565 clear_cpu_cap(c, X86_FEATURE_NOPL);
566 if (c->x86 >= 6) {
567 asm volatile("\n"
568 "1: .byte 0x0f,0x1f,0xc0\n" /* nopl %eax */
569 "2:\n"
570 " .section .fixup,\"ax\"\n"
571 "3: xor %0,%0\n"
572 " jmp 2b\n"
573 " .previous\n"
574 _ASM_EXTABLE(1b,3b)
575 : "+a" (has_nopl));
576
577 if (has_nopl == nopl_signature)
578 set_cpu_cap(c, X86_FEATURE_NOPL);
579 }
580 }
581
582 static void __cpuinit generic_identify(struct cpuinfo_x86 *c)
583 {
584 c->extended_cpuid_level = 0;
585
586 cpu_detect(c);
587
588 get_cpu_vendor(c);
589
590 get_cpu_cap(c);
591
592 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xff;
593 #ifdef CONFIG_SMP
594 c->phys_proc_id = c->initial_apicid;
595 #endif
596
597 if (c->extended_cpuid_level >= 0x80000004)
598 get_model_name(c); /* Default name */
599
600 init_scattered_cpuid_features(c);
601 detect_nopl(c);
602 }
603
604 /*
605 * This does the hard work of actually picking apart the CPU stuff...
606 */
607 static void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
608 {
609 int i;
610
611 c->loops_per_jiffy = loops_per_jiffy;
612 c->x86_cache_size = -1;
613 c->x86_vendor = X86_VENDOR_UNKNOWN;
614 c->x86_model = c->x86_mask = 0; /* So far unknown... */
615 c->x86_vendor_id[0] = '\0'; /* Unset */
616 c->x86_model_id[0] = '\0'; /* Unset */
617 c->x86_max_cores = 1;
618 c->x86_coreid_bits = 0;
619 c->x86_clflush_size = 64;
620 c->x86_cache_alignment = c->x86_clflush_size;
621 memset(&c->x86_capability, 0, sizeof c->x86_capability);
622
623 generic_identify(c);
624
625 c->apicid = phys_pkg_id(0);
626
627 /*
628 * Vendor-specific initialization. In this section we
629 * canonicalize the feature flags, meaning if there are
630 * features a certain CPU supports which CPUID doesn't
631 * tell us, CPUID claiming incorrect flags, or other bugs,
632 * we handle them here.
633 *
634 * At the end of this section, c->x86_capability better
635 * indicate the features this CPU genuinely supports!
636 */
637 if (this_cpu->c_init)
638 this_cpu->c_init(c);
639
640 detect_ht(c);
641
642 /*
643 * On SMP, boot_cpu_data holds the common feature set between
644 * all CPUs; so make sure that we indicate which features are
645 * common between the CPUs. The first time this routine gets
646 * executed, c == &boot_cpu_data.
647 */
648 if (c != &boot_cpu_data) {
649 /* AND the already accumulated flags with these */
650 for (i = 0; i < NCAPINTS; i++)
651 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
652 }
653
654 /* Clear all flags overriden by options */
655 for (i = 0; i < NCAPINTS; i++)
656 c->x86_capability[i] &= ~cleared_cpu_caps[i];
657
658 #ifdef CONFIG_X86_MCE
659 mcheck_init(c);
660 #endif
661 select_idle_routine(c);
662
663 #ifdef CONFIG_NUMA
664 numa_add_cpu(smp_processor_id());
665 #endif
666
667 }
668
669 void __init identify_boot_cpu(void)
670 {
671 identify_cpu(&boot_cpu_data);
672 }
673
674 void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c)
675 {
676 BUG_ON(c == &boot_cpu_data);
677 identify_cpu(c);
678 mtrr_ap_init();
679 }
680
681 struct msr_range {
682 unsigned min;
683 unsigned max;
684 };
685
686 static struct msr_range msr_range_array[] __cpuinitdata = {
687 { 0x00000000, 0x00000418},
688 { 0xc0000000, 0xc000040b},
689 { 0xc0010000, 0xc0010142},
690 { 0xc0011000, 0xc001103b},
691 };
692
693 static void __cpuinit print_cpu_msr(void)
694 {
695 unsigned index;
696 u64 val;
697 int i;
698 unsigned index_min, index_max;
699
700 for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) {
701 index_min = msr_range_array[i].min;
702 index_max = msr_range_array[i].max;
703 for (index = index_min; index < index_max; index++) {
704 if (rdmsrl_amd_safe(index, &val))
705 continue;
706 printk(KERN_INFO " MSR%08x: %016llx\n", index, val);
707 }
708 }
709 }
710
711 static int show_msr __cpuinitdata;
712 static __init int setup_show_msr(char *arg)
713 {
714 int num;
715
716 get_option(&arg, &num);
717
718 if (num > 0)
719 show_msr = num;
720 return 1;
721 }
722 __setup("show_msr=", setup_show_msr);
723
724 static __init int setup_noclflush(char *arg)
725 {
726 setup_clear_cpu_cap(X86_FEATURE_CLFLSH);
727 return 1;
728 }
729 __setup("noclflush", setup_noclflush);
730
731 void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
732 {
733 if (c->x86_model_id[0])
734 printk(KERN_CONT "%s", c->x86_model_id);
735
736 if (c->x86_mask || c->cpuid_level >= 0)
737 printk(KERN_CONT " stepping %02x\n", c->x86_mask);
738 else
739 printk(KERN_CONT "\n");
740
741 #ifdef CONFIG_SMP
742 if (c->cpu_index < show_msr)
743 print_cpu_msr();
744 #else
745 if (show_msr)
746 print_cpu_msr();
747 #endif
748 }
749
750 static __init int setup_disablecpuid(char *arg)
751 {
752 int bit;
753 if (get_option(&arg, &bit) && bit < NCAPINTS*32)
754 setup_clear_cpu_cap(bit);
755 else
756 return 0;
757 return 1;
758 }
759 __setup("clearcpuid=", setup_disablecpuid);
760
761 cpumask_t cpu_initialized __cpuinitdata = CPU_MASK_NONE;
762
763 #ifdef CONFIG_X86_64
764 struct x8664_pda **_cpu_pda __read_mostly;
765 EXPORT_SYMBOL(_cpu_pda);
766
767 struct desc_ptr idt_descr = { 256 * 16 - 1, (unsigned long) idt_table };
768
769 char boot_cpu_stack[IRQSTACKSIZE] __page_aligned_bss;
770
771 unsigned long __supported_pte_mask __read_mostly = ~0UL;
772 EXPORT_SYMBOL_GPL(__supported_pte_mask);
773
774 static int do_not_nx __cpuinitdata;
775
776 /* noexec=on|off
777 Control non executable mappings for 64bit processes.
778
779 on Enable(default)
780 off Disable
781 */
782 static int __init nonx_setup(char *str)
783 {
784 if (!str)
785 return -EINVAL;
786 if (!strncmp(str, "on", 2)) {
787 __supported_pte_mask |= _PAGE_NX;
788 do_not_nx = 0;
789 } else if (!strncmp(str, "off", 3)) {
790 do_not_nx = 1;
791 __supported_pte_mask &= ~_PAGE_NX;
792 }
793 return 0;
794 }
795 early_param("noexec", nonx_setup);
796
797 int force_personality32;
798
799 /* noexec32=on|off
800 Control non executable heap for 32bit processes.
801 To control the stack too use noexec=off
802
803 on PROT_READ does not imply PROT_EXEC for 32bit processes (default)
804 off PROT_READ implies PROT_EXEC
805 */
806 static int __init nonx32_setup(char *str)
807 {
808 if (!strcmp(str, "on"))
809 force_personality32 &= ~READ_IMPLIES_EXEC;
810 else if (!strcmp(str, "off"))
811 force_personality32 |= READ_IMPLIES_EXEC;
812 return 1;
813 }
814 __setup("noexec32=", nonx32_setup);
815
816 void pda_init(int cpu)
817 {
818 struct x8664_pda *pda = cpu_pda(cpu);
819
820 /* Setup up data that may be needed in __get_free_pages early */
821 loadsegment(fs, 0);
822 loadsegment(gs, 0);
823 /* Memory clobbers used to order PDA accessed */
824 mb();
825 wrmsrl(MSR_GS_BASE, pda);
826 mb();
827
828 pda->cpunumber = cpu;
829 pda->irqcount = -1;
830 pda->kernelstack = (unsigned long)stack_thread_info() -
831 PDA_STACKOFFSET + THREAD_SIZE;
832 pda->active_mm = &init_mm;
833 pda->mmu_state = 0;
834
835 if (cpu == 0) {
836 /* others are initialized in smpboot.c */
837 pda->pcurrent = &init_task;
838 pda->irqstackptr = boot_cpu_stack;
839 pda->irqstackptr += IRQSTACKSIZE - 64;
840 } else {
841 if (!pda->irqstackptr) {
842 pda->irqstackptr = (char *)
843 __get_free_pages(GFP_ATOMIC, IRQSTACK_ORDER);
844 if (!pda->irqstackptr)
845 panic("cannot allocate irqstack for cpu %d",
846 cpu);
847 pda->irqstackptr += IRQSTACKSIZE - 64;
848 }
849
850 if (pda->nodenumber == 0 && cpu_to_node(cpu) != NUMA_NO_NODE)
851 pda->nodenumber = cpu_to_node(cpu);
852 }
853 }
854
855 char boot_exception_stacks[(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ +
856 DEBUG_STKSZ] __page_aligned_bss;
857
858 extern asmlinkage void ignore_sysret(void);
859
860 /* May not be marked __init: used by software suspend */
861 void syscall_init(void)
862 {
863 /*
864 * LSTAR and STAR live in a bit strange symbiosis.
865 * They both write to the same internal register. STAR allows to
866 * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip.
867 */
868 wrmsrl(MSR_STAR, ((u64)__USER32_CS)<<48 | ((u64)__KERNEL_CS)<<32);
869 wrmsrl(MSR_LSTAR, system_call);
870 wrmsrl(MSR_CSTAR, ignore_sysret);
871
872 #ifdef CONFIG_IA32_EMULATION
873 syscall32_cpu_init();
874 #endif
875
876 /* Flags to clear on syscall */
877 wrmsrl(MSR_SYSCALL_MASK,
878 X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|X86_EFLAGS_IOPL);
879 }
880
881 void __cpuinit check_efer(void)
882 {
883 unsigned long efer;
884
885 rdmsrl(MSR_EFER, efer);
886 if (!(efer & EFER_NX) || do_not_nx)
887 __supported_pte_mask &= ~_PAGE_NX;
888 }
889
890 unsigned long kernel_eflags;
891
892 /*
893 * Copies of the original ist values from the tss are only accessed during
894 * debugging, no special alignment required.
895 */
896 DEFINE_PER_CPU(struct orig_ist, orig_ist);
897
898 #else
899
900 /* Make sure %fs is initialized properly in idle threads */
901 struct pt_regs * __cpuinit idle_regs(struct pt_regs *regs)
902 {
903 memset(regs, 0, sizeof(struct pt_regs));
904 regs->fs = __KERNEL_PERCPU;
905 return regs;
906 }
907 #endif
908
909 /*
910 * cpu_init() initializes state that is per-CPU. Some data is already
911 * initialized (naturally) in the bootstrap process, such as the GDT
912 * and IDT. We reload them nevertheless, this function acts as a
913 * 'CPU state barrier', nothing should get across.
914 * A lot of state is already set up in PDA init for 64 bit
915 */
916 #ifdef CONFIG_X86_64
917 void __cpuinit cpu_init(void)
918 {
919 int cpu = stack_smp_processor_id();
920 struct tss_struct *t = &per_cpu(init_tss, cpu);
921 struct orig_ist *orig_ist = &per_cpu(orig_ist, cpu);
922 unsigned long v;
923 char *estacks = NULL;
924 struct task_struct *me;
925 int i;
926
927 /* CPU 0 is initialised in head64.c */
928 if (cpu != 0)
929 pda_init(cpu);
930 else
931 estacks = boot_exception_stacks;
932
933 me = current;
934
935 if (cpu_test_and_set(cpu, cpu_initialized))
936 panic("CPU#%d already initialized!\n", cpu);
937
938 printk(KERN_INFO "Initializing CPU#%d\n", cpu);
939
940 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
941
942 /*
943 * Initialize the per-CPU GDT with the boot GDT,
944 * and set up the GDT descriptor:
945 */
946
947 switch_to_new_gdt();
948 load_idt((const struct desc_ptr *)&idt_descr);
949
950 memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8);
951 syscall_init();
952
953 wrmsrl(MSR_FS_BASE, 0);
954 wrmsrl(MSR_KERNEL_GS_BASE, 0);
955 barrier();
956
957 check_efer();
958 if (cpu != 0 && x2apic)
959 enable_x2apic();
960
961 /*
962 * set up and load the per-CPU TSS
963 */
964 if (!orig_ist->ist[0]) {
965 static const unsigned int order[N_EXCEPTION_STACKS] = {
966 [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STACK_ORDER,
967 [DEBUG_STACK - 1] = DEBUG_STACK_ORDER
968 };
969 for (v = 0; v < N_EXCEPTION_STACKS; v++) {
970 if (cpu) {
971 estacks = (char *)__get_free_pages(GFP_ATOMIC, order[v]);
972 if (!estacks)
973 panic("Cannot allocate exception "
974 "stack %ld %d\n", v, cpu);
975 }
976 estacks += PAGE_SIZE << order[v];
977 orig_ist->ist[v] = t->x86_tss.ist[v] =
978 (unsigned long)estacks;
979 }
980 }
981
982 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap);
983 /*
984 * <= is required because the CPU will access up to
985 * 8 bits beyond the end of the IO permission bitmap.
986 */
987 for (i = 0; i <= IO_BITMAP_LONGS; i++)
988 t->io_bitmap[i] = ~0UL;
989
990 atomic_inc(&init_mm.mm_count);
991 me->active_mm = &init_mm;
992 if (me->mm)
993 BUG();
994 enter_lazy_tlb(&init_mm, me);
995
996 load_sp0(t, &current->thread);
997 set_tss_desc(cpu, t);
998 load_TR_desc();
999 load_LDT(&init_mm.context);
1000
1001 #ifdef CONFIG_KGDB
1002 /*
1003 * If the kgdb is connected no debug regs should be altered. This
1004 * is only applicable when KGDB and a KGDB I/O module are built
1005 * into the kernel and you are using early debugging with
1006 * kgdbwait. KGDB will control the kernel HW breakpoint registers.
1007 */
1008 if (kgdb_connected && arch_kgdb_ops.correct_hw_break)
1009 arch_kgdb_ops.correct_hw_break();
1010 else {
1011 #endif
1012 /*
1013 * Clear all 6 debug registers:
1014 */
1015
1016 set_debugreg(0UL, 0);
1017 set_debugreg(0UL, 1);
1018 set_debugreg(0UL, 2);
1019 set_debugreg(0UL, 3);
1020 set_debugreg(0UL, 6);
1021 set_debugreg(0UL, 7);
1022 #ifdef CONFIG_KGDB
1023 /* If the kgdb is connected no debug regs should be altered. */
1024 }
1025 #endif
1026
1027 fpu_init();
1028
1029 raw_local_save_flags(kernel_eflags);
1030
1031 if (is_uv_system())
1032 uv_cpu_init();
1033 }
1034
1035 #else
1036
1037 void __cpuinit cpu_init(void)
1038 {
1039 int cpu = smp_processor_id();
1040 struct task_struct *curr = current;
1041 struct tss_struct *t = &per_cpu(init_tss, cpu);
1042 struct thread_struct *thread = &curr->thread;
1043
1044 if (cpu_test_and_set(cpu, cpu_initialized)) {
1045 printk(KERN_WARNING "CPU#%d already initialized!\n", cpu);
1046 for (;;) local_irq_enable();
1047 }
1048
1049 printk(KERN_INFO "Initializing CPU#%d\n", cpu);
1050
1051 if (cpu_has_vme || cpu_has_tsc || cpu_has_de)
1052 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1053
1054 load_idt(&idt_descr);
1055 switch_to_new_gdt();
1056
1057 /*
1058 * Set up and load the per-CPU TSS and LDT
1059 */
1060 atomic_inc(&init_mm.mm_count);
1061 curr->active_mm = &init_mm;
1062 if (curr->mm)
1063 BUG();
1064 enter_lazy_tlb(&init_mm, curr);
1065
1066 load_sp0(t, thread);
1067 set_tss_desc(cpu, t);
1068 load_TR_desc();
1069 load_LDT(&init_mm.context);
1070
1071 #ifdef CONFIG_DOUBLEFAULT
1072 /* Set up doublefault TSS pointer in the GDT */
1073 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss);
1074 #endif
1075
1076 /* Clear %gs. */
1077 asm volatile ("mov %0, %%gs" : : "r" (0));
1078
1079 /* Clear all 6 debug registers: */
1080 set_debugreg(0, 0);
1081 set_debugreg(0, 1);
1082 set_debugreg(0, 2);
1083 set_debugreg(0, 3);
1084 set_debugreg(0, 6);
1085 set_debugreg(0, 7);
1086
1087 /*
1088 * Force FPU initialization:
1089 */
1090 if (cpu_has_xsave)
1091 current_thread_info()->status = TS_XSAVE;
1092 else
1093 current_thread_info()->status = 0;
1094 clear_used_math();
1095 mxcsr_feature_mask_init();
1096
1097 /*
1098 * Boot processor to setup the FP and extended state context info.
1099 */
1100 if (!smp_processor_id())
1101 init_thread_xstate();
1102
1103 xsave_init();
1104 }
1105
1106 #ifdef CONFIG_HOTPLUG_CPU
1107 void __cpuinit cpu_uninit(void)
1108 {
1109 int cpu = raw_smp_processor_id();
1110 cpu_clear(cpu, cpu_initialized);
1111
1112 /* lazy TLB state */
1113 per_cpu(cpu_tlbstate, cpu).state = 0;
1114 per_cpu(cpu_tlbstate, cpu).active_mm = &init_mm;
1115 }
1116 #endif
1117
1118 #endif
Linux kernel - Deliverables
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