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[deliverable/linux.git] / arch / x86 / kernel / cpu / common_64.c
1 #include <linux/init.h>
2 #include <linux/kernel.h>
3 #include <linux/sched.h>
4 #include <linux/string.h>
5 #include <linux/bootmem.h>
6 #include <linux/bitops.h>
7 #include <linux/module.h>
8 #include <linux/kgdb.h>
9 #include <linux/topology.h>
10 #include <linux/delay.h>
11 #include <linux/smp.h>
12 #include <linux/percpu.h>
13 #include <asm/i387.h>
14 #include <asm/msr.h>
15 #include <asm/io.h>
16 #include <asm/linkage.h>
17 #include <asm/mmu_context.h>
18 #include <asm/mtrr.h>
19 #include <asm/mce.h>
20 #include <asm/pat.h>
21 #include <asm/asm.h>
22 #include <asm/numa.h>
23 #ifdef CONFIG_X86_LOCAL_APIC
24 #include <asm/mpspec.h>
25 #include <asm/apic.h>
26 #include <mach_apic.h>
27 #include <asm/genapic.h>
28 #endif
29 #include <asm/pda.h>
30 #include <asm/pgtable.h>
31 #include <asm/processor.h>
32 #include <asm/desc.h>
33 #include <asm/atomic.h>
34 #include <asm/proto.h>
35 #include <asm/sections.h>
36 #include <asm/setup.h>
37
38 #include "cpu.h"
39
40 static struct cpu_dev *this_cpu __cpuinitdata;
41
42 #ifdef CONFIG_X86_64
43 /* We need valid kernel segments for data and code in long mode too
44 * IRET will check the segment types kkeil 2000/10/28
45 * Also sysret mandates a special GDT layout
46 */
47 /* The TLS descriptors are currently at a different place compared to i386.
48 Hopefully nobody expects them at a fixed place (Wine?) */
49 DEFINE_PER_CPU(struct gdt_page, gdt_page) = { .gdt = {
50 [GDT_ENTRY_KERNEL32_CS] = { { { 0x0000ffff, 0x00cf9b00 } } },
51 [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00af9b00 } } },
52 [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9300 } } },
53 [GDT_ENTRY_DEFAULT_USER32_CS] = { { { 0x0000ffff, 0x00cffb00 } } },
54 [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff300 } } },
55 [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00affb00 } } },
56 } };
57 #else
58 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = {
59 [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00cf9a00 } } },
60 [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9200 } } },
61 [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00cffa00 } } },
62 [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff200 } } },
63 /*
64 * Segments used for calling PnP BIOS have byte granularity.
65 * They code segments and data segments have fixed 64k limits,
66 * the transfer segment sizes are set at run time.
67 */
68 /* 32-bit code */
69 [GDT_ENTRY_PNPBIOS_CS32] = { { { 0x0000ffff, 0x00409a00 } } },
70 /* 16-bit code */
71 [GDT_ENTRY_PNPBIOS_CS16] = { { { 0x0000ffff, 0x00009a00 } } },
72 /* 16-bit data */
73 [GDT_ENTRY_PNPBIOS_DS] = { { { 0x0000ffff, 0x00009200 } } },
74 /* 16-bit data */
75 [GDT_ENTRY_PNPBIOS_TS1] = { { { 0x00000000, 0x00009200 } } },
76 /* 16-bit data */
77 [GDT_ENTRY_PNPBIOS_TS2] = { { { 0x00000000, 0x00009200 } } },
78 /*
79 * The APM segments have byte granularity and their bases
80 * are set at run time. All have 64k limits.
81 */
82 /* 32-bit code */
83 [GDT_ENTRY_APMBIOS_BASE] = { { { 0x0000ffff, 0x00409a00 } } },
84 /* 16-bit code */
85 [GDT_ENTRY_APMBIOS_BASE+1] = { { { 0x0000ffff, 0x00009a00 } } },
86 /* data */
87 [GDT_ENTRY_APMBIOS_BASE+2] = { { { 0x0000ffff, 0x00409200 } } },
88
89 [GDT_ENTRY_ESPFIX_SS] = { { { 0x00000000, 0x00c09200 } } },
90 [GDT_ENTRY_PERCPU] = { { { 0x00000000, 0x00000000 } } },
91 } };
92 #endif
93 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page);
94
95 #ifdef CONFIG_X86_32
96 static int cachesize_override __cpuinitdata = -1;
97 static int disable_x86_serial_nr __cpuinitdata = 1;
98
99 static int __init cachesize_setup(char *str)
100 {
101 get_option(&str, &cachesize_override);
102 return 1;
103 }
104 __setup("cachesize=", cachesize_setup);
105
106 /*
107 * Naming convention should be: <Name> [(<Codename>)]
108 * This table only is used unless init_<vendor>() below doesn't set it;
109 * in particular, if CPUID levels 0x80000002..4 are supported, this isn't used
110 *
111 */
112
113 /* Look up CPU names by table lookup. */
114 static char __cpuinit *table_lookup_model(struct cpuinfo_x86 *c)
115 {
116 struct cpu_model_info *info;
117
118 if (c->x86_model >= 16)
119 return NULL; /* Range check */
120
121 if (!this_cpu)
122 return NULL;
123
124 info = this_cpu->c_models;
125
126 while (info && info->family) {
127 if (info->family == c->x86)
128 return info->model_names[c->x86_model];
129 info++;
130 }
131 return NULL; /* Not found */
132 }
133
134 static int __init x86_fxsr_setup(char *s)
135 {
136 setup_clear_cpu_cap(X86_FEATURE_FXSR);
137 setup_clear_cpu_cap(X86_FEATURE_XMM);
138 return 1;
139 }
140 __setup("nofxsr", x86_fxsr_setup);
141
142 static int __init x86_sep_setup(char *s)
143 {
144 setup_clear_cpu_cap(X86_FEATURE_SEP);
145 return 1;
146 }
147 __setup("nosep", x86_sep_setup);
148
149 /* Standard macro to see if a specific flag is changeable */
150 static inline int flag_is_changeable_p(u32 flag)
151 {
152 u32 f1, f2;
153
154 asm("pushfl\n\t"
155 "pushfl\n\t"
156 "popl %0\n\t"
157 "movl %0,%1\n\t"
158 "xorl %2,%0\n\t"
159 "pushl %0\n\t"
160 "popfl\n\t"
161 "pushfl\n\t"
162 "popl %0\n\t"
163 "popfl\n\t"
164 : "=&r" (f1), "=&r" (f2)
165 : "ir" (flag));
166
167 return ((f1^f2) & flag) != 0;
168 }
169
170 /* Probe for the CPUID instruction */
171 static int __cpuinit have_cpuid_p(void)
172 {
173 return flag_is_changeable_p(X86_EFLAGS_ID);
174 }
175
176 static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
177 {
178 if (cpu_has(c, X86_FEATURE_PN) && disable_x86_serial_nr) {
179 /* Disable processor serial number */
180 unsigned long lo, hi;
181 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
182 lo |= 0x200000;
183 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
184 printk(KERN_NOTICE "CPU serial number disabled.\n");
185 clear_cpu_cap(c, X86_FEATURE_PN);
186
187 /* Disabling the serial number may affect the cpuid level */
188 c->cpuid_level = cpuid_eax(0);
189 }
190 }
191
192 static int __init x86_serial_nr_setup(char *s)
193 {
194 disable_x86_serial_nr = 0;
195 return 1;
196 }
197 __setup("serialnumber", x86_serial_nr_setup);
198 #else
199 /* Probe for the CPUID instruction */
200 static inline int have_cpuid_p(void)
201 {
202 return 1;
203 }
204 #endif
205
206 __u32 cleared_cpu_caps[NCAPINTS] __cpuinitdata;
207
208 /* Current gdt points %fs at the "master" per-cpu area: after this,
209 * it's on the real one. */
210 void switch_to_new_gdt(void)
211 {
212 struct desc_ptr gdt_descr;
213
214 gdt_descr.address = (long)get_cpu_gdt_table(smp_processor_id());
215 gdt_descr.size = GDT_SIZE - 1;
216 load_gdt(&gdt_descr);
217 #ifdef CONFIG_X86_32
218 asm("mov %0, %%fs" : : "r" (__KERNEL_PERCPU) : "memory");
219 #endif
220 }
221
222 static struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {};
223
224 static void __cpuinit default_init(struct cpuinfo_x86 *c)
225 {
226 #ifdef CONFIG_X86_64
227 display_cacheinfo(c);
228 #else
229 /* Not much we can do here... */
230 /* Check if at least it has cpuid */
231 if (c->cpuid_level == -1) {
232 /* No cpuid. It must be an ancient CPU */
233 if (c->x86 == 4)
234 strcpy(c->x86_model_id, "486");
235 else if (c->x86 == 3)
236 strcpy(c->x86_model_id, "386");
237 }
238 #endif
239 }
240
241 static struct cpu_dev __cpuinitdata default_cpu = {
242 .c_init = default_init,
243 .c_vendor = "Unknown",
244 .c_x86_vendor = X86_VENDOR_UNKNOWN,
245 };
246
247 int __cpuinit get_model_name(struct cpuinfo_x86 *c)
248 {
249 unsigned int *v;
250 char *p, *q;
251
252 if (c->extended_cpuid_level < 0x80000004)
253 return 0;
254
255 v = (unsigned int *) c->x86_model_id;
256 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
257 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
258 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
259 c->x86_model_id[48] = 0;
260
261 /* Intel chips right-justify this string for some dumb reason;
262 undo that brain damage */
263 p = q = &c->x86_model_id[0];
264 while (*p == ' ')
265 p++;
266 if (p != q) {
267 while (*p)
268 *q++ = *p++;
269 while (q <= &c->x86_model_id[48])
270 *q++ = '\0'; /* Zero-pad the rest */
271 }
272
273 return 1;
274 }
275
276
277 void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
278 {
279 unsigned int n, dummy, ebx, ecx, edx, l2size;
280
281 n = c->extended_cpuid_level;
282
283 if (n >= 0x80000005) {
284 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
285 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
286 edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
287 c->x86_cache_size = (ecx>>24) + (edx>>24);
288 #ifdef CONFIG_X86_64
289 /* On K8 L1 TLB is inclusive, so don't count it */
290 c->x86_tlbsize = 0;
291 #endif
292 }
293
294 if (n < 0x80000006) /* Some chips just has a large L1. */
295 return;
296
297 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
298 l2size = ecx >> 16;
299
300 #ifdef CONFIG_X86_64
301 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
302 #else
303
304 /* do processor-specific cache resizing */
305 if (this_cpu->c_size_cache)
306 l2size = this_cpu->c_size_cache(c, l2size);
307
308 /* Allow user to override all this if necessary. */
309 if (cachesize_override != -1)
310 l2size = cachesize_override;
311
312 if (l2size == 0)
313 return; /* Again, no L2 cache is possible */
314 #endif
315
316 c->x86_cache_size = l2size;
317
318 printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
319 l2size, ecx & 0xFF);
320 }
321
322 void __cpuinit detect_ht(struct cpuinfo_x86 *c)
323 {
324 #ifdef CONFIG_X86_HT
325 u32 eax, ebx, ecx, edx;
326 int index_msb, core_bits;
327
328 if (!cpu_has(c, X86_FEATURE_HT))
329 return;
330 if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
331 goto out;
332
333 if (cpu_has(c, X86_FEATURE_XTOPOLOGY))
334 return;
335
336 cpuid(1, &eax, &ebx, &ecx, &edx);
337
338 smp_num_siblings = (ebx & 0xff0000) >> 16;
339
340 if (smp_num_siblings == 1) {
341 printk(KERN_INFO "CPU: Hyper-Threading is disabled\n");
342 } else if (smp_num_siblings > 1) {
343
344 if (smp_num_siblings > NR_CPUS) {
345 printk(KERN_WARNING "CPU: Unsupported number of siblings %d",
346 smp_num_siblings);
347 smp_num_siblings = 1;
348 return;
349 }
350
351 index_msb = get_count_order(smp_num_siblings);
352 c->phys_proc_id = phys_pkg_id(index_msb);
353
354 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
355
356 index_msb = get_count_order(smp_num_siblings);
357
358 core_bits = get_count_order(c->x86_max_cores);
359
360 c->cpu_core_id = phys_pkg_id(index_msb) &
361 ((1 << core_bits) - 1);
362 }
363
364 out:
365 if ((c->x86_max_cores * smp_num_siblings) > 1) {
366 printk(KERN_INFO "CPU: Physical Processor ID: %d\n",
367 c->phys_proc_id);
368 printk(KERN_INFO "CPU: Processor Core ID: %d\n",
369 c->cpu_core_id);
370 }
371 #endif
372 }
373
374 static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
375 {
376 char *v = c->x86_vendor_id;
377 int i;
378 static int printed;
379
380 for (i = 0; i < X86_VENDOR_NUM; i++) {
381 if (!cpu_devs[i])
382 break;
383
384 if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||
385 (cpu_devs[i]->c_ident[1] &&
386 !strcmp(v, cpu_devs[i]->c_ident[1]))) {
387 this_cpu = cpu_devs[i];
388 c->x86_vendor = this_cpu->c_x86_vendor;
389 return;
390 }
391 }
392
393 if (!printed) {
394 printed++;
395 printk(KERN_ERR "CPU: Vendor unknown, using generic init.\n");
396 printk(KERN_ERR "CPU: Your system may be unstable.\n");
397 }
398
399 c->x86_vendor = X86_VENDOR_UNKNOWN;
400 this_cpu = &default_cpu;
401 }
402
403 void __cpuinit cpu_detect(struct cpuinfo_x86 *c)
404 {
405 /* Get vendor name */
406 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
407 (unsigned int *)&c->x86_vendor_id[0],
408 (unsigned int *)&c->x86_vendor_id[8],
409 (unsigned int *)&c->x86_vendor_id[4]);
410
411 c->x86 = 4;
412 /* Intel-defined flags: level 0x00000001 */
413 if (c->cpuid_level >= 0x00000001) {
414 u32 junk, tfms, cap0, misc;
415 cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
416 c->x86 = (tfms >> 8) & 0xf;
417 c->x86_model = (tfms >> 4) & 0xf;
418 c->x86_mask = tfms & 0xf;
419 if (c->x86 == 0xf)
420 c->x86 += (tfms >> 20) & 0xff;
421 if (c->x86 >= 0x6)
422 c->x86_model += ((tfms >> 16) & 0xf) << 4;
423 if (cap0 & (1<<19)) {
424 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
425 c->x86_cache_alignment = c->x86_clflush_size;
426 }
427 }
428 }
429
430
431 static void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c)
432 {
433 u32 tfms, xlvl;
434 u32 ebx;
435
436 /* Intel-defined flags: level 0x00000001 */
437 if (c->cpuid_level >= 0x00000001) {
438 u32 capability, excap;
439
440 cpuid(0x00000001, &tfms, &ebx, &excap, &capability);
441 c->x86_capability[0] = capability;
442 c->x86_capability[4] = excap;
443 }
444
445 /* AMD-defined flags: level 0x80000001 */
446 xlvl = cpuid_eax(0x80000000);
447 c->extended_cpuid_level = xlvl;
448 if ((xlvl & 0xffff0000) == 0x80000000) {
449 if (xlvl >= 0x80000001) {
450 c->x86_capability[1] = cpuid_edx(0x80000001);
451 c->x86_capability[6] = cpuid_ecx(0x80000001);
452 }
453 }
454
455 /* Transmeta-defined flags: level 0x80860001 */
456 xlvl = cpuid_eax(0x80860000);
457 if ((xlvl & 0xffff0000) == 0x80860000) {
458 /* Don't set x86_cpuid_level here for now to not confuse. */
459 if (xlvl >= 0x80860001)
460 c->x86_capability[2] = cpuid_edx(0x80860001);
461 }
462
463 if (c->extended_cpuid_level >= 0x80000007)
464 c->x86_power = cpuid_edx(0x80000007);
465
466 if (c->extended_cpuid_level >= 0x80000008) {
467 u32 eax = cpuid_eax(0x80000008);
468
469 c->x86_virt_bits = (eax >> 8) & 0xff;
470 c->x86_phys_bits = eax & 0xff;
471 }
472 }
473
474 /* Do some early cpuid on the boot CPU to get some parameter that are
475 needed before check_bugs. Everything advanced is in identify_cpu
476 below. */
477 static void __init early_identify_cpu(struct cpuinfo_x86 *c)
478 {
479
480 c->x86_clflush_size = 64;
481 c->x86_cache_alignment = c->x86_clflush_size;
482
483 memset(&c->x86_capability, 0, sizeof c->x86_capability);
484
485 c->extended_cpuid_level = 0;
486
487 cpu_detect(c);
488
489 get_cpu_vendor(c);
490
491 get_cpu_cap(c);
492
493 if (this_cpu->c_early_init)
494 this_cpu->c_early_init(c);
495
496 validate_pat_support(c);
497 }
498
499 void __init early_cpu_init(void)
500 {
501 struct cpu_dev **cdev;
502 int count = 0;
503
504 printk("KERNEL supported cpus:\n");
505 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) {
506 struct cpu_dev *cpudev = *cdev;
507 unsigned int j;
508
509 if (count >= X86_VENDOR_NUM)
510 break;
511 cpu_devs[count] = cpudev;
512 count++;
513
514 for (j = 0; j < 2; j++) {
515 if (!cpudev->c_ident[j])
516 continue;
517 printk(" %s %s\n", cpudev->c_vendor,
518 cpudev->c_ident[j]);
519 }
520 }
521
522 early_identify_cpu(&boot_cpu_data);
523 }
524
525 /*
526 * The NOPL instruction is supposed to exist on all CPUs with
527 * family >= 6, unfortunately, that's not true in practice because
528 * of early VIA chips and (more importantly) broken virtualizers that
529 * are not easy to detect. Hence, probe for it based on first
530 * principles.
531 *
532 * Note: no 64-bit chip is known to lack these, but put the code here
533 * for consistency with 32 bits, and to make it utterly trivial to
534 * diagnose the problem should it ever surface.
535 */
536 static void __cpuinit detect_nopl(struct cpuinfo_x86 *c)
537 {
538 const u32 nopl_signature = 0x888c53b1; /* Random number */
539 u32 has_nopl = nopl_signature;
540
541 clear_cpu_cap(c, X86_FEATURE_NOPL);
542 if (c->x86 >= 6) {
543 asm volatile("\n"
544 "1: .byte 0x0f,0x1f,0xc0\n" /* nopl %eax */
545 "2:\n"
546 " .section .fixup,\"ax\"\n"
547 "3: xor %0,%0\n"
548 " jmp 2b\n"
549 " .previous\n"
550 _ASM_EXTABLE(1b,3b)
551 : "+a" (has_nopl));
552
553 if (has_nopl == nopl_signature)
554 set_cpu_cap(c, X86_FEATURE_NOPL);
555 }
556 }
557
558 static void __cpuinit generic_identify(struct cpuinfo_x86 *c)
559 {
560 c->extended_cpuid_level = 0;
561
562 cpu_detect(c);
563
564 get_cpu_vendor(c);
565
566 get_cpu_cap(c);
567
568 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xff;
569 #ifdef CONFIG_SMP
570 c->phys_proc_id = c->initial_apicid;
571 #endif
572
573 if (c->extended_cpuid_level >= 0x80000004)
574 get_model_name(c); /* Default name */
575
576 init_scattered_cpuid_features(c);
577 detect_nopl(c);
578 }
579
580 /*
581 * This does the hard work of actually picking apart the CPU stuff...
582 */
583 static void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
584 {
585 int i;
586
587 c->loops_per_jiffy = loops_per_jiffy;
588 c->x86_cache_size = -1;
589 c->x86_vendor = X86_VENDOR_UNKNOWN;
590 c->x86_model = c->x86_mask = 0; /* So far unknown... */
591 c->x86_vendor_id[0] = '\0'; /* Unset */
592 c->x86_model_id[0] = '\0'; /* Unset */
593 c->x86_max_cores = 1;
594 c->x86_coreid_bits = 0;
595 c->x86_clflush_size = 64;
596 c->x86_cache_alignment = c->x86_clflush_size;
597 memset(&c->x86_capability, 0, sizeof c->x86_capability);
598
599 generic_identify(c);
600
601 c->apicid = phys_pkg_id(0);
602
603 /*
604 * Vendor-specific initialization. In this section we
605 * canonicalize the feature flags, meaning if there are
606 * features a certain CPU supports which CPUID doesn't
607 * tell us, CPUID claiming incorrect flags, or other bugs,
608 * we handle them here.
609 *
610 * At the end of this section, c->x86_capability better
611 * indicate the features this CPU genuinely supports!
612 */
613 if (this_cpu->c_init)
614 this_cpu->c_init(c);
615
616 detect_ht(c);
617
618 /*
619 * On SMP, boot_cpu_data holds the common feature set between
620 * all CPUs; so make sure that we indicate which features are
621 * common between the CPUs. The first time this routine gets
622 * executed, c == &boot_cpu_data.
623 */
624 if (c != &boot_cpu_data) {
625 /* AND the already accumulated flags with these */
626 for (i = 0; i < NCAPINTS; i++)
627 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
628 }
629
630 /* Clear all flags overriden by options */
631 for (i = 0; i < NCAPINTS; i++)
632 c->x86_capability[i] &= ~cleared_cpu_caps[i];
633
634 #ifdef CONFIG_X86_MCE
635 mcheck_init(c);
636 #endif
637 select_idle_routine(c);
638
639 #ifdef CONFIG_NUMA
640 numa_add_cpu(smp_processor_id());
641 #endif
642
643 }
644
645 void __init identify_boot_cpu(void)
646 {
647 identify_cpu(&boot_cpu_data);
648 }
649
650 void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c)
651 {
652 BUG_ON(c == &boot_cpu_data);
653 identify_cpu(c);
654 mtrr_ap_init();
655 }
656
657 struct msr_range {
658 unsigned min;
659 unsigned max;
660 };
661
662 static struct msr_range msr_range_array[] __cpuinitdata = {
663 { 0x00000000, 0x00000418},
664 { 0xc0000000, 0xc000040b},
665 { 0xc0010000, 0xc0010142},
666 { 0xc0011000, 0xc001103b},
667 };
668
669 static void __cpuinit print_cpu_msr(void)
670 {
671 unsigned index;
672 u64 val;
673 int i;
674 unsigned index_min, index_max;
675
676 for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) {
677 index_min = msr_range_array[i].min;
678 index_max = msr_range_array[i].max;
679 for (index = index_min; index < index_max; index++) {
680 if (rdmsrl_amd_safe(index, &val))
681 continue;
682 printk(KERN_INFO " MSR%08x: %016llx\n", index, val);
683 }
684 }
685 }
686
687 static int show_msr __cpuinitdata;
688 static __init int setup_show_msr(char *arg)
689 {
690 int num;
691
692 get_option(&arg, &num);
693
694 if (num > 0)
695 show_msr = num;
696 return 1;
697 }
698 __setup("show_msr=", setup_show_msr);
699
700 static __init int setup_noclflush(char *arg)
701 {
702 setup_clear_cpu_cap(X86_FEATURE_CLFLSH);
703 return 1;
704 }
705 __setup("noclflush", setup_noclflush);
706
707 void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
708 {
709 if (c->x86_model_id[0])
710 printk(KERN_CONT "%s", c->x86_model_id);
711
712 if (c->x86_mask || c->cpuid_level >= 0)
713 printk(KERN_CONT " stepping %02x\n", c->x86_mask);
714 else
715 printk(KERN_CONT "\n");
716
717 #ifdef CONFIG_SMP
718 if (c->cpu_index < show_msr)
719 print_cpu_msr();
720 #else
721 if (show_msr)
722 print_cpu_msr();
723 #endif
724 }
725
726 static __init int setup_disablecpuid(char *arg)
727 {
728 int bit;
729 if (get_option(&arg, &bit) && bit < NCAPINTS*32)
730 setup_clear_cpu_cap(bit);
731 else
732 return 0;
733 return 1;
734 }
735 __setup("clearcpuid=", setup_disablecpuid);
736
737 cpumask_t cpu_initialized __cpuinitdata = CPU_MASK_NONE;
738
739 #ifdef CONFIG_X86_64
740 struct x8664_pda **_cpu_pda __read_mostly;
741 EXPORT_SYMBOL(_cpu_pda);
742
743 struct desc_ptr idt_descr = { 256 * 16 - 1, (unsigned long) idt_table };
744
745 char boot_cpu_stack[IRQSTACKSIZE] __page_aligned_bss;
746
747 unsigned long __supported_pte_mask __read_mostly = ~0UL;
748 EXPORT_SYMBOL_GPL(__supported_pte_mask);
749
750 static int do_not_nx __cpuinitdata;
751
752 /* noexec=on|off
753 Control non executable mappings for 64bit processes.
754
755 on Enable(default)
756 off Disable
757 */
758 static int __init nonx_setup(char *str)
759 {
760 if (!str)
761 return -EINVAL;
762 if (!strncmp(str, "on", 2)) {
763 __supported_pte_mask |= _PAGE_NX;
764 do_not_nx = 0;
765 } else if (!strncmp(str, "off", 3)) {
766 do_not_nx = 1;
767 __supported_pte_mask &= ~_PAGE_NX;
768 }
769 return 0;
770 }
771 early_param("noexec", nonx_setup);
772
773 int force_personality32;
774
775 /* noexec32=on|off
776 Control non executable heap for 32bit processes.
777 To control the stack too use noexec=off
778
779 on PROT_READ does not imply PROT_EXEC for 32bit processes (default)
780 off PROT_READ implies PROT_EXEC
781 */
782 static int __init nonx32_setup(char *str)
783 {
784 if (!strcmp(str, "on"))
785 force_personality32 &= ~READ_IMPLIES_EXEC;
786 else if (!strcmp(str, "off"))
787 force_personality32 |= READ_IMPLIES_EXEC;
788 return 1;
789 }
790 __setup("noexec32=", nonx32_setup);
791
792 void pda_init(int cpu)
793 {
794 struct x8664_pda *pda = cpu_pda(cpu);
795
796 /* Setup up data that may be needed in __get_free_pages early */
797 loadsegment(fs, 0);
798 loadsegment(gs, 0);
799 /* Memory clobbers used to order PDA accessed */
800 mb();
801 wrmsrl(MSR_GS_BASE, pda);
802 mb();
803
804 pda->cpunumber = cpu;
805 pda->irqcount = -1;
806 pda->kernelstack = (unsigned long)stack_thread_info() -
807 PDA_STACKOFFSET + THREAD_SIZE;
808 pda->active_mm = &init_mm;
809 pda->mmu_state = 0;
810
811 if (cpu == 0) {
812 /* others are initialized in smpboot.c */
813 pda->pcurrent = &init_task;
814 pda->irqstackptr = boot_cpu_stack;
815 pda->irqstackptr += IRQSTACKSIZE - 64;
816 } else {
817 if (!pda->irqstackptr) {
818 pda->irqstackptr = (char *)
819 __get_free_pages(GFP_ATOMIC, IRQSTACK_ORDER);
820 if (!pda->irqstackptr)
821 panic("cannot allocate irqstack for cpu %d",
822 cpu);
823 pda->irqstackptr += IRQSTACKSIZE - 64;
824 }
825
826 if (pda->nodenumber == 0 && cpu_to_node(cpu) != NUMA_NO_NODE)
827 pda->nodenumber = cpu_to_node(cpu);
828 }
829 }
830
831 char boot_exception_stacks[(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ +
832 DEBUG_STKSZ] __page_aligned_bss;
833
834 extern asmlinkage void ignore_sysret(void);
835
836 /* May not be marked __init: used by software suspend */
837 void syscall_init(void)
838 {
839 /*
840 * LSTAR and STAR live in a bit strange symbiosis.
841 * They both write to the same internal register. STAR allows to
842 * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip.
843 */
844 wrmsrl(MSR_STAR, ((u64)__USER32_CS)<<48 | ((u64)__KERNEL_CS)<<32);
845 wrmsrl(MSR_LSTAR, system_call);
846 wrmsrl(MSR_CSTAR, ignore_sysret);
847
848 #ifdef CONFIG_IA32_EMULATION
849 syscall32_cpu_init();
850 #endif
851
852 /* Flags to clear on syscall */
853 wrmsrl(MSR_SYSCALL_MASK,
854 X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|X86_EFLAGS_IOPL);
855 }
856
857 void __cpuinit check_efer(void)
858 {
859 unsigned long efer;
860
861 rdmsrl(MSR_EFER, efer);
862 if (!(efer & EFER_NX) || do_not_nx)
863 __supported_pte_mask &= ~_PAGE_NX;
864 }
865
866 unsigned long kernel_eflags;
867
868 /*
869 * Copies of the original ist values from the tss are only accessed during
870 * debugging, no special alignment required.
871 */
872 DEFINE_PER_CPU(struct orig_ist, orig_ist);
873
874 #else
875
876 /* Make sure %fs is initialized properly in idle threads */
877 struct pt_regs * __cpuinit idle_regs(struct pt_regs *regs)
878 {
879 memset(regs, 0, sizeof(struct pt_regs));
880 regs->fs = __KERNEL_PERCPU;
881 return regs;
882 }
883 #endif
884
885 /*
886 * cpu_init() initializes state that is per-CPU. Some data is already
887 * initialized (naturally) in the bootstrap process, such as the GDT
888 * and IDT. We reload them nevertheless, this function acts as a
889 * 'CPU state barrier', nothing should get across.
890 * A lot of state is already set up in PDA init for 64 bit
891 */
892 #ifdef CONFIG_X86_64
893 void __cpuinit cpu_init(void)
894 {
895 int cpu = stack_smp_processor_id();
896 struct tss_struct *t = &per_cpu(init_tss, cpu);
897 struct orig_ist *orig_ist = &per_cpu(orig_ist, cpu);
898 unsigned long v;
899 char *estacks = NULL;
900 struct task_struct *me;
901 int i;
902
903 /* CPU 0 is initialised in head64.c */
904 if (cpu != 0)
905 pda_init(cpu);
906 else
907 estacks = boot_exception_stacks;
908
909 me = current;
910
911 if (cpu_test_and_set(cpu, cpu_initialized))
912 panic("CPU#%d already initialized!\n", cpu);
913
914 printk(KERN_INFO "Initializing CPU#%d\n", cpu);
915
916 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
917
918 /*
919 * Initialize the per-CPU GDT with the boot GDT,
920 * and set up the GDT descriptor:
921 */
922
923 switch_to_new_gdt();
924 load_idt((const struct desc_ptr *)&idt_descr);
925
926 memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8);
927 syscall_init();
928
929 wrmsrl(MSR_FS_BASE, 0);
930 wrmsrl(MSR_KERNEL_GS_BASE, 0);
931 barrier();
932
933 check_efer();
934 if (cpu != 0 && x2apic)
935 enable_x2apic();
936
937 /*
938 * set up and load the per-CPU TSS
939 */
940 if (!orig_ist->ist[0]) {
941 static const unsigned int order[N_EXCEPTION_STACKS] = {
942 [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STACK_ORDER,
943 [DEBUG_STACK - 1] = DEBUG_STACK_ORDER
944 };
945 for (v = 0; v < N_EXCEPTION_STACKS; v++) {
946 if (cpu) {
947 estacks = (char *)__get_free_pages(GFP_ATOMIC, order[v]);
948 if (!estacks)
949 panic("Cannot allocate exception "
950 "stack %ld %d\n", v, cpu);
951 }
952 estacks += PAGE_SIZE << order[v];
953 orig_ist->ist[v] = t->x86_tss.ist[v] =
954 (unsigned long)estacks;
955 }
956 }
957
958 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap);
959 /*
960 * <= is required because the CPU will access up to
961 * 8 bits beyond the end of the IO permission bitmap.
962 */
963 for (i = 0; i <= IO_BITMAP_LONGS; i++)
964 t->io_bitmap[i] = ~0UL;
965
966 atomic_inc(&init_mm.mm_count);
967 me->active_mm = &init_mm;
968 if (me->mm)
969 BUG();
970 enter_lazy_tlb(&init_mm, me);
971
972 load_sp0(t, &current->thread);
973 set_tss_desc(cpu, t);
974 load_TR_desc();
975 load_LDT(&init_mm.context);
976
977 #ifdef CONFIG_KGDB
978 /*
979 * If the kgdb is connected no debug regs should be altered. This
980 * is only applicable when KGDB and a KGDB I/O module are built
981 * into the kernel and you are using early debugging with
982 * kgdbwait. KGDB will control the kernel HW breakpoint registers.
983 */
984 if (kgdb_connected && arch_kgdb_ops.correct_hw_break)
985 arch_kgdb_ops.correct_hw_break();
986 else {
987 #endif
988 /*
989 * Clear all 6 debug registers:
990 */
991
992 set_debugreg(0UL, 0);
993 set_debugreg(0UL, 1);
994 set_debugreg(0UL, 2);
995 set_debugreg(0UL, 3);
996 set_debugreg(0UL, 6);
997 set_debugreg(0UL, 7);
998 #ifdef CONFIG_KGDB
999 /* If the kgdb is connected no debug regs should be altered. */
1000 }
1001 #endif
1002
1003 fpu_init();
1004
1005 raw_local_save_flags(kernel_eflags);
1006
1007 if (is_uv_system())
1008 uv_cpu_init();
1009 }
1010
1011 #else
1012
1013 void __cpuinit cpu_init(void)
1014 {
1015 int cpu = smp_processor_id();
1016 struct task_struct *curr = current;
1017 struct tss_struct *t = &per_cpu(init_tss, cpu);
1018 struct thread_struct *thread = &curr->thread;
1019
1020 if (cpu_test_and_set(cpu, cpu_initialized)) {
1021 printk(KERN_WARNING "CPU#%d already initialized!\n", cpu);
1022 for (;;) local_irq_enable();
1023 }
1024
1025 printk(KERN_INFO "Initializing CPU#%d\n", cpu);
1026
1027 if (cpu_has_vme || cpu_has_tsc || cpu_has_de)
1028 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1029
1030 load_idt(&idt_descr);
1031 switch_to_new_gdt();
1032
1033 /*
1034 * Set up and load the per-CPU TSS and LDT
1035 */
1036 atomic_inc(&init_mm.mm_count);
1037 curr->active_mm = &init_mm;
1038 if (curr->mm)
1039 BUG();
1040 enter_lazy_tlb(&init_mm, curr);
1041
1042 load_sp0(t, thread);
1043 set_tss_desc(cpu, t);
1044 load_TR_desc();
1045 load_LDT(&init_mm.context);
1046
1047 #ifdef CONFIG_DOUBLEFAULT
1048 /* Set up doublefault TSS pointer in the GDT */
1049 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss);
1050 #endif
1051
1052 /* Clear %gs. */
1053 asm volatile ("mov %0, %%gs" : : "r" (0));
1054
1055 /* Clear all 6 debug registers: */
1056 set_debugreg(0, 0);
1057 set_debugreg(0, 1);
1058 set_debugreg(0, 2);
1059 set_debugreg(0, 3);
1060 set_debugreg(0, 6);
1061 set_debugreg(0, 7);
1062
1063 /*
1064 * Force FPU initialization:
1065 */
1066 if (cpu_has_xsave)
1067 current_thread_info()->status = TS_XSAVE;
1068 else
1069 current_thread_info()->status = 0;
1070 clear_used_math();
1071 mxcsr_feature_mask_init();
1072
1073 /*
1074 * Boot processor to setup the FP and extended state context info.
1075 */
1076 if (!smp_processor_id())
1077 init_thread_xstate();
1078
1079 xsave_init();
1080 }
1081
1082 #ifdef CONFIG_HOTPLUG_CPU
1083 void __cpuinit cpu_uninit(void)
1084 {
1085 int cpu = raw_smp_processor_id();
1086 cpu_clear(cpu, cpu_initialized);
1087
1088 /* lazy TLB state */
1089 per_cpu(cpu_tlbstate, cpu).state = 0;
1090 per_cpu(cpu_tlbstate, cpu).active_mm = &init_mm;
1091 }
1092 #endif
1093
1094 #endif
Linux kernel - Deliverables
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