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Merge tag 'pci-v3.15-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaa...
[deliverable/linux.git] / arch / x86 / kernel / cpu / intel.c
1 #include <linux/kernel.h>
2
3 #include <linux/string.h>
4 #include <linux/bitops.h>
5 #include <linux/smp.h>
6 #include <linux/sched.h>
7 #include <linux/thread_info.h>
8 #include <linux/module.h>
9 #include <linux/uaccess.h>
10
11 #include <asm/processor.h>
12 #include <asm/pgtable.h>
13 #include <asm/msr.h>
14 #include <asm/bugs.h>
15 #include <asm/cpu.h>
16
17 #ifdef CONFIG_X86_64
18 #include <linux/topology.h>
19 #endif
20
21 #include "cpu.h"
22
23 #ifdef CONFIG_X86_LOCAL_APIC
24 #include <asm/mpspec.h>
25 #include <asm/apic.h>
26 #endif
27
28 static void early_init_intel(struct cpuinfo_x86 *c)
29 {
30 u64 misc_enable;
31
32 /* Unmask CPUID levels if masked: */
33 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {
34 if (msr_clear_bit(MSR_IA32_MISC_ENABLE,
35 MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT) > 0) {
36 c->cpuid_level = cpuid_eax(0);
37 get_cpu_cap(c);
38 }
39 }
40
41 if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
42 (c->x86 == 0x6 && c->x86_model >= 0x0e))
43 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
44
45 if (c->x86 >= 6 && !cpu_has(c, X86_FEATURE_IA64)) {
46 unsigned lower_word;
47
48 wrmsr(MSR_IA32_UCODE_REV, 0, 0);
49 /* Required by the SDM */
50 sync_core();
51 rdmsr(MSR_IA32_UCODE_REV, lower_word, c->microcode);
52 }
53
54 /*
55 * Atom erratum AAE44/AAF40/AAG38/AAH41:
56 *
57 * A race condition between speculative fetches and invalidating
58 * a large page. This is worked around in microcode, but we
59 * need the microcode to have already been loaded... so if it is
60 * not, recommend a BIOS update and disable large pages.
61 */
62 if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_mask <= 2 &&
63 c->microcode < 0x20e) {
64 printk(KERN_WARNING "Atom PSE erratum detected, BIOS microcode update recommended\n");
65 clear_cpu_cap(c, X86_FEATURE_PSE);
66 }
67
68 #ifdef CONFIG_X86_64
69 set_cpu_cap(c, X86_FEATURE_SYSENTER32);
70 #else
71 /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */
72 if (c->x86 == 15 && c->x86_cache_alignment == 64)
73 c->x86_cache_alignment = 128;
74 #endif
75
76 /* CPUID workaround for 0F33/0F34 CPU */
77 if (c->x86 == 0xF && c->x86_model == 0x3
78 && (c->x86_mask == 0x3 || c->x86_mask == 0x4))
79 c->x86_phys_bits = 36;
80
81 /*
82 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
83 * with P/T states and does not stop in deep C-states.
84 *
85 * It is also reliable across cores and sockets. (but not across
86 * cabinets - we turn it off in that case explicitly.)
87 */
88 if (c->x86_power & (1 << 8)) {
89 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
90 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
91 if (!check_tsc_unstable())
92 set_sched_clock_stable();
93 }
94
95 /* Penwell and Cloverview have the TSC which doesn't sleep on S3 */
96 if (c->x86 == 6) {
97 switch (c->x86_model) {
98 case 0x27: /* Penwell */
99 case 0x35: /* Cloverview */
100 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC_S3);
101 break;
102 default:
103 break;
104 }
105 }
106
107 /*
108 * There is a known erratum on Pentium III and Core Solo
109 * and Core Duo CPUs.
110 * " Page with PAT set to WC while associated MTRR is UC
111 * may consolidate to UC "
112 * Because of this erratum, it is better to stick with
113 * setting WC in MTRR rather than using PAT on these CPUs.
114 *
115 * Enable PAT WC only on P4, Core 2 or later CPUs.
116 */
117 if (c->x86 == 6 && c->x86_model < 15)
118 clear_cpu_cap(c, X86_FEATURE_PAT);
119
120 #ifdef CONFIG_KMEMCHECK
121 /*
122 * P4s have a "fast strings" feature which causes single-
123 * stepping REP instructions to only generate a #DB on
124 * cache-line boundaries.
125 *
126 * Ingo Molnar reported a Pentium D (model 6) and a Xeon
127 * (model 2) with the same problem.
128 */
129 if (c->x86 == 15)
130 if (msr_clear_bit(MSR_IA32_MISC_ENABLE,
131 MSR_IA32_MISC_ENABLE_FAST_STRING_BIT) > 0)
132 pr_info("kmemcheck: Disabling fast string operations\n");
133 #endif
134
135 /*
136 * If fast string is not enabled in IA32_MISC_ENABLE for any reason,
137 * clear the fast string and enhanced fast string CPU capabilities.
138 */
139 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {
140 rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
141 if (!(misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING)) {
142 printk(KERN_INFO "Disabled fast string operations\n");
143 setup_clear_cpu_cap(X86_FEATURE_REP_GOOD);
144 setup_clear_cpu_cap(X86_FEATURE_ERMS);
145 }
146 }
147 }
148
149 #ifdef CONFIG_X86_32
150 /*
151 * Early probe support logic for ppro memory erratum #50
152 *
153 * This is called before we do cpu ident work
154 */
155
156 int ppro_with_ram_bug(void)
157 {
158 /* Uses data from early_cpu_detect now */
159 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
160 boot_cpu_data.x86 == 6 &&
161 boot_cpu_data.x86_model == 1 &&
162 boot_cpu_data.x86_mask < 8) {
163 printk(KERN_INFO "Pentium Pro with Errata#50 detected. Taking evasive action.\n");
164 return 1;
165 }
166 return 0;
167 }
168
169 static void intel_smp_check(struct cpuinfo_x86 *c)
170 {
171 /* calling is from identify_secondary_cpu() ? */
172 if (!c->cpu_index)
173 return;
174
175 /*
176 * Mask B, Pentium, but not Pentium MMX
177 */
178 if (c->x86 == 5 &&
179 c->x86_mask >= 1 && c->x86_mask <= 4 &&
180 c->x86_model <= 3) {
181 /*
182 * Remember we have B step Pentia with bugs
183 */
184 WARN_ONCE(1, "WARNING: SMP operation may be unreliable"
185 "with B stepping processors.\n");
186 }
187 }
188
189 static int forcepae;
190 static int __init forcepae_setup(char *__unused)
191 {
192 forcepae = 1;
193 return 1;
194 }
195 __setup("forcepae", forcepae_setup);
196
197 static void intel_workarounds(struct cpuinfo_x86 *c)
198 {
199 #ifdef CONFIG_X86_F00F_BUG
200 /*
201 * All current models of Pentium and Pentium with MMX technology CPUs
202 * have the F0 0F bug, which lets nonprivileged users lock up the
203 * system. Announce that the fault handler will be checking for it.
204 */
205 clear_cpu_bug(c, X86_BUG_F00F);
206 if (!paravirt_enabled() && c->x86 == 5) {
207 static int f00f_workaround_enabled;
208
209 set_cpu_bug(c, X86_BUG_F00F);
210 if (!f00f_workaround_enabled) {
211 printk(KERN_NOTICE "Intel Pentium with F0 0F bug - workaround enabled.\n");
212 f00f_workaround_enabled = 1;
213 }
214 }
215 #endif
216
217 /*
218 * SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until
219 * model 3 mask 3
220 */
221 if ((c->x86<<8 | c->x86_model<<4 | c->x86_mask) < 0x633)
222 clear_cpu_cap(c, X86_FEATURE_SEP);
223
224 /*
225 * PAE CPUID issue: many Pentium M report no PAE but may have a
226 * functionally usable PAE implementation.
227 * Forcefully enable PAE if kernel parameter "forcepae" is present.
228 */
229 if (forcepae) {
230 printk(KERN_WARNING "PAE forced!\n");
231 set_cpu_cap(c, X86_FEATURE_PAE);
232 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE);
233 }
234
235 /*
236 * P4 Xeon errata 037 workaround.
237 * Hardware prefetcher may cause stale data to be loaded into the cache.
238 */
239 if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) {
240 if (msr_set_bit(MSR_IA32_MISC_ENABLE,
241 MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT)
242 > 0) {
243 pr_info("CPU: C0 stepping P4 Xeon detected.\n");
244 pr_info("CPU: Disabling hardware prefetching (Errata 037)\n");
245 }
246 }
247
248 /*
249 * See if we have a good local APIC by checking for buggy Pentia,
250 * i.e. all B steppings and the C2 stepping of P54C when using their
251 * integrated APIC (see 11AP erratum in "Pentium Processor
252 * Specification Update").
253 */
254 if (cpu_has_apic && (c->x86<<8 | c->x86_model<<4) == 0x520 &&
255 (c->x86_mask < 0x6 || c->x86_mask == 0xb))
256 set_cpu_cap(c, X86_FEATURE_11AP);
257
258
259 #ifdef CONFIG_X86_INTEL_USERCOPY
260 /*
261 * Set up the preferred alignment for movsl bulk memory moves
262 */
263 switch (c->x86) {
264 case 4: /* 486: untested */
265 break;
266 case 5: /* Old Pentia: untested */
267 break;
268 case 6: /* PII/PIII only like movsl with 8-byte alignment */
269 movsl_mask.mask = 7;
270 break;
271 case 15: /* P4 is OK down to 8-byte alignment */
272 movsl_mask.mask = 7;
273 break;
274 }
275 #endif
276
277 #ifdef CONFIG_X86_NUMAQ
278 numaq_tsc_disable();
279 #endif
280
281 intel_smp_check(c);
282 }
283 #else
284 static void intel_workarounds(struct cpuinfo_x86 *c)
285 {
286 }
287 #endif
288
289 static void srat_detect_node(struct cpuinfo_x86 *c)
290 {
291 #ifdef CONFIG_NUMA
292 unsigned node;
293 int cpu = smp_processor_id();
294
295 /* Don't do the funky fallback heuristics the AMD version employs
296 for now. */
297 node = numa_cpu_node(cpu);
298 if (node == NUMA_NO_NODE || !node_online(node)) {
299 /* reuse the value from init_cpu_to_node() */
300 node = cpu_to_node(cpu);
301 }
302 numa_set_node(cpu, node);
303 #endif
304 }
305
306 /*
307 * find out the number of processor cores on the die
308 */
309 static int intel_num_cpu_cores(struct cpuinfo_x86 *c)
310 {
311 unsigned int eax, ebx, ecx, edx;
312
313 if (c->cpuid_level < 4)
314 return 1;
315
316 /* Intel has a non-standard dependency on %ecx for this CPUID level. */
317 cpuid_count(4, 0, &eax, &ebx, &ecx, &edx);
318 if (eax & 0x1f)
319 return (eax >> 26) + 1;
320 else
321 return 1;
322 }
323
324 static void detect_vmx_virtcap(struct cpuinfo_x86 *c)
325 {
326 /* Intel VMX MSR indicated features */
327 #define X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW 0x00200000
328 #define X86_VMX_FEATURE_PROC_CTLS_VNMI 0x00400000
329 #define X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS 0x80000000
330 #define X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC 0x00000001
331 #define X86_VMX_FEATURE_PROC_CTLS2_EPT 0x00000002
332 #define X86_VMX_FEATURE_PROC_CTLS2_VPID 0x00000020
333
334 u32 vmx_msr_low, vmx_msr_high, msr_ctl, msr_ctl2;
335
336 clear_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
337 clear_cpu_cap(c, X86_FEATURE_VNMI);
338 clear_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
339 clear_cpu_cap(c, X86_FEATURE_EPT);
340 clear_cpu_cap(c, X86_FEATURE_VPID);
341
342 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, vmx_msr_low, vmx_msr_high);
343 msr_ctl = vmx_msr_high | vmx_msr_low;
344 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW)
345 set_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
346 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_VNMI)
347 set_cpu_cap(c, X86_FEATURE_VNMI);
348 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS) {
349 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
350 vmx_msr_low, vmx_msr_high);
351 msr_ctl2 = vmx_msr_high | vmx_msr_low;
352 if ((msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC) &&
353 (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW))
354 set_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
355 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_EPT)
356 set_cpu_cap(c, X86_FEATURE_EPT);
357 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VPID)
358 set_cpu_cap(c, X86_FEATURE_VPID);
359 }
360 }
361
362 static void init_intel(struct cpuinfo_x86 *c)
363 {
364 unsigned int l2 = 0;
365
366 early_init_intel(c);
367
368 intel_workarounds(c);
369
370 /*
371 * Detect the extended topology information if available. This
372 * will reinitialise the initial_apicid which will be used
373 * in init_intel_cacheinfo()
374 */
375 detect_extended_topology(c);
376
377 l2 = init_intel_cacheinfo(c);
378 if (c->cpuid_level > 9) {
379 unsigned eax = cpuid_eax(10);
380 /* Check for version and the number of counters */
381 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
382 set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
383 }
384
385 if (cpu_has_xmm2)
386 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
387 if (cpu_has_ds) {
388 unsigned int l1;
389 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
390 if (!(l1 & (1<<11)))
391 set_cpu_cap(c, X86_FEATURE_BTS);
392 if (!(l1 & (1<<12)))
393 set_cpu_cap(c, X86_FEATURE_PEBS);
394 }
395
396 if (c->x86 == 6 && cpu_has_clflush &&
397 (c->x86_model == 29 || c->x86_model == 46 || c->x86_model == 47))
398 set_cpu_cap(c, X86_FEATURE_CLFLUSH_MONITOR);
399
400 #ifdef CONFIG_X86_64
401 if (c->x86 == 15)
402 c->x86_cache_alignment = c->x86_clflush_size * 2;
403 if (c->x86 == 6)
404 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
405 #else
406 /*
407 * Names for the Pentium II/Celeron processors
408 * detectable only by also checking the cache size.
409 * Dixon is NOT a Celeron.
410 */
411 if (c->x86 == 6) {
412 char *p = NULL;
413
414 switch (c->x86_model) {
415 case 5:
416 if (l2 == 0)
417 p = "Celeron (Covington)";
418 else if (l2 == 256)
419 p = "Mobile Pentium II (Dixon)";
420 break;
421
422 case 6:
423 if (l2 == 128)
424 p = "Celeron (Mendocino)";
425 else if (c->x86_mask == 0 || c->x86_mask == 5)
426 p = "Celeron-A";
427 break;
428
429 case 8:
430 if (l2 == 128)
431 p = "Celeron (Coppermine)";
432 break;
433 }
434
435 if (p)
436 strcpy(c->x86_model_id, p);
437 }
438
439 if (c->x86 == 15)
440 set_cpu_cap(c, X86_FEATURE_P4);
441 if (c->x86 == 6)
442 set_cpu_cap(c, X86_FEATURE_P3);
443 #endif
444
445 if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) {
446 /*
447 * let's use the legacy cpuid vector 0x1 and 0x4 for topology
448 * detection.
449 */
450 c->x86_max_cores = intel_num_cpu_cores(c);
451 #ifdef CONFIG_X86_32
452 detect_ht(c);
453 #endif
454 }
455
456 /* Work around errata */
457 srat_detect_node(c);
458
459 if (cpu_has(c, X86_FEATURE_VMX))
460 detect_vmx_virtcap(c);
461
462 /*
463 * Initialize MSR_IA32_ENERGY_PERF_BIAS if BIOS did not.
464 * x86_energy_perf_policy(8) is available to change it at run-time
465 */
466 if (cpu_has(c, X86_FEATURE_EPB)) {
467 u64 epb;
468
469 rdmsrl(MSR_IA32_ENERGY_PERF_BIAS, epb);
470 if ((epb & 0xF) == ENERGY_PERF_BIAS_PERFORMANCE) {
471 printk_once(KERN_WARNING "ENERGY_PERF_BIAS:"
472 " Set to 'normal', was 'performance'\n"
473 "ENERGY_PERF_BIAS: View and update with"
474 " x86_energy_perf_policy(8)\n");
475 epb = (epb & ~0xF) | ENERGY_PERF_BIAS_NORMAL;
476 wrmsrl(MSR_IA32_ENERGY_PERF_BIAS, epb);
477 }
478 }
479 }
480
481 #ifdef CONFIG_X86_32
482 static unsigned int intel_size_cache(struct cpuinfo_x86 *c, unsigned int size)
483 {
484 /*
485 * Intel PIII Tualatin. This comes in two flavours.
486 * One has 256kb of cache, the other 512. We have no way
487 * to determine which, so we use a boottime override
488 * for the 512kb model, and assume 256 otherwise.
489 */
490 if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0))
491 size = 256;
492 return size;
493 }
494 #endif
495
496 #define TLB_INST_4K 0x01
497 #define TLB_INST_4M 0x02
498 #define TLB_INST_2M_4M 0x03
499
500 #define TLB_INST_ALL 0x05
501 #define TLB_INST_1G 0x06
502
503 #define TLB_DATA_4K 0x11
504 #define TLB_DATA_4M 0x12
505 #define TLB_DATA_2M_4M 0x13
506 #define TLB_DATA_4K_4M 0x14
507
508 #define TLB_DATA_1G 0x16
509
510 #define TLB_DATA0_4K 0x21
511 #define TLB_DATA0_4M 0x22
512 #define TLB_DATA0_2M_4M 0x23
513
514 #define STLB_4K 0x41
515 #define STLB_4K_2M 0x42
516
517 static const struct _tlb_table intel_tlb_table[] = {
518 { 0x01, TLB_INST_4K, 32, " TLB_INST 4 KByte pages, 4-way set associative" },
519 { 0x02, TLB_INST_4M, 2, " TLB_INST 4 MByte pages, full associative" },
520 { 0x03, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way set associative" },
521 { 0x04, TLB_DATA_4M, 8, " TLB_DATA 4 MByte pages, 4-way set associative" },
522 { 0x05, TLB_DATA_4M, 32, " TLB_DATA 4 MByte pages, 4-way set associative" },
523 { 0x0b, TLB_INST_4M, 4, " TLB_INST 4 MByte pages, 4-way set associative" },
524 { 0x4f, TLB_INST_4K, 32, " TLB_INST 4 KByte pages */" },
525 { 0x50, TLB_INST_ALL, 64, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
526 { 0x51, TLB_INST_ALL, 128, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
527 { 0x52, TLB_INST_ALL, 256, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
528 { 0x55, TLB_INST_2M_4M, 7, " TLB_INST 2-MByte or 4-MByte pages, fully associative" },
529 { 0x56, TLB_DATA0_4M, 16, " TLB_DATA0 4 MByte pages, 4-way set associative" },
530 { 0x57, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, 4-way associative" },
531 { 0x59, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, fully associative" },
532 { 0x5a, TLB_DATA0_2M_4M, 32, " TLB_DATA0 2-MByte or 4 MByte pages, 4-way set associative" },
533 { 0x5b, TLB_DATA_4K_4M, 64, " TLB_DATA 4 KByte and 4 MByte pages" },
534 { 0x5c, TLB_DATA_4K_4M, 128, " TLB_DATA 4 KByte and 4 MByte pages" },
535 { 0x5d, TLB_DATA_4K_4M, 256, " TLB_DATA 4 KByte and 4 MByte pages" },
536 { 0x61, TLB_INST_4K, 48, " TLB_INST 4 KByte pages, full associative" },
537 { 0x63, TLB_DATA_1G, 4, " TLB_DATA 1 GByte pages, 4-way set associative" },
538 { 0x76, TLB_INST_2M_4M, 8, " TLB_INST 2-MByte or 4-MByte pages, fully associative" },
539 { 0xb0, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 4-way set associative" },
540 { 0xb1, TLB_INST_2M_4M, 4, " TLB_INST 2M pages, 4-way, 8 entries or 4M pages, 4-way entries" },
541 { 0xb2, TLB_INST_4K, 64, " TLB_INST 4KByte pages, 4-way set associative" },
542 { 0xb3, TLB_DATA_4K, 128, " TLB_DATA 4 KByte pages, 4-way set associative" },
543 { 0xb4, TLB_DATA_4K, 256, " TLB_DATA 4 KByte pages, 4-way associative" },
544 { 0xb5, TLB_INST_4K, 64, " TLB_INST 4 KByte pages, 8-way set ssociative" },
545 { 0xb6, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 8-way set ssociative" },
546 { 0xba, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way associative" },
547 { 0xc0, TLB_DATA_4K_4M, 8, " TLB_DATA 4 KByte and 4 MByte pages, 4-way associative" },
548 { 0xc1, STLB_4K_2M, 1024, " STLB 4 KByte and 2 MByte pages, 8-way associative" },
549 { 0xc2, TLB_DATA_2M_4M, 16, " DTLB 2 MByte/4MByte pages, 4-way associative" },
550 { 0xca, STLB_4K, 512, " STLB 4 KByte pages, 4-way associative" },
551 { 0x00, 0, 0 }
552 };
553
554 static void intel_tlb_lookup(const unsigned char desc)
555 {
556 unsigned char k;
557 if (desc == 0)
558 return;
559
560 /* look up this descriptor in the table */
561 for (k = 0; intel_tlb_table[k].descriptor != desc && \
562 intel_tlb_table[k].descriptor != 0; k++)
563 ;
564
565 if (intel_tlb_table[k].tlb_type == 0)
566 return;
567
568 switch (intel_tlb_table[k].tlb_type) {
569 case STLB_4K:
570 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
571 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
572 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
573 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
574 break;
575 case STLB_4K_2M:
576 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
577 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
578 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
579 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
580 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries)
581 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries;
582 if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries)
583 tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries;
584 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
585 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
586 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
587 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
588 break;
589 case TLB_INST_ALL:
590 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
591 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
592 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries)
593 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries;
594 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
595 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
596 break;
597 case TLB_INST_4K:
598 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
599 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
600 break;
601 case TLB_INST_4M:
602 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
603 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
604 break;
605 case TLB_INST_2M_4M:
606 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries)
607 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries;
608 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
609 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
610 break;
611 case TLB_DATA_4K:
612 case TLB_DATA0_4K:
613 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
614 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
615 break;
616 case TLB_DATA_4M:
617 case TLB_DATA0_4M:
618 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
619 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
620 break;
621 case TLB_DATA_2M_4M:
622 case TLB_DATA0_2M_4M:
623 if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries)
624 tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries;
625 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
626 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
627 break;
628 case TLB_DATA_4K_4M:
629 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
630 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
631 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
632 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
633 break;
634 case TLB_DATA_1G:
635 if (tlb_lld_1g[ENTRIES] < intel_tlb_table[k].entries)
636 tlb_lld_1g[ENTRIES] = intel_tlb_table[k].entries;
637 break;
638 }
639 }
640
641 static void intel_tlb_flushall_shift_set(struct cpuinfo_x86 *c)
642 {
643 switch ((c->x86 << 8) + c->x86_model) {
644 case 0x60f: /* original 65 nm celeron/pentium/core2/xeon, "Merom"/"Conroe" */
645 case 0x616: /* single-core 65 nm celeron/core2solo "Merom-L"/"Conroe-L" */
646 case 0x617: /* current 45 nm celeron/core2/xeon "Penryn"/"Wolfdale" */
647 case 0x61d: /* six-core 45 nm xeon "Dunnington" */
648 tlb_flushall_shift = -1;
649 break;
650 case 0x63a: /* Ivybridge */
651 tlb_flushall_shift = 2;
652 break;
653 case 0x61a: /* 45 nm nehalem, "Bloomfield" */
654 case 0x61e: /* 45 nm nehalem, "Lynnfield" */
655 case 0x625: /* 32 nm nehalem, "Clarkdale" */
656 case 0x62c: /* 32 nm nehalem, "Gulftown" */
657 case 0x62e: /* 45 nm nehalem-ex, "Beckton" */
658 case 0x62f: /* 32 nm Xeon E7 */
659 case 0x62a: /* SandyBridge */
660 case 0x62d: /* SandyBridge, "Romely-EP" */
661 default:
662 tlb_flushall_shift = 6;
663 }
664 }
665
666 static void intel_detect_tlb(struct cpuinfo_x86 *c)
667 {
668 int i, j, n;
669 unsigned int regs[4];
670 unsigned char *desc = (unsigned char *)regs;
671
672 if (c->cpuid_level < 2)
673 return;
674
675 /* Number of times to iterate */
676 n = cpuid_eax(2) & 0xFF;
677
678 for (i = 0 ; i < n ; i++) {
679 cpuid(2, &regs[0], &regs[1], &regs[2], &regs[3]);
680
681 /* If bit 31 is set, this is an unknown format */
682 for (j = 0 ; j < 3 ; j++)
683 if (regs[j] & (1 << 31))
684 regs[j] = 0;
685
686 /* Byte 0 is level count, not a descriptor */
687 for (j = 1 ; j < 16 ; j++)
688 intel_tlb_lookup(desc[j]);
689 }
690 intel_tlb_flushall_shift_set(c);
691 }
692
693 static const struct cpu_dev intel_cpu_dev = {
694 .c_vendor = "Intel",
695 .c_ident = { "GenuineIntel" },
696 #ifdef CONFIG_X86_32
697 .legacy_models = {
698 { .family = 4, .model_names =
699 {
700 [0] = "486 DX-25/33",
701 [1] = "486 DX-50",
702 [2] = "486 SX",
703 [3] = "486 DX/2",
704 [4] = "486 SL",
705 [5] = "486 SX/2",
706 [7] = "486 DX/2-WB",
707 [8] = "486 DX/4",
708 [9] = "486 DX/4-WB"
709 }
710 },
711 { .family = 5, .model_names =
712 {
713 [0] = "Pentium 60/66 A-step",
714 [1] = "Pentium 60/66",
715 [2] = "Pentium 75 - 200",
716 [3] = "OverDrive PODP5V83",
717 [4] = "Pentium MMX",
718 [7] = "Mobile Pentium 75 - 200",
719 [8] = "Mobile Pentium MMX"
720 }
721 },
722 { .family = 6, .model_names =
723 {
724 [0] = "Pentium Pro A-step",
725 [1] = "Pentium Pro",
726 [3] = "Pentium II (Klamath)",
727 [4] = "Pentium II (Deschutes)",
728 [5] = "Pentium II (Deschutes)",
729 [6] = "Mobile Pentium II",
730 [7] = "Pentium III (Katmai)",
731 [8] = "Pentium III (Coppermine)",
732 [10] = "Pentium III (Cascades)",
733 [11] = "Pentium III (Tualatin)",
734 }
735 },
736 { .family = 15, .model_names =
737 {
738 [0] = "Pentium 4 (Unknown)",
739 [1] = "Pentium 4 (Willamette)",
740 [2] = "Pentium 4 (Northwood)",
741 [4] = "Pentium 4 (Foster)",
742 [5] = "Pentium 4 (Foster)",
743 }
744 },
745 },
746 .legacy_cache_size = intel_size_cache,
747 #endif
748 .c_detect_tlb = intel_detect_tlb,
749 .c_early_init = early_init_intel,
750 .c_init = init_intel,
751 .c_x86_vendor = X86_VENDOR_INTEL,
752 };
753
754 cpu_dev_register(intel_cpu_dev);
755
Linux kernel - Deliverables
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