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Merge branch 'x86-headers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[deliverable/linux.git] / arch / x86 / kernel / cpu / intel.c
1 #include <linux/kernel.h>
2
3 #include <linux/string.h>
4 #include <linux/bitops.h>
5 #include <linux/smp.h>
6 #include <linux/sched.h>
7 #include <linux/thread_info.h>
8 #include <linux/init.h>
9 #include <linux/uaccess.h>
10
11 #include <asm/cpufeature.h>
12 #include <asm/pgtable.h>
13 #include <asm/msr.h>
14 #include <asm/bugs.h>
15 #include <asm/cpu.h>
16 #include <asm/intel-family.h>
17
18 #ifdef CONFIG_X86_64
19 #include <linux/topology.h>
20 #endif
21
22 #include "cpu.h"
23
24 #ifdef CONFIG_X86_LOCAL_APIC
25 #include <asm/mpspec.h>
26 #include <asm/apic.h>
27 #endif
28
29 /*
30 * Just in case our CPU detection goes bad, or you have a weird system,
31 * allow a way to override the automatic disabling of MPX.
32 */
33 static int forcempx;
34
35 static int __init forcempx_setup(char *__unused)
36 {
37 forcempx = 1;
38
39 return 1;
40 }
41 __setup("intel-skd-046-workaround=disable", forcempx_setup);
42
43 void check_mpx_erratum(struct cpuinfo_x86 *c)
44 {
45 if (forcempx)
46 return;
47 /*
48 * Turn off the MPX feature on CPUs where SMEP is not
49 * available or disabled.
50 *
51 * Works around Intel Erratum SKD046: "Branch Instructions
52 * May Initialize MPX Bound Registers Incorrectly".
53 *
54 * This might falsely disable MPX on systems without
55 * SMEP, like Atom processors without SMEP. But there
56 * is no such hardware known at the moment.
57 */
58 if (cpu_has(c, X86_FEATURE_MPX) && !cpu_has(c, X86_FEATURE_SMEP)) {
59 setup_clear_cpu_cap(X86_FEATURE_MPX);
60 pr_warn("x86/mpx: Disabling MPX since SMEP not present\n");
61 }
62 }
63
64 static void early_init_intel(struct cpuinfo_x86 *c)
65 {
66 u64 misc_enable;
67
68 /* Unmask CPUID levels if masked: */
69 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {
70 if (msr_clear_bit(MSR_IA32_MISC_ENABLE,
71 MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT) > 0) {
72 c->cpuid_level = cpuid_eax(0);
73 get_cpu_cap(c);
74 }
75 }
76
77 if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
78 (c->x86 == 0x6 && c->x86_model >= 0x0e))
79 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
80
81 if (c->x86 >= 6 && !cpu_has(c, X86_FEATURE_IA64)) {
82 unsigned lower_word;
83
84 wrmsr(MSR_IA32_UCODE_REV, 0, 0);
85 /* Required by the SDM */
86 sync_core();
87 rdmsr(MSR_IA32_UCODE_REV, lower_word, c->microcode);
88 }
89
90 /*
91 * Atom erratum AAE44/AAF40/AAG38/AAH41:
92 *
93 * A race condition between speculative fetches and invalidating
94 * a large page. This is worked around in microcode, but we
95 * need the microcode to have already been loaded... so if it is
96 * not, recommend a BIOS update and disable large pages.
97 */
98 if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_mask <= 2 &&
99 c->microcode < 0x20e) {
100 pr_warn("Atom PSE erratum detected, BIOS microcode update recommended\n");
101 clear_cpu_cap(c, X86_FEATURE_PSE);
102 }
103
104 #ifdef CONFIG_X86_64
105 set_cpu_cap(c, X86_FEATURE_SYSENTER32);
106 #else
107 /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */
108 if (c->x86 == 15 && c->x86_cache_alignment == 64)
109 c->x86_cache_alignment = 128;
110 #endif
111
112 /* CPUID workaround for 0F33/0F34 CPU */
113 if (c->x86 == 0xF && c->x86_model == 0x3
114 && (c->x86_mask == 0x3 || c->x86_mask == 0x4))
115 c->x86_phys_bits = 36;
116
117 /*
118 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
119 * with P/T states and does not stop in deep C-states.
120 *
121 * It is also reliable across cores and sockets. (but not across
122 * cabinets - we turn it off in that case explicitly.)
123 */
124 if (c->x86_power & (1 << 8)) {
125 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
126 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
127 if (!check_tsc_unstable())
128 set_sched_clock_stable();
129 }
130
131 /* Penwell and Cloverview have the TSC which doesn't sleep on S3 */
132 if (c->x86 == 6) {
133 switch (c->x86_model) {
134 case 0x27: /* Penwell */
135 case 0x35: /* Cloverview */
136 case 0x4a: /* Merrifield */
137 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC_S3);
138 break;
139 default:
140 break;
141 }
142 }
143
144 /*
145 * There is a known erratum on Pentium III and Core Solo
146 * and Core Duo CPUs.
147 * " Page with PAT set to WC while associated MTRR is UC
148 * may consolidate to UC "
149 * Because of this erratum, it is better to stick with
150 * setting WC in MTRR rather than using PAT on these CPUs.
151 *
152 * Enable PAT WC only on P4, Core 2 or later CPUs.
153 */
154 if (c->x86 == 6 && c->x86_model < 15)
155 clear_cpu_cap(c, X86_FEATURE_PAT);
156
157 #ifdef CONFIG_KMEMCHECK
158 /*
159 * P4s have a "fast strings" feature which causes single-
160 * stepping REP instructions to only generate a #DB on
161 * cache-line boundaries.
162 *
163 * Ingo Molnar reported a Pentium D (model 6) and a Xeon
164 * (model 2) with the same problem.
165 */
166 if (c->x86 == 15)
167 if (msr_clear_bit(MSR_IA32_MISC_ENABLE,
168 MSR_IA32_MISC_ENABLE_FAST_STRING_BIT) > 0)
169 pr_info("kmemcheck: Disabling fast string operations\n");
170 #endif
171
172 /*
173 * If fast string is not enabled in IA32_MISC_ENABLE for any reason,
174 * clear the fast string and enhanced fast string CPU capabilities.
175 */
176 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {
177 rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
178 if (!(misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING)) {
179 pr_info("Disabled fast string operations\n");
180 setup_clear_cpu_cap(X86_FEATURE_REP_GOOD);
181 setup_clear_cpu_cap(X86_FEATURE_ERMS);
182 }
183 }
184
185 /*
186 * Intel Quark Core DevMan_001.pdf section 6.4.11
187 * "The operating system also is required to invalidate (i.e., flush)
188 * the TLB when any changes are made to any of the page table entries.
189 * The operating system must reload CR3 to cause the TLB to be flushed"
190 *
191 * As a result, boot_cpu_has(X86_FEATURE_PGE) in arch/x86/include/asm/tlbflush.h
192 * should be false so that __flush_tlb_all() causes CR3 insted of CR4.PGE
193 * to be modified.
194 */
195 if (c->x86 == 5 && c->x86_model == 9) {
196 pr_info("Disabling PGE capability bit\n");
197 setup_clear_cpu_cap(X86_FEATURE_PGE);
198 }
199
200 if (c->cpuid_level >= 0x00000001) {
201 u32 eax, ebx, ecx, edx;
202
203 cpuid(0x00000001, &eax, &ebx, &ecx, &edx);
204 /*
205 * If HTT (EDX[28]) is set EBX[16:23] contain the number of
206 * apicids which are reserved per package. Store the resulting
207 * shift value for the package management code.
208 */
209 if (edx & (1U << 28))
210 c->x86_coreid_bits = get_count_order((ebx >> 16) & 0xff);
211 }
212
213 check_mpx_erratum(c);
214 }
215
216 #ifdef CONFIG_X86_32
217 /*
218 * Early probe support logic for ppro memory erratum #50
219 *
220 * This is called before we do cpu ident work
221 */
222
223 int ppro_with_ram_bug(void)
224 {
225 /* Uses data from early_cpu_detect now */
226 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
227 boot_cpu_data.x86 == 6 &&
228 boot_cpu_data.x86_model == 1 &&
229 boot_cpu_data.x86_mask < 8) {
230 pr_info("Pentium Pro with Errata#50 detected. Taking evasive action.\n");
231 return 1;
232 }
233 return 0;
234 }
235
236 static void intel_smp_check(struct cpuinfo_x86 *c)
237 {
238 /* calling is from identify_secondary_cpu() ? */
239 if (!c->cpu_index)
240 return;
241
242 /*
243 * Mask B, Pentium, but not Pentium MMX
244 */
245 if (c->x86 == 5 &&
246 c->x86_mask >= 1 && c->x86_mask <= 4 &&
247 c->x86_model <= 3) {
248 /*
249 * Remember we have B step Pentia with bugs
250 */
251 WARN_ONCE(1, "WARNING: SMP operation may be unreliable"
252 "with B stepping processors.\n");
253 }
254 }
255
256 static int forcepae;
257 static int __init forcepae_setup(char *__unused)
258 {
259 forcepae = 1;
260 return 1;
261 }
262 __setup("forcepae", forcepae_setup);
263
264 static void intel_workarounds(struct cpuinfo_x86 *c)
265 {
266 #ifdef CONFIG_X86_F00F_BUG
267 /*
268 * All models of Pentium and Pentium with MMX technology CPUs
269 * have the F0 0F bug, which lets nonprivileged users lock up the
270 * system. Announce that the fault handler will be checking for it.
271 * The Quark is also family 5, but does not have the same bug.
272 */
273 clear_cpu_bug(c, X86_BUG_F00F);
274 if (c->x86 == 5 && c->x86_model < 9) {
275 static int f00f_workaround_enabled;
276
277 set_cpu_bug(c, X86_BUG_F00F);
278 if (!f00f_workaround_enabled) {
279 pr_notice("Intel Pentium with F0 0F bug - workaround enabled.\n");
280 f00f_workaround_enabled = 1;
281 }
282 }
283 #endif
284
285 /*
286 * SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until
287 * model 3 mask 3
288 */
289 if ((c->x86<<8 | c->x86_model<<4 | c->x86_mask) < 0x633)
290 clear_cpu_cap(c, X86_FEATURE_SEP);
291
292 /*
293 * PAE CPUID issue: many Pentium M report no PAE but may have a
294 * functionally usable PAE implementation.
295 * Forcefully enable PAE if kernel parameter "forcepae" is present.
296 */
297 if (forcepae) {
298 pr_warn("PAE forced!\n");
299 set_cpu_cap(c, X86_FEATURE_PAE);
300 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE);
301 }
302
303 /*
304 * P4 Xeon erratum 037 workaround.
305 * Hardware prefetcher may cause stale data to be loaded into the cache.
306 */
307 if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) {
308 if (msr_set_bit(MSR_IA32_MISC_ENABLE,
309 MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) > 0) {
310 pr_info("CPU: C0 stepping P4 Xeon detected.\n");
311 pr_info("CPU: Disabling hardware prefetching (Erratum 037)\n");
312 }
313 }
314
315 /*
316 * See if we have a good local APIC by checking for buggy Pentia,
317 * i.e. all B steppings and the C2 stepping of P54C when using their
318 * integrated APIC (see 11AP erratum in "Pentium Processor
319 * Specification Update").
320 */
321 if (boot_cpu_has(X86_FEATURE_APIC) && (c->x86<<8 | c->x86_model<<4) == 0x520 &&
322 (c->x86_mask < 0x6 || c->x86_mask == 0xb))
323 set_cpu_bug(c, X86_BUG_11AP);
324
325
326 #ifdef CONFIG_X86_INTEL_USERCOPY
327 /*
328 * Set up the preferred alignment for movsl bulk memory moves
329 */
330 switch (c->x86) {
331 case 4: /* 486: untested */
332 break;
333 case 5: /* Old Pentia: untested */
334 break;
335 case 6: /* PII/PIII only like movsl with 8-byte alignment */
336 movsl_mask.mask = 7;
337 break;
338 case 15: /* P4 is OK down to 8-byte alignment */
339 movsl_mask.mask = 7;
340 break;
341 }
342 #endif
343
344 intel_smp_check(c);
345 }
346 #else
347 static void intel_workarounds(struct cpuinfo_x86 *c)
348 {
349 }
350 #endif
351
352 static void srat_detect_node(struct cpuinfo_x86 *c)
353 {
354 #ifdef CONFIG_NUMA
355 unsigned node;
356 int cpu = smp_processor_id();
357
358 /* Don't do the funky fallback heuristics the AMD version employs
359 for now. */
360 node = numa_cpu_node(cpu);
361 if (node == NUMA_NO_NODE || !node_online(node)) {
362 /* reuse the value from init_cpu_to_node() */
363 node = cpu_to_node(cpu);
364 }
365 numa_set_node(cpu, node);
366 #endif
367 }
368
369 /*
370 * find out the number of processor cores on the die
371 */
372 static int intel_num_cpu_cores(struct cpuinfo_x86 *c)
373 {
374 unsigned int eax, ebx, ecx, edx;
375
376 if (!IS_ENABLED(CONFIG_SMP) || c->cpuid_level < 4)
377 return 1;
378
379 /* Intel has a non-standard dependency on %ecx for this CPUID level. */
380 cpuid_count(4, 0, &eax, &ebx, &ecx, &edx);
381 if (eax & 0x1f)
382 return (eax >> 26) + 1;
383 else
384 return 1;
385 }
386
387 static void detect_vmx_virtcap(struct cpuinfo_x86 *c)
388 {
389 /* Intel VMX MSR indicated features */
390 #define X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW 0x00200000
391 #define X86_VMX_FEATURE_PROC_CTLS_VNMI 0x00400000
392 #define X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS 0x80000000
393 #define X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC 0x00000001
394 #define X86_VMX_FEATURE_PROC_CTLS2_EPT 0x00000002
395 #define X86_VMX_FEATURE_PROC_CTLS2_VPID 0x00000020
396
397 u32 vmx_msr_low, vmx_msr_high, msr_ctl, msr_ctl2;
398
399 clear_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
400 clear_cpu_cap(c, X86_FEATURE_VNMI);
401 clear_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
402 clear_cpu_cap(c, X86_FEATURE_EPT);
403 clear_cpu_cap(c, X86_FEATURE_VPID);
404
405 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, vmx_msr_low, vmx_msr_high);
406 msr_ctl = vmx_msr_high | vmx_msr_low;
407 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW)
408 set_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
409 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_VNMI)
410 set_cpu_cap(c, X86_FEATURE_VNMI);
411 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS) {
412 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
413 vmx_msr_low, vmx_msr_high);
414 msr_ctl2 = vmx_msr_high | vmx_msr_low;
415 if ((msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC) &&
416 (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW))
417 set_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
418 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_EPT)
419 set_cpu_cap(c, X86_FEATURE_EPT);
420 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VPID)
421 set_cpu_cap(c, X86_FEATURE_VPID);
422 }
423 }
424
425 static void init_intel_energy_perf(struct cpuinfo_x86 *c)
426 {
427 u64 epb;
428
429 /*
430 * Initialize MSR_IA32_ENERGY_PERF_BIAS if not already initialized.
431 * (x86_energy_perf_policy(8) is available to change it at run-time.)
432 */
433 if (!cpu_has(c, X86_FEATURE_EPB))
434 return;
435
436 rdmsrl(MSR_IA32_ENERGY_PERF_BIAS, epb);
437 if ((epb & 0xF) != ENERGY_PERF_BIAS_PERFORMANCE)
438 return;
439
440 pr_warn_once("ENERGY_PERF_BIAS: Set to 'normal', was 'performance'\n");
441 pr_warn_once("ENERGY_PERF_BIAS: View and update with x86_energy_perf_policy(8)\n");
442 epb = (epb & ~0xF) | ENERGY_PERF_BIAS_NORMAL;
443 wrmsrl(MSR_IA32_ENERGY_PERF_BIAS, epb);
444 }
445
446 static void intel_bsp_resume(struct cpuinfo_x86 *c)
447 {
448 /*
449 * MSR_IA32_ENERGY_PERF_BIAS is lost across suspend/resume,
450 * so reinitialize it properly like during bootup:
451 */
452 init_intel_energy_perf(c);
453 }
454
455 static void init_intel(struct cpuinfo_x86 *c)
456 {
457 unsigned int l2 = 0;
458
459 early_init_intel(c);
460
461 intel_workarounds(c);
462
463 /*
464 * Detect the extended topology information if available. This
465 * will reinitialise the initial_apicid which will be used
466 * in init_intel_cacheinfo()
467 */
468 detect_extended_topology(c);
469
470 if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) {
471 /*
472 * let's use the legacy cpuid vector 0x1 and 0x4 for topology
473 * detection.
474 */
475 c->x86_max_cores = intel_num_cpu_cores(c);
476 #ifdef CONFIG_X86_32
477 detect_ht(c);
478 #endif
479 }
480
481 l2 = init_intel_cacheinfo(c);
482
483 /* Detect legacy cache sizes if init_intel_cacheinfo did not */
484 if (l2 == 0) {
485 cpu_detect_cache_sizes(c);
486 l2 = c->x86_cache_size;
487 }
488
489 if (c->cpuid_level > 9) {
490 unsigned eax = cpuid_eax(10);
491 /* Check for version and the number of counters */
492 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
493 set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
494 }
495
496 if (cpu_has(c, X86_FEATURE_XMM2))
497 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
498
499 if (boot_cpu_has(X86_FEATURE_DS)) {
500 unsigned int l1;
501 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
502 if (!(l1 & (1<<11)))
503 set_cpu_cap(c, X86_FEATURE_BTS);
504 if (!(l1 & (1<<12)))
505 set_cpu_cap(c, X86_FEATURE_PEBS);
506 }
507
508 if (c->x86 == 6 && boot_cpu_has(X86_FEATURE_CLFLUSH) &&
509 (c->x86_model == 29 || c->x86_model == 46 || c->x86_model == 47))
510 set_cpu_bug(c, X86_BUG_CLFLUSH_MONITOR);
511
512 if (c->x86 == 6 && boot_cpu_has(X86_FEATURE_MWAIT) &&
513 ((c->x86_model == INTEL_FAM6_ATOM_GOLDMONT)))
514 set_cpu_bug(c, X86_BUG_MONITOR);
515
516 #ifdef CONFIG_X86_64
517 if (c->x86 == 15)
518 c->x86_cache_alignment = c->x86_clflush_size * 2;
519 if (c->x86 == 6)
520 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
521 #else
522 /*
523 * Names for the Pentium II/Celeron processors
524 * detectable only by also checking the cache size.
525 * Dixon is NOT a Celeron.
526 */
527 if (c->x86 == 6) {
528 char *p = NULL;
529
530 switch (c->x86_model) {
531 case 5:
532 if (l2 == 0)
533 p = "Celeron (Covington)";
534 else if (l2 == 256)
535 p = "Mobile Pentium II (Dixon)";
536 break;
537
538 case 6:
539 if (l2 == 128)
540 p = "Celeron (Mendocino)";
541 else if (c->x86_mask == 0 || c->x86_mask == 5)
542 p = "Celeron-A";
543 break;
544
545 case 8:
546 if (l2 == 128)
547 p = "Celeron (Coppermine)";
548 break;
549 }
550
551 if (p)
552 strcpy(c->x86_model_id, p);
553 }
554
555 if (c->x86 == 15)
556 set_cpu_cap(c, X86_FEATURE_P4);
557 if (c->x86 == 6)
558 set_cpu_cap(c, X86_FEATURE_P3);
559 #endif
560
561 /* Work around errata */
562 srat_detect_node(c);
563
564 if (cpu_has(c, X86_FEATURE_VMX))
565 detect_vmx_virtcap(c);
566
567 init_intel_energy_perf(c);
568 }
569
570 #ifdef CONFIG_X86_32
571 static unsigned int intel_size_cache(struct cpuinfo_x86 *c, unsigned int size)
572 {
573 /*
574 * Intel PIII Tualatin. This comes in two flavours.
575 * One has 256kb of cache, the other 512. We have no way
576 * to determine which, so we use a boottime override
577 * for the 512kb model, and assume 256 otherwise.
578 */
579 if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0))
580 size = 256;
581
582 /*
583 * Intel Quark SoC X1000 contains a 4-way set associative
584 * 16K cache with a 16 byte cache line and 256 lines per tag
585 */
586 if ((c->x86 == 5) && (c->x86_model == 9))
587 size = 16;
588 return size;
589 }
590 #endif
591
592 #define TLB_INST_4K 0x01
593 #define TLB_INST_4M 0x02
594 #define TLB_INST_2M_4M 0x03
595
596 #define TLB_INST_ALL 0x05
597 #define TLB_INST_1G 0x06
598
599 #define TLB_DATA_4K 0x11
600 #define TLB_DATA_4M 0x12
601 #define TLB_DATA_2M_4M 0x13
602 #define TLB_DATA_4K_4M 0x14
603
604 #define TLB_DATA_1G 0x16
605
606 #define TLB_DATA0_4K 0x21
607 #define TLB_DATA0_4M 0x22
608 #define TLB_DATA0_2M_4M 0x23
609
610 #define STLB_4K 0x41
611 #define STLB_4K_2M 0x42
612
613 static const struct _tlb_table intel_tlb_table[] = {
614 { 0x01, TLB_INST_4K, 32, " TLB_INST 4 KByte pages, 4-way set associative" },
615 { 0x02, TLB_INST_4M, 2, " TLB_INST 4 MByte pages, full associative" },
616 { 0x03, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way set associative" },
617 { 0x04, TLB_DATA_4M, 8, " TLB_DATA 4 MByte pages, 4-way set associative" },
618 { 0x05, TLB_DATA_4M, 32, " TLB_DATA 4 MByte pages, 4-way set associative" },
619 { 0x0b, TLB_INST_4M, 4, " TLB_INST 4 MByte pages, 4-way set associative" },
620 { 0x4f, TLB_INST_4K, 32, " TLB_INST 4 KByte pages */" },
621 { 0x50, TLB_INST_ALL, 64, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
622 { 0x51, TLB_INST_ALL, 128, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
623 { 0x52, TLB_INST_ALL, 256, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
624 { 0x55, TLB_INST_2M_4M, 7, " TLB_INST 2-MByte or 4-MByte pages, fully associative" },
625 { 0x56, TLB_DATA0_4M, 16, " TLB_DATA0 4 MByte pages, 4-way set associative" },
626 { 0x57, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, 4-way associative" },
627 { 0x59, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, fully associative" },
628 { 0x5a, TLB_DATA0_2M_4M, 32, " TLB_DATA0 2-MByte or 4 MByte pages, 4-way set associative" },
629 { 0x5b, TLB_DATA_4K_4M, 64, " TLB_DATA 4 KByte and 4 MByte pages" },
630 { 0x5c, TLB_DATA_4K_4M, 128, " TLB_DATA 4 KByte and 4 MByte pages" },
631 { 0x5d, TLB_DATA_4K_4M, 256, " TLB_DATA 4 KByte and 4 MByte pages" },
632 { 0x61, TLB_INST_4K, 48, " TLB_INST 4 KByte pages, full associative" },
633 { 0x63, TLB_DATA_1G, 4, " TLB_DATA 1 GByte pages, 4-way set associative" },
634 { 0x76, TLB_INST_2M_4M, 8, " TLB_INST 2-MByte or 4-MByte pages, fully associative" },
635 { 0xb0, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 4-way set associative" },
636 { 0xb1, TLB_INST_2M_4M, 4, " TLB_INST 2M pages, 4-way, 8 entries or 4M pages, 4-way entries" },
637 { 0xb2, TLB_INST_4K, 64, " TLB_INST 4KByte pages, 4-way set associative" },
638 { 0xb3, TLB_DATA_4K, 128, " TLB_DATA 4 KByte pages, 4-way set associative" },
639 { 0xb4, TLB_DATA_4K, 256, " TLB_DATA 4 KByte pages, 4-way associative" },
640 { 0xb5, TLB_INST_4K, 64, " TLB_INST 4 KByte pages, 8-way set associative" },
641 { 0xb6, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 8-way set associative" },
642 { 0xba, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way associative" },
643 { 0xc0, TLB_DATA_4K_4M, 8, " TLB_DATA 4 KByte and 4 MByte pages, 4-way associative" },
644 { 0xc1, STLB_4K_2M, 1024, " STLB 4 KByte and 2 MByte pages, 8-way associative" },
645 { 0xc2, TLB_DATA_2M_4M, 16, " DTLB 2 MByte/4MByte pages, 4-way associative" },
646 { 0xca, STLB_4K, 512, " STLB 4 KByte pages, 4-way associative" },
647 { 0x00, 0, 0 }
648 };
649
650 static void intel_tlb_lookup(const unsigned char desc)
651 {
652 unsigned char k;
653 if (desc == 0)
654 return;
655
656 /* look up this descriptor in the table */
657 for (k = 0; intel_tlb_table[k].descriptor != desc && \
658 intel_tlb_table[k].descriptor != 0; k++)
659 ;
660
661 if (intel_tlb_table[k].tlb_type == 0)
662 return;
663
664 switch (intel_tlb_table[k].tlb_type) {
665 case STLB_4K:
666 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
667 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
668 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
669 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
670 break;
671 case STLB_4K_2M:
672 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
673 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
674 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
675 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
676 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries)
677 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries;
678 if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries)
679 tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries;
680 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
681 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
682 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
683 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
684 break;
685 case TLB_INST_ALL:
686 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
687 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
688 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries)
689 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries;
690 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
691 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
692 break;
693 case TLB_INST_4K:
694 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
695 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
696 break;
697 case TLB_INST_4M:
698 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
699 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
700 break;
701 case TLB_INST_2M_4M:
702 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries)
703 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries;
704 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
705 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
706 break;
707 case TLB_DATA_4K:
708 case TLB_DATA0_4K:
709 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
710 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
711 break;
712 case TLB_DATA_4M:
713 case TLB_DATA0_4M:
714 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
715 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
716 break;
717 case TLB_DATA_2M_4M:
718 case TLB_DATA0_2M_4M:
719 if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries)
720 tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries;
721 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
722 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
723 break;
724 case TLB_DATA_4K_4M:
725 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
726 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
727 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
728 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
729 break;
730 case TLB_DATA_1G:
731 if (tlb_lld_1g[ENTRIES] < intel_tlb_table[k].entries)
732 tlb_lld_1g[ENTRIES] = intel_tlb_table[k].entries;
733 break;
734 }
735 }
736
737 static void intel_detect_tlb(struct cpuinfo_x86 *c)
738 {
739 int i, j, n;
740 unsigned int regs[4];
741 unsigned char *desc = (unsigned char *)regs;
742
743 if (c->cpuid_level < 2)
744 return;
745
746 /* Number of times to iterate */
747 n = cpuid_eax(2) & 0xFF;
748
749 for (i = 0 ; i < n ; i++) {
750 cpuid(2, &regs[0], &regs[1], &regs[2], &regs[3]);
751
752 /* If bit 31 is set, this is an unknown format */
753 for (j = 0 ; j < 3 ; j++)
754 if (regs[j] & (1 << 31))
755 regs[j] = 0;
756
757 /* Byte 0 is level count, not a descriptor */
758 for (j = 1 ; j < 16 ; j++)
759 intel_tlb_lookup(desc[j]);
760 }
761 }
762
763 static const struct cpu_dev intel_cpu_dev = {
764 .c_vendor = "Intel",
765 .c_ident = { "GenuineIntel" },
766 #ifdef CONFIG_X86_32
767 .legacy_models = {
768 { .family = 4, .model_names =
769 {
770 [0] = "486 DX-25/33",
771 [1] = "486 DX-50",
772 [2] = "486 SX",
773 [3] = "486 DX/2",
774 [4] = "486 SL",
775 [5] = "486 SX/2",
776 [7] = "486 DX/2-WB",
777 [8] = "486 DX/4",
778 [9] = "486 DX/4-WB"
779 }
780 },
781 { .family = 5, .model_names =
782 {
783 [0] = "Pentium 60/66 A-step",
784 [1] = "Pentium 60/66",
785 [2] = "Pentium 75 - 200",
786 [3] = "OverDrive PODP5V83",
787 [4] = "Pentium MMX",
788 [7] = "Mobile Pentium 75 - 200",
789 [8] = "Mobile Pentium MMX",
790 [9] = "Quark SoC X1000",
791 }
792 },
793 { .family = 6, .model_names =
794 {
795 [0] = "Pentium Pro A-step",
796 [1] = "Pentium Pro",
797 [3] = "Pentium II (Klamath)",
798 [4] = "Pentium II (Deschutes)",
799 [5] = "Pentium II (Deschutes)",
800 [6] = "Mobile Pentium II",
801 [7] = "Pentium III (Katmai)",
802 [8] = "Pentium III (Coppermine)",
803 [10] = "Pentium III (Cascades)",
804 [11] = "Pentium III (Tualatin)",
805 }
806 },
807 { .family = 15, .model_names =
808 {
809 [0] = "Pentium 4 (Unknown)",
810 [1] = "Pentium 4 (Willamette)",
811 [2] = "Pentium 4 (Northwood)",
812 [4] = "Pentium 4 (Foster)",
813 [5] = "Pentium 4 (Foster)",
814 }
815 },
816 },
817 .legacy_cache_size = intel_size_cache,
818 #endif
819 .c_detect_tlb = intel_detect_tlb,
820 .c_early_init = early_init_intel,
821 .c_init = init_intel,
822 .c_bsp_resume = intel_bsp_resume,
823 .c_x86_vendor = X86_VENDOR_INTEL,
824 };
825
826 cpu_dev_register(intel_cpu_dev);
827
Linux kernel - Deliverables
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