2 * Athlon specific Machine Check Exception Reporting
3 * (C) Copyright 2002 Dave Jones <davej@redhat.com>
5 #include <linux/interrupt.h>
6 #include <linux/kernel.h>
7 #include <linux/types.h>
8 #include <linux/init.h>
11 #include <asm/processor.h>
12 #include <asm/system.h>
17 /* Machine Check Handler For AMD Athlon/Duron: */
18 static void k7_machine_check(struct pt_regs
*regs
, long error_code
)
20 u32 alow
, ahigh
, high
, low
;
25 rdmsr(MSR_IA32_MCG_STATUS
, mcgstl
, mcgsth
);
26 if (mcgstl
& (1<<0)) /* Recoverable ? */
29 printk(KERN_EMERG
"CPU %d: Machine Check Exception: %08x%08x\n",
30 smp_processor_id(), mcgsth
, mcgstl
);
32 for (i
= 1; i
< nr_mce_banks
; i
++) {
33 rdmsr(MSR_IA32_MC0_STATUS
+i
*4, low
, high
);
48 rdmsr(MSR_IA32_MC0_MISC
+i
*4, alow
, ahigh
);
49 snprintf(misc
, 20, "[%08x%08x]", ahigh
, alow
);
52 rdmsr(MSR_IA32_MC0_ADDR
+i
*4, alow
, ahigh
);
53 snprintf(addr
, 24, " at %08x%08x", ahigh
, alow
);
56 printk(KERN_EMERG
"CPU %d: Bank %d: %08x%08x%s%s\n",
57 smp_processor_id(), i
, high
, low
, misc
, addr
);
60 wrmsr(MSR_IA32_MC0_STATUS
+i
*4, 0UL, 0UL);
63 add_taint(TAINT_MACHINE_CHECK
);
68 panic("CPU context corrupt");
70 panic("Unable to continue");
72 printk(KERN_EMERG
"Attempting to continue.\n");
75 wrmsr(MSR_IA32_MCG_STATUS
, mcgstl
, mcgsth
);
79 /* AMD K7 machine check is Intel like: */
80 void amd_mcheck_init(struct cpuinfo_x86
*c
)
85 if (!cpu_has(c
, X86_FEATURE_MCE
))
88 machine_check_vector
= k7_machine_check
;
89 /* Make sure the vector pointer is visible before we enable MCEs: */
92 printk(KERN_INFO
"Intel machine check architecture supported.\n");
94 rdmsr(MSR_IA32_MCG_CAP
, l
, h
);
95 if (l
& (1<<8)) /* Control register present ? */
96 wrmsr(MSR_IA32_MCG_CTL
, 0xffffffff, 0xffffffff);
97 nr_mce_banks
= l
& 0xff;
100 * Clear status for MC index 0 separately, we don't touch CTL,
101 * as some K7 Athlons cause spurious MCEs when its enabled:
103 if (boot_cpu_data
.x86
== 6) {
104 wrmsr(MSR_IA32_MC0_STATUS
, 0x0, 0x0);
109 for (; i
< nr_mce_banks
; i
++) {
110 wrmsr(MSR_IA32_MC0_CTL
+4*i
, 0xffffffff, 0xffffffff);
111 wrmsr(MSR_IA32_MC0_STATUS
+4*i
, 0x0, 0x0);
114 set_in_cr4(X86_CR4_MCE
);
115 printk(KERN_INFO
"Intel machine check reporting enabled on CPU#%d.\n",
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