arch/x86/kernel/cpu/mcheck/k7.c

   1 /*
   2  * Athlon specific Machine Check Exception Reporting
   3  * (C) Copyright 2002 Dave Jones <davej@redhat.com>
   4  */
   5 #include <linux/interrupt.h>
   6 #include <linux/kernel.h>
   7 #include <linux/types.h>
   8 #include <linux/init.h>
   9 #include <linux/smp.h>
  10
  11 #include <asm/processor.h>
  12 #include <asm/system.h>
  13 #include <asm/msr.h>
  14
  15 #include "mce.h"
  16
  17 /* Machine Check Handler For AMD Athlon/Duron: */
  18 static void k7_machine_check(struct pt_regs *regs, long error_code)
  19 {
  20         u32 alow, ahigh, high, low;
  21         u32 mcgstl, mcgsth;
  22         int recover = 1;
  23         int i;
  24
  25         rdmsr(MSR_IA32_MCG_STATUS, mcgstl, mcgsth);
  26         if (mcgstl & (1<<0))    /* Recoverable ? */
  27                 recover = 0;
  28
  29         printk(KERN_EMERG "CPU %d: Machine Check Exception: %08x%08x\n",
  30                 smp_processor_id(), mcgsth, mcgstl);
  31
  32         for (i = 1; i < nr_mce_banks; i++) {
  33                 rdmsr(MSR_IA32_MC0_STATUS+i*4, low, high);
  34                 if (high & (1<<31)) {
  35                         char misc[20];
  36                         char addr[24];
  37
  38                         misc[0] = '\0';
  39                         addr[0] = '\0';
  40
  41                         if (high & (1<<29))
  42                                 recover |= 1;
  43                         if (high & (1<<25))
  44                                 recover |= 2;
  45                         high &= ~(1<<31);
  46
  47                         if (high & (1<<27)) {
  48                                 rdmsr(MSR_IA32_MC0_MISC+i*4, alow, ahigh);
  49                                 snprintf(misc, 20, "[%08x%08x]", ahigh, alow);
  50                         }
  51                         if (high & (1<<26)) {
  52                                 rdmsr(MSR_IA32_MC0_ADDR+i*4, alow, ahigh);
  53                                 snprintf(addr, 24, " at %08x%08x", ahigh, alow);
  54                         }
  55
  56                         printk(KERN_EMERG "CPU %d: Bank %d: %08x%08x%s%s\n",
  57                                 smp_processor_id(), i, high, low, misc, addr);
  58
  59                         /* Clear it: */
  60                         wrmsr(MSR_IA32_MC0_STATUS+i*4, 0UL, 0UL);
  61                         /* Serialize: */
  62                         wmb();
  63                         add_taint(TAINT_MACHINE_CHECK);
  64                 }
  65         }
  66
  67         if (recover & 2)
  68                 panic("CPU context corrupt");
  69         if (recover & 1)
  70                 panic("Unable to continue");
  71
  72         printk(KERN_EMERG "Attempting to continue.\n");
  73
  74         mcgstl &= ~(1<<2);
  75         wrmsr(MSR_IA32_MCG_STATUS, mcgstl, mcgsth);
  76 }
  77
  78
  79 /* AMD K7 machine check is Intel like: */
  80 void amd_mcheck_init(struct cpuinfo_x86 *c)
  81 {
  82         u32 l, h;
  83         int i;
  84
  85         if (!cpu_has(c, X86_FEATURE_MCE))
  86                 return;
  87
  88         machine_check_vector = k7_machine_check;
  89         /* Make sure the vector pointer is visible before we enable MCEs: */
  90         wmb();
  91
  92         printk(KERN_INFO "Intel machine check architecture supported.\n");
  93
  94         rdmsr(MSR_IA32_MCG_CAP, l, h);
  95         if (l & (1<<8)) /* Control register present ? */
  96                 wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
  97         nr_mce_banks = l & 0xff;
  98
  99         /*
 100          * Clear status for MC index 0 separately, we don't touch CTL,
 101          * as some K7 Athlons cause spurious MCEs when its enabled:
 102          */
 103         if (boot_cpu_data.x86 == 6) {
 104                 wrmsr(MSR_IA32_MC0_STATUS, 0x0, 0x0);
 105                 i = 1;
 106         } else
 107                 i = 0;
 108
 109         for (; i < nr_mce_banks; i++) {
 110                 wrmsr(MSR_IA32_MC0_CTL+4*i, 0xffffffff, 0xffffffff);
 111                 wrmsr(MSR_IA32_MC0_STATUS+4*i, 0x0, 0x0);
 112         }
 113
 114         set_in_cr4(X86_CR4_MCE);
 115         printk(KERN_INFO "Intel machine check reporting enabled on CPU#%d.\n",
 116                 smp_processor_id());
 117 }