2 * Machine check handler.
4 * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs.
5 * Rest from unknown author(s).
6 * 2004 Andi Kleen. Rewrote most of it.
7 * Copyright 2008 Intel Corporation
11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
13 #include <linux/thread_info.h>
14 #include <linux/capability.h>
15 #include <linux/miscdevice.h>
16 #include <linux/ratelimit.h>
17 #include <linux/kallsyms.h>
18 #include <linux/rcupdate.h>
19 #include <linux/kobject.h>
20 #include <linux/uaccess.h>
21 #include <linux/kdebug.h>
22 #include <linux/kernel.h>
23 #include <linux/percpu.h>
24 #include <linux/string.h>
25 #include <linux/device.h>
26 #include <linux/syscore_ops.h>
27 #include <linux/delay.h>
28 #include <linux/ctype.h>
29 #include <linux/sched.h>
30 #include <linux/sysfs.h>
31 #include <linux/types.h>
32 #include <linux/slab.h>
33 #include <linux/init.h>
34 #include <linux/kmod.h>
35 #include <linux/poll.h>
36 #include <linux/nmi.h>
37 #include <linux/cpu.h>
38 #include <linux/smp.h>
41 #include <linux/debugfs.h>
42 #include <linux/irq_work.h>
43 #include <linux/export.h>
45 #include <asm/processor.h>
49 #include "mce-internal.h"
51 static DEFINE_MUTEX(mce_chrdev_read_mutex
);
53 #define rcu_dereference_check_mce(p) \
54 rcu_dereference_index_check((p), \
55 rcu_read_lock_sched_held() || \
56 lockdep_is_held(&mce_chrdev_read_mutex))
58 #define CREATE_TRACE_POINTS
59 #include <trace/events/mce.h>
61 int mce_disabled __read_mostly
;
63 #define MISC_MCELOG_MINOR 227
65 #define SPINUNIT 100 /* 100ns */
69 DEFINE_PER_CPU(unsigned, mce_exception_count
);
73 * 0: always panic on uncorrected errors, log corrected errors
74 * 1: panic or SIGBUS on uncorrected errors, log corrected errors
75 * 2: SIGBUS or log uncorrected errors (if possible), log corrected errors
76 * 3: never panic or SIGBUS, log all errors (for testing only)
78 static int tolerant __read_mostly
= 1;
79 static int banks __read_mostly
;
80 static int rip_msr __read_mostly
;
81 static int mce_bootlog __read_mostly
= -1;
82 static int monarch_timeout __read_mostly
= -1;
83 static int mce_panic_timeout __read_mostly
;
84 static int mce_dont_log_ce __read_mostly
;
85 int mce_cmci_disabled __read_mostly
;
86 int mce_ignore_ce __read_mostly
;
87 int mce_ser __read_mostly
;
89 struct mce_bank
*mce_banks __read_mostly
;
91 /* User mode helper program triggered by machine check event */
92 static unsigned long mce_need_notify
;
93 static char mce_helper
[128];
94 static char *mce_helper_argv
[2] = { mce_helper
, NULL
};
96 static DECLARE_WAIT_QUEUE_HEAD(mce_chrdev_wait
);
98 static DEFINE_PER_CPU(struct mce
, mces_seen
);
99 static int cpu_missing
;
101 /* MCA banks polled by the period polling timer for corrected events */
102 DEFINE_PER_CPU(mce_banks_t
, mce_poll_banks
) = {
103 [0 ... BITS_TO_LONGS(MAX_NR_BANKS
)-1] = ~0UL
106 static DEFINE_PER_CPU(struct work_struct
, mce_work
);
109 * CPU/chipset specific EDAC code can register a notifier call here to print
110 * MCE errors in a human-readable form.
112 ATOMIC_NOTIFIER_HEAD(x86_mce_decoder_chain
);
114 /* Do initial initialization of a struct mce */
115 void mce_setup(struct mce
*m
)
117 memset(m
, 0, sizeof(struct mce
));
118 m
->cpu
= m
->extcpu
= smp_processor_id();
120 /* We hope get_seconds stays lockless */
121 m
->time
= get_seconds();
122 m
->cpuvendor
= boot_cpu_data
.x86_vendor
;
123 m
->cpuid
= cpuid_eax(1);
124 m
->socketid
= cpu_data(m
->extcpu
).phys_proc_id
;
125 m
->apicid
= cpu_data(m
->extcpu
).initial_apicid
;
126 rdmsrl(MSR_IA32_MCG_CAP
, m
->mcgcap
);
129 DEFINE_PER_CPU(struct mce
, injectm
);
130 EXPORT_PER_CPU_SYMBOL_GPL(injectm
);
133 * Lockless MCE logging infrastructure.
134 * This avoids deadlocks on printk locks without having to break locks. Also
135 * separate MCEs from kernel messages to avoid bogus bug reports.
138 static struct mce_log mcelog
= {
139 .signature
= MCE_LOG_SIGNATURE
,
141 .recordlen
= sizeof(struct mce
),
144 void mce_log(struct mce
*mce
)
146 unsigned next
, entry
;
149 /* Emit the trace record: */
150 trace_mce_record(mce
);
152 ret
= atomic_notifier_call_chain(&x86_mce_decoder_chain
, 0, mce
);
153 if (ret
== NOTIFY_STOP
)
159 entry
= rcu_dereference_check_mce(mcelog
.next
);
163 * When the buffer fills up discard new entries.
164 * Assume that the earlier errors are the more
167 if (entry
>= MCE_LOG_LEN
) {
168 set_bit(MCE_OVERFLOW
,
169 (unsigned long *)&mcelog
.flags
);
172 /* Old left over entry. Skip: */
173 if (mcelog
.entry
[entry
].finished
) {
181 if (cmpxchg(&mcelog
.next
, entry
, next
) == entry
)
184 memcpy(mcelog
.entry
+ entry
, mce
, sizeof(struct mce
));
186 mcelog
.entry
[entry
].finished
= 1;
190 set_bit(0, &mce_need_notify
);
193 static void drain_mcelog_buffer(void)
195 unsigned int next
, i
, prev
= 0;
197 next
= ACCESS_ONCE(mcelog
.next
);
202 /* drain what was logged during boot */
203 for (i
= prev
; i
< next
; i
++) {
204 unsigned long start
= jiffies
;
205 unsigned retries
= 1;
207 m
= &mcelog
.entry
[i
];
209 while (!m
->finished
) {
210 if (time_after_eq(jiffies
, start
+ 2*retries
))
215 if (!m
->finished
&& retries
>= 4) {
216 pr_err("skipping error being logged currently!\n");
221 atomic_notifier_call_chain(&x86_mce_decoder_chain
, 0, m
);
224 memset(mcelog
.entry
+ prev
, 0, (next
- prev
) * sizeof(*m
));
226 next
= cmpxchg(&mcelog
.next
, prev
, 0);
227 } while (next
!= prev
);
231 void mce_register_decode_chain(struct notifier_block
*nb
)
233 atomic_notifier_chain_register(&x86_mce_decoder_chain
, nb
);
234 drain_mcelog_buffer();
236 EXPORT_SYMBOL_GPL(mce_register_decode_chain
);
238 void mce_unregister_decode_chain(struct notifier_block
*nb
)
240 atomic_notifier_chain_unregister(&x86_mce_decoder_chain
, nb
);
242 EXPORT_SYMBOL_GPL(mce_unregister_decode_chain
);
244 static void print_mce(struct mce
*m
)
248 pr_emerg(HW_ERR
"CPU %d: Machine Check Exception: %Lx Bank %d: %016Lx\n",
249 m
->extcpu
, m
->mcgstatus
, m
->bank
, m
->status
);
252 pr_emerg(HW_ERR
"RIP%s %02x:<%016Lx> ",
253 !(m
->mcgstatus
& MCG_STATUS_EIPV
) ? " !INEXACT!" : "",
256 if (m
->cs
== __KERNEL_CS
)
257 print_symbol("{%s}", m
->ip
);
261 pr_emerg(HW_ERR
"TSC %llx ", m
->tsc
);
263 pr_cont("ADDR %llx ", m
->addr
);
265 pr_cont("MISC %llx ", m
->misc
);
269 * Note this output is parsed by external tools and old fields
270 * should not be changed.
272 pr_emerg(HW_ERR
"PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x microcode %x\n",
273 m
->cpuvendor
, m
->cpuid
, m
->time
, m
->socketid
, m
->apicid
,
274 cpu_data(m
->extcpu
).microcode
);
277 * Print out human-readable details about the MCE error,
278 * (if the CPU has an implementation for that)
280 ret
= atomic_notifier_call_chain(&x86_mce_decoder_chain
, 0, m
);
281 if (ret
== NOTIFY_STOP
)
284 pr_emerg_ratelimited(HW_ERR
"Run the above through 'mcelog --ascii'\n");
287 #define PANIC_TIMEOUT 5 /* 5 seconds */
289 static atomic_t mce_paniced
;
291 static int fake_panic
;
292 static atomic_t mce_fake_paniced
;
294 /* Panic in progress. Enable interrupts and wait for final IPI */
295 static void wait_for_panic(void)
297 long timeout
= PANIC_TIMEOUT
*USEC_PER_SEC
;
301 while (timeout
-- > 0)
303 if (panic_timeout
== 0)
304 panic_timeout
= mce_panic_timeout
;
305 panic("Panicing machine check CPU died");
308 static void mce_panic(char *msg
, struct mce
*final
, char *exp
)
314 * Make sure only one CPU runs in machine check panic
316 if (atomic_inc_return(&mce_paniced
) > 1)
323 /* Don't log too much for fake panic */
324 if (atomic_inc_return(&mce_fake_paniced
) > 1)
327 /* First print corrected ones that are still unlogged */
328 for (i
= 0; i
< MCE_LOG_LEN
; i
++) {
329 struct mce
*m
= &mcelog
.entry
[i
];
330 if (!(m
->status
& MCI_STATUS_VAL
))
332 if (!(m
->status
& MCI_STATUS_UC
)) {
335 apei_err
= apei_write_mce(m
);
338 /* Now print uncorrected but with the final one last */
339 for (i
= 0; i
< MCE_LOG_LEN
; i
++) {
340 struct mce
*m
= &mcelog
.entry
[i
];
341 if (!(m
->status
& MCI_STATUS_VAL
))
343 if (!(m
->status
& MCI_STATUS_UC
))
345 if (!final
|| memcmp(m
, final
, sizeof(struct mce
))) {
348 apei_err
= apei_write_mce(m
);
354 apei_err
= apei_write_mce(final
);
357 pr_emerg(HW_ERR
"Some CPUs didn't answer in synchronization\n");
359 pr_emerg(HW_ERR
"Machine check: %s\n", exp
);
361 if (panic_timeout
== 0)
362 panic_timeout
= mce_panic_timeout
;
365 pr_emerg(HW_ERR
"Fake kernel panic: %s\n", msg
);
368 /* Support code for software error injection */
370 static int msr_to_offset(u32 msr
)
372 unsigned bank
= __this_cpu_read(injectm
.bank
);
375 return offsetof(struct mce
, ip
);
376 if (msr
== MSR_IA32_MCx_STATUS(bank
))
377 return offsetof(struct mce
, status
);
378 if (msr
== MSR_IA32_MCx_ADDR(bank
))
379 return offsetof(struct mce
, addr
);
380 if (msr
== MSR_IA32_MCx_MISC(bank
))
381 return offsetof(struct mce
, misc
);
382 if (msr
== MSR_IA32_MCG_STATUS
)
383 return offsetof(struct mce
, mcgstatus
);
387 /* MSR access wrappers used for error injection */
388 static u64
mce_rdmsrl(u32 msr
)
392 if (__this_cpu_read(injectm
.finished
)) {
393 int offset
= msr_to_offset(msr
);
397 return *(u64
*)((char *)&__get_cpu_var(injectm
) + offset
);
400 if (rdmsrl_safe(msr
, &v
)) {
401 WARN_ONCE(1, "mce: Unable to read msr %d!\n", msr
);
403 * Return zero in case the access faulted. This should
404 * not happen normally but can happen if the CPU does
405 * something weird, or if the code is buggy.
413 static void mce_wrmsrl(u32 msr
, u64 v
)
415 if (__this_cpu_read(injectm
.finished
)) {
416 int offset
= msr_to_offset(msr
);
419 *(u64
*)((char *)&__get_cpu_var(injectm
) + offset
) = v
;
426 * Collect all global (w.r.t. this processor) status about this machine
427 * check into our "mce" struct so that we can use it later to assess
428 * the severity of the problem as we read per-bank specific details.
430 static inline void mce_gather_info(struct mce
*m
, struct pt_regs
*regs
)
434 m
->mcgstatus
= mce_rdmsrl(MSR_IA32_MCG_STATUS
);
437 * Get the address of the instruction at the time of
438 * the machine check error.
440 if (m
->mcgstatus
& (MCG_STATUS_RIPV
|MCG_STATUS_EIPV
)) {
445 * When in VM86 mode make the cs look like ring 3
446 * always. This is a lie, but it's better than passing
447 * the additional vm86 bit around everywhere.
449 if (v8086_mode(regs
))
452 /* Use accurate RIP reporting if available. */
454 m
->ip
= mce_rdmsrl(rip_msr
);
459 * Simple lockless ring to communicate PFNs from the exception handler with the
460 * process context work function. This is vastly simplified because there's
461 * only a single reader and a single writer.
463 #define MCE_RING_SIZE 16 /* we use one entry less */
466 unsigned short start
;
468 unsigned long ring
[MCE_RING_SIZE
];
470 static DEFINE_PER_CPU(struct mce_ring
, mce_ring
);
472 /* Runs with CPU affinity in workqueue */
473 static int mce_ring_empty(void)
475 struct mce_ring
*r
= &__get_cpu_var(mce_ring
);
477 return r
->start
== r
->end
;
480 static int mce_ring_get(unsigned long *pfn
)
487 r
= &__get_cpu_var(mce_ring
);
488 if (r
->start
== r
->end
)
490 *pfn
= r
->ring
[r
->start
];
491 r
->start
= (r
->start
+ 1) % MCE_RING_SIZE
;
498 /* Always runs in MCE context with preempt off */
499 static int mce_ring_add(unsigned long pfn
)
501 struct mce_ring
*r
= &__get_cpu_var(mce_ring
);
504 next
= (r
->end
+ 1) % MCE_RING_SIZE
;
505 if (next
== r
->start
)
507 r
->ring
[r
->end
] = pfn
;
513 int mce_available(struct cpuinfo_x86
*c
)
517 return cpu_has(c
, X86_FEATURE_MCE
) && cpu_has(c
, X86_FEATURE_MCA
);
520 static void mce_schedule_work(void)
522 if (!mce_ring_empty()) {
523 struct work_struct
*work
= &__get_cpu_var(mce_work
);
524 if (!work_pending(work
))
529 DEFINE_PER_CPU(struct irq_work
, mce_irq_work
);
531 static void mce_irq_work_cb(struct irq_work
*entry
)
537 static void mce_report_event(struct pt_regs
*regs
)
539 if (regs
->flags
& (X86_VM_MASK
|X86_EFLAGS_IF
)) {
542 * Triggering the work queue here is just an insurance
543 * policy in case the syscall exit notify handler
544 * doesn't run soon enough or ends up running on the
545 * wrong CPU (can happen when audit sleeps)
551 irq_work_queue(&__get_cpu_var(mce_irq_work
));
555 * Read ADDR and MISC registers.
557 static void mce_read_aux(struct mce
*m
, int i
)
559 if (m
->status
& MCI_STATUS_MISCV
)
560 m
->misc
= mce_rdmsrl(MSR_IA32_MCx_MISC(i
));
561 if (m
->status
& MCI_STATUS_ADDRV
) {
562 m
->addr
= mce_rdmsrl(MSR_IA32_MCx_ADDR(i
));
565 * Mask the reported address by the reported granularity.
567 if (mce_ser
&& (m
->status
& MCI_STATUS_MISCV
)) {
568 u8 shift
= MCI_MISC_ADDR_LSB(m
->misc
);
575 DEFINE_PER_CPU(unsigned, mce_poll_count
);
578 * Poll for corrected events or events that happened before reset.
579 * Those are just logged through /dev/mcelog.
581 * This is executed in standard interrupt context.
583 * Note: spec recommends to panic for fatal unsignalled
584 * errors here. However this would be quite problematic --
585 * we would need to reimplement the Monarch handling and
586 * it would mess up the exclusion between exception handler
587 * and poll hander -- * so we skip this for now.
588 * These cases should not happen anyways, or only when the CPU
589 * is already totally * confused. In this case it's likely it will
590 * not fully execute the machine check handler either.
592 void machine_check_poll(enum mcp_flags flags
, mce_banks_t
*b
)
597 this_cpu_inc(mce_poll_count
);
599 mce_gather_info(&m
, NULL
);
601 for (i
= 0; i
< banks
; i
++) {
602 if (!mce_banks
[i
].ctl
|| !test_bit(i
, *b
))
611 m
.status
= mce_rdmsrl(MSR_IA32_MCx_STATUS(i
));
612 if (!(m
.status
& MCI_STATUS_VAL
))
616 * Uncorrected or signalled events are handled by the exception
617 * handler when it is enabled, so don't process those here.
619 * TBD do the same check for MCI_STATUS_EN here?
621 if (!(flags
& MCP_UC
) &&
622 (m
.status
& (mce_ser
? MCI_STATUS_S
: MCI_STATUS_UC
)))
627 if (!(flags
& MCP_TIMESTAMP
))
630 * Don't get the IP here because it's unlikely to
631 * have anything to do with the actual error location.
633 if (!(flags
& MCP_DONTLOG
) && !mce_dont_log_ce
)
637 * Clear state for this bank.
639 mce_wrmsrl(MSR_IA32_MCx_STATUS(i
), 0);
643 * Don't clear MCG_STATUS here because it's only defined for
649 EXPORT_SYMBOL_GPL(machine_check_poll
);
652 * Do a quick check if any of the events requires a panic.
653 * This decides if we keep the events around or clear them.
655 static int mce_no_way_out(struct mce
*m
, char **msg
, unsigned long *validp
)
659 for (i
= 0; i
< banks
; i
++) {
660 m
->status
= mce_rdmsrl(MSR_IA32_MCx_STATUS(i
));
661 if (m
->status
& MCI_STATUS_VAL
)
662 __set_bit(i
, validp
);
663 if (mce_severity(m
, tolerant
, msg
) >= MCE_PANIC_SEVERITY
)
670 * Variable to establish order between CPUs while scanning.
671 * Each CPU spins initially until executing is equal its number.
673 static atomic_t mce_executing
;
676 * Defines order of CPUs on entry. First CPU becomes Monarch.
678 static atomic_t mce_callin
;
681 * Check if a timeout waiting for other CPUs happened.
683 static int mce_timed_out(u64
*t
)
686 * The others already did panic for some reason.
687 * Bail out like in a timeout.
688 * rmb() to tell the compiler that system_state
689 * might have been modified by someone else.
692 if (atomic_read(&mce_paniced
))
694 if (!monarch_timeout
)
696 if ((s64
)*t
< SPINUNIT
) {
697 /* CHECKME: Make panic default for 1 too? */
699 mce_panic("Timeout synchronizing machine check over CPUs",
706 touch_nmi_watchdog();
711 * The Monarch's reign. The Monarch is the CPU who entered
712 * the machine check handler first. It waits for the others to
713 * raise the exception too and then grades them. When any
714 * error is fatal panic. Only then let the others continue.
716 * The other CPUs entering the MCE handler will be controlled by the
717 * Monarch. They are called Subjects.
719 * This way we prevent any potential data corruption in a unrecoverable case
720 * and also makes sure always all CPU's errors are examined.
722 * Also this detects the case of a machine check event coming from outer
723 * space (not detected by any CPUs) In this case some external agent wants
724 * us to shut down, so panic too.
726 * The other CPUs might still decide to panic if the handler happens
727 * in a unrecoverable place, but in this case the system is in a semi-stable
728 * state and won't corrupt anything by itself. It's ok to let the others
729 * continue for a bit first.
731 * All the spin loops have timeouts; when a timeout happens a CPU
732 * typically elects itself to be Monarch.
734 static void mce_reign(void)
737 struct mce
*m
= NULL
;
738 int global_worst
= 0;
743 * This CPU is the Monarch and the other CPUs have run
744 * through their handlers.
745 * Grade the severity of the errors of all the CPUs.
747 for_each_possible_cpu(cpu
) {
748 int severity
= mce_severity(&per_cpu(mces_seen
, cpu
), tolerant
,
750 if (severity
> global_worst
) {
752 global_worst
= severity
;
753 m
= &per_cpu(mces_seen
, cpu
);
758 * Cannot recover? Panic here then.
759 * This dumps all the mces in the log buffer and stops the
762 if (m
&& global_worst
>= MCE_PANIC_SEVERITY
&& tolerant
< 3)
763 mce_panic("Fatal Machine check", m
, msg
);
766 * For UC somewhere we let the CPU who detects it handle it.
767 * Also must let continue the others, otherwise the handling
768 * CPU could deadlock on a lock.
772 * No machine check event found. Must be some external
773 * source or one CPU is hung. Panic.
775 if (global_worst
<= MCE_KEEP_SEVERITY
&& tolerant
< 3)
776 mce_panic("Machine check from unknown source", NULL
, NULL
);
779 * Now clear all the mces_seen so that they don't reappear on
782 for_each_possible_cpu(cpu
)
783 memset(&per_cpu(mces_seen
, cpu
), 0, sizeof(struct mce
));
786 static atomic_t global_nwo
;
789 * Start of Monarch synchronization. This waits until all CPUs have
790 * entered the exception handler and then determines if any of them
791 * saw a fatal event that requires panic. Then it executes them
792 * in the entry order.
793 * TBD double check parallel CPU hotunplug
795 static int mce_start(int *no_way_out
)
798 int cpus
= num_online_cpus();
799 u64 timeout
= (u64
)monarch_timeout
* NSEC_PER_USEC
;
804 atomic_add(*no_way_out
, &global_nwo
);
806 * global_nwo should be updated before mce_callin
809 order
= atomic_inc_return(&mce_callin
);
814 while (atomic_read(&mce_callin
) != cpus
) {
815 if (mce_timed_out(&timeout
)) {
816 atomic_set(&global_nwo
, 0);
823 * mce_callin should be read before global_nwo
829 * Monarch: Starts executing now, the others wait.
831 atomic_set(&mce_executing
, 1);
834 * Subject: Now start the scanning loop one by one in
835 * the original callin order.
836 * This way when there are any shared banks it will be
837 * only seen by one CPU before cleared, avoiding duplicates.
839 while (atomic_read(&mce_executing
) < order
) {
840 if (mce_timed_out(&timeout
)) {
841 atomic_set(&global_nwo
, 0);
849 * Cache the global no_way_out state.
851 *no_way_out
= atomic_read(&global_nwo
);
857 * Synchronize between CPUs after main scanning loop.
858 * This invokes the bulk of the Monarch processing.
860 static int mce_end(int order
)
863 u64 timeout
= (u64
)monarch_timeout
* NSEC_PER_USEC
;
871 * Allow others to run.
873 atomic_inc(&mce_executing
);
876 /* CHECKME: Can this race with a parallel hotplug? */
877 int cpus
= num_online_cpus();
880 * Monarch: Wait for everyone to go through their scanning
883 while (atomic_read(&mce_executing
) <= cpus
) {
884 if (mce_timed_out(&timeout
))
894 * Subject: Wait for Monarch to finish.
896 while (atomic_read(&mce_executing
) != 0) {
897 if (mce_timed_out(&timeout
))
903 * Don't reset anything. That's done by the Monarch.
909 * Reset all global state.
912 atomic_set(&global_nwo
, 0);
913 atomic_set(&mce_callin
, 0);
917 * Let others run again.
919 atomic_set(&mce_executing
, 0);
924 * Check if the address reported by the CPU is in a format we can parse.
925 * It would be possible to add code for most other cases, but all would
926 * be somewhat complicated (e.g. segment offset would require an instruction
927 * parser). So only support physical addresses up to page granuality for now.
929 static int mce_usable_address(struct mce
*m
)
931 if (!(m
->status
& MCI_STATUS_MISCV
) || !(m
->status
& MCI_STATUS_ADDRV
))
933 if (MCI_MISC_ADDR_LSB(m
->misc
) > PAGE_SHIFT
)
935 if (MCI_MISC_ADDR_MODE(m
->misc
) != MCI_MISC_ADDR_PHYS
)
940 static void mce_clear_state(unsigned long *toclear
)
944 for (i
= 0; i
< banks
; i
++) {
945 if (test_bit(i
, toclear
))
946 mce_wrmsrl(MSR_IA32_MCx_STATUS(i
), 0);
951 * Need to save faulting physical address associated with a process
952 * in the machine check handler some place where we can grab it back
953 * later in mce_notify_process()
955 #define MCE_INFO_MAX 16
959 struct task_struct
*t
;
962 } mce_info
[MCE_INFO_MAX
];
964 static void mce_save_info(__u64 addr
, int c
)
968 for (mi
= mce_info
; mi
< &mce_info
[MCE_INFO_MAX
]; mi
++) {
969 if (atomic_cmpxchg(&mi
->inuse
, 0, 1) == 0) {
977 mce_panic("Too many concurrent recoverable errors", NULL
, NULL
);
980 static struct mce_info
*mce_find_info(void)
984 for (mi
= mce_info
; mi
< &mce_info
[MCE_INFO_MAX
]; mi
++)
985 if (atomic_read(&mi
->inuse
) && mi
->t
== current
)
990 static void mce_clear_info(struct mce_info
*mi
)
992 atomic_set(&mi
->inuse
, 0);
996 * The actual machine check handler. This only handles real
997 * exceptions when something got corrupted coming in through int 18.
999 * This is executed in NMI context not subject to normal locking rules. This
1000 * implies that most kernel services cannot be safely used. Don't even
1001 * think about putting a printk in there!
1003 * On Intel systems this is entered on all CPUs in parallel through
1004 * MCE broadcast. However some CPUs might be broken beyond repair,
1005 * so be always careful when synchronizing with others.
1007 void do_machine_check(struct pt_regs
*regs
, long error_code
)
1009 struct mce m
, *final
;
1014 * Establish sequential order between the CPUs entering the machine
1019 * If no_way_out gets set, there is no safe way to recover from this
1020 * MCE. If tolerant is cranked up, we'll try anyway.
1024 * If kill_it gets set, there might be a way to recover from this
1028 DECLARE_BITMAP(toclear
, MAX_NR_BANKS
);
1029 DECLARE_BITMAP(valid_banks
, MAX_NR_BANKS
);
1030 char *msg
= "Unknown";
1032 atomic_inc(&mce_entry
);
1034 this_cpu_inc(mce_exception_count
);
1039 mce_gather_info(&m
, regs
);
1041 final
= &__get_cpu_var(mces_seen
);
1044 memset(valid_banks
, 0, sizeof(valid_banks
));
1045 no_way_out
= mce_no_way_out(&m
, &msg
, valid_banks
);
1050 * When no restart IP might need to kill or panic.
1051 * Assume the worst for now, but if we find the
1052 * severity is MCE_AR_SEVERITY we have other options.
1054 if (!(m
.mcgstatus
& MCG_STATUS_RIPV
))
1058 * Go through all the banks in exclusion of the other CPUs.
1059 * This way we don't report duplicated events on shared banks
1060 * because the first one to see it will clear it.
1062 order
= mce_start(&no_way_out
);
1063 for (i
= 0; i
< banks
; i
++) {
1064 __clear_bit(i
, toclear
);
1065 if (!test_bit(i
, valid_banks
))
1067 if (!mce_banks
[i
].ctl
)
1074 m
.status
= mce_rdmsrl(MSR_IA32_MCx_STATUS(i
));
1075 if ((m
.status
& MCI_STATUS_VAL
) == 0)
1079 * Non uncorrected or non signaled errors are handled by
1080 * machine_check_poll. Leave them alone, unless this panics.
1082 if (!(m
.status
& (mce_ser
? MCI_STATUS_S
: MCI_STATUS_UC
)) &&
1087 * Set taint even when machine check was not enabled.
1089 add_taint(TAINT_MACHINE_CHECK
);
1091 severity
= mce_severity(&m
, tolerant
, NULL
);
1094 * When machine check was for corrected handler don't touch,
1095 * unless we're panicing.
1097 if (severity
== MCE_KEEP_SEVERITY
&& !no_way_out
)
1099 __set_bit(i
, toclear
);
1100 if (severity
== MCE_NO_SEVERITY
) {
1102 * Machine check event was not enabled. Clear, but
1108 mce_read_aux(&m
, i
);
1111 * Action optional error. Queue address for later processing.
1112 * When the ring overflows we just ignore the AO error.
1113 * RED-PEN add some logging mechanism when
1114 * usable_address or mce_add_ring fails.
1115 * RED-PEN don't ignore overflow for tolerant == 0
1117 if (severity
== MCE_AO_SEVERITY
&& mce_usable_address(&m
))
1118 mce_ring_add(m
.addr
>> PAGE_SHIFT
);
1122 if (severity
> worst
) {
1128 /* mce_clear_state will clear *final, save locally for use later */
1132 mce_clear_state(toclear
);
1135 * Do most of the synchronization with other CPUs.
1136 * When there's any problem use only local no_way_out state.
1138 if (mce_end(order
) < 0)
1139 no_way_out
= worst
>= MCE_PANIC_SEVERITY
;
1142 * At insane "tolerant" levels we take no action. Otherwise
1143 * we only die if we have no other choice. For less serious
1144 * issues we try to recover, or limit damage to the current
1149 mce_panic("Fatal machine check on current CPU", &m
, msg
);
1150 if (worst
== MCE_AR_SEVERITY
) {
1151 /* schedule action before return to userland */
1152 mce_save_info(m
.addr
, m
.mcgstatus
& MCG_STATUS_RIPV
);
1153 set_thread_flag(TIF_MCE_NOTIFY
);
1154 } else if (kill_it
) {
1155 force_sig(SIGBUS
, current
);
1160 mce_report_event(regs
);
1161 mce_wrmsrl(MSR_IA32_MCG_STATUS
, 0);
1163 atomic_dec(&mce_entry
);
1166 EXPORT_SYMBOL_GPL(do_machine_check
);
1168 #ifndef CONFIG_MEMORY_FAILURE
1169 int memory_failure(unsigned long pfn
, int vector
, int flags
)
1171 /* mce_severity() should not hand us an ACTION_REQUIRED error */
1172 BUG_ON(flags
& MF_ACTION_REQUIRED
);
1173 pr_err("Uncorrected memory error in page 0x%lx ignored\n"
1174 "Rebuild kernel with CONFIG_MEMORY_FAILURE=y for smarter handling\n",
1182 * Called in process context that interrupted by MCE and marked with
1183 * TIF_MCE_NOTIFY, just before returning to erroneous userland.
1184 * This code is allowed to sleep.
1185 * Attempt possible recovery such as calling the high level VM handler to
1186 * process any corrupted pages, and kill/signal current process if required.
1187 * Action required errors are handled here.
1189 void mce_notify_process(void)
1192 struct mce_info
*mi
= mce_find_info();
1193 int flags
= MF_ACTION_REQUIRED
;
1196 mce_panic("Lost physical address for unconsumed uncorrectable error", NULL
, NULL
);
1197 pfn
= mi
->paddr
>> PAGE_SHIFT
;
1199 clear_thread_flag(TIF_MCE_NOTIFY
);
1201 pr_err("Uncorrected hardware memory error in user-access at %llx",
1204 * We must call memory_failure() here even if the current process is
1205 * doomed. We still need to mark the page as poisoned and alert any
1206 * other users of the page.
1208 if (!mi
->restartable
)
1209 flags
|= MF_MUST_KILL
;
1210 if (memory_failure(pfn
, MCE_VECTOR
, flags
) < 0) {
1211 pr_err("Memory error not recovered");
1212 force_sig(SIGBUS
, current
);
1218 * Action optional processing happens here (picking up
1219 * from the list of faulting pages that do_machine_check()
1220 * placed into the "ring").
1222 static void mce_process_work(struct work_struct
*dummy
)
1226 while (mce_ring_get(&pfn
))
1227 memory_failure(pfn
, MCE_VECTOR
, 0);
1230 #ifdef CONFIG_X86_MCE_INTEL
1232 * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog
1233 * @cpu: The CPU on which the event occurred.
1234 * @status: Event status information
1236 * This function should be called by the thermal interrupt after the
1237 * event has been processed and the decision was made to log the event
1240 * The status parameter will be saved to the 'status' field of 'struct mce'
1241 * and historically has been the register value of the
1242 * MSR_IA32_THERMAL_STATUS (Intel) msr.
1244 void mce_log_therm_throt_event(__u64 status
)
1249 m
.bank
= MCE_THERMAL_BANK
;
1253 #endif /* CONFIG_X86_MCE_INTEL */
1256 * Periodic polling timer for "silent" machine check errors. If the
1257 * poller finds an MCE, poll 2x faster. When the poller finds no more
1258 * errors, poll 2x slower (up to check_interval seconds).
1260 static unsigned long check_interval
= 5 * 60; /* 5 minutes */
1262 static DEFINE_PER_CPU(unsigned long, mce_next_interval
); /* in jiffies */
1263 static DEFINE_PER_CPU(struct timer_list
, mce_timer
);
1265 static void mce_timer_fn(unsigned long data
)
1267 struct timer_list
*t
= &__get_cpu_var(mce_timer
);
1270 WARN_ON(smp_processor_id() != data
);
1272 if (mce_available(__this_cpu_ptr(&cpu_info
))) {
1273 machine_check_poll(MCP_TIMESTAMP
,
1274 &__get_cpu_var(mce_poll_banks
));
1278 * Alert userspace if needed. If we logged an MCE, reduce the
1279 * polling interval, otherwise increase the polling interval.
1281 iv
= __this_cpu_read(mce_next_interval
);
1282 if (mce_notify_irq())
1283 iv
= max(iv
/ 2, (unsigned long) HZ
/100);
1285 iv
= min(iv
* 2, round_jiffies_relative(check_interval
* HZ
));
1286 __this_cpu_write(mce_next_interval
, iv
);
1288 t
->expires
= jiffies
+ iv
;
1289 add_timer_on(t
, smp_processor_id());
1292 /* Must not be called in IRQ context where del_timer_sync() can deadlock */
1293 static void mce_timer_delete_all(void)
1297 for_each_online_cpu(cpu
)
1298 del_timer_sync(&per_cpu(mce_timer
, cpu
));
1301 static void mce_do_trigger(struct work_struct
*work
)
1303 call_usermodehelper(mce_helper
, mce_helper_argv
, NULL
, UMH_NO_WAIT
);
1306 static DECLARE_WORK(mce_trigger_work
, mce_do_trigger
);
1309 * Notify the user(s) about new machine check events.
1310 * Can be called from interrupt context, but not from machine check/NMI
1313 int mce_notify_irq(void)
1315 /* Not more than two messages every minute */
1316 static DEFINE_RATELIMIT_STATE(ratelimit
, 60*HZ
, 2);
1318 if (test_and_clear_bit(0, &mce_need_notify
)) {
1319 /* wake processes polling /dev/mcelog */
1320 wake_up_interruptible(&mce_chrdev_wait
);
1323 * There is no risk of missing notifications because
1324 * work_pending is always cleared before the function is
1327 if (mce_helper
[0] && !work_pending(&mce_trigger_work
))
1328 schedule_work(&mce_trigger_work
);
1330 if (__ratelimit(&ratelimit
))
1331 pr_info(HW_ERR
"Machine check events logged\n");
1337 EXPORT_SYMBOL_GPL(mce_notify_irq
);
1339 static int __cpuinit
__mcheck_cpu_mce_banks_init(void)
1343 mce_banks
= kzalloc(banks
* sizeof(struct mce_bank
), GFP_KERNEL
);
1346 for (i
= 0; i
< banks
; i
++) {
1347 struct mce_bank
*b
= &mce_banks
[i
];
1356 * Initialize Machine Checks for a CPU.
1358 static int __cpuinit
__mcheck_cpu_cap_init(void)
1363 rdmsrl(MSR_IA32_MCG_CAP
, cap
);
1365 b
= cap
& MCG_BANKCNT_MASK
;
1367 pr_info("CPU supports %d MCE banks\n", b
);
1369 if (b
> MAX_NR_BANKS
) {
1370 pr_warn("Using only %u machine check banks out of %u\n",
1375 /* Don't support asymmetric configurations today */
1376 WARN_ON(banks
!= 0 && b
!= banks
);
1379 int err
= __mcheck_cpu_mce_banks_init();
1385 /* Use accurate RIP reporting if available. */
1386 if ((cap
& MCG_EXT_P
) && MCG_EXT_CNT(cap
) >= 9)
1387 rip_msr
= MSR_IA32_MCG_EIP
;
1389 if (cap
& MCG_SER_P
)
1395 static void __mcheck_cpu_init_generic(void)
1397 mce_banks_t all_banks
;
1402 * Log the machine checks left over from the previous reset.
1404 bitmap_fill(all_banks
, MAX_NR_BANKS
);
1405 machine_check_poll(MCP_UC
|(!mce_bootlog
? MCP_DONTLOG
: 0), &all_banks
);
1407 set_in_cr4(X86_CR4_MCE
);
1409 rdmsrl(MSR_IA32_MCG_CAP
, cap
);
1410 if (cap
& MCG_CTL_P
)
1411 wrmsr(MSR_IA32_MCG_CTL
, 0xffffffff, 0xffffffff);
1413 for (i
= 0; i
< banks
; i
++) {
1414 struct mce_bank
*b
= &mce_banks
[i
];
1418 wrmsrl(MSR_IA32_MCx_CTL(i
), b
->ctl
);
1419 wrmsrl(MSR_IA32_MCx_STATUS(i
), 0);
1423 /* Add per CPU specific workarounds here */
1424 static int __cpuinit
__mcheck_cpu_apply_quirks(struct cpuinfo_x86
*c
)
1426 if (c
->x86_vendor
== X86_VENDOR_UNKNOWN
) {
1427 pr_info("unknown CPU type - not enabling MCE support\n");
1431 /* This should be disabled by the BIOS, but isn't always */
1432 if (c
->x86_vendor
== X86_VENDOR_AMD
) {
1433 if (c
->x86
== 15 && banks
> 4) {
1435 * disable GART TBL walk error reporting, which
1436 * trips off incorrectly with the IOMMU & 3ware
1439 clear_bit(10, (unsigned long *)&mce_banks
[4].ctl
);
1441 if (c
->x86
<= 17 && mce_bootlog
< 0) {
1443 * Lots of broken BIOS around that don't clear them
1444 * by default and leave crap in there. Don't log:
1449 * Various K7s with broken bank 0 around. Always disable
1452 if (c
->x86
== 6 && banks
> 0)
1453 mce_banks
[0].ctl
= 0;
1456 * Turn off MC4_MISC thresholding banks on those models since
1457 * they're not supported there.
1459 if (c
->x86
== 0x15 &&
1460 (c
->x86_model
>= 0x10 && c
->x86_model
<= 0x1f)) {
1465 0x00000413, /* MC4_MISC0 */
1466 0xc0000408, /* MC4_MISC1 */
1469 rdmsrl(MSR_K7_HWCR
, hwcr
);
1471 /* McStatusWrEn has to be set */
1472 need_toggle
= !(hwcr
& BIT(18));
1475 wrmsrl(MSR_K7_HWCR
, hwcr
| BIT(18));
1477 for (i
= 0; i
< ARRAY_SIZE(msrs
); i
++) {
1478 rdmsrl(msrs
[i
], val
);
1481 if (val
& BIT_64(62)) {
1483 wrmsrl(msrs
[i
], val
);
1487 /* restore old settings */
1489 wrmsrl(MSR_K7_HWCR
, hwcr
);
1493 if (c
->x86_vendor
== X86_VENDOR_INTEL
) {
1495 * SDM documents that on family 6 bank 0 should not be written
1496 * because it aliases to another special BIOS controlled
1498 * But it's not aliased anymore on model 0x1a+
1499 * Don't ignore bank 0 completely because there could be a
1500 * valid event later, merely don't write CTL0.
1503 if (c
->x86
== 6 && c
->x86_model
< 0x1A && banks
> 0)
1504 mce_banks
[0].init
= 0;
1507 * All newer Intel systems support MCE broadcasting. Enable
1508 * synchronization with a one second timeout.
1510 if ((c
->x86
> 6 || (c
->x86
== 6 && c
->x86_model
>= 0xe)) &&
1511 monarch_timeout
< 0)
1512 monarch_timeout
= USEC_PER_SEC
;
1515 * There are also broken BIOSes on some Pentium M and
1518 if (c
->x86
== 6 && c
->x86_model
<= 13 && mce_bootlog
< 0)
1521 if (monarch_timeout
< 0)
1522 monarch_timeout
= 0;
1523 if (mce_bootlog
!= 0)
1524 mce_panic_timeout
= 30;
1529 static int __cpuinit
__mcheck_cpu_ancient_init(struct cpuinfo_x86
*c
)
1534 switch (c
->x86_vendor
) {
1535 case X86_VENDOR_INTEL
:
1536 intel_p5_mcheck_init(c
);
1539 case X86_VENDOR_CENTAUR
:
1540 winchip_mcheck_init(c
);
1548 static void __mcheck_cpu_init_vendor(struct cpuinfo_x86
*c
)
1550 switch (c
->x86_vendor
) {
1551 case X86_VENDOR_INTEL
:
1552 mce_intel_feature_init(c
);
1554 case X86_VENDOR_AMD
:
1555 mce_amd_feature_init(c
);
1562 static void __mcheck_cpu_init_timer(void)
1564 struct timer_list
*t
= &__get_cpu_var(mce_timer
);
1565 unsigned long iv
= check_interval
* HZ
;
1567 setup_timer(t
, mce_timer_fn
, smp_processor_id());
1572 __this_cpu_write(mce_next_interval
, iv
);
1575 t
->expires
= round_jiffies(jiffies
+ iv
);
1576 add_timer_on(t
, smp_processor_id());
1579 /* Handle unconfigured int18 (should never happen) */
1580 static void unexpected_machine_check(struct pt_regs
*regs
, long error_code
)
1582 pr_err("CPU#%d: Unexpected int18 (Machine Check)\n",
1583 smp_processor_id());
1586 /* Call the installed machine check handler for this CPU setup. */
1587 void (*machine_check_vector
)(struct pt_regs
*, long error_code
) =
1588 unexpected_machine_check
;
1591 * Called for each booted CPU to set up machine checks.
1592 * Must be called with preempt off:
1594 void __cpuinit
mcheck_cpu_init(struct cpuinfo_x86
*c
)
1599 if (__mcheck_cpu_ancient_init(c
))
1602 if (!mce_available(c
))
1605 if (__mcheck_cpu_cap_init() < 0 || __mcheck_cpu_apply_quirks(c
) < 0) {
1610 machine_check_vector
= do_machine_check
;
1612 __mcheck_cpu_init_generic();
1613 __mcheck_cpu_init_vendor(c
);
1614 __mcheck_cpu_init_timer();
1615 INIT_WORK(&__get_cpu_var(mce_work
), mce_process_work
);
1616 init_irq_work(&__get_cpu_var(mce_irq_work
), &mce_irq_work_cb
);
1620 * mce_chrdev: Character device /dev/mcelog to read and clear the MCE log.
1623 static DEFINE_SPINLOCK(mce_chrdev_state_lock
);
1624 static int mce_chrdev_open_count
; /* #times opened */
1625 static int mce_chrdev_open_exclu
; /* already open exclusive? */
1627 static int mce_chrdev_open(struct inode
*inode
, struct file
*file
)
1629 spin_lock(&mce_chrdev_state_lock
);
1631 if (mce_chrdev_open_exclu
||
1632 (mce_chrdev_open_count
&& (file
->f_flags
& O_EXCL
))) {
1633 spin_unlock(&mce_chrdev_state_lock
);
1638 if (file
->f_flags
& O_EXCL
)
1639 mce_chrdev_open_exclu
= 1;
1640 mce_chrdev_open_count
++;
1642 spin_unlock(&mce_chrdev_state_lock
);
1644 return nonseekable_open(inode
, file
);
1647 static int mce_chrdev_release(struct inode
*inode
, struct file
*file
)
1649 spin_lock(&mce_chrdev_state_lock
);
1651 mce_chrdev_open_count
--;
1652 mce_chrdev_open_exclu
= 0;
1654 spin_unlock(&mce_chrdev_state_lock
);
1659 static void collect_tscs(void *data
)
1661 unsigned long *cpu_tsc
= (unsigned long *)data
;
1663 rdtscll(cpu_tsc
[smp_processor_id()]);
1666 static int mce_apei_read_done
;
1668 /* Collect MCE record of previous boot in persistent storage via APEI ERST. */
1669 static int __mce_read_apei(char __user
**ubuf
, size_t usize
)
1675 if (usize
< sizeof(struct mce
))
1678 rc
= apei_read_mce(&m
, &record_id
);
1679 /* Error or no more MCE record */
1681 mce_apei_read_done
= 1;
1683 * When ERST is disabled, mce_chrdev_read() should return
1684 * "no record" instead of "no device."
1691 if (copy_to_user(*ubuf
, &m
, sizeof(struct mce
)))
1694 * In fact, we should have cleared the record after that has
1695 * been flushed to the disk or sent to network in
1696 * /sbin/mcelog, but we have no interface to support that now,
1697 * so just clear it to avoid duplication.
1699 rc
= apei_clear_mce(record_id
);
1701 mce_apei_read_done
= 1;
1704 *ubuf
+= sizeof(struct mce
);
1709 static ssize_t
mce_chrdev_read(struct file
*filp
, char __user
*ubuf
,
1710 size_t usize
, loff_t
*off
)
1712 char __user
*buf
= ubuf
;
1713 unsigned long *cpu_tsc
;
1714 unsigned prev
, next
;
1717 cpu_tsc
= kmalloc(nr_cpu_ids
* sizeof(long), GFP_KERNEL
);
1721 mutex_lock(&mce_chrdev_read_mutex
);
1723 if (!mce_apei_read_done
) {
1724 err
= __mce_read_apei(&buf
, usize
);
1725 if (err
|| buf
!= ubuf
)
1729 next
= rcu_dereference_check_mce(mcelog
.next
);
1731 /* Only supports full reads right now */
1733 if (*off
!= 0 || usize
< MCE_LOG_LEN
*sizeof(struct mce
))
1739 for (i
= prev
; i
< next
; i
++) {
1740 unsigned long start
= jiffies
;
1741 struct mce
*m
= &mcelog
.entry
[i
];
1743 while (!m
->finished
) {
1744 if (time_after_eq(jiffies
, start
+ 2)) {
1745 memset(m
, 0, sizeof(*m
));
1751 err
|= copy_to_user(buf
, m
, sizeof(*m
));
1757 memset(mcelog
.entry
+ prev
, 0,
1758 (next
- prev
) * sizeof(struct mce
));
1760 next
= cmpxchg(&mcelog
.next
, prev
, 0);
1761 } while (next
!= prev
);
1763 synchronize_sched();
1766 * Collect entries that were still getting written before the
1769 on_each_cpu(collect_tscs
, cpu_tsc
, 1);
1771 for (i
= next
; i
< MCE_LOG_LEN
; i
++) {
1772 struct mce
*m
= &mcelog
.entry
[i
];
1774 if (m
->finished
&& m
->tsc
< cpu_tsc
[m
->cpu
]) {
1775 err
|= copy_to_user(buf
, m
, sizeof(*m
));
1778 memset(m
, 0, sizeof(*m
));
1786 mutex_unlock(&mce_chrdev_read_mutex
);
1789 return err
? err
: buf
- ubuf
;
1792 static unsigned int mce_chrdev_poll(struct file
*file
, poll_table
*wait
)
1794 poll_wait(file
, &mce_chrdev_wait
, wait
);
1795 if (rcu_access_index(mcelog
.next
))
1796 return POLLIN
| POLLRDNORM
;
1797 if (!mce_apei_read_done
&& apei_check_mce())
1798 return POLLIN
| POLLRDNORM
;
1802 static long mce_chrdev_ioctl(struct file
*f
, unsigned int cmd
,
1805 int __user
*p
= (int __user
*)arg
;
1807 if (!capable(CAP_SYS_ADMIN
))
1811 case MCE_GET_RECORD_LEN
:
1812 return put_user(sizeof(struct mce
), p
);
1813 case MCE_GET_LOG_LEN
:
1814 return put_user(MCE_LOG_LEN
, p
);
1815 case MCE_GETCLEAR_FLAGS
: {
1819 flags
= mcelog
.flags
;
1820 } while (cmpxchg(&mcelog
.flags
, flags
, 0) != flags
);
1822 return put_user(flags
, p
);
1829 static ssize_t (*mce_write
)(struct file
*filp
, const char __user
*ubuf
,
1830 size_t usize
, loff_t
*off
);
1832 void register_mce_write_callback(ssize_t (*fn
)(struct file
*filp
,
1833 const char __user
*ubuf
,
1834 size_t usize
, loff_t
*off
))
1838 EXPORT_SYMBOL_GPL(register_mce_write_callback
);
1840 ssize_t
mce_chrdev_write(struct file
*filp
, const char __user
*ubuf
,
1841 size_t usize
, loff_t
*off
)
1844 return mce_write(filp
, ubuf
, usize
, off
);
1849 static const struct file_operations mce_chrdev_ops
= {
1850 .open
= mce_chrdev_open
,
1851 .release
= mce_chrdev_release
,
1852 .read
= mce_chrdev_read
,
1853 .write
= mce_chrdev_write
,
1854 .poll
= mce_chrdev_poll
,
1855 .unlocked_ioctl
= mce_chrdev_ioctl
,
1856 .llseek
= no_llseek
,
1859 static struct miscdevice mce_chrdev_device
= {
1866 * mce=off Disables machine check
1867 * mce=no_cmci Disables CMCI
1868 * mce=dont_log_ce Clears corrected events silently, no log created for CEs.
1869 * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared.
1870 * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above)
1871 * monarchtimeout is how long to wait for other CPUs on machine
1872 * check, or 0 to not wait
1873 * mce=bootlog Log MCEs from before booting. Disabled by default on AMD.
1874 * mce=nobootlog Don't log MCEs from before booting.
1876 static int __init
mcheck_enable(char *str
)
1884 if (!strcmp(str
, "off"))
1886 else if (!strcmp(str
, "no_cmci"))
1887 mce_cmci_disabled
= 1;
1888 else if (!strcmp(str
, "dont_log_ce"))
1889 mce_dont_log_ce
= 1;
1890 else if (!strcmp(str
, "ignore_ce"))
1892 else if (!strcmp(str
, "bootlog") || !strcmp(str
, "nobootlog"))
1893 mce_bootlog
= (str
[0] == 'b');
1894 else if (isdigit(str
[0])) {
1895 get_option(&str
, &tolerant
);
1898 get_option(&str
, &monarch_timeout
);
1901 pr_info("mce argument %s ignored. Please use /sys\n", str
);
1906 __setup("mce", mcheck_enable
);
1908 int __init
mcheck_init(void)
1910 mcheck_intel_therm_init();
1916 * mce_syscore: PM support
1920 * Disable machine checks on suspend and shutdown. We can't really handle
1923 static int mce_disable_error_reporting(void)
1927 for (i
= 0; i
< banks
; i
++) {
1928 struct mce_bank
*b
= &mce_banks
[i
];
1931 wrmsrl(MSR_IA32_MCx_CTL(i
), 0);
1936 static int mce_syscore_suspend(void)
1938 return mce_disable_error_reporting();
1941 static void mce_syscore_shutdown(void)
1943 mce_disable_error_reporting();
1947 * On resume clear all MCE state. Don't want to see leftovers from the BIOS.
1948 * Only one CPU is active at this time, the others get re-added later using
1951 static void mce_syscore_resume(void)
1953 __mcheck_cpu_init_generic();
1954 __mcheck_cpu_init_vendor(__this_cpu_ptr(&cpu_info
));
1957 static struct syscore_ops mce_syscore_ops
= {
1958 .suspend
= mce_syscore_suspend
,
1959 .shutdown
= mce_syscore_shutdown
,
1960 .resume
= mce_syscore_resume
,
1964 * mce_device: Sysfs support
1967 static void mce_cpu_restart(void *data
)
1969 if (!mce_available(__this_cpu_ptr(&cpu_info
)))
1971 __mcheck_cpu_init_generic();
1972 __mcheck_cpu_init_timer();
1975 /* Reinit MCEs after user configuration changes */
1976 static void mce_restart(void)
1978 mce_timer_delete_all();
1979 on_each_cpu(mce_cpu_restart
, NULL
, 1);
1982 /* Toggle features for corrected errors */
1983 static void mce_disable_cmci(void *data
)
1985 if (!mce_available(__this_cpu_ptr(&cpu_info
)))
1990 static void mce_enable_ce(void *all
)
1992 if (!mce_available(__this_cpu_ptr(&cpu_info
)))
1997 __mcheck_cpu_init_timer();
2000 static struct bus_type mce_subsys
= {
2001 .name
= "machinecheck",
2002 .dev_name
= "machinecheck",
2005 DEFINE_PER_CPU(struct device
*, mce_device
);
2008 void (*threshold_cpu_callback
)(unsigned long action
, unsigned int cpu
);
2010 static inline struct mce_bank
*attr_to_bank(struct device_attribute
*attr
)
2012 return container_of(attr
, struct mce_bank
, attr
);
2015 static ssize_t
show_bank(struct device
*s
, struct device_attribute
*attr
,
2018 return sprintf(buf
, "%llx\n", attr_to_bank(attr
)->ctl
);
2021 static ssize_t
set_bank(struct device
*s
, struct device_attribute
*attr
,
2022 const char *buf
, size_t size
)
2026 if (strict_strtoull(buf
, 0, &new) < 0)
2029 attr_to_bank(attr
)->ctl
= new;
2036 show_trigger(struct device
*s
, struct device_attribute
*attr
, char *buf
)
2038 strcpy(buf
, mce_helper
);
2040 return strlen(mce_helper
) + 1;
2043 static ssize_t
set_trigger(struct device
*s
, struct device_attribute
*attr
,
2044 const char *buf
, size_t siz
)
2048 strncpy(mce_helper
, buf
, sizeof(mce_helper
));
2049 mce_helper
[sizeof(mce_helper
)-1] = 0;
2050 p
= strchr(mce_helper
, '\n');
2055 return strlen(mce_helper
) + !!p
;
2058 static ssize_t
set_ignore_ce(struct device
*s
,
2059 struct device_attribute
*attr
,
2060 const char *buf
, size_t size
)
2064 if (strict_strtoull(buf
, 0, &new) < 0)
2067 if (mce_ignore_ce
^ !!new) {
2069 /* disable ce features */
2070 mce_timer_delete_all();
2071 on_each_cpu(mce_disable_cmci
, NULL
, 1);
2074 /* enable ce features */
2076 on_each_cpu(mce_enable_ce
, (void *)1, 1);
2082 static ssize_t
set_cmci_disabled(struct device
*s
,
2083 struct device_attribute
*attr
,
2084 const char *buf
, size_t size
)
2088 if (strict_strtoull(buf
, 0, &new) < 0)
2091 if (mce_cmci_disabled
^ !!new) {
2094 on_each_cpu(mce_disable_cmci
, NULL
, 1);
2095 mce_cmci_disabled
= 1;
2098 mce_cmci_disabled
= 0;
2099 on_each_cpu(mce_enable_ce
, NULL
, 1);
2105 static ssize_t
store_int_with_restart(struct device
*s
,
2106 struct device_attribute
*attr
,
2107 const char *buf
, size_t size
)
2109 ssize_t ret
= device_store_int(s
, attr
, buf
, size
);
2114 static DEVICE_ATTR(trigger
, 0644, show_trigger
, set_trigger
);
2115 static DEVICE_INT_ATTR(tolerant
, 0644, tolerant
);
2116 static DEVICE_INT_ATTR(monarch_timeout
, 0644, monarch_timeout
);
2117 static DEVICE_INT_ATTR(dont_log_ce
, 0644, mce_dont_log_ce
);
2119 static struct dev_ext_attribute dev_attr_check_interval
= {
2120 __ATTR(check_interval
, 0644, device_show_int
, store_int_with_restart
),
2124 static struct dev_ext_attribute dev_attr_ignore_ce
= {
2125 __ATTR(ignore_ce
, 0644, device_show_int
, set_ignore_ce
),
2129 static struct dev_ext_attribute dev_attr_cmci_disabled
= {
2130 __ATTR(cmci_disabled
, 0644, device_show_int
, set_cmci_disabled
),
2134 static struct device_attribute
*mce_device_attrs
[] = {
2135 &dev_attr_tolerant
.attr
,
2136 &dev_attr_check_interval
.attr
,
2138 &dev_attr_monarch_timeout
.attr
,
2139 &dev_attr_dont_log_ce
.attr
,
2140 &dev_attr_ignore_ce
.attr
,
2141 &dev_attr_cmci_disabled
.attr
,
2145 static cpumask_var_t mce_device_initialized
;
2147 static void mce_device_release(struct device
*dev
)
2152 /* Per cpu device init. All of the cpus still share the same ctrl bank: */
2153 static __cpuinit
int mce_device_create(unsigned int cpu
)
2159 if (!mce_available(&boot_cpu_data
))
2162 dev
= kzalloc(sizeof *dev
, GFP_KERNEL
);
2166 dev
->bus
= &mce_subsys
;
2167 dev
->release
= &mce_device_release
;
2169 err
= device_register(dev
);
2173 for (i
= 0; mce_device_attrs
[i
]; i
++) {
2174 err
= device_create_file(dev
, mce_device_attrs
[i
]);
2178 for (j
= 0; j
< banks
; j
++) {
2179 err
= device_create_file(dev
, &mce_banks
[j
].attr
);
2183 cpumask_set_cpu(cpu
, mce_device_initialized
);
2184 per_cpu(mce_device
, cpu
) = dev
;
2189 device_remove_file(dev
, &mce_banks
[j
].attr
);
2192 device_remove_file(dev
, mce_device_attrs
[i
]);
2194 device_unregister(dev
);
2199 static __cpuinit
void mce_device_remove(unsigned int cpu
)
2201 struct device
*dev
= per_cpu(mce_device
, cpu
);
2204 if (!cpumask_test_cpu(cpu
, mce_device_initialized
))
2207 for (i
= 0; mce_device_attrs
[i
]; i
++)
2208 device_remove_file(dev
, mce_device_attrs
[i
]);
2210 for (i
= 0; i
< banks
; i
++)
2211 device_remove_file(dev
, &mce_banks
[i
].attr
);
2213 device_unregister(dev
);
2214 cpumask_clear_cpu(cpu
, mce_device_initialized
);
2215 per_cpu(mce_device
, cpu
) = NULL
;
2218 /* Make sure there are no machine checks on offlined CPUs. */
2219 static void __cpuinit
mce_disable_cpu(void *h
)
2221 unsigned long action
= *(unsigned long *)h
;
2224 if (!mce_available(__this_cpu_ptr(&cpu_info
)))
2227 if (!(action
& CPU_TASKS_FROZEN
))
2229 for (i
= 0; i
< banks
; i
++) {
2230 struct mce_bank
*b
= &mce_banks
[i
];
2233 wrmsrl(MSR_IA32_MCx_CTL(i
), 0);
2237 static void __cpuinit
mce_reenable_cpu(void *h
)
2239 unsigned long action
= *(unsigned long *)h
;
2242 if (!mce_available(__this_cpu_ptr(&cpu_info
)))
2245 if (!(action
& CPU_TASKS_FROZEN
))
2247 for (i
= 0; i
< banks
; i
++) {
2248 struct mce_bank
*b
= &mce_banks
[i
];
2251 wrmsrl(MSR_IA32_MCx_CTL(i
), b
->ctl
);
2255 /* Get notified when a cpu comes on/off. Be hotplug friendly. */
2256 static int __cpuinit
2257 mce_cpu_callback(struct notifier_block
*nfb
, unsigned long action
, void *hcpu
)
2259 unsigned int cpu
= (unsigned long)hcpu
;
2260 struct timer_list
*t
= &per_cpu(mce_timer
, cpu
);
2264 case CPU_ONLINE_FROZEN
:
2265 mce_device_create(cpu
);
2266 if (threshold_cpu_callback
)
2267 threshold_cpu_callback(action
, cpu
);
2270 case CPU_DEAD_FROZEN
:
2271 if (threshold_cpu_callback
)
2272 threshold_cpu_callback(action
, cpu
);
2273 mce_device_remove(cpu
);
2275 case CPU_DOWN_PREPARE
:
2276 case CPU_DOWN_PREPARE_FROZEN
:
2278 smp_call_function_single(cpu
, mce_disable_cpu
, &action
, 1);
2280 case CPU_DOWN_FAILED
:
2281 case CPU_DOWN_FAILED_FROZEN
:
2282 if (!mce_ignore_ce
&& check_interval
) {
2283 t
->expires
= round_jiffies(jiffies
+
2284 per_cpu(mce_next_interval
, cpu
));
2285 add_timer_on(t
, cpu
);
2287 smp_call_function_single(cpu
, mce_reenable_cpu
, &action
, 1);
2290 /* intentionally ignoring frozen here */
2291 cmci_rediscover(cpu
);
2297 static struct notifier_block mce_cpu_notifier __cpuinitdata
= {
2298 .notifier_call
= mce_cpu_callback
,
2301 static __init
void mce_init_banks(void)
2305 for (i
= 0; i
< banks
; i
++) {
2306 struct mce_bank
*b
= &mce_banks
[i
];
2307 struct device_attribute
*a
= &b
->attr
;
2309 sysfs_attr_init(&a
->attr
);
2310 a
->attr
.name
= b
->attrname
;
2311 snprintf(b
->attrname
, ATTR_LEN
, "bank%d", i
);
2313 a
->attr
.mode
= 0644;
2314 a
->show
= show_bank
;
2315 a
->store
= set_bank
;
2319 static __init
int mcheck_init_device(void)
2324 if (!mce_available(&boot_cpu_data
))
2327 zalloc_cpumask_var(&mce_device_initialized
, GFP_KERNEL
);
2331 err
= subsys_system_register(&mce_subsys
, NULL
);
2335 for_each_online_cpu(i
) {
2336 err
= mce_device_create(i
);
2341 register_syscore_ops(&mce_syscore_ops
);
2342 register_hotcpu_notifier(&mce_cpu_notifier
);
2344 /* register character device /dev/mcelog */
2345 misc_register(&mce_chrdev_device
);
2349 device_initcall(mcheck_init_device
);
2352 * Old style boot options parsing. Only for compatibility.
2354 static int __init
mcheck_disable(char *str
)
2359 __setup("nomce", mcheck_disable
);
2361 #ifdef CONFIG_DEBUG_FS
2362 struct dentry
*mce_get_debugfs_dir(void)
2364 static struct dentry
*dmce
;
2367 dmce
= debugfs_create_dir("mce", NULL
);
2372 static void mce_reset(void)
2375 atomic_set(&mce_fake_paniced
, 0);
2376 atomic_set(&mce_executing
, 0);
2377 atomic_set(&mce_callin
, 0);
2378 atomic_set(&global_nwo
, 0);
2381 static int fake_panic_get(void *data
, u64
*val
)
2387 static int fake_panic_set(void *data
, u64 val
)
2394 DEFINE_SIMPLE_ATTRIBUTE(fake_panic_fops
, fake_panic_get
,
2395 fake_panic_set
, "%llu\n");
2397 static int __init
mcheck_debugfs_init(void)
2399 struct dentry
*dmce
, *ffake_panic
;
2401 dmce
= mce_get_debugfs_dir();
2404 ffake_panic
= debugfs_create_file("fake_panic", 0444, dmce
, NULL
,
2411 late_initcall(mcheck_debugfs_init
);