2 * Machine check handler.
4 * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs.
5 * Rest from unknown author(s).
6 * 2004 Andi Kleen. Rewrote most of it.
7 * Copyright 2008 Intel Corporation
10 #include <linux/thread_info.h>
11 #include <linux/capability.h>
12 #include <linux/miscdevice.h>
13 #include <linux/ratelimit.h>
14 #include <linux/kallsyms.h>
15 #include <linux/rcupdate.h>
16 #include <linux/kobject.h>
17 #include <linux/uaccess.h>
18 #include <linux/kdebug.h>
19 #include <linux/kernel.h>
20 #include <linux/percpu.h>
21 #include <linux/string.h>
22 #include <linux/device.h>
23 #include <linux/syscore_ops.h>
24 #include <linux/delay.h>
25 #include <linux/ctype.h>
26 #include <linux/sched.h>
27 #include <linux/sysfs.h>
28 #include <linux/types.h>
29 #include <linux/slab.h>
30 #include <linux/init.h>
31 #include <linux/kmod.h>
32 #include <linux/poll.h>
33 #include <linux/nmi.h>
34 #include <linux/cpu.h>
35 #include <linux/smp.h>
38 #include <linux/debugfs.h>
39 #include <linux/irq_work.h>
40 #include <linux/export.h>
42 #include <asm/processor.h>
46 #include "mce-internal.h"
48 static DEFINE_MUTEX(mce_chrdev_read_mutex
);
50 #define rcu_dereference_check_mce(p) \
51 rcu_dereference_index_check((p), \
52 rcu_read_lock_sched_held() || \
53 lockdep_is_held(&mce_chrdev_read_mutex))
55 #define CREATE_TRACE_POINTS
56 #include <trace/events/mce.h>
58 int mce_disabled __read_mostly
;
60 #define SPINUNIT 100 /* 100ns */
64 DEFINE_PER_CPU(unsigned, mce_exception_count
);
68 * 0: always panic on uncorrected errors, log corrected errors
69 * 1: panic or SIGBUS on uncorrected errors, log corrected errors
70 * 2: SIGBUS or log uncorrected errors (if possible), log corrected errors
71 * 3: never panic or SIGBUS, log all errors (for testing only)
73 static int tolerant __read_mostly
= 1;
74 static int banks __read_mostly
;
75 static int rip_msr __read_mostly
;
76 static int mce_bootlog __read_mostly
= -1;
77 static int monarch_timeout __read_mostly
= -1;
78 static int mce_panic_timeout __read_mostly
;
79 static int mce_dont_log_ce __read_mostly
;
80 int mce_cmci_disabled __read_mostly
;
81 int mce_ignore_ce __read_mostly
;
82 int mce_ser __read_mostly
;
84 struct mce_bank
*mce_banks __read_mostly
;
86 /* User mode helper program triggered by machine check event */
87 static unsigned long mce_need_notify
;
88 static char mce_helper
[128];
89 static char *mce_helper_argv
[2] = { mce_helper
, NULL
};
91 static DECLARE_WAIT_QUEUE_HEAD(mce_chrdev_wait
);
93 static DEFINE_PER_CPU(struct mce
, mces_seen
);
94 static int cpu_missing
;
96 /* MCA banks polled by the period polling timer for corrected events */
97 DEFINE_PER_CPU(mce_banks_t
, mce_poll_banks
) = {
98 [0 ... BITS_TO_LONGS(MAX_NR_BANKS
)-1] = ~0UL
101 static DEFINE_PER_CPU(struct work_struct
, mce_work
);
104 * CPU/chipset specific EDAC code can register a notifier call here to print
105 * MCE errors in a human-readable form.
107 ATOMIC_NOTIFIER_HEAD(x86_mce_decoder_chain
);
109 /* Do initial initialization of a struct mce */
110 void mce_setup(struct mce
*m
)
112 memset(m
, 0, sizeof(struct mce
));
113 m
->cpu
= m
->extcpu
= smp_processor_id();
115 /* We hope get_seconds stays lockless */
116 m
->time
= get_seconds();
117 m
->cpuvendor
= boot_cpu_data
.x86_vendor
;
118 m
->cpuid
= cpuid_eax(1);
119 m
->socketid
= cpu_data(m
->extcpu
).phys_proc_id
;
120 m
->apicid
= cpu_data(m
->extcpu
).initial_apicid
;
121 rdmsrl(MSR_IA32_MCG_CAP
, m
->mcgcap
);
124 DEFINE_PER_CPU(struct mce
, injectm
);
125 EXPORT_PER_CPU_SYMBOL_GPL(injectm
);
128 * Lockless MCE logging infrastructure.
129 * This avoids deadlocks on printk locks without having to break locks. Also
130 * separate MCEs from kernel messages to avoid bogus bug reports.
133 static struct mce_log mcelog
= {
134 .signature
= MCE_LOG_SIGNATURE
,
136 .recordlen
= sizeof(struct mce
),
139 void mce_log(struct mce
*mce
)
141 unsigned next
, entry
;
144 /* Emit the trace record: */
145 trace_mce_record(mce
);
147 ret
= atomic_notifier_call_chain(&x86_mce_decoder_chain
, 0, mce
);
148 if (ret
== NOTIFY_STOP
)
154 entry
= rcu_dereference_check_mce(mcelog
.next
);
158 * When the buffer fills up discard new entries.
159 * Assume that the earlier errors are the more
162 if (entry
>= MCE_LOG_LEN
) {
163 set_bit(MCE_OVERFLOW
,
164 (unsigned long *)&mcelog
.flags
);
167 /* Old left over entry. Skip: */
168 if (mcelog
.entry
[entry
].finished
) {
176 if (cmpxchg(&mcelog
.next
, entry
, next
) == entry
)
179 memcpy(mcelog
.entry
+ entry
, mce
, sizeof(struct mce
));
181 mcelog
.entry
[entry
].finished
= 1;
185 set_bit(0, &mce_need_notify
);
188 static void drain_mcelog_buffer(void)
190 unsigned int next
, i
, prev
= 0;
192 next
= ACCESS_ONCE(mcelog
.next
);
197 /* drain what was logged during boot */
198 for (i
= prev
; i
< next
; i
++) {
199 unsigned long start
= jiffies
;
200 unsigned retries
= 1;
202 m
= &mcelog
.entry
[i
];
204 while (!m
->finished
) {
205 if (time_after_eq(jiffies
, start
+ 2*retries
))
210 if (!m
->finished
&& retries
>= 4) {
211 pr_err("MCE: skipping error being logged currently!\n");
216 atomic_notifier_call_chain(&x86_mce_decoder_chain
, 0, m
);
219 memset(mcelog
.entry
+ prev
, 0, (next
- prev
) * sizeof(*m
));
221 next
= cmpxchg(&mcelog
.next
, prev
, 0);
222 } while (next
!= prev
);
226 void mce_register_decode_chain(struct notifier_block
*nb
)
228 atomic_notifier_chain_register(&x86_mce_decoder_chain
, nb
);
229 drain_mcelog_buffer();
231 EXPORT_SYMBOL_GPL(mce_register_decode_chain
);
233 void mce_unregister_decode_chain(struct notifier_block
*nb
)
235 atomic_notifier_chain_unregister(&x86_mce_decoder_chain
, nb
);
237 EXPORT_SYMBOL_GPL(mce_unregister_decode_chain
);
239 static void print_mce(struct mce
*m
)
243 pr_emerg(HW_ERR
"CPU %d: Machine Check Exception: %Lx Bank %d: %016Lx\n",
244 m
->extcpu
, m
->mcgstatus
, m
->bank
, m
->status
);
247 pr_emerg(HW_ERR
"RIP%s %02x:<%016Lx> ",
248 !(m
->mcgstatus
& MCG_STATUS_EIPV
) ? " !INEXACT!" : "",
251 if (m
->cs
== __KERNEL_CS
)
252 print_symbol("{%s}", m
->ip
);
256 pr_emerg(HW_ERR
"TSC %llx ", m
->tsc
);
258 pr_cont("ADDR %llx ", m
->addr
);
260 pr_cont("MISC %llx ", m
->misc
);
264 * Note this output is parsed by external tools and old fields
265 * should not be changed.
267 pr_emerg(HW_ERR
"PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x microcode %x\n",
268 m
->cpuvendor
, m
->cpuid
, m
->time
, m
->socketid
, m
->apicid
,
269 cpu_data(m
->extcpu
).microcode
);
272 * Print out human-readable details about the MCE error,
273 * (if the CPU has an implementation for that)
275 ret
= atomic_notifier_call_chain(&x86_mce_decoder_chain
, 0, m
);
276 if (ret
== NOTIFY_STOP
)
279 pr_emerg_ratelimited(HW_ERR
"Run the above through 'mcelog --ascii'\n");
282 #define PANIC_TIMEOUT 5 /* 5 seconds */
284 static atomic_t mce_paniced
;
286 static int fake_panic
;
287 static atomic_t mce_fake_paniced
;
289 /* Panic in progress. Enable interrupts and wait for final IPI */
290 static void wait_for_panic(void)
292 long timeout
= PANIC_TIMEOUT
*USEC_PER_SEC
;
296 while (timeout
-- > 0)
298 if (panic_timeout
== 0)
299 panic_timeout
= mce_panic_timeout
;
300 panic("Panicing machine check CPU died");
303 static void mce_panic(char *msg
, struct mce
*final
, char *exp
)
309 * Make sure only one CPU runs in machine check panic
311 if (atomic_inc_return(&mce_paniced
) > 1)
318 /* Don't log too much for fake panic */
319 if (atomic_inc_return(&mce_fake_paniced
) > 1)
322 /* First print corrected ones that are still unlogged */
323 for (i
= 0; i
< MCE_LOG_LEN
; i
++) {
324 struct mce
*m
= &mcelog
.entry
[i
];
325 if (!(m
->status
& MCI_STATUS_VAL
))
327 if (!(m
->status
& MCI_STATUS_UC
)) {
330 apei_err
= apei_write_mce(m
);
333 /* Now print uncorrected but with the final one last */
334 for (i
= 0; i
< MCE_LOG_LEN
; i
++) {
335 struct mce
*m
= &mcelog
.entry
[i
];
336 if (!(m
->status
& MCI_STATUS_VAL
))
338 if (!(m
->status
& MCI_STATUS_UC
))
340 if (!final
|| memcmp(m
, final
, sizeof(struct mce
))) {
343 apei_err
= apei_write_mce(m
);
349 apei_err
= apei_write_mce(final
);
352 pr_emerg(HW_ERR
"Some CPUs didn't answer in synchronization\n");
354 pr_emerg(HW_ERR
"Machine check: %s\n", exp
);
356 if (panic_timeout
== 0)
357 panic_timeout
= mce_panic_timeout
;
360 pr_emerg(HW_ERR
"Fake kernel panic: %s\n", msg
);
363 /* Support code for software error injection */
365 static int msr_to_offset(u32 msr
)
367 unsigned bank
= __this_cpu_read(injectm
.bank
);
370 return offsetof(struct mce
, ip
);
371 if (msr
== MSR_IA32_MCx_STATUS(bank
))
372 return offsetof(struct mce
, status
);
373 if (msr
== MSR_IA32_MCx_ADDR(bank
))
374 return offsetof(struct mce
, addr
);
375 if (msr
== MSR_IA32_MCx_MISC(bank
))
376 return offsetof(struct mce
, misc
);
377 if (msr
== MSR_IA32_MCG_STATUS
)
378 return offsetof(struct mce
, mcgstatus
);
382 /* MSR access wrappers used for error injection */
383 static u64
mce_rdmsrl(u32 msr
)
387 if (__this_cpu_read(injectm
.finished
)) {
388 int offset
= msr_to_offset(msr
);
392 return *(u64
*)((char *)&__get_cpu_var(injectm
) + offset
);
395 if (rdmsrl_safe(msr
, &v
)) {
396 WARN_ONCE(1, "mce: Unable to read msr %d!\n", msr
);
398 * Return zero in case the access faulted. This should
399 * not happen normally but can happen if the CPU does
400 * something weird, or if the code is buggy.
408 static void mce_wrmsrl(u32 msr
, u64 v
)
410 if (__this_cpu_read(injectm
.finished
)) {
411 int offset
= msr_to_offset(msr
);
414 *(u64
*)((char *)&__get_cpu_var(injectm
) + offset
) = v
;
421 * Collect all global (w.r.t. this processor) status about this machine
422 * check into our "mce" struct so that we can use it later to assess
423 * the severity of the problem as we read per-bank specific details.
425 static inline void mce_gather_info(struct mce
*m
, struct pt_regs
*regs
)
429 m
->mcgstatus
= mce_rdmsrl(MSR_IA32_MCG_STATUS
);
432 * Get the address of the instruction at the time of
433 * the machine check error.
435 if (m
->mcgstatus
& (MCG_STATUS_RIPV
|MCG_STATUS_EIPV
)) {
440 * When in VM86 mode make the cs look like ring 3
441 * always. This is a lie, but it's better than passing
442 * the additional vm86 bit around everywhere.
444 if (v8086_mode(regs
))
447 /* Use accurate RIP reporting if available. */
449 m
->ip
= mce_rdmsrl(rip_msr
);
454 * Simple lockless ring to communicate PFNs from the exception handler with the
455 * process context work function. This is vastly simplified because there's
456 * only a single reader and a single writer.
458 #define MCE_RING_SIZE 16 /* we use one entry less */
461 unsigned short start
;
463 unsigned long ring
[MCE_RING_SIZE
];
465 static DEFINE_PER_CPU(struct mce_ring
, mce_ring
);
467 /* Runs with CPU affinity in workqueue */
468 static int mce_ring_empty(void)
470 struct mce_ring
*r
= &__get_cpu_var(mce_ring
);
472 return r
->start
== r
->end
;
475 static int mce_ring_get(unsigned long *pfn
)
482 r
= &__get_cpu_var(mce_ring
);
483 if (r
->start
== r
->end
)
485 *pfn
= r
->ring
[r
->start
];
486 r
->start
= (r
->start
+ 1) % MCE_RING_SIZE
;
493 /* Always runs in MCE context with preempt off */
494 static int mce_ring_add(unsigned long pfn
)
496 struct mce_ring
*r
= &__get_cpu_var(mce_ring
);
499 next
= (r
->end
+ 1) % MCE_RING_SIZE
;
500 if (next
== r
->start
)
502 r
->ring
[r
->end
] = pfn
;
508 int mce_available(struct cpuinfo_x86
*c
)
512 return cpu_has(c
, X86_FEATURE_MCE
) && cpu_has(c
, X86_FEATURE_MCA
);
515 static void mce_schedule_work(void)
517 if (!mce_ring_empty()) {
518 struct work_struct
*work
= &__get_cpu_var(mce_work
);
519 if (!work_pending(work
))
524 DEFINE_PER_CPU(struct irq_work
, mce_irq_work
);
526 static void mce_irq_work_cb(struct irq_work
*entry
)
532 static void mce_report_event(struct pt_regs
*regs
)
534 if (regs
->flags
& (X86_VM_MASK
|X86_EFLAGS_IF
)) {
537 * Triggering the work queue here is just an insurance
538 * policy in case the syscall exit notify handler
539 * doesn't run soon enough or ends up running on the
540 * wrong CPU (can happen when audit sleeps)
546 irq_work_queue(&__get_cpu_var(mce_irq_work
));
550 * Read ADDR and MISC registers.
552 static void mce_read_aux(struct mce
*m
, int i
)
554 if (m
->status
& MCI_STATUS_MISCV
)
555 m
->misc
= mce_rdmsrl(MSR_IA32_MCx_MISC(i
));
556 if (m
->status
& MCI_STATUS_ADDRV
) {
557 m
->addr
= mce_rdmsrl(MSR_IA32_MCx_ADDR(i
));
560 * Mask the reported address by the reported granularity.
562 if (mce_ser
&& (m
->status
& MCI_STATUS_MISCV
)) {
563 u8 shift
= MCI_MISC_ADDR_LSB(m
->misc
);
570 DEFINE_PER_CPU(unsigned, mce_poll_count
);
573 * Poll for corrected events or events that happened before reset.
574 * Those are just logged through /dev/mcelog.
576 * This is executed in standard interrupt context.
578 * Note: spec recommends to panic for fatal unsignalled
579 * errors here. However this would be quite problematic --
580 * we would need to reimplement the Monarch handling and
581 * it would mess up the exclusion between exception handler
582 * and poll hander -- * so we skip this for now.
583 * These cases should not happen anyways, or only when the CPU
584 * is already totally * confused. In this case it's likely it will
585 * not fully execute the machine check handler either.
587 void machine_check_poll(enum mcp_flags flags
, mce_banks_t
*b
)
592 this_cpu_inc(mce_poll_count
);
594 mce_gather_info(&m
, NULL
);
596 for (i
= 0; i
< banks
; i
++) {
597 if (!mce_banks
[i
].ctl
|| !test_bit(i
, *b
))
606 m
.status
= mce_rdmsrl(MSR_IA32_MCx_STATUS(i
));
607 if (!(m
.status
& MCI_STATUS_VAL
))
611 * Uncorrected or signalled events are handled by the exception
612 * handler when it is enabled, so don't process those here.
614 * TBD do the same check for MCI_STATUS_EN here?
616 if (!(flags
& MCP_UC
) &&
617 (m
.status
& (mce_ser
? MCI_STATUS_S
: MCI_STATUS_UC
)))
622 if (!(flags
& MCP_TIMESTAMP
))
625 * Don't get the IP here because it's unlikely to
626 * have anything to do with the actual error location.
628 if (!(flags
& MCP_DONTLOG
) && !mce_dont_log_ce
)
632 * Clear state for this bank.
634 mce_wrmsrl(MSR_IA32_MCx_STATUS(i
), 0);
638 * Don't clear MCG_STATUS here because it's only defined for
644 EXPORT_SYMBOL_GPL(machine_check_poll
);
647 * Do a quick check if any of the events requires a panic.
648 * This decides if we keep the events around or clear them.
650 static int mce_no_way_out(struct mce
*m
, char **msg
, unsigned long *validp
)
654 for (i
= 0; i
< banks
; i
++) {
655 m
->status
= mce_rdmsrl(MSR_IA32_MCx_STATUS(i
));
656 if (m
->status
& MCI_STATUS_VAL
)
657 __set_bit(i
, validp
);
658 if (mce_severity(m
, tolerant
, msg
) >= MCE_PANIC_SEVERITY
)
665 * Variable to establish order between CPUs while scanning.
666 * Each CPU spins initially until executing is equal its number.
668 static atomic_t mce_executing
;
671 * Defines order of CPUs on entry. First CPU becomes Monarch.
673 static atomic_t mce_callin
;
676 * Check if a timeout waiting for other CPUs happened.
678 static int mce_timed_out(u64
*t
)
681 * The others already did panic for some reason.
682 * Bail out like in a timeout.
683 * rmb() to tell the compiler that system_state
684 * might have been modified by someone else.
687 if (atomic_read(&mce_paniced
))
689 if (!monarch_timeout
)
691 if ((s64
)*t
< SPINUNIT
) {
692 /* CHECKME: Make panic default for 1 too? */
694 mce_panic("Timeout synchronizing machine check over CPUs",
701 touch_nmi_watchdog();
706 * The Monarch's reign. The Monarch is the CPU who entered
707 * the machine check handler first. It waits for the others to
708 * raise the exception too and then grades them. When any
709 * error is fatal panic. Only then let the others continue.
711 * The other CPUs entering the MCE handler will be controlled by the
712 * Monarch. They are called Subjects.
714 * This way we prevent any potential data corruption in a unrecoverable case
715 * and also makes sure always all CPU's errors are examined.
717 * Also this detects the case of a machine check event coming from outer
718 * space (not detected by any CPUs) In this case some external agent wants
719 * us to shut down, so panic too.
721 * The other CPUs might still decide to panic if the handler happens
722 * in a unrecoverable place, but in this case the system is in a semi-stable
723 * state and won't corrupt anything by itself. It's ok to let the others
724 * continue for a bit first.
726 * All the spin loops have timeouts; when a timeout happens a CPU
727 * typically elects itself to be Monarch.
729 static void mce_reign(void)
732 struct mce
*m
= NULL
;
733 int global_worst
= 0;
738 * This CPU is the Monarch and the other CPUs have run
739 * through their handlers.
740 * Grade the severity of the errors of all the CPUs.
742 for_each_possible_cpu(cpu
) {
743 int severity
= mce_severity(&per_cpu(mces_seen
, cpu
), tolerant
,
745 if (severity
> global_worst
) {
747 global_worst
= severity
;
748 m
= &per_cpu(mces_seen
, cpu
);
753 * Cannot recover? Panic here then.
754 * This dumps all the mces in the log buffer and stops the
757 if (m
&& global_worst
>= MCE_PANIC_SEVERITY
&& tolerant
< 3)
758 mce_panic("Fatal Machine check", m
, msg
);
761 * For UC somewhere we let the CPU who detects it handle it.
762 * Also must let continue the others, otherwise the handling
763 * CPU could deadlock on a lock.
767 * No machine check event found. Must be some external
768 * source or one CPU is hung. Panic.
770 if (global_worst
<= MCE_KEEP_SEVERITY
&& tolerant
< 3)
771 mce_panic("Machine check from unknown source", NULL
, NULL
);
774 * Now clear all the mces_seen so that they don't reappear on
777 for_each_possible_cpu(cpu
)
778 memset(&per_cpu(mces_seen
, cpu
), 0, sizeof(struct mce
));
781 static atomic_t global_nwo
;
784 * Start of Monarch synchronization. This waits until all CPUs have
785 * entered the exception handler and then determines if any of them
786 * saw a fatal event that requires panic. Then it executes them
787 * in the entry order.
788 * TBD double check parallel CPU hotunplug
790 static int mce_start(int *no_way_out
)
793 int cpus
= num_online_cpus();
794 u64 timeout
= (u64
)monarch_timeout
* NSEC_PER_USEC
;
799 atomic_add(*no_way_out
, &global_nwo
);
801 * global_nwo should be updated before mce_callin
804 order
= atomic_inc_return(&mce_callin
);
809 while (atomic_read(&mce_callin
) != cpus
) {
810 if (mce_timed_out(&timeout
)) {
811 atomic_set(&global_nwo
, 0);
818 * mce_callin should be read before global_nwo
824 * Monarch: Starts executing now, the others wait.
826 atomic_set(&mce_executing
, 1);
829 * Subject: Now start the scanning loop one by one in
830 * the original callin order.
831 * This way when there are any shared banks it will be
832 * only seen by one CPU before cleared, avoiding duplicates.
834 while (atomic_read(&mce_executing
) < order
) {
835 if (mce_timed_out(&timeout
)) {
836 atomic_set(&global_nwo
, 0);
844 * Cache the global no_way_out state.
846 *no_way_out
= atomic_read(&global_nwo
);
852 * Synchronize between CPUs after main scanning loop.
853 * This invokes the bulk of the Monarch processing.
855 static int mce_end(int order
)
858 u64 timeout
= (u64
)monarch_timeout
* NSEC_PER_USEC
;
866 * Allow others to run.
868 atomic_inc(&mce_executing
);
871 /* CHECKME: Can this race with a parallel hotplug? */
872 int cpus
= num_online_cpus();
875 * Monarch: Wait for everyone to go through their scanning
878 while (atomic_read(&mce_executing
) <= cpus
) {
879 if (mce_timed_out(&timeout
))
889 * Subject: Wait for Monarch to finish.
891 while (atomic_read(&mce_executing
) != 0) {
892 if (mce_timed_out(&timeout
))
898 * Don't reset anything. That's done by the Monarch.
904 * Reset all global state.
907 atomic_set(&global_nwo
, 0);
908 atomic_set(&mce_callin
, 0);
912 * Let others run again.
914 atomic_set(&mce_executing
, 0);
919 * Check if the address reported by the CPU is in a format we can parse.
920 * It would be possible to add code for most other cases, but all would
921 * be somewhat complicated (e.g. segment offset would require an instruction
922 * parser). So only support physical addresses up to page granuality for now.
924 static int mce_usable_address(struct mce
*m
)
926 if (!(m
->status
& MCI_STATUS_MISCV
) || !(m
->status
& MCI_STATUS_ADDRV
))
928 if (MCI_MISC_ADDR_LSB(m
->misc
) > PAGE_SHIFT
)
930 if (MCI_MISC_ADDR_MODE(m
->misc
) != MCI_MISC_ADDR_PHYS
)
935 static void mce_clear_state(unsigned long *toclear
)
939 for (i
= 0; i
< banks
; i
++) {
940 if (test_bit(i
, toclear
))
941 mce_wrmsrl(MSR_IA32_MCx_STATUS(i
), 0);
946 * Need to save faulting physical address associated with a process
947 * in the machine check handler some place where we can grab it back
948 * later in mce_notify_process()
950 #define MCE_INFO_MAX 16
954 struct task_struct
*t
;
957 } mce_info
[MCE_INFO_MAX
];
959 static void mce_save_info(__u64 addr
, int c
)
963 for (mi
= mce_info
; mi
< &mce_info
[MCE_INFO_MAX
]; mi
++) {
964 if (atomic_cmpxchg(&mi
->inuse
, 0, 1) == 0) {
972 mce_panic("Too many concurrent recoverable errors", NULL
, NULL
);
975 static struct mce_info
*mce_find_info(void)
979 for (mi
= mce_info
; mi
< &mce_info
[MCE_INFO_MAX
]; mi
++)
980 if (atomic_read(&mi
->inuse
) && mi
->t
== current
)
985 static void mce_clear_info(struct mce_info
*mi
)
987 atomic_set(&mi
->inuse
, 0);
991 * The actual machine check handler. This only handles real
992 * exceptions when something got corrupted coming in through int 18.
994 * This is executed in NMI context not subject to normal locking rules. This
995 * implies that most kernel services cannot be safely used. Don't even
996 * think about putting a printk in there!
998 * On Intel systems this is entered on all CPUs in parallel through
999 * MCE broadcast. However some CPUs might be broken beyond repair,
1000 * so be always careful when synchronizing with others.
1002 void do_machine_check(struct pt_regs
*regs
, long error_code
)
1004 struct mce m
, *final
;
1009 * Establish sequential order between the CPUs entering the machine
1014 * If no_way_out gets set, there is no safe way to recover from this
1015 * MCE. If tolerant is cranked up, we'll try anyway.
1019 * If kill_it gets set, there might be a way to recover from this
1023 DECLARE_BITMAP(toclear
, MAX_NR_BANKS
);
1024 DECLARE_BITMAP(valid_banks
, MAX_NR_BANKS
);
1025 char *msg
= "Unknown";
1027 atomic_inc(&mce_entry
);
1029 this_cpu_inc(mce_exception_count
);
1034 mce_gather_info(&m
, regs
);
1036 final
= &__get_cpu_var(mces_seen
);
1039 memset(valid_banks
, 0, sizeof(valid_banks
));
1040 no_way_out
= mce_no_way_out(&m
, &msg
, valid_banks
);
1045 * When no restart IP might need to kill or panic.
1046 * Assume the worst for now, but if we find the
1047 * severity is MCE_AR_SEVERITY we have other options.
1049 if (!(m
.mcgstatus
& MCG_STATUS_RIPV
))
1053 * Go through all the banks in exclusion of the other CPUs.
1054 * This way we don't report duplicated events on shared banks
1055 * because the first one to see it will clear it.
1057 order
= mce_start(&no_way_out
);
1058 for (i
= 0; i
< banks
; i
++) {
1059 __clear_bit(i
, toclear
);
1060 if (!test_bit(i
, valid_banks
))
1062 if (!mce_banks
[i
].ctl
)
1069 m
.status
= mce_rdmsrl(MSR_IA32_MCx_STATUS(i
));
1070 if ((m
.status
& MCI_STATUS_VAL
) == 0)
1074 * Non uncorrected or non signaled errors are handled by
1075 * machine_check_poll. Leave them alone, unless this panics.
1077 if (!(m
.status
& (mce_ser
? MCI_STATUS_S
: MCI_STATUS_UC
)) &&
1082 * Set taint even when machine check was not enabled.
1084 add_taint(TAINT_MACHINE_CHECK
);
1086 severity
= mce_severity(&m
, tolerant
, NULL
);
1089 * When machine check was for corrected handler don't touch,
1090 * unless we're panicing.
1092 if (severity
== MCE_KEEP_SEVERITY
&& !no_way_out
)
1094 __set_bit(i
, toclear
);
1095 if (severity
== MCE_NO_SEVERITY
) {
1097 * Machine check event was not enabled. Clear, but
1103 mce_read_aux(&m
, i
);
1106 * Action optional error. Queue address for later processing.
1107 * When the ring overflows we just ignore the AO error.
1108 * RED-PEN add some logging mechanism when
1109 * usable_address or mce_add_ring fails.
1110 * RED-PEN don't ignore overflow for tolerant == 0
1112 if (severity
== MCE_AO_SEVERITY
&& mce_usable_address(&m
))
1113 mce_ring_add(m
.addr
>> PAGE_SHIFT
);
1117 if (severity
> worst
) {
1123 /* mce_clear_state will clear *final, save locally for use later */
1127 mce_clear_state(toclear
);
1130 * Do most of the synchronization with other CPUs.
1131 * When there's any problem use only local no_way_out state.
1133 if (mce_end(order
) < 0)
1134 no_way_out
= worst
>= MCE_PANIC_SEVERITY
;
1137 * At insane "tolerant" levels we take no action. Otherwise
1138 * we only die if we have no other choice. For less serious
1139 * issues we try to recover, or limit damage to the current
1144 mce_panic("Fatal machine check on current CPU", &m
, msg
);
1145 if (worst
== MCE_AR_SEVERITY
) {
1146 /* schedule action before return to userland */
1147 mce_save_info(m
.addr
, m
.mcgstatus
& MCG_STATUS_RIPV
);
1148 set_thread_flag(TIF_MCE_NOTIFY
);
1149 } else if (kill_it
) {
1150 force_sig(SIGBUS
, current
);
1155 mce_report_event(regs
);
1156 mce_wrmsrl(MSR_IA32_MCG_STATUS
, 0);
1158 atomic_dec(&mce_entry
);
1161 EXPORT_SYMBOL_GPL(do_machine_check
);
1163 #ifndef CONFIG_MEMORY_FAILURE
1164 int memory_failure(unsigned long pfn
, int vector
, int flags
)
1166 /* mce_severity() should not hand us an ACTION_REQUIRED error */
1167 BUG_ON(flags
& MF_ACTION_REQUIRED
);
1168 printk(KERN_ERR
"Uncorrected memory error in page 0x%lx ignored\n"
1169 "Rebuild kernel with CONFIG_MEMORY_FAILURE=y for smarter handling\n", pfn
);
1176 * Called in process context that interrupted by MCE and marked with
1177 * TIF_MCE_NOTIFY, just before returning to erroneous userland.
1178 * This code is allowed to sleep.
1179 * Attempt possible recovery such as calling the high level VM handler to
1180 * process any corrupted pages, and kill/signal current process if required.
1181 * Action required errors are handled here.
1183 void mce_notify_process(void)
1186 struct mce_info
*mi
= mce_find_info();
1189 mce_panic("Lost physical address for unconsumed uncorrectable error", NULL
, NULL
);
1190 pfn
= mi
->paddr
>> PAGE_SHIFT
;
1192 clear_thread_flag(TIF_MCE_NOTIFY
);
1194 pr_err("Uncorrected hardware memory error in user-access at %llx",
1197 * We must call memory_failure() here even if the current process is
1198 * doomed. We still need to mark the page as poisoned and alert any
1199 * other users of the page.
1201 if (memory_failure(pfn
, MCE_VECTOR
, MF_ACTION_REQUIRED
) < 0 ||
1202 mi
->restartable
== 0) {
1203 pr_err("Memory error not recovered");
1204 force_sig(SIGBUS
, current
);
1210 * Action optional processing happens here (picking up
1211 * from the list of faulting pages that do_machine_check()
1212 * placed into the "ring").
1214 static void mce_process_work(struct work_struct
*dummy
)
1218 while (mce_ring_get(&pfn
))
1219 memory_failure(pfn
, MCE_VECTOR
, 0);
1222 #ifdef CONFIG_X86_MCE_INTEL
1224 * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog
1225 * @cpu: The CPU on which the event occurred.
1226 * @status: Event status information
1228 * This function should be called by the thermal interrupt after the
1229 * event has been processed and the decision was made to log the event
1232 * The status parameter will be saved to the 'status' field of 'struct mce'
1233 * and historically has been the register value of the
1234 * MSR_IA32_THERMAL_STATUS (Intel) msr.
1236 void mce_log_therm_throt_event(__u64 status
)
1241 m
.bank
= MCE_THERMAL_BANK
;
1245 #endif /* CONFIG_X86_MCE_INTEL */
1248 * Periodic polling timer for "silent" machine check errors. If the
1249 * poller finds an MCE, poll 2x faster. When the poller finds no more
1250 * errors, poll 2x slower (up to check_interval seconds).
1252 static unsigned long check_interval
= 5 * 60; /* 5 minutes */
1254 static DEFINE_PER_CPU(unsigned long, mce_next_interval
); /* in jiffies */
1255 static DEFINE_PER_CPU(struct timer_list
, mce_timer
);
1257 static void mce_timer_fn(unsigned long data
)
1259 struct timer_list
*t
= &__get_cpu_var(mce_timer
);
1262 WARN_ON(smp_processor_id() != data
);
1264 if (mce_available(__this_cpu_ptr(&cpu_info
))) {
1265 machine_check_poll(MCP_TIMESTAMP
,
1266 &__get_cpu_var(mce_poll_banks
));
1270 * Alert userspace if needed. If we logged an MCE, reduce the
1271 * polling interval, otherwise increase the polling interval.
1273 iv
= __this_cpu_read(mce_next_interval
);
1274 if (mce_notify_irq())
1275 iv
= max(iv
/ 2, (unsigned long) HZ
/100);
1277 iv
= min(iv
* 2, round_jiffies_relative(check_interval
* HZ
));
1278 __this_cpu_write(mce_next_interval
, iv
);
1280 t
->expires
= jiffies
+ iv
;
1281 add_timer_on(t
, smp_processor_id());
1284 /* Must not be called in IRQ context where del_timer_sync() can deadlock */
1285 static void mce_timer_delete_all(void)
1289 for_each_online_cpu(cpu
)
1290 del_timer_sync(&per_cpu(mce_timer
, cpu
));
1293 static void mce_do_trigger(struct work_struct
*work
)
1295 call_usermodehelper(mce_helper
, mce_helper_argv
, NULL
, UMH_NO_WAIT
);
1298 static DECLARE_WORK(mce_trigger_work
, mce_do_trigger
);
1301 * Notify the user(s) about new machine check events.
1302 * Can be called from interrupt context, but not from machine check/NMI
1305 int mce_notify_irq(void)
1307 /* Not more than two messages every minute */
1308 static DEFINE_RATELIMIT_STATE(ratelimit
, 60*HZ
, 2);
1310 if (test_and_clear_bit(0, &mce_need_notify
)) {
1311 /* wake processes polling /dev/mcelog */
1312 wake_up_interruptible(&mce_chrdev_wait
);
1315 * There is no risk of missing notifications because
1316 * work_pending is always cleared before the function is
1319 if (mce_helper
[0] && !work_pending(&mce_trigger_work
))
1320 schedule_work(&mce_trigger_work
);
1322 if (__ratelimit(&ratelimit
))
1323 pr_info(HW_ERR
"Machine check events logged\n");
1329 EXPORT_SYMBOL_GPL(mce_notify_irq
);
1331 static int __cpuinit
__mcheck_cpu_mce_banks_init(void)
1335 mce_banks
= kzalloc(banks
* sizeof(struct mce_bank
), GFP_KERNEL
);
1338 for (i
= 0; i
< banks
; i
++) {
1339 struct mce_bank
*b
= &mce_banks
[i
];
1348 * Initialize Machine Checks for a CPU.
1350 static int __cpuinit
__mcheck_cpu_cap_init(void)
1355 rdmsrl(MSR_IA32_MCG_CAP
, cap
);
1357 b
= cap
& MCG_BANKCNT_MASK
;
1359 printk(KERN_INFO
"mce: CPU supports %d MCE banks\n", b
);
1361 if (b
> MAX_NR_BANKS
) {
1363 "MCE: Using only %u machine check banks out of %u\n",
1368 /* Don't support asymmetric configurations today */
1369 WARN_ON(banks
!= 0 && b
!= banks
);
1372 int err
= __mcheck_cpu_mce_banks_init();
1378 /* Use accurate RIP reporting if available. */
1379 if ((cap
& MCG_EXT_P
) && MCG_EXT_CNT(cap
) >= 9)
1380 rip_msr
= MSR_IA32_MCG_EIP
;
1382 if (cap
& MCG_SER_P
)
1388 static void __mcheck_cpu_init_generic(void)
1390 mce_banks_t all_banks
;
1395 * Log the machine checks left over from the previous reset.
1397 bitmap_fill(all_banks
, MAX_NR_BANKS
);
1398 machine_check_poll(MCP_UC
|(!mce_bootlog
? MCP_DONTLOG
: 0), &all_banks
);
1400 set_in_cr4(X86_CR4_MCE
);
1402 rdmsrl(MSR_IA32_MCG_CAP
, cap
);
1403 if (cap
& MCG_CTL_P
)
1404 wrmsr(MSR_IA32_MCG_CTL
, 0xffffffff, 0xffffffff);
1406 for (i
= 0; i
< banks
; i
++) {
1407 struct mce_bank
*b
= &mce_banks
[i
];
1411 wrmsrl(MSR_IA32_MCx_CTL(i
), b
->ctl
);
1412 wrmsrl(MSR_IA32_MCx_STATUS(i
), 0);
1416 /* Add per CPU specific workarounds here */
1417 static int __cpuinit
__mcheck_cpu_apply_quirks(struct cpuinfo_x86
*c
)
1419 if (c
->x86_vendor
== X86_VENDOR_UNKNOWN
) {
1420 pr_info("MCE: unknown CPU type - not enabling MCE support.\n");
1424 /* This should be disabled by the BIOS, but isn't always */
1425 if (c
->x86_vendor
== X86_VENDOR_AMD
) {
1426 if (c
->x86
== 15 && banks
> 4) {
1428 * disable GART TBL walk error reporting, which
1429 * trips off incorrectly with the IOMMU & 3ware
1432 clear_bit(10, (unsigned long *)&mce_banks
[4].ctl
);
1434 if (c
->x86
<= 17 && mce_bootlog
< 0) {
1436 * Lots of broken BIOS around that don't clear them
1437 * by default and leave crap in there. Don't log:
1442 * Various K7s with broken bank 0 around. Always disable
1445 if (c
->x86
== 6 && banks
> 0)
1446 mce_banks
[0].ctl
= 0;
1449 * Turn off MC4_MISC thresholding banks on those models since
1450 * they're not supported there.
1452 if (c
->x86
== 0x15 &&
1453 (c
->x86_model
>= 0x10 && c
->x86_model
<= 0x1f)) {
1458 0x00000413, /* MC4_MISC0 */
1459 0xc0000408, /* MC4_MISC1 */
1462 rdmsrl(MSR_K7_HWCR
, hwcr
);
1464 /* McStatusWrEn has to be set */
1465 need_toggle
= !(hwcr
& BIT(18));
1468 wrmsrl(MSR_K7_HWCR
, hwcr
| BIT(18));
1470 for (i
= 0; i
< ARRAY_SIZE(msrs
); i
++) {
1471 rdmsrl(msrs
[i
], val
);
1474 if (val
& BIT_64(62)) {
1476 wrmsrl(msrs
[i
], val
);
1480 /* restore old settings */
1482 wrmsrl(MSR_K7_HWCR
, hwcr
);
1486 if (c
->x86_vendor
== X86_VENDOR_INTEL
) {
1488 * SDM documents that on family 6 bank 0 should not be written
1489 * because it aliases to another special BIOS controlled
1491 * But it's not aliased anymore on model 0x1a+
1492 * Don't ignore bank 0 completely because there could be a
1493 * valid event later, merely don't write CTL0.
1496 if (c
->x86
== 6 && c
->x86_model
< 0x1A && banks
> 0)
1497 mce_banks
[0].init
= 0;
1500 * All newer Intel systems support MCE broadcasting. Enable
1501 * synchronization with a one second timeout.
1503 if ((c
->x86
> 6 || (c
->x86
== 6 && c
->x86_model
>= 0xe)) &&
1504 monarch_timeout
< 0)
1505 monarch_timeout
= USEC_PER_SEC
;
1508 * There are also broken BIOSes on some Pentium M and
1511 if (c
->x86
== 6 && c
->x86_model
<= 13 && mce_bootlog
< 0)
1514 if (monarch_timeout
< 0)
1515 monarch_timeout
= 0;
1516 if (mce_bootlog
!= 0)
1517 mce_panic_timeout
= 30;
1522 static int __cpuinit
__mcheck_cpu_ancient_init(struct cpuinfo_x86
*c
)
1527 switch (c
->x86_vendor
) {
1528 case X86_VENDOR_INTEL
:
1529 intel_p5_mcheck_init(c
);
1532 case X86_VENDOR_CENTAUR
:
1533 winchip_mcheck_init(c
);
1541 static void __mcheck_cpu_init_vendor(struct cpuinfo_x86
*c
)
1543 switch (c
->x86_vendor
) {
1544 case X86_VENDOR_INTEL
:
1545 mce_intel_feature_init(c
);
1547 case X86_VENDOR_AMD
:
1548 mce_amd_feature_init(c
);
1555 static void __mcheck_cpu_init_timer(void)
1557 struct timer_list
*t
= &__get_cpu_var(mce_timer
);
1558 unsigned long iv
= check_interval
* HZ
;
1560 setup_timer(t
, mce_timer_fn
, smp_processor_id());
1565 __this_cpu_write(mce_next_interval
, iv
);
1568 t
->expires
= round_jiffies(jiffies
+ iv
);
1569 add_timer_on(t
, smp_processor_id());
1572 /* Handle unconfigured int18 (should never happen) */
1573 static void unexpected_machine_check(struct pt_regs
*regs
, long error_code
)
1575 printk(KERN_ERR
"CPU#%d: Unexpected int18 (Machine Check).\n",
1576 smp_processor_id());
1579 /* Call the installed machine check handler for this CPU setup. */
1580 void (*machine_check_vector
)(struct pt_regs
*, long error_code
) =
1581 unexpected_machine_check
;
1584 * Called for each booted CPU to set up machine checks.
1585 * Must be called with preempt off:
1587 void __cpuinit
mcheck_cpu_init(struct cpuinfo_x86
*c
)
1592 if (__mcheck_cpu_ancient_init(c
))
1595 if (!mce_available(c
))
1598 if (__mcheck_cpu_cap_init() < 0 || __mcheck_cpu_apply_quirks(c
) < 0) {
1603 machine_check_vector
= do_machine_check
;
1605 __mcheck_cpu_init_generic();
1606 __mcheck_cpu_init_vendor(c
);
1607 __mcheck_cpu_init_timer();
1608 INIT_WORK(&__get_cpu_var(mce_work
), mce_process_work
);
1609 init_irq_work(&__get_cpu_var(mce_irq_work
), &mce_irq_work_cb
);
1613 * mce_chrdev: Character device /dev/mcelog to read and clear the MCE log.
1616 static DEFINE_SPINLOCK(mce_chrdev_state_lock
);
1617 static int mce_chrdev_open_count
; /* #times opened */
1618 static int mce_chrdev_open_exclu
; /* already open exclusive? */
1620 static int mce_chrdev_open(struct inode
*inode
, struct file
*file
)
1622 spin_lock(&mce_chrdev_state_lock
);
1624 if (mce_chrdev_open_exclu
||
1625 (mce_chrdev_open_count
&& (file
->f_flags
& O_EXCL
))) {
1626 spin_unlock(&mce_chrdev_state_lock
);
1631 if (file
->f_flags
& O_EXCL
)
1632 mce_chrdev_open_exclu
= 1;
1633 mce_chrdev_open_count
++;
1635 spin_unlock(&mce_chrdev_state_lock
);
1637 return nonseekable_open(inode
, file
);
1640 static int mce_chrdev_release(struct inode
*inode
, struct file
*file
)
1642 spin_lock(&mce_chrdev_state_lock
);
1644 mce_chrdev_open_count
--;
1645 mce_chrdev_open_exclu
= 0;
1647 spin_unlock(&mce_chrdev_state_lock
);
1652 static void collect_tscs(void *data
)
1654 unsigned long *cpu_tsc
= (unsigned long *)data
;
1656 rdtscll(cpu_tsc
[smp_processor_id()]);
1659 static int mce_apei_read_done
;
1661 /* Collect MCE record of previous boot in persistent storage via APEI ERST. */
1662 static int __mce_read_apei(char __user
**ubuf
, size_t usize
)
1668 if (usize
< sizeof(struct mce
))
1671 rc
= apei_read_mce(&m
, &record_id
);
1672 /* Error or no more MCE record */
1674 mce_apei_read_done
= 1;
1676 * When ERST is disabled, mce_chrdev_read() should return
1677 * "no record" instead of "no device."
1684 if (copy_to_user(*ubuf
, &m
, sizeof(struct mce
)))
1687 * In fact, we should have cleared the record after that has
1688 * been flushed to the disk or sent to network in
1689 * /sbin/mcelog, but we have no interface to support that now,
1690 * so just clear it to avoid duplication.
1692 rc
= apei_clear_mce(record_id
);
1694 mce_apei_read_done
= 1;
1697 *ubuf
+= sizeof(struct mce
);
1702 static ssize_t
mce_chrdev_read(struct file
*filp
, char __user
*ubuf
,
1703 size_t usize
, loff_t
*off
)
1705 char __user
*buf
= ubuf
;
1706 unsigned long *cpu_tsc
;
1707 unsigned prev
, next
;
1710 cpu_tsc
= kmalloc(nr_cpu_ids
* sizeof(long), GFP_KERNEL
);
1714 mutex_lock(&mce_chrdev_read_mutex
);
1716 if (!mce_apei_read_done
) {
1717 err
= __mce_read_apei(&buf
, usize
);
1718 if (err
|| buf
!= ubuf
)
1722 next
= rcu_dereference_check_mce(mcelog
.next
);
1724 /* Only supports full reads right now */
1726 if (*off
!= 0 || usize
< MCE_LOG_LEN
*sizeof(struct mce
))
1732 for (i
= prev
; i
< next
; i
++) {
1733 unsigned long start
= jiffies
;
1734 struct mce
*m
= &mcelog
.entry
[i
];
1736 while (!m
->finished
) {
1737 if (time_after_eq(jiffies
, start
+ 2)) {
1738 memset(m
, 0, sizeof(*m
));
1744 err
|= copy_to_user(buf
, m
, sizeof(*m
));
1750 memset(mcelog
.entry
+ prev
, 0,
1751 (next
- prev
) * sizeof(struct mce
));
1753 next
= cmpxchg(&mcelog
.next
, prev
, 0);
1754 } while (next
!= prev
);
1756 synchronize_sched();
1759 * Collect entries that were still getting written before the
1762 on_each_cpu(collect_tscs
, cpu_tsc
, 1);
1764 for (i
= next
; i
< MCE_LOG_LEN
; i
++) {
1765 struct mce
*m
= &mcelog
.entry
[i
];
1767 if (m
->finished
&& m
->tsc
< cpu_tsc
[m
->cpu
]) {
1768 err
|= copy_to_user(buf
, m
, sizeof(*m
));
1771 memset(m
, 0, sizeof(*m
));
1779 mutex_unlock(&mce_chrdev_read_mutex
);
1782 return err
? err
: buf
- ubuf
;
1785 static unsigned int mce_chrdev_poll(struct file
*file
, poll_table
*wait
)
1787 poll_wait(file
, &mce_chrdev_wait
, wait
);
1788 if (rcu_access_index(mcelog
.next
))
1789 return POLLIN
| POLLRDNORM
;
1790 if (!mce_apei_read_done
&& apei_check_mce())
1791 return POLLIN
| POLLRDNORM
;
1795 static long mce_chrdev_ioctl(struct file
*f
, unsigned int cmd
,
1798 int __user
*p
= (int __user
*)arg
;
1800 if (!capable(CAP_SYS_ADMIN
))
1804 case MCE_GET_RECORD_LEN
:
1805 return put_user(sizeof(struct mce
), p
);
1806 case MCE_GET_LOG_LEN
:
1807 return put_user(MCE_LOG_LEN
, p
);
1808 case MCE_GETCLEAR_FLAGS
: {
1812 flags
= mcelog
.flags
;
1813 } while (cmpxchg(&mcelog
.flags
, flags
, 0) != flags
);
1815 return put_user(flags
, p
);
1822 static ssize_t (*mce_write
)(struct file
*filp
, const char __user
*ubuf
,
1823 size_t usize
, loff_t
*off
);
1825 void register_mce_write_callback(ssize_t (*fn
)(struct file
*filp
,
1826 const char __user
*ubuf
,
1827 size_t usize
, loff_t
*off
))
1831 EXPORT_SYMBOL_GPL(register_mce_write_callback
);
1833 ssize_t
mce_chrdev_write(struct file
*filp
, const char __user
*ubuf
,
1834 size_t usize
, loff_t
*off
)
1837 return mce_write(filp
, ubuf
, usize
, off
);
1842 static const struct file_operations mce_chrdev_ops
= {
1843 .open
= mce_chrdev_open
,
1844 .release
= mce_chrdev_release
,
1845 .read
= mce_chrdev_read
,
1846 .write
= mce_chrdev_write
,
1847 .poll
= mce_chrdev_poll
,
1848 .unlocked_ioctl
= mce_chrdev_ioctl
,
1849 .llseek
= no_llseek
,
1852 static struct miscdevice mce_chrdev_device
= {
1859 * mce=off Disables machine check
1860 * mce=no_cmci Disables CMCI
1861 * mce=dont_log_ce Clears corrected events silently, no log created for CEs.
1862 * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared.
1863 * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above)
1864 * monarchtimeout is how long to wait for other CPUs on machine
1865 * check, or 0 to not wait
1866 * mce=bootlog Log MCEs from before booting. Disabled by default on AMD.
1867 * mce=nobootlog Don't log MCEs from before booting.
1869 static int __init
mcheck_enable(char *str
)
1877 if (!strcmp(str
, "off"))
1879 else if (!strcmp(str
, "no_cmci"))
1880 mce_cmci_disabled
= 1;
1881 else if (!strcmp(str
, "dont_log_ce"))
1882 mce_dont_log_ce
= 1;
1883 else if (!strcmp(str
, "ignore_ce"))
1885 else if (!strcmp(str
, "bootlog") || !strcmp(str
, "nobootlog"))
1886 mce_bootlog
= (str
[0] == 'b');
1887 else if (isdigit(str
[0])) {
1888 get_option(&str
, &tolerant
);
1891 get_option(&str
, &monarch_timeout
);
1894 printk(KERN_INFO
"mce argument %s ignored. Please use /sys\n",
1900 __setup("mce", mcheck_enable
);
1902 int __init
mcheck_init(void)
1904 mcheck_intel_therm_init();
1910 * mce_syscore: PM support
1914 * Disable machine checks on suspend and shutdown. We can't really handle
1917 static int mce_disable_error_reporting(void)
1921 for (i
= 0; i
< banks
; i
++) {
1922 struct mce_bank
*b
= &mce_banks
[i
];
1925 wrmsrl(MSR_IA32_MCx_CTL(i
), 0);
1930 static int mce_syscore_suspend(void)
1932 return mce_disable_error_reporting();
1935 static void mce_syscore_shutdown(void)
1937 mce_disable_error_reporting();
1941 * On resume clear all MCE state. Don't want to see leftovers from the BIOS.
1942 * Only one CPU is active at this time, the others get re-added later using
1945 static void mce_syscore_resume(void)
1947 __mcheck_cpu_init_generic();
1948 __mcheck_cpu_init_vendor(__this_cpu_ptr(&cpu_info
));
1951 static struct syscore_ops mce_syscore_ops
= {
1952 .suspend
= mce_syscore_suspend
,
1953 .shutdown
= mce_syscore_shutdown
,
1954 .resume
= mce_syscore_resume
,
1958 * mce_device: Sysfs support
1961 static void mce_cpu_restart(void *data
)
1963 if (!mce_available(__this_cpu_ptr(&cpu_info
)))
1965 __mcheck_cpu_init_generic();
1966 __mcheck_cpu_init_timer();
1969 /* Reinit MCEs after user configuration changes */
1970 static void mce_restart(void)
1972 mce_timer_delete_all();
1973 on_each_cpu(mce_cpu_restart
, NULL
, 1);
1976 /* Toggle features for corrected errors */
1977 static void mce_disable_cmci(void *data
)
1979 if (!mce_available(__this_cpu_ptr(&cpu_info
)))
1984 static void mce_enable_ce(void *all
)
1986 if (!mce_available(__this_cpu_ptr(&cpu_info
)))
1991 __mcheck_cpu_init_timer();
1994 static struct bus_type mce_subsys
= {
1995 .name
= "machinecheck",
1996 .dev_name
= "machinecheck",
1999 DEFINE_PER_CPU(struct device
*, mce_device
);
2002 void (*threshold_cpu_callback
)(unsigned long action
, unsigned int cpu
);
2004 static inline struct mce_bank
*attr_to_bank(struct device_attribute
*attr
)
2006 return container_of(attr
, struct mce_bank
, attr
);
2009 static ssize_t
show_bank(struct device
*s
, struct device_attribute
*attr
,
2012 return sprintf(buf
, "%llx\n", attr_to_bank(attr
)->ctl
);
2015 static ssize_t
set_bank(struct device
*s
, struct device_attribute
*attr
,
2016 const char *buf
, size_t size
)
2020 if (strict_strtoull(buf
, 0, &new) < 0)
2023 attr_to_bank(attr
)->ctl
= new;
2030 show_trigger(struct device
*s
, struct device_attribute
*attr
, char *buf
)
2032 strcpy(buf
, mce_helper
);
2034 return strlen(mce_helper
) + 1;
2037 static ssize_t
set_trigger(struct device
*s
, struct device_attribute
*attr
,
2038 const char *buf
, size_t siz
)
2042 strncpy(mce_helper
, buf
, sizeof(mce_helper
));
2043 mce_helper
[sizeof(mce_helper
)-1] = 0;
2044 p
= strchr(mce_helper
, '\n');
2049 return strlen(mce_helper
) + !!p
;
2052 static ssize_t
set_ignore_ce(struct device
*s
,
2053 struct device_attribute
*attr
,
2054 const char *buf
, size_t size
)
2058 if (strict_strtoull(buf
, 0, &new) < 0)
2061 if (mce_ignore_ce
^ !!new) {
2063 /* disable ce features */
2064 mce_timer_delete_all();
2065 on_each_cpu(mce_disable_cmci
, NULL
, 1);
2068 /* enable ce features */
2070 on_each_cpu(mce_enable_ce
, (void *)1, 1);
2076 static ssize_t
set_cmci_disabled(struct device
*s
,
2077 struct device_attribute
*attr
,
2078 const char *buf
, size_t size
)
2082 if (strict_strtoull(buf
, 0, &new) < 0)
2085 if (mce_cmci_disabled
^ !!new) {
2088 on_each_cpu(mce_disable_cmci
, NULL
, 1);
2089 mce_cmci_disabled
= 1;
2092 mce_cmci_disabled
= 0;
2093 on_each_cpu(mce_enable_ce
, NULL
, 1);
2099 static ssize_t
store_int_with_restart(struct device
*s
,
2100 struct device_attribute
*attr
,
2101 const char *buf
, size_t size
)
2103 ssize_t ret
= device_store_int(s
, attr
, buf
, size
);
2108 static DEVICE_ATTR(trigger
, 0644, show_trigger
, set_trigger
);
2109 static DEVICE_INT_ATTR(tolerant
, 0644, tolerant
);
2110 static DEVICE_INT_ATTR(monarch_timeout
, 0644, monarch_timeout
);
2111 static DEVICE_INT_ATTR(dont_log_ce
, 0644, mce_dont_log_ce
);
2113 static struct dev_ext_attribute dev_attr_check_interval
= {
2114 __ATTR(check_interval
, 0644, device_show_int
, store_int_with_restart
),
2118 static struct dev_ext_attribute dev_attr_ignore_ce
= {
2119 __ATTR(ignore_ce
, 0644, device_show_int
, set_ignore_ce
),
2123 static struct dev_ext_attribute dev_attr_cmci_disabled
= {
2124 __ATTR(cmci_disabled
, 0644, device_show_int
, set_cmci_disabled
),
2128 static struct device_attribute
*mce_device_attrs
[] = {
2129 &dev_attr_tolerant
.attr
,
2130 &dev_attr_check_interval
.attr
,
2132 &dev_attr_monarch_timeout
.attr
,
2133 &dev_attr_dont_log_ce
.attr
,
2134 &dev_attr_ignore_ce
.attr
,
2135 &dev_attr_cmci_disabled
.attr
,
2139 static cpumask_var_t mce_device_initialized
;
2141 static void mce_device_release(struct device
*dev
)
2146 /* Per cpu device init. All of the cpus still share the same ctrl bank: */
2147 static __cpuinit
int mce_device_create(unsigned int cpu
)
2153 if (!mce_available(&boot_cpu_data
))
2156 dev
= kzalloc(sizeof *dev
, GFP_KERNEL
);
2160 dev
->bus
= &mce_subsys
;
2161 dev
->release
= &mce_device_release
;
2163 err
= device_register(dev
);
2167 for (i
= 0; mce_device_attrs
[i
]; i
++) {
2168 err
= device_create_file(dev
, mce_device_attrs
[i
]);
2172 for (j
= 0; j
< banks
; j
++) {
2173 err
= device_create_file(dev
, &mce_banks
[j
].attr
);
2177 cpumask_set_cpu(cpu
, mce_device_initialized
);
2178 per_cpu(mce_device
, cpu
) = dev
;
2183 device_remove_file(dev
, &mce_banks
[j
].attr
);
2186 device_remove_file(dev
, mce_device_attrs
[i
]);
2188 device_unregister(dev
);
2193 static __cpuinit
void mce_device_remove(unsigned int cpu
)
2195 struct device
*dev
= per_cpu(mce_device
, cpu
);
2198 if (!cpumask_test_cpu(cpu
, mce_device_initialized
))
2201 for (i
= 0; mce_device_attrs
[i
]; i
++)
2202 device_remove_file(dev
, mce_device_attrs
[i
]);
2204 for (i
= 0; i
< banks
; i
++)
2205 device_remove_file(dev
, &mce_banks
[i
].attr
);
2207 device_unregister(dev
);
2208 cpumask_clear_cpu(cpu
, mce_device_initialized
);
2209 per_cpu(mce_device
, cpu
) = NULL
;
2212 /* Make sure there are no machine checks on offlined CPUs. */
2213 static void __cpuinit
mce_disable_cpu(void *h
)
2215 unsigned long action
= *(unsigned long *)h
;
2218 if (!mce_available(__this_cpu_ptr(&cpu_info
)))
2221 if (!(action
& CPU_TASKS_FROZEN
))
2223 for (i
= 0; i
< banks
; i
++) {
2224 struct mce_bank
*b
= &mce_banks
[i
];
2227 wrmsrl(MSR_IA32_MCx_CTL(i
), 0);
2231 static void __cpuinit
mce_reenable_cpu(void *h
)
2233 unsigned long action
= *(unsigned long *)h
;
2236 if (!mce_available(__this_cpu_ptr(&cpu_info
)))
2239 if (!(action
& CPU_TASKS_FROZEN
))
2241 for (i
= 0; i
< banks
; i
++) {
2242 struct mce_bank
*b
= &mce_banks
[i
];
2245 wrmsrl(MSR_IA32_MCx_CTL(i
), b
->ctl
);
2249 /* Get notified when a cpu comes on/off. Be hotplug friendly. */
2250 static int __cpuinit
2251 mce_cpu_callback(struct notifier_block
*nfb
, unsigned long action
, void *hcpu
)
2253 unsigned int cpu
= (unsigned long)hcpu
;
2254 struct timer_list
*t
= &per_cpu(mce_timer
, cpu
);
2258 case CPU_ONLINE_FROZEN
:
2259 mce_device_create(cpu
);
2260 if (threshold_cpu_callback
)
2261 threshold_cpu_callback(action
, cpu
);
2264 case CPU_DEAD_FROZEN
:
2265 if (threshold_cpu_callback
)
2266 threshold_cpu_callback(action
, cpu
);
2267 mce_device_remove(cpu
);
2269 case CPU_DOWN_PREPARE
:
2270 case CPU_DOWN_PREPARE_FROZEN
:
2272 smp_call_function_single(cpu
, mce_disable_cpu
, &action
, 1);
2274 case CPU_DOWN_FAILED
:
2275 case CPU_DOWN_FAILED_FROZEN
:
2276 if (!mce_ignore_ce
&& check_interval
) {
2277 t
->expires
= round_jiffies(jiffies
+
2278 per_cpu(mce_next_interval
, cpu
));
2279 add_timer_on(t
, cpu
);
2281 smp_call_function_single(cpu
, mce_reenable_cpu
, &action
, 1);
2284 /* intentionally ignoring frozen here */
2285 cmci_rediscover(cpu
);
2291 static struct notifier_block mce_cpu_notifier __cpuinitdata
= {
2292 .notifier_call
= mce_cpu_callback
,
2295 static __init
void mce_init_banks(void)
2299 for (i
= 0; i
< banks
; i
++) {
2300 struct mce_bank
*b
= &mce_banks
[i
];
2301 struct device_attribute
*a
= &b
->attr
;
2303 sysfs_attr_init(&a
->attr
);
2304 a
->attr
.name
= b
->attrname
;
2305 snprintf(b
->attrname
, ATTR_LEN
, "bank%d", i
);
2307 a
->attr
.mode
= 0644;
2308 a
->show
= show_bank
;
2309 a
->store
= set_bank
;
2313 static __init
int mcheck_init_device(void)
2318 if (!mce_available(&boot_cpu_data
))
2321 zalloc_cpumask_var(&mce_device_initialized
, GFP_KERNEL
);
2325 err
= subsys_system_register(&mce_subsys
, NULL
);
2329 for_each_online_cpu(i
) {
2330 err
= mce_device_create(i
);
2335 register_syscore_ops(&mce_syscore_ops
);
2336 register_hotcpu_notifier(&mce_cpu_notifier
);
2338 /* register character device /dev/mcelog */
2339 misc_register(&mce_chrdev_device
);
2343 device_initcall_sync(mcheck_init_device
);
2346 * Old style boot options parsing. Only for compatibility.
2348 static int __init
mcheck_disable(char *str
)
2353 __setup("nomce", mcheck_disable
);
2355 #ifdef CONFIG_DEBUG_FS
2356 struct dentry
*mce_get_debugfs_dir(void)
2358 static struct dentry
*dmce
;
2361 dmce
= debugfs_create_dir("mce", NULL
);
2366 static void mce_reset(void)
2369 atomic_set(&mce_fake_paniced
, 0);
2370 atomic_set(&mce_executing
, 0);
2371 atomic_set(&mce_callin
, 0);
2372 atomic_set(&global_nwo
, 0);
2375 static int fake_panic_get(void *data
, u64
*val
)
2381 static int fake_panic_set(void *data
, u64 val
)
2388 DEFINE_SIMPLE_ATTRIBUTE(fake_panic_fops
, fake_panic_get
,
2389 fake_panic_set
, "%llu\n");
2391 static int __init
mcheck_debugfs_init(void)
2393 struct dentry
*dmce
, *ffake_panic
;
2395 dmce
= mce_get_debugfs_dir();
2398 ffake_panic
= debugfs_create_file("fake_panic", 0444, dmce
, NULL
,
2405 late_initcall(mcheck_debugfs_init
);