2 * Machine check handler.
4 * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs.
5 * Rest from unknown author(s).
6 * 2004 Andi Kleen. Rewrote most of it.
7 * Copyright 2008 Intel Corporation
10 #include <linux/thread_info.h>
11 #include <linux/capability.h>
12 #include <linux/miscdevice.h>
13 #include <linux/ratelimit.h>
14 #include <linux/kallsyms.h>
15 #include <linux/rcupdate.h>
16 #include <linux/kobject.h>
17 #include <linux/uaccess.h>
18 #include <linux/kdebug.h>
19 #include <linux/kernel.h>
20 #include <linux/percpu.h>
21 #include <linux/string.h>
22 #include <linux/device.h>
23 #include <linux/syscore_ops.h>
24 #include <linux/delay.h>
25 #include <linux/ctype.h>
26 #include <linux/sched.h>
27 #include <linux/sysfs.h>
28 #include <linux/types.h>
29 #include <linux/slab.h>
30 #include <linux/init.h>
31 #include <linux/kmod.h>
32 #include <linux/poll.h>
33 #include <linux/nmi.h>
34 #include <linux/cpu.h>
35 #include <linux/smp.h>
38 #include <linux/debugfs.h>
39 #include <linux/irq_work.h>
40 #include <linux/export.h>
42 #include <asm/processor.h>
46 #include "mce-internal.h"
48 static DEFINE_MUTEX(mce_chrdev_read_mutex
);
50 #define rcu_dereference_check_mce(p) \
51 rcu_dereference_index_check((p), \
52 rcu_read_lock_sched_held() || \
53 lockdep_is_held(&mce_chrdev_read_mutex))
55 #define CREATE_TRACE_POINTS
56 #include <trace/events/mce.h>
58 int mce_disabled __read_mostly
;
60 #define MISC_MCELOG_MINOR 227
62 #define SPINUNIT 100 /* 100ns */
66 DEFINE_PER_CPU(unsigned, mce_exception_count
);
70 * 0: always panic on uncorrected errors, log corrected errors
71 * 1: panic or SIGBUS on uncorrected errors, log corrected errors
72 * 2: SIGBUS or log uncorrected errors (if possible), log corrected errors
73 * 3: never panic or SIGBUS, log all errors (for testing only)
75 static int tolerant __read_mostly
= 1;
76 static int banks __read_mostly
;
77 static int rip_msr __read_mostly
;
78 static int mce_bootlog __read_mostly
= -1;
79 static int monarch_timeout __read_mostly
= -1;
80 static int mce_panic_timeout __read_mostly
;
81 static int mce_dont_log_ce __read_mostly
;
82 int mce_cmci_disabled __read_mostly
;
83 int mce_ignore_ce __read_mostly
;
84 int mce_ser __read_mostly
;
86 struct mce_bank
*mce_banks __read_mostly
;
88 /* User mode helper program triggered by machine check event */
89 static unsigned long mce_need_notify
;
90 static char mce_helper
[128];
91 static char *mce_helper_argv
[2] = { mce_helper
, NULL
};
93 static DECLARE_WAIT_QUEUE_HEAD(mce_chrdev_wait
);
95 static DEFINE_PER_CPU(struct mce
, mces_seen
);
96 static int cpu_missing
;
98 /* MCA banks polled by the period polling timer for corrected events */
99 DEFINE_PER_CPU(mce_banks_t
, mce_poll_banks
) = {
100 [0 ... BITS_TO_LONGS(MAX_NR_BANKS
)-1] = ~0UL
103 static DEFINE_PER_CPU(struct work_struct
, mce_work
);
106 * CPU/chipset specific EDAC code can register a notifier call here to print
107 * MCE errors in a human-readable form.
109 ATOMIC_NOTIFIER_HEAD(x86_mce_decoder_chain
);
111 /* Do initial initialization of a struct mce */
112 void mce_setup(struct mce
*m
)
114 memset(m
, 0, sizeof(struct mce
));
115 m
->cpu
= m
->extcpu
= smp_processor_id();
117 /* We hope get_seconds stays lockless */
118 m
->time
= get_seconds();
119 m
->cpuvendor
= boot_cpu_data
.x86_vendor
;
120 m
->cpuid
= cpuid_eax(1);
121 m
->socketid
= cpu_data(m
->extcpu
).phys_proc_id
;
122 m
->apicid
= cpu_data(m
->extcpu
).initial_apicid
;
123 rdmsrl(MSR_IA32_MCG_CAP
, m
->mcgcap
);
126 DEFINE_PER_CPU(struct mce
, injectm
);
127 EXPORT_PER_CPU_SYMBOL_GPL(injectm
);
130 * Lockless MCE logging infrastructure.
131 * This avoids deadlocks on printk locks without having to break locks. Also
132 * separate MCEs from kernel messages to avoid bogus bug reports.
135 static struct mce_log mcelog
= {
136 .signature
= MCE_LOG_SIGNATURE
,
138 .recordlen
= sizeof(struct mce
),
141 void mce_log(struct mce
*mce
)
143 unsigned next
, entry
;
146 /* Emit the trace record: */
147 trace_mce_record(mce
);
149 ret
= atomic_notifier_call_chain(&x86_mce_decoder_chain
, 0, mce
);
150 if (ret
== NOTIFY_STOP
)
156 entry
= rcu_dereference_check_mce(mcelog
.next
);
160 * When the buffer fills up discard new entries.
161 * Assume that the earlier errors are the more
164 if (entry
>= MCE_LOG_LEN
) {
165 set_bit(MCE_OVERFLOW
,
166 (unsigned long *)&mcelog
.flags
);
169 /* Old left over entry. Skip: */
170 if (mcelog
.entry
[entry
].finished
) {
178 if (cmpxchg(&mcelog
.next
, entry
, next
) == entry
)
181 memcpy(mcelog
.entry
+ entry
, mce
, sizeof(struct mce
));
183 mcelog
.entry
[entry
].finished
= 1;
187 set_bit(0, &mce_need_notify
);
190 static void drain_mcelog_buffer(void)
192 unsigned int next
, i
, prev
= 0;
194 next
= ACCESS_ONCE(mcelog
.next
);
199 /* drain what was logged during boot */
200 for (i
= prev
; i
< next
; i
++) {
201 unsigned long start
= jiffies
;
202 unsigned retries
= 1;
204 m
= &mcelog
.entry
[i
];
206 while (!m
->finished
) {
207 if (time_after_eq(jiffies
, start
+ 2*retries
))
212 if (!m
->finished
&& retries
>= 4) {
213 pr_err("MCE: skipping error being logged currently!\n");
218 atomic_notifier_call_chain(&x86_mce_decoder_chain
, 0, m
);
221 memset(mcelog
.entry
+ prev
, 0, (next
- prev
) * sizeof(*m
));
223 next
= cmpxchg(&mcelog
.next
, prev
, 0);
224 } while (next
!= prev
);
228 void mce_register_decode_chain(struct notifier_block
*nb
)
230 atomic_notifier_chain_register(&x86_mce_decoder_chain
, nb
);
231 drain_mcelog_buffer();
233 EXPORT_SYMBOL_GPL(mce_register_decode_chain
);
235 void mce_unregister_decode_chain(struct notifier_block
*nb
)
237 atomic_notifier_chain_unregister(&x86_mce_decoder_chain
, nb
);
239 EXPORT_SYMBOL_GPL(mce_unregister_decode_chain
);
241 static void print_mce(struct mce
*m
)
245 pr_emerg(HW_ERR
"CPU %d: Machine Check Exception: %Lx Bank %d: %016Lx\n",
246 m
->extcpu
, m
->mcgstatus
, m
->bank
, m
->status
);
249 pr_emerg(HW_ERR
"RIP%s %02x:<%016Lx> ",
250 !(m
->mcgstatus
& MCG_STATUS_EIPV
) ? " !INEXACT!" : "",
253 if (m
->cs
== __KERNEL_CS
)
254 print_symbol("{%s}", m
->ip
);
258 pr_emerg(HW_ERR
"TSC %llx ", m
->tsc
);
260 pr_cont("ADDR %llx ", m
->addr
);
262 pr_cont("MISC %llx ", m
->misc
);
266 * Note this output is parsed by external tools and old fields
267 * should not be changed.
269 pr_emerg(HW_ERR
"PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x microcode %x\n",
270 m
->cpuvendor
, m
->cpuid
, m
->time
, m
->socketid
, m
->apicid
,
271 cpu_data(m
->extcpu
).microcode
);
274 * Print out human-readable details about the MCE error,
275 * (if the CPU has an implementation for that)
277 ret
= atomic_notifier_call_chain(&x86_mce_decoder_chain
, 0, m
);
278 if (ret
== NOTIFY_STOP
)
281 pr_emerg_ratelimited(HW_ERR
"Run the above through 'mcelog --ascii'\n");
284 #define PANIC_TIMEOUT 5 /* 5 seconds */
286 static atomic_t mce_paniced
;
288 static int fake_panic
;
289 static atomic_t mce_fake_paniced
;
291 /* Panic in progress. Enable interrupts and wait for final IPI */
292 static void wait_for_panic(void)
294 long timeout
= PANIC_TIMEOUT
*USEC_PER_SEC
;
298 while (timeout
-- > 0)
300 if (panic_timeout
== 0)
301 panic_timeout
= mce_panic_timeout
;
302 panic("Panicing machine check CPU died");
305 static void mce_panic(char *msg
, struct mce
*final
, char *exp
)
311 * Make sure only one CPU runs in machine check panic
313 if (atomic_inc_return(&mce_paniced
) > 1)
320 /* Don't log too much for fake panic */
321 if (atomic_inc_return(&mce_fake_paniced
) > 1)
324 /* First print corrected ones that are still unlogged */
325 for (i
= 0; i
< MCE_LOG_LEN
; i
++) {
326 struct mce
*m
= &mcelog
.entry
[i
];
327 if (!(m
->status
& MCI_STATUS_VAL
))
329 if (!(m
->status
& MCI_STATUS_UC
)) {
332 apei_err
= apei_write_mce(m
);
335 /* Now print uncorrected but with the final one last */
336 for (i
= 0; i
< MCE_LOG_LEN
; i
++) {
337 struct mce
*m
= &mcelog
.entry
[i
];
338 if (!(m
->status
& MCI_STATUS_VAL
))
340 if (!(m
->status
& MCI_STATUS_UC
))
342 if (!final
|| memcmp(m
, final
, sizeof(struct mce
))) {
345 apei_err
= apei_write_mce(m
);
351 apei_err
= apei_write_mce(final
);
354 pr_emerg(HW_ERR
"Some CPUs didn't answer in synchronization\n");
356 pr_emerg(HW_ERR
"Machine check: %s\n", exp
);
358 if (panic_timeout
== 0)
359 panic_timeout
= mce_panic_timeout
;
362 pr_emerg(HW_ERR
"Fake kernel panic: %s\n", msg
);
365 /* Support code for software error injection */
367 static int msr_to_offset(u32 msr
)
369 unsigned bank
= __this_cpu_read(injectm
.bank
);
372 return offsetof(struct mce
, ip
);
373 if (msr
== MSR_IA32_MCx_STATUS(bank
))
374 return offsetof(struct mce
, status
);
375 if (msr
== MSR_IA32_MCx_ADDR(bank
))
376 return offsetof(struct mce
, addr
);
377 if (msr
== MSR_IA32_MCx_MISC(bank
))
378 return offsetof(struct mce
, misc
);
379 if (msr
== MSR_IA32_MCG_STATUS
)
380 return offsetof(struct mce
, mcgstatus
);
384 /* MSR access wrappers used for error injection */
385 static u64
mce_rdmsrl(u32 msr
)
389 if (__this_cpu_read(injectm
.finished
)) {
390 int offset
= msr_to_offset(msr
);
394 return *(u64
*)((char *)&__get_cpu_var(injectm
) + offset
);
397 if (rdmsrl_safe(msr
, &v
)) {
398 WARN_ONCE(1, "mce: Unable to read msr %d!\n", msr
);
400 * Return zero in case the access faulted. This should
401 * not happen normally but can happen if the CPU does
402 * something weird, or if the code is buggy.
410 static void mce_wrmsrl(u32 msr
, u64 v
)
412 if (__this_cpu_read(injectm
.finished
)) {
413 int offset
= msr_to_offset(msr
);
416 *(u64
*)((char *)&__get_cpu_var(injectm
) + offset
) = v
;
423 * Collect all global (w.r.t. this processor) status about this machine
424 * check into our "mce" struct so that we can use it later to assess
425 * the severity of the problem as we read per-bank specific details.
427 static inline void mce_gather_info(struct mce
*m
, struct pt_regs
*regs
)
431 m
->mcgstatus
= mce_rdmsrl(MSR_IA32_MCG_STATUS
);
434 * Get the address of the instruction at the time of
435 * the machine check error.
437 if (m
->mcgstatus
& (MCG_STATUS_RIPV
|MCG_STATUS_EIPV
)) {
441 /* Use accurate RIP reporting if available. */
443 m
->ip
= mce_rdmsrl(rip_msr
);
448 * Simple lockless ring to communicate PFNs from the exception handler with the
449 * process context work function. This is vastly simplified because there's
450 * only a single reader and a single writer.
452 #define MCE_RING_SIZE 16 /* we use one entry less */
455 unsigned short start
;
457 unsigned long ring
[MCE_RING_SIZE
];
459 static DEFINE_PER_CPU(struct mce_ring
, mce_ring
);
461 /* Runs with CPU affinity in workqueue */
462 static int mce_ring_empty(void)
464 struct mce_ring
*r
= &__get_cpu_var(mce_ring
);
466 return r
->start
== r
->end
;
469 static int mce_ring_get(unsigned long *pfn
)
476 r
= &__get_cpu_var(mce_ring
);
477 if (r
->start
== r
->end
)
479 *pfn
= r
->ring
[r
->start
];
480 r
->start
= (r
->start
+ 1) % MCE_RING_SIZE
;
487 /* Always runs in MCE context with preempt off */
488 static int mce_ring_add(unsigned long pfn
)
490 struct mce_ring
*r
= &__get_cpu_var(mce_ring
);
493 next
= (r
->end
+ 1) % MCE_RING_SIZE
;
494 if (next
== r
->start
)
496 r
->ring
[r
->end
] = pfn
;
502 int mce_available(struct cpuinfo_x86
*c
)
506 return cpu_has(c
, X86_FEATURE_MCE
) && cpu_has(c
, X86_FEATURE_MCA
);
509 static void mce_schedule_work(void)
511 if (!mce_ring_empty()) {
512 struct work_struct
*work
= &__get_cpu_var(mce_work
);
513 if (!work_pending(work
))
518 DEFINE_PER_CPU(struct irq_work
, mce_irq_work
);
520 static void mce_irq_work_cb(struct irq_work
*entry
)
526 static void mce_report_event(struct pt_regs
*regs
)
528 if (regs
->flags
& (X86_VM_MASK
|X86_EFLAGS_IF
)) {
531 * Triggering the work queue here is just an insurance
532 * policy in case the syscall exit notify handler
533 * doesn't run soon enough or ends up running on the
534 * wrong CPU (can happen when audit sleeps)
540 irq_work_queue(&__get_cpu_var(mce_irq_work
));
544 * Read ADDR and MISC registers.
546 static void mce_read_aux(struct mce
*m
, int i
)
548 if (m
->status
& MCI_STATUS_MISCV
)
549 m
->misc
= mce_rdmsrl(MSR_IA32_MCx_MISC(i
));
550 if (m
->status
& MCI_STATUS_ADDRV
) {
551 m
->addr
= mce_rdmsrl(MSR_IA32_MCx_ADDR(i
));
554 * Mask the reported address by the reported granularity.
556 if (mce_ser
&& (m
->status
& MCI_STATUS_MISCV
)) {
557 u8 shift
= MCI_MISC_ADDR_LSB(m
->misc
);
564 DEFINE_PER_CPU(unsigned, mce_poll_count
);
567 * Poll for corrected events or events that happened before reset.
568 * Those are just logged through /dev/mcelog.
570 * This is executed in standard interrupt context.
572 * Note: spec recommends to panic for fatal unsignalled
573 * errors here. However this would be quite problematic --
574 * we would need to reimplement the Monarch handling and
575 * it would mess up the exclusion between exception handler
576 * and poll hander -- * so we skip this for now.
577 * These cases should not happen anyways, or only when the CPU
578 * is already totally * confused. In this case it's likely it will
579 * not fully execute the machine check handler either.
581 void machine_check_poll(enum mcp_flags flags
, mce_banks_t
*b
)
586 percpu_inc(mce_poll_count
);
588 mce_gather_info(&m
, NULL
);
590 for (i
= 0; i
< banks
; i
++) {
591 if (!mce_banks
[i
].ctl
|| !test_bit(i
, *b
))
600 m
.status
= mce_rdmsrl(MSR_IA32_MCx_STATUS(i
));
601 if (!(m
.status
& MCI_STATUS_VAL
))
605 * Uncorrected or signalled events are handled by the exception
606 * handler when it is enabled, so don't process those here.
608 * TBD do the same check for MCI_STATUS_EN here?
610 if (!(flags
& MCP_UC
) &&
611 (m
.status
& (mce_ser
? MCI_STATUS_S
: MCI_STATUS_UC
)))
616 if (!(flags
& MCP_TIMESTAMP
))
619 * Don't get the IP here because it's unlikely to
620 * have anything to do with the actual error location.
622 if (!(flags
& MCP_DONTLOG
) && !mce_dont_log_ce
)
626 * Clear state for this bank.
628 mce_wrmsrl(MSR_IA32_MCx_STATUS(i
), 0);
632 * Don't clear MCG_STATUS here because it's only defined for
638 EXPORT_SYMBOL_GPL(machine_check_poll
);
641 * Do a quick check if any of the events requires a panic.
642 * This decides if we keep the events around or clear them.
644 static int mce_no_way_out(struct mce
*m
, char **msg
)
648 for (i
= 0; i
< banks
; i
++) {
649 m
->status
= mce_rdmsrl(MSR_IA32_MCx_STATUS(i
));
650 if (mce_severity(m
, tolerant
, msg
) >= MCE_PANIC_SEVERITY
)
657 * Variable to establish order between CPUs while scanning.
658 * Each CPU spins initially until executing is equal its number.
660 static atomic_t mce_executing
;
663 * Defines order of CPUs on entry. First CPU becomes Monarch.
665 static atomic_t mce_callin
;
668 * Check if a timeout waiting for other CPUs happened.
670 static int mce_timed_out(u64
*t
)
673 * The others already did panic for some reason.
674 * Bail out like in a timeout.
675 * rmb() to tell the compiler that system_state
676 * might have been modified by someone else.
679 if (atomic_read(&mce_paniced
))
681 if (!monarch_timeout
)
683 if ((s64
)*t
< SPINUNIT
) {
684 /* CHECKME: Make panic default for 1 too? */
686 mce_panic("Timeout synchronizing machine check over CPUs",
693 touch_nmi_watchdog();
698 * The Monarch's reign. The Monarch is the CPU who entered
699 * the machine check handler first. It waits for the others to
700 * raise the exception too and then grades them. When any
701 * error is fatal panic. Only then let the others continue.
703 * The other CPUs entering the MCE handler will be controlled by the
704 * Monarch. They are called Subjects.
706 * This way we prevent any potential data corruption in a unrecoverable case
707 * and also makes sure always all CPU's errors are examined.
709 * Also this detects the case of a machine check event coming from outer
710 * space (not detected by any CPUs) In this case some external agent wants
711 * us to shut down, so panic too.
713 * The other CPUs might still decide to panic if the handler happens
714 * in a unrecoverable place, but in this case the system is in a semi-stable
715 * state and won't corrupt anything by itself. It's ok to let the others
716 * continue for a bit first.
718 * All the spin loops have timeouts; when a timeout happens a CPU
719 * typically elects itself to be Monarch.
721 static void mce_reign(void)
724 struct mce
*m
= NULL
;
725 int global_worst
= 0;
730 * This CPU is the Monarch and the other CPUs have run
731 * through their handlers.
732 * Grade the severity of the errors of all the CPUs.
734 for_each_possible_cpu(cpu
) {
735 int severity
= mce_severity(&per_cpu(mces_seen
, cpu
), tolerant
,
737 if (severity
> global_worst
) {
739 global_worst
= severity
;
740 m
= &per_cpu(mces_seen
, cpu
);
745 * Cannot recover? Panic here then.
746 * This dumps all the mces in the log buffer and stops the
749 if (m
&& global_worst
>= MCE_PANIC_SEVERITY
&& tolerant
< 3)
750 mce_panic("Fatal Machine check", m
, msg
);
753 * For UC somewhere we let the CPU who detects it handle it.
754 * Also must let continue the others, otherwise the handling
755 * CPU could deadlock on a lock.
759 * No machine check event found. Must be some external
760 * source or one CPU is hung. Panic.
762 if (global_worst
<= MCE_KEEP_SEVERITY
&& tolerant
< 3)
763 mce_panic("Machine check from unknown source", NULL
, NULL
);
766 * Now clear all the mces_seen so that they don't reappear on
769 for_each_possible_cpu(cpu
)
770 memset(&per_cpu(mces_seen
, cpu
), 0, sizeof(struct mce
));
773 static atomic_t global_nwo
;
776 * Start of Monarch synchronization. This waits until all CPUs have
777 * entered the exception handler and then determines if any of them
778 * saw a fatal event that requires panic. Then it executes them
779 * in the entry order.
780 * TBD double check parallel CPU hotunplug
782 static int mce_start(int *no_way_out
)
785 int cpus
= num_online_cpus();
786 u64 timeout
= (u64
)monarch_timeout
* NSEC_PER_USEC
;
791 atomic_add(*no_way_out
, &global_nwo
);
793 * global_nwo should be updated before mce_callin
796 order
= atomic_inc_return(&mce_callin
);
801 while (atomic_read(&mce_callin
) != cpus
) {
802 if (mce_timed_out(&timeout
)) {
803 atomic_set(&global_nwo
, 0);
810 * mce_callin should be read before global_nwo
816 * Monarch: Starts executing now, the others wait.
818 atomic_set(&mce_executing
, 1);
821 * Subject: Now start the scanning loop one by one in
822 * the original callin order.
823 * This way when there are any shared banks it will be
824 * only seen by one CPU before cleared, avoiding duplicates.
826 while (atomic_read(&mce_executing
) < order
) {
827 if (mce_timed_out(&timeout
)) {
828 atomic_set(&global_nwo
, 0);
836 * Cache the global no_way_out state.
838 *no_way_out
= atomic_read(&global_nwo
);
844 * Synchronize between CPUs after main scanning loop.
845 * This invokes the bulk of the Monarch processing.
847 static int mce_end(int order
)
850 u64 timeout
= (u64
)monarch_timeout
* NSEC_PER_USEC
;
858 * Allow others to run.
860 atomic_inc(&mce_executing
);
863 /* CHECKME: Can this race with a parallel hotplug? */
864 int cpus
= num_online_cpus();
867 * Monarch: Wait for everyone to go through their scanning
870 while (atomic_read(&mce_executing
) <= cpus
) {
871 if (mce_timed_out(&timeout
))
881 * Subject: Wait for Monarch to finish.
883 while (atomic_read(&mce_executing
) != 0) {
884 if (mce_timed_out(&timeout
))
890 * Don't reset anything. That's done by the Monarch.
896 * Reset all global state.
899 atomic_set(&global_nwo
, 0);
900 atomic_set(&mce_callin
, 0);
904 * Let others run again.
906 atomic_set(&mce_executing
, 0);
911 * Check if the address reported by the CPU is in a format we can parse.
912 * It would be possible to add code for most other cases, but all would
913 * be somewhat complicated (e.g. segment offset would require an instruction
914 * parser). So only support physical addresses up to page granuality for now.
916 static int mce_usable_address(struct mce
*m
)
918 if (!(m
->status
& MCI_STATUS_MISCV
) || !(m
->status
& MCI_STATUS_ADDRV
))
920 if (MCI_MISC_ADDR_LSB(m
->misc
) > PAGE_SHIFT
)
922 if (MCI_MISC_ADDR_MODE(m
->misc
) != MCI_MISC_ADDR_PHYS
)
927 static void mce_clear_state(unsigned long *toclear
)
931 for (i
= 0; i
< banks
; i
++) {
932 if (test_bit(i
, toclear
))
933 mce_wrmsrl(MSR_IA32_MCx_STATUS(i
), 0);
938 * Need to save faulting physical address associated with a process
939 * in the machine check handler some place where we can grab it back
940 * later in mce_notify_process()
942 #define MCE_INFO_MAX 16
946 struct task_struct
*t
;
948 } mce_info
[MCE_INFO_MAX
];
950 static void mce_save_info(__u64 addr
)
954 for (mi
= mce_info
; mi
< &mce_info
[MCE_INFO_MAX
]; mi
++) {
955 if (atomic_cmpxchg(&mi
->inuse
, 0, 1) == 0) {
962 mce_panic("Too many concurrent recoverable errors", NULL
, NULL
);
965 static struct mce_info
*mce_find_info(void)
969 for (mi
= mce_info
; mi
< &mce_info
[MCE_INFO_MAX
]; mi
++)
970 if (atomic_read(&mi
->inuse
) && mi
->t
== current
)
975 static void mce_clear_info(struct mce_info
*mi
)
977 atomic_set(&mi
->inuse
, 0);
981 * The actual machine check handler. This only handles real
982 * exceptions when something got corrupted coming in through int 18.
984 * This is executed in NMI context not subject to normal locking rules. This
985 * implies that most kernel services cannot be safely used. Don't even
986 * think about putting a printk in there!
988 * On Intel systems this is entered on all CPUs in parallel through
989 * MCE broadcast. However some CPUs might be broken beyond repair,
990 * so be always careful when synchronizing with others.
992 void do_machine_check(struct pt_regs
*regs
, long error_code
)
994 struct mce m
, *final
;
999 * Establish sequential order between the CPUs entering the machine
1004 * If no_way_out gets set, there is no safe way to recover from this
1005 * MCE. If tolerant is cranked up, we'll try anyway.
1009 * If kill_it gets set, there might be a way to recover from this
1013 DECLARE_BITMAP(toclear
, MAX_NR_BANKS
);
1014 char *msg
= "Unknown";
1016 atomic_inc(&mce_entry
);
1018 percpu_inc(mce_exception_count
);
1023 mce_gather_info(&m
, regs
);
1025 final
= &__get_cpu_var(mces_seen
);
1028 no_way_out
= mce_no_way_out(&m
, &msg
);
1033 * When no restart IP might need to kill or panic.
1034 * Assume the worst for now, but if we find the
1035 * severity is MCE_AR_SEVERITY we have other options.
1037 if (!(m
.mcgstatus
& MCG_STATUS_RIPV
))
1041 * Go through all the banks in exclusion of the other CPUs.
1042 * This way we don't report duplicated events on shared banks
1043 * because the first one to see it will clear it.
1045 order
= mce_start(&no_way_out
);
1046 for (i
= 0; i
< banks
; i
++) {
1047 __clear_bit(i
, toclear
);
1048 if (!mce_banks
[i
].ctl
)
1055 m
.status
= mce_rdmsrl(MSR_IA32_MCx_STATUS(i
));
1056 if ((m
.status
& MCI_STATUS_VAL
) == 0)
1060 * Non uncorrected or non signaled errors are handled by
1061 * machine_check_poll. Leave them alone, unless this panics.
1063 if (!(m
.status
& (mce_ser
? MCI_STATUS_S
: MCI_STATUS_UC
)) &&
1068 * Set taint even when machine check was not enabled.
1070 add_taint(TAINT_MACHINE_CHECK
);
1072 severity
= mce_severity(&m
, tolerant
, NULL
);
1075 * When machine check was for corrected handler don't touch,
1076 * unless we're panicing.
1078 if (severity
== MCE_KEEP_SEVERITY
&& !no_way_out
)
1080 __set_bit(i
, toclear
);
1081 if (severity
== MCE_NO_SEVERITY
) {
1083 * Machine check event was not enabled. Clear, but
1089 mce_read_aux(&m
, i
);
1092 * Action optional error. Queue address for later processing.
1093 * When the ring overflows we just ignore the AO error.
1094 * RED-PEN add some logging mechanism when
1095 * usable_address or mce_add_ring fails.
1096 * RED-PEN don't ignore overflow for tolerant == 0
1098 if (severity
== MCE_AO_SEVERITY
&& mce_usable_address(&m
))
1099 mce_ring_add(m
.addr
>> PAGE_SHIFT
);
1103 if (severity
> worst
) {
1109 /* mce_clear_state will clear *final, save locally for use later */
1113 mce_clear_state(toclear
);
1116 * Do most of the synchronization with other CPUs.
1117 * When there's any problem use only local no_way_out state.
1119 if (mce_end(order
) < 0)
1120 no_way_out
= worst
>= MCE_PANIC_SEVERITY
;
1123 * At insane "tolerant" levels we take no action. Otherwise
1124 * we only die if we have no other choice. For less serious
1125 * issues we try to recover, or limit damage to the current
1130 mce_panic("Fatal machine check on current CPU", &m
, msg
);
1131 if (worst
== MCE_AR_SEVERITY
) {
1132 /* schedule action before return to userland */
1133 mce_save_info(m
.addr
);
1134 set_thread_flag(TIF_MCE_NOTIFY
);
1135 } else if (kill_it
) {
1136 force_sig(SIGBUS
, current
);
1141 mce_report_event(regs
);
1142 mce_wrmsrl(MSR_IA32_MCG_STATUS
, 0);
1144 atomic_dec(&mce_entry
);
1147 EXPORT_SYMBOL_GPL(do_machine_check
);
1149 #ifndef CONFIG_MEMORY_FAILURE
1150 int memory_failure(unsigned long pfn
, int vector
, int flags
)
1152 /* mce_severity() should not hand us an ACTION_REQUIRED error */
1153 BUG_ON(flags
& MF_ACTION_REQUIRED
);
1154 printk(KERN_ERR
"Uncorrected memory error in page 0x%lx ignored\n"
1155 "Rebuild kernel with CONFIG_MEMORY_FAILURE=y for smarter handling\n", pfn
);
1162 * Called in process context that interrupted by MCE and marked with
1163 * TIF_MCE_NOTIFY, just before returning to erroneous userland.
1164 * This code is allowed to sleep.
1165 * Attempt possible recovery such as calling the high level VM handler to
1166 * process any corrupted pages, and kill/signal current process if required.
1167 * Action required errors are handled here.
1169 void mce_notify_process(void)
1172 struct mce_info
*mi
= mce_find_info();
1175 mce_panic("Lost physical address for unconsumed uncorrectable error", NULL
, NULL
);
1176 pfn
= mi
->paddr
>> PAGE_SHIFT
;
1178 clear_thread_flag(TIF_MCE_NOTIFY
);
1180 pr_err("Uncorrected hardware memory error in user-access at %llx",
1182 if (memory_failure(pfn
, MCE_VECTOR
, MF_ACTION_REQUIRED
) < 0) {
1183 pr_err("Memory error not recovered");
1184 force_sig(SIGBUS
, current
);
1190 * Action optional processing happens here (picking up
1191 * from the list of faulting pages that do_machine_check()
1192 * placed into the "ring").
1194 static void mce_process_work(struct work_struct
*dummy
)
1198 while (mce_ring_get(&pfn
))
1199 memory_failure(pfn
, MCE_VECTOR
, 0);
1202 #ifdef CONFIG_X86_MCE_INTEL
1204 * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog
1205 * @cpu: The CPU on which the event occurred.
1206 * @status: Event status information
1208 * This function should be called by the thermal interrupt after the
1209 * event has been processed and the decision was made to log the event
1212 * The status parameter will be saved to the 'status' field of 'struct mce'
1213 * and historically has been the register value of the
1214 * MSR_IA32_THERMAL_STATUS (Intel) msr.
1216 void mce_log_therm_throt_event(__u64 status
)
1221 m
.bank
= MCE_THERMAL_BANK
;
1225 #endif /* CONFIG_X86_MCE_INTEL */
1228 * Periodic polling timer for "silent" machine check errors. If the
1229 * poller finds an MCE, poll 2x faster. When the poller finds no more
1230 * errors, poll 2x slower (up to check_interval seconds).
1232 static int check_interval
= 5 * 60; /* 5 minutes */
1234 static DEFINE_PER_CPU(int, mce_next_interval
); /* in jiffies */
1235 static DEFINE_PER_CPU(struct timer_list
, mce_timer
);
1237 static void mce_start_timer(unsigned long data
)
1239 struct timer_list
*t
= &per_cpu(mce_timer
, data
);
1242 WARN_ON(smp_processor_id() != data
);
1244 if (mce_available(__this_cpu_ptr(&cpu_info
))) {
1245 machine_check_poll(MCP_TIMESTAMP
,
1246 &__get_cpu_var(mce_poll_banks
));
1250 * Alert userspace if needed. If we logged an MCE, reduce the
1251 * polling interval, otherwise increase the polling interval.
1253 n
= &__get_cpu_var(mce_next_interval
);
1254 if (mce_notify_irq())
1255 *n
= max(*n
/2, HZ
/100);
1257 *n
= min(*n
*2, (int)round_jiffies_relative(check_interval
*HZ
));
1259 t
->expires
= jiffies
+ *n
;
1260 add_timer_on(t
, smp_processor_id());
1263 /* Must not be called in IRQ context where del_timer_sync() can deadlock */
1264 static void mce_timer_delete_all(void)
1268 for_each_online_cpu(cpu
)
1269 del_timer_sync(&per_cpu(mce_timer
, cpu
));
1272 static void mce_do_trigger(struct work_struct
*work
)
1274 call_usermodehelper(mce_helper
, mce_helper_argv
, NULL
, UMH_NO_WAIT
);
1277 static DECLARE_WORK(mce_trigger_work
, mce_do_trigger
);
1280 * Notify the user(s) about new machine check events.
1281 * Can be called from interrupt context, but not from machine check/NMI
1284 int mce_notify_irq(void)
1286 /* Not more than two messages every minute */
1287 static DEFINE_RATELIMIT_STATE(ratelimit
, 60*HZ
, 2);
1289 if (test_and_clear_bit(0, &mce_need_notify
)) {
1290 /* wake processes polling /dev/mcelog */
1291 wake_up_interruptible(&mce_chrdev_wait
);
1294 * There is no risk of missing notifications because
1295 * work_pending is always cleared before the function is
1298 if (mce_helper
[0] && !work_pending(&mce_trigger_work
))
1299 schedule_work(&mce_trigger_work
);
1301 if (__ratelimit(&ratelimit
))
1302 pr_info(HW_ERR
"Machine check events logged\n");
1308 EXPORT_SYMBOL_GPL(mce_notify_irq
);
1310 static int __cpuinit
__mcheck_cpu_mce_banks_init(void)
1314 mce_banks
= kzalloc(banks
* sizeof(struct mce_bank
), GFP_KERNEL
);
1317 for (i
= 0; i
< banks
; i
++) {
1318 struct mce_bank
*b
= &mce_banks
[i
];
1327 * Initialize Machine Checks for a CPU.
1329 static int __cpuinit
__mcheck_cpu_cap_init(void)
1334 rdmsrl(MSR_IA32_MCG_CAP
, cap
);
1336 b
= cap
& MCG_BANKCNT_MASK
;
1338 printk(KERN_INFO
"mce: CPU supports %d MCE banks\n", b
);
1340 if (b
> MAX_NR_BANKS
) {
1342 "MCE: Using only %u machine check banks out of %u\n",
1347 /* Don't support asymmetric configurations today */
1348 WARN_ON(banks
!= 0 && b
!= banks
);
1351 int err
= __mcheck_cpu_mce_banks_init();
1357 /* Use accurate RIP reporting if available. */
1358 if ((cap
& MCG_EXT_P
) && MCG_EXT_CNT(cap
) >= 9)
1359 rip_msr
= MSR_IA32_MCG_EIP
;
1361 if (cap
& MCG_SER_P
)
1367 static void __mcheck_cpu_init_generic(void)
1369 mce_banks_t all_banks
;
1374 * Log the machine checks left over from the previous reset.
1376 bitmap_fill(all_banks
, MAX_NR_BANKS
);
1377 machine_check_poll(MCP_UC
|(!mce_bootlog
? MCP_DONTLOG
: 0), &all_banks
);
1379 set_in_cr4(X86_CR4_MCE
);
1381 rdmsrl(MSR_IA32_MCG_CAP
, cap
);
1382 if (cap
& MCG_CTL_P
)
1383 wrmsr(MSR_IA32_MCG_CTL
, 0xffffffff, 0xffffffff);
1385 for (i
= 0; i
< banks
; i
++) {
1386 struct mce_bank
*b
= &mce_banks
[i
];
1390 wrmsrl(MSR_IA32_MCx_CTL(i
), b
->ctl
);
1391 wrmsrl(MSR_IA32_MCx_STATUS(i
), 0);
1395 /* Add per CPU specific workarounds here */
1396 static int __cpuinit
__mcheck_cpu_apply_quirks(struct cpuinfo_x86
*c
)
1398 if (c
->x86_vendor
== X86_VENDOR_UNKNOWN
) {
1399 pr_info("MCE: unknown CPU type - not enabling MCE support.\n");
1403 /* This should be disabled by the BIOS, but isn't always */
1404 if (c
->x86_vendor
== X86_VENDOR_AMD
) {
1405 if (c
->x86
== 15 && banks
> 4) {
1407 * disable GART TBL walk error reporting, which
1408 * trips off incorrectly with the IOMMU & 3ware
1411 clear_bit(10, (unsigned long *)&mce_banks
[4].ctl
);
1413 if (c
->x86
<= 17 && mce_bootlog
< 0) {
1415 * Lots of broken BIOS around that don't clear them
1416 * by default and leave crap in there. Don't log:
1421 * Various K7s with broken bank 0 around. Always disable
1424 if (c
->x86
== 6 && banks
> 0)
1425 mce_banks
[0].ctl
= 0;
1428 if (c
->x86_vendor
== X86_VENDOR_INTEL
) {
1430 * SDM documents that on family 6 bank 0 should not be written
1431 * because it aliases to another special BIOS controlled
1433 * But it's not aliased anymore on model 0x1a+
1434 * Don't ignore bank 0 completely because there could be a
1435 * valid event later, merely don't write CTL0.
1438 if (c
->x86
== 6 && c
->x86_model
< 0x1A && banks
> 0)
1439 mce_banks
[0].init
= 0;
1442 * All newer Intel systems support MCE broadcasting. Enable
1443 * synchronization with a one second timeout.
1445 if ((c
->x86
> 6 || (c
->x86
== 6 && c
->x86_model
>= 0xe)) &&
1446 monarch_timeout
< 0)
1447 monarch_timeout
= USEC_PER_SEC
;
1450 * There are also broken BIOSes on some Pentium M and
1453 if (c
->x86
== 6 && c
->x86_model
<= 13 && mce_bootlog
< 0)
1456 if (monarch_timeout
< 0)
1457 monarch_timeout
= 0;
1458 if (mce_bootlog
!= 0)
1459 mce_panic_timeout
= 30;
1464 static int __cpuinit
__mcheck_cpu_ancient_init(struct cpuinfo_x86
*c
)
1469 switch (c
->x86_vendor
) {
1470 case X86_VENDOR_INTEL
:
1471 intel_p5_mcheck_init(c
);
1474 case X86_VENDOR_CENTAUR
:
1475 winchip_mcheck_init(c
);
1483 static void __mcheck_cpu_init_vendor(struct cpuinfo_x86
*c
)
1485 switch (c
->x86_vendor
) {
1486 case X86_VENDOR_INTEL
:
1487 mce_intel_feature_init(c
);
1489 case X86_VENDOR_AMD
:
1490 mce_amd_feature_init(c
);
1497 static void __mcheck_cpu_init_timer(void)
1499 struct timer_list
*t
= &__get_cpu_var(mce_timer
);
1500 int *n
= &__get_cpu_var(mce_next_interval
);
1502 setup_timer(t
, mce_start_timer
, smp_processor_id());
1507 *n
= check_interval
* HZ
;
1510 t
->expires
= round_jiffies(jiffies
+ *n
);
1511 add_timer_on(t
, smp_processor_id());
1514 /* Handle unconfigured int18 (should never happen) */
1515 static void unexpected_machine_check(struct pt_regs
*regs
, long error_code
)
1517 printk(KERN_ERR
"CPU#%d: Unexpected int18 (Machine Check).\n",
1518 smp_processor_id());
1521 /* Call the installed machine check handler for this CPU setup. */
1522 void (*machine_check_vector
)(struct pt_regs
*, long error_code
) =
1523 unexpected_machine_check
;
1526 * Called for each booted CPU to set up machine checks.
1527 * Must be called with preempt off:
1529 void __cpuinit
mcheck_cpu_init(struct cpuinfo_x86
*c
)
1534 if (__mcheck_cpu_ancient_init(c
))
1537 if (!mce_available(c
))
1540 if (__mcheck_cpu_cap_init() < 0 || __mcheck_cpu_apply_quirks(c
) < 0) {
1545 machine_check_vector
= do_machine_check
;
1547 __mcheck_cpu_init_generic();
1548 __mcheck_cpu_init_vendor(c
);
1549 __mcheck_cpu_init_timer();
1550 INIT_WORK(&__get_cpu_var(mce_work
), mce_process_work
);
1551 init_irq_work(&__get_cpu_var(mce_irq_work
), &mce_irq_work_cb
);
1555 * mce_chrdev: Character device /dev/mcelog to read and clear the MCE log.
1558 static DEFINE_SPINLOCK(mce_chrdev_state_lock
);
1559 static int mce_chrdev_open_count
; /* #times opened */
1560 static int mce_chrdev_open_exclu
; /* already open exclusive? */
1562 static int mce_chrdev_open(struct inode
*inode
, struct file
*file
)
1564 spin_lock(&mce_chrdev_state_lock
);
1566 if (mce_chrdev_open_exclu
||
1567 (mce_chrdev_open_count
&& (file
->f_flags
& O_EXCL
))) {
1568 spin_unlock(&mce_chrdev_state_lock
);
1573 if (file
->f_flags
& O_EXCL
)
1574 mce_chrdev_open_exclu
= 1;
1575 mce_chrdev_open_count
++;
1577 spin_unlock(&mce_chrdev_state_lock
);
1579 return nonseekable_open(inode
, file
);
1582 static int mce_chrdev_release(struct inode
*inode
, struct file
*file
)
1584 spin_lock(&mce_chrdev_state_lock
);
1586 mce_chrdev_open_count
--;
1587 mce_chrdev_open_exclu
= 0;
1589 spin_unlock(&mce_chrdev_state_lock
);
1594 static void collect_tscs(void *data
)
1596 unsigned long *cpu_tsc
= (unsigned long *)data
;
1598 rdtscll(cpu_tsc
[smp_processor_id()]);
1601 static int mce_apei_read_done
;
1603 /* Collect MCE record of previous boot in persistent storage via APEI ERST. */
1604 static int __mce_read_apei(char __user
**ubuf
, size_t usize
)
1610 if (usize
< sizeof(struct mce
))
1613 rc
= apei_read_mce(&m
, &record_id
);
1614 /* Error or no more MCE record */
1616 mce_apei_read_done
= 1;
1618 * When ERST is disabled, mce_chrdev_read() should return
1619 * "no record" instead of "no device."
1626 if (copy_to_user(*ubuf
, &m
, sizeof(struct mce
)))
1629 * In fact, we should have cleared the record after that has
1630 * been flushed to the disk or sent to network in
1631 * /sbin/mcelog, but we have no interface to support that now,
1632 * so just clear it to avoid duplication.
1634 rc
= apei_clear_mce(record_id
);
1636 mce_apei_read_done
= 1;
1639 *ubuf
+= sizeof(struct mce
);
1644 static ssize_t
mce_chrdev_read(struct file
*filp
, char __user
*ubuf
,
1645 size_t usize
, loff_t
*off
)
1647 char __user
*buf
= ubuf
;
1648 unsigned long *cpu_tsc
;
1649 unsigned prev
, next
;
1652 cpu_tsc
= kmalloc(nr_cpu_ids
* sizeof(long), GFP_KERNEL
);
1656 mutex_lock(&mce_chrdev_read_mutex
);
1658 if (!mce_apei_read_done
) {
1659 err
= __mce_read_apei(&buf
, usize
);
1660 if (err
|| buf
!= ubuf
)
1664 next
= rcu_dereference_check_mce(mcelog
.next
);
1666 /* Only supports full reads right now */
1668 if (*off
!= 0 || usize
< MCE_LOG_LEN
*sizeof(struct mce
))
1674 for (i
= prev
; i
< next
; i
++) {
1675 unsigned long start
= jiffies
;
1676 struct mce
*m
= &mcelog
.entry
[i
];
1678 while (!m
->finished
) {
1679 if (time_after_eq(jiffies
, start
+ 2)) {
1680 memset(m
, 0, sizeof(*m
));
1686 err
|= copy_to_user(buf
, m
, sizeof(*m
));
1692 memset(mcelog
.entry
+ prev
, 0,
1693 (next
- prev
) * sizeof(struct mce
));
1695 next
= cmpxchg(&mcelog
.next
, prev
, 0);
1696 } while (next
!= prev
);
1698 synchronize_sched();
1701 * Collect entries that were still getting written before the
1704 on_each_cpu(collect_tscs
, cpu_tsc
, 1);
1706 for (i
= next
; i
< MCE_LOG_LEN
; i
++) {
1707 struct mce
*m
= &mcelog
.entry
[i
];
1709 if (m
->finished
&& m
->tsc
< cpu_tsc
[m
->cpu
]) {
1710 err
|= copy_to_user(buf
, m
, sizeof(*m
));
1713 memset(m
, 0, sizeof(*m
));
1721 mutex_unlock(&mce_chrdev_read_mutex
);
1724 return err
? err
: buf
- ubuf
;
1727 static unsigned int mce_chrdev_poll(struct file
*file
, poll_table
*wait
)
1729 poll_wait(file
, &mce_chrdev_wait
, wait
);
1730 if (rcu_access_index(mcelog
.next
))
1731 return POLLIN
| POLLRDNORM
;
1732 if (!mce_apei_read_done
&& apei_check_mce())
1733 return POLLIN
| POLLRDNORM
;
1737 static long mce_chrdev_ioctl(struct file
*f
, unsigned int cmd
,
1740 int __user
*p
= (int __user
*)arg
;
1742 if (!capable(CAP_SYS_ADMIN
))
1746 case MCE_GET_RECORD_LEN
:
1747 return put_user(sizeof(struct mce
), p
);
1748 case MCE_GET_LOG_LEN
:
1749 return put_user(MCE_LOG_LEN
, p
);
1750 case MCE_GETCLEAR_FLAGS
: {
1754 flags
= mcelog
.flags
;
1755 } while (cmpxchg(&mcelog
.flags
, flags
, 0) != flags
);
1757 return put_user(flags
, p
);
1764 static ssize_t (*mce_write
)(struct file
*filp
, const char __user
*ubuf
,
1765 size_t usize
, loff_t
*off
);
1767 void register_mce_write_callback(ssize_t (*fn
)(struct file
*filp
,
1768 const char __user
*ubuf
,
1769 size_t usize
, loff_t
*off
))
1773 EXPORT_SYMBOL_GPL(register_mce_write_callback
);
1775 ssize_t
mce_chrdev_write(struct file
*filp
, const char __user
*ubuf
,
1776 size_t usize
, loff_t
*off
)
1779 return mce_write(filp
, ubuf
, usize
, off
);
1784 static const struct file_operations mce_chrdev_ops
= {
1785 .open
= mce_chrdev_open
,
1786 .release
= mce_chrdev_release
,
1787 .read
= mce_chrdev_read
,
1788 .write
= mce_chrdev_write
,
1789 .poll
= mce_chrdev_poll
,
1790 .unlocked_ioctl
= mce_chrdev_ioctl
,
1791 .llseek
= no_llseek
,
1794 static struct miscdevice mce_chrdev_device
= {
1801 * mce=off Disables machine check
1802 * mce=no_cmci Disables CMCI
1803 * mce=dont_log_ce Clears corrected events silently, no log created for CEs.
1804 * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared.
1805 * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above)
1806 * monarchtimeout is how long to wait for other CPUs on machine
1807 * check, or 0 to not wait
1808 * mce=bootlog Log MCEs from before booting. Disabled by default on AMD.
1809 * mce=nobootlog Don't log MCEs from before booting.
1811 static int __init
mcheck_enable(char *str
)
1819 if (!strcmp(str
, "off"))
1821 else if (!strcmp(str
, "no_cmci"))
1822 mce_cmci_disabled
= 1;
1823 else if (!strcmp(str
, "dont_log_ce"))
1824 mce_dont_log_ce
= 1;
1825 else if (!strcmp(str
, "ignore_ce"))
1827 else if (!strcmp(str
, "bootlog") || !strcmp(str
, "nobootlog"))
1828 mce_bootlog
= (str
[0] == 'b');
1829 else if (isdigit(str
[0])) {
1830 get_option(&str
, &tolerant
);
1833 get_option(&str
, &monarch_timeout
);
1836 printk(KERN_INFO
"mce argument %s ignored. Please use /sys\n",
1842 __setup("mce", mcheck_enable
);
1844 int __init
mcheck_init(void)
1846 mcheck_intel_therm_init();
1852 * mce_syscore: PM support
1856 * Disable machine checks on suspend and shutdown. We can't really handle
1859 static int mce_disable_error_reporting(void)
1863 for (i
= 0; i
< banks
; i
++) {
1864 struct mce_bank
*b
= &mce_banks
[i
];
1867 wrmsrl(MSR_IA32_MCx_CTL(i
), 0);
1872 static int mce_syscore_suspend(void)
1874 return mce_disable_error_reporting();
1877 static void mce_syscore_shutdown(void)
1879 mce_disable_error_reporting();
1883 * On resume clear all MCE state. Don't want to see leftovers from the BIOS.
1884 * Only one CPU is active at this time, the others get re-added later using
1887 static void mce_syscore_resume(void)
1889 __mcheck_cpu_init_generic();
1890 __mcheck_cpu_init_vendor(__this_cpu_ptr(&cpu_info
));
1893 static struct syscore_ops mce_syscore_ops
= {
1894 .suspend
= mce_syscore_suspend
,
1895 .shutdown
= mce_syscore_shutdown
,
1896 .resume
= mce_syscore_resume
,
1900 * mce_device: Sysfs support
1903 static void mce_cpu_restart(void *data
)
1905 if (!mce_available(__this_cpu_ptr(&cpu_info
)))
1907 __mcheck_cpu_init_generic();
1908 __mcheck_cpu_init_timer();
1911 /* Reinit MCEs after user configuration changes */
1912 static void mce_restart(void)
1914 mce_timer_delete_all();
1915 on_each_cpu(mce_cpu_restart
, NULL
, 1);
1918 /* Toggle features for corrected errors */
1919 static void mce_disable_cmci(void *data
)
1921 if (!mce_available(__this_cpu_ptr(&cpu_info
)))
1926 static void mce_enable_ce(void *all
)
1928 if (!mce_available(__this_cpu_ptr(&cpu_info
)))
1933 __mcheck_cpu_init_timer();
1936 static struct bus_type mce_subsys
= {
1937 .name
= "machinecheck",
1938 .dev_name
= "machinecheck",
1941 DEFINE_PER_CPU(struct device
*, mce_device
);
1944 void (*threshold_cpu_callback
)(unsigned long action
, unsigned int cpu
);
1946 static inline struct mce_bank
*attr_to_bank(struct device_attribute
*attr
)
1948 return container_of(attr
, struct mce_bank
, attr
);
1951 static ssize_t
show_bank(struct device
*s
, struct device_attribute
*attr
,
1954 return sprintf(buf
, "%llx\n", attr_to_bank(attr
)->ctl
);
1957 static ssize_t
set_bank(struct device
*s
, struct device_attribute
*attr
,
1958 const char *buf
, size_t size
)
1962 if (strict_strtoull(buf
, 0, &new) < 0)
1965 attr_to_bank(attr
)->ctl
= new;
1972 show_trigger(struct device
*s
, struct device_attribute
*attr
, char *buf
)
1974 strcpy(buf
, mce_helper
);
1976 return strlen(mce_helper
) + 1;
1979 static ssize_t
set_trigger(struct device
*s
, struct device_attribute
*attr
,
1980 const char *buf
, size_t siz
)
1984 strncpy(mce_helper
, buf
, sizeof(mce_helper
));
1985 mce_helper
[sizeof(mce_helper
)-1] = 0;
1986 p
= strchr(mce_helper
, '\n');
1991 return strlen(mce_helper
) + !!p
;
1994 static ssize_t
set_ignore_ce(struct device
*s
,
1995 struct device_attribute
*attr
,
1996 const char *buf
, size_t size
)
2000 if (strict_strtoull(buf
, 0, &new) < 0)
2003 if (mce_ignore_ce
^ !!new) {
2005 /* disable ce features */
2006 mce_timer_delete_all();
2007 on_each_cpu(mce_disable_cmci
, NULL
, 1);
2010 /* enable ce features */
2012 on_each_cpu(mce_enable_ce
, (void *)1, 1);
2018 static ssize_t
set_cmci_disabled(struct device
*s
,
2019 struct device_attribute
*attr
,
2020 const char *buf
, size_t size
)
2024 if (strict_strtoull(buf
, 0, &new) < 0)
2027 if (mce_cmci_disabled
^ !!new) {
2030 on_each_cpu(mce_disable_cmci
, NULL
, 1);
2031 mce_cmci_disabled
= 1;
2034 mce_cmci_disabled
= 0;
2035 on_each_cpu(mce_enable_ce
, NULL
, 1);
2041 static ssize_t
store_int_with_restart(struct device
*s
,
2042 struct device_attribute
*attr
,
2043 const char *buf
, size_t size
)
2045 ssize_t ret
= device_store_int(s
, attr
, buf
, size
);
2050 static DEVICE_ATTR(trigger
, 0644, show_trigger
, set_trigger
);
2051 static DEVICE_INT_ATTR(tolerant
, 0644, tolerant
);
2052 static DEVICE_INT_ATTR(monarch_timeout
, 0644, monarch_timeout
);
2053 static DEVICE_INT_ATTR(dont_log_ce
, 0644, mce_dont_log_ce
);
2055 static struct dev_ext_attribute dev_attr_check_interval
= {
2056 __ATTR(check_interval
, 0644, device_show_int
, store_int_with_restart
),
2060 static struct dev_ext_attribute dev_attr_ignore_ce
= {
2061 __ATTR(ignore_ce
, 0644, device_show_int
, set_ignore_ce
),
2065 static struct dev_ext_attribute dev_attr_cmci_disabled
= {
2066 __ATTR(cmci_disabled
, 0644, device_show_int
, set_cmci_disabled
),
2070 static struct device_attribute
*mce_device_attrs
[] = {
2071 &dev_attr_tolerant
.attr
,
2072 &dev_attr_check_interval
.attr
,
2074 &dev_attr_monarch_timeout
.attr
,
2075 &dev_attr_dont_log_ce
.attr
,
2076 &dev_attr_ignore_ce
.attr
,
2077 &dev_attr_cmci_disabled
.attr
,
2081 static cpumask_var_t mce_device_initialized
;
2083 static void mce_device_release(struct device
*dev
)
2088 /* Per cpu device init. All of the cpus still share the same ctrl bank: */
2089 static __cpuinit
int mce_device_create(unsigned int cpu
)
2095 if (!mce_available(&boot_cpu_data
))
2098 dev
= kzalloc(sizeof *dev
, GFP_KERNEL
);
2102 dev
->bus
= &mce_subsys
;
2103 dev
->release
= &mce_device_release
;
2105 err
= device_register(dev
);
2109 for (i
= 0; mce_device_attrs
[i
]; i
++) {
2110 err
= device_create_file(dev
, mce_device_attrs
[i
]);
2114 for (j
= 0; j
< banks
; j
++) {
2115 err
= device_create_file(dev
, &mce_banks
[j
].attr
);
2119 cpumask_set_cpu(cpu
, mce_device_initialized
);
2120 per_cpu(mce_device
, cpu
) = dev
;
2125 device_remove_file(dev
, &mce_banks
[j
].attr
);
2128 device_remove_file(dev
, mce_device_attrs
[i
]);
2130 device_unregister(dev
);
2135 static __cpuinit
void mce_device_remove(unsigned int cpu
)
2137 struct device
*dev
= per_cpu(mce_device
, cpu
);
2140 if (!cpumask_test_cpu(cpu
, mce_device_initialized
))
2143 for (i
= 0; mce_device_attrs
[i
]; i
++)
2144 device_remove_file(dev
, mce_device_attrs
[i
]);
2146 for (i
= 0; i
< banks
; i
++)
2147 device_remove_file(dev
, &mce_banks
[i
].attr
);
2149 device_unregister(dev
);
2150 cpumask_clear_cpu(cpu
, mce_device_initialized
);
2151 per_cpu(mce_device
, cpu
) = NULL
;
2154 /* Make sure there are no machine checks on offlined CPUs. */
2155 static void __cpuinit
mce_disable_cpu(void *h
)
2157 unsigned long action
= *(unsigned long *)h
;
2160 if (!mce_available(__this_cpu_ptr(&cpu_info
)))
2163 if (!(action
& CPU_TASKS_FROZEN
))
2165 for (i
= 0; i
< banks
; i
++) {
2166 struct mce_bank
*b
= &mce_banks
[i
];
2169 wrmsrl(MSR_IA32_MCx_CTL(i
), 0);
2173 static void __cpuinit
mce_reenable_cpu(void *h
)
2175 unsigned long action
= *(unsigned long *)h
;
2178 if (!mce_available(__this_cpu_ptr(&cpu_info
)))
2181 if (!(action
& CPU_TASKS_FROZEN
))
2183 for (i
= 0; i
< banks
; i
++) {
2184 struct mce_bank
*b
= &mce_banks
[i
];
2187 wrmsrl(MSR_IA32_MCx_CTL(i
), b
->ctl
);
2191 /* Get notified when a cpu comes on/off. Be hotplug friendly. */
2192 static int __cpuinit
2193 mce_cpu_callback(struct notifier_block
*nfb
, unsigned long action
, void *hcpu
)
2195 unsigned int cpu
= (unsigned long)hcpu
;
2196 struct timer_list
*t
= &per_cpu(mce_timer
, cpu
);
2200 case CPU_ONLINE_FROZEN
:
2201 mce_device_create(cpu
);
2202 if (threshold_cpu_callback
)
2203 threshold_cpu_callback(action
, cpu
);
2206 case CPU_DEAD_FROZEN
:
2207 if (threshold_cpu_callback
)
2208 threshold_cpu_callback(action
, cpu
);
2209 mce_device_remove(cpu
);
2211 case CPU_DOWN_PREPARE
:
2212 case CPU_DOWN_PREPARE_FROZEN
:
2214 smp_call_function_single(cpu
, mce_disable_cpu
, &action
, 1);
2216 case CPU_DOWN_FAILED
:
2217 case CPU_DOWN_FAILED_FROZEN
:
2218 if (!mce_ignore_ce
&& check_interval
) {
2219 t
->expires
= round_jiffies(jiffies
+
2220 __get_cpu_var(mce_next_interval
));
2221 add_timer_on(t
, cpu
);
2223 smp_call_function_single(cpu
, mce_reenable_cpu
, &action
, 1);
2226 /* intentionally ignoring frozen here */
2227 cmci_rediscover(cpu
);
2233 static struct notifier_block mce_cpu_notifier __cpuinitdata
= {
2234 .notifier_call
= mce_cpu_callback
,
2237 static __init
void mce_init_banks(void)
2241 for (i
= 0; i
< banks
; i
++) {
2242 struct mce_bank
*b
= &mce_banks
[i
];
2243 struct device_attribute
*a
= &b
->attr
;
2245 sysfs_attr_init(&a
->attr
);
2246 a
->attr
.name
= b
->attrname
;
2247 snprintf(b
->attrname
, ATTR_LEN
, "bank%d", i
);
2249 a
->attr
.mode
= 0644;
2250 a
->show
= show_bank
;
2251 a
->store
= set_bank
;
2255 static __init
int mcheck_init_device(void)
2260 if (!mce_available(&boot_cpu_data
))
2263 zalloc_cpumask_var(&mce_device_initialized
, GFP_KERNEL
);
2267 err
= subsys_system_register(&mce_subsys
, NULL
);
2271 for_each_online_cpu(i
) {
2272 err
= mce_device_create(i
);
2277 register_syscore_ops(&mce_syscore_ops
);
2278 register_hotcpu_notifier(&mce_cpu_notifier
);
2280 /* register character device /dev/mcelog */
2281 misc_register(&mce_chrdev_device
);
2285 device_initcall(mcheck_init_device
);
2288 * Old style boot options parsing. Only for compatibility.
2290 static int __init
mcheck_disable(char *str
)
2295 __setup("nomce", mcheck_disable
);
2297 #ifdef CONFIG_DEBUG_FS
2298 struct dentry
*mce_get_debugfs_dir(void)
2300 static struct dentry
*dmce
;
2303 dmce
= debugfs_create_dir("mce", NULL
);
2308 static void mce_reset(void)
2311 atomic_set(&mce_fake_paniced
, 0);
2312 atomic_set(&mce_executing
, 0);
2313 atomic_set(&mce_callin
, 0);
2314 atomic_set(&global_nwo
, 0);
2317 static int fake_panic_get(void *data
, u64
*val
)
2323 static int fake_panic_set(void *data
, u64 val
)
2330 DEFINE_SIMPLE_ATTRIBUTE(fake_panic_fops
, fake_panic_get
,
2331 fake_panic_set
, "%llu\n");
2333 static int __init
mcheck_debugfs_init(void)
2335 struct dentry
*dmce
, *ffake_panic
;
2337 dmce
= mce_get_debugfs_dir();
2340 ffake_panic
= debugfs_create_file("fake_panic", 0444, dmce
, NULL
,
2347 late_initcall(mcheck_debugfs_init
);