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[deliverable/linux.git] / arch / x86 / kernel / cpu / mcheck / mce_amd.c
1 /*
2 * (c) 2005-2012 Advanced Micro Devices, Inc.
3 * Your use of this code is subject to the terms and conditions of the
4 * GNU general public license version 2. See "COPYING" or
5 * http://www.gnu.org/licenses/gpl.html
6 *
7 * Written by Jacob Shin - AMD, Inc.
8 *
9 * Maintained by: Borislav Petkov <bp@alien8.de>
10 *
11 * April 2006
12 * - added support for AMD Family 0x10 processors
13 * May 2012
14 * - major scrubbing
15 *
16 * All MC4_MISCi registers are shared between multi-cores
17 */
18 #include <linux/interrupt.h>
19 #include <linux/notifier.h>
20 #include <linux/kobject.h>
21 #include <linux/percpu.h>
22 #include <linux/errno.h>
23 #include <linux/sched.h>
24 #include <linux/sysfs.h>
25 #include <linux/slab.h>
26 #include <linux/init.h>
27 #include <linux/cpu.h>
28 #include <linux/smp.h>
29
30 #include <asm/amd_nb.h>
31 #include <asm/apic.h>
32 #include <asm/idle.h>
33 #include <asm/mce.h>
34 #include <asm/msr.h>
35
36 #define NR_BLOCKS 9
37 #define THRESHOLD_MAX 0xFFF
38 #define INT_TYPE_APIC 0x00020000
39 #define MASK_VALID_HI 0x80000000
40 #define MASK_CNTP_HI 0x40000000
41 #define MASK_LOCKED_HI 0x20000000
42 #define MASK_LVTOFF_HI 0x00F00000
43 #define MASK_COUNT_EN_HI 0x00080000
44 #define MASK_INT_TYPE_HI 0x00060000
45 #define MASK_OVERFLOW_HI 0x00010000
46 #define MASK_ERR_COUNT_HI 0x00000FFF
47 #define MASK_BLKPTR_LO 0xFF000000
48 #define MCG_XBLK_ADDR 0xC0000400
49
50 static const char * const th_names[] = {
51 "load_store",
52 "insn_fetch",
53 "combined_unit",
54 "",
55 "northbridge",
56 "execution_unit",
57 };
58
59 static DEFINE_PER_CPU(struct threshold_bank **, threshold_banks);
60 static DEFINE_PER_CPU(unsigned char, bank_map); /* see which banks are on */
61
62 static void amd_threshold_interrupt(void);
63
64 /*
65 * CPU Initialization
66 */
67
68 struct thresh_restart {
69 struct threshold_block *b;
70 int reset;
71 int set_lvt_off;
72 int lvt_off;
73 u16 old_limit;
74 };
75
76 static inline bool is_shared_bank(int bank)
77 {
78 /* Bank 4 is for northbridge reporting and is thus shared */
79 return (bank == 4);
80 }
81
82 static const char *bank4_names(const struct threshold_block *b)
83 {
84 switch (b->address) {
85 /* MSR4_MISC0 */
86 case 0x00000413:
87 return "dram";
88
89 case 0xc0000408:
90 return "ht_links";
91
92 case 0xc0000409:
93 return "l3_cache";
94
95 default:
96 WARN(1, "Funny MSR: 0x%08x\n", b->address);
97 return "";
98 }
99 };
100
101
102 static bool lvt_interrupt_supported(unsigned int bank, u32 msr_high_bits)
103 {
104 /*
105 * bank 4 supports APIC LVT interrupts implicitly since forever.
106 */
107 if (bank == 4)
108 return true;
109
110 /*
111 * IntP: interrupt present; if this bit is set, the thresholding
112 * bank can generate APIC LVT interrupts
113 */
114 return msr_high_bits & BIT(28);
115 }
116
117 static int lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi)
118 {
119 int msr = (hi & MASK_LVTOFF_HI) >> 20;
120
121 if (apic < 0) {
122 pr_err(FW_BUG "cpu %d, failed to setup threshold interrupt "
123 "for bank %d, block %d (MSR%08X=0x%x%08x)\n", b->cpu,
124 b->bank, b->block, b->address, hi, lo);
125 return 0;
126 }
127
128 if (apic != msr) {
129 pr_err(FW_BUG "cpu %d, invalid threshold interrupt offset %d "
130 "for bank %d, block %d (MSR%08X=0x%x%08x)\n",
131 b->cpu, apic, b->bank, b->block, b->address, hi, lo);
132 return 0;
133 }
134
135 return 1;
136 };
137
138 /*
139 * Called via smp_call_function_single(), must be called with correct
140 * cpu affinity.
141 */
142 static void threshold_restart_bank(void *_tr)
143 {
144 struct thresh_restart *tr = _tr;
145 u32 hi, lo;
146
147 rdmsr(tr->b->address, lo, hi);
148
149 if (tr->b->threshold_limit < (hi & THRESHOLD_MAX))
150 tr->reset = 1; /* limit cannot be lower than err count */
151
152 if (tr->reset) { /* reset err count and overflow bit */
153 hi =
154 (hi & ~(MASK_ERR_COUNT_HI | MASK_OVERFLOW_HI)) |
155 (THRESHOLD_MAX - tr->b->threshold_limit);
156 } else if (tr->old_limit) { /* change limit w/o reset */
157 int new_count = (hi & THRESHOLD_MAX) +
158 (tr->old_limit - tr->b->threshold_limit);
159
160 hi = (hi & ~MASK_ERR_COUNT_HI) |
161 (new_count & THRESHOLD_MAX);
162 }
163
164 /* clear IntType */
165 hi &= ~MASK_INT_TYPE_HI;
166
167 if (!tr->b->interrupt_capable)
168 goto done;
169
170 if (tr->set_lvt_off) {
171 if (lvt_off_valid(tr->b, tr->lvt_off, lo, hi)) {
172 /* set new lvt offset */
173 hi &= ~MASK_LVTOFF_HI;
174 hi |= tr->lvt_off << 20;
175 }
176 }
177
178 if (tr->b->interrupt_enable)
179 hi |= INT_TYPE_APIC;
180
181 done:
182
183 hi |= MASK_COUNT_EN_HI;
184 wrmsr(tr->b->address, lo, hi);
185 }
186
187 static void mce_threshold_block_init(struct threshold_block *b, int offset)
188 {
189 struct thresh_restart tr = {
190 .b = b,
191 .set_lvt_off = 1,
192 .lvt_off = offset,
193 };
194
195 b->threshold_limit = THRESHOLD_MAX;
196 threshold_restart_bank(&tr);
197 };
198
199 static int setup_APIC_mce(int reserved, int new)
200 {
201 if (reserved < 0 && !setup_APIC_eilvt(new, THRESHOLD_APIC_VECTOR,
202 APIC_EILVT_MSG_FIX, 0))
203 return new;
204
205 return reserved;
206 }
207
208 /* cpu init entry point, called from mce.c with preempt off */
209 void mce_amd_feature_init(struct cpuinfo_x86 *c)
210 {
211 struct threshold_block b;
212 unsigned int cpu = smp_processor_id();
213 u32 low = 0, high = 0, address = 0;
214 unsigned int bank, block;
215 int offset = -1, new;
216
217 for (bank = 0; bank < mca_cfg.banks; ++bank) {
218 for (block = 0; block < NR_BLOCKS; ++block) {
219 if (block == 0)
220 address = MSR_IA32_MCx_MISC(bank);
221 else if (block == 1) {
222 address = (low & MASK_BLKPTR_LO) >> 21;
223 if (!address)
224 break;
225
226 address += MCG_XBLK_ADDR;
227 } else
228 ++address;
229
230 if (rdmsr_safe(address, &low, &high))
231 break;
232
233 if (!(high & MASK_VALID_HI))
234 continue;
235
236 if (!(high & MASK_CNTP_HI) ||
237 (high & MASK_LOCKED_HI))
238 continue;
239
240 if (!block)
241 per_cpu(bank_map, cpu) |= (1 << bank);
242
243 memset(&b, 0, sizeof(b));
244 b.cpu = cpu;
245 b.bank = bank;
246 b.block = block;
247 b.address = address;
248 b.interrupt_capable = lvt_interrupt_supported(bank, high);
249
250 if (!b.interrupt_capable)
251 goto init;
252
253 b.interrupt_enable = 1;
254 new = (high & MASK_LVTOFF_HI) >> 20;
255 offset = setup_APIC_mce(offset, new);
256
257 if ((offset == new) &&
258 (mce_threshold_vector != amd_threshold_interrupt))
259 mce_threshold_vector = amd_threshold_interrupt;
260
261 init:
262 mce_threshold_block_init(&b, offset);
263 }
264 }
265 }
266
267 static void __log_error(unsigned int bank, bool threshold_err, u64 misc)
268 {
269 struct mce m;
270 u64 status;
271
272 rdmsrl(MSR_IA32_MCx_STATUS(bank), status);
273 if (!(status & MCI_STATUS_VAL))
274 return;
275
276 mce_setup(&m);
277
278 m.status = status;
279 m.bank = bank;
280 if (threshold_err)
281 m.misc = misc;
282
283 mce_log(&m);
284
285 wrmsrl(MSR_IA32_MCx_STATUS(bank), 0);
286 }
287
288 /*
289 * APIC Interrupt Handler
290 */
291
292 /*
293 * threshold interrupt handler will service THRESHOLD_APIC_VECTOR.
294 * the interrupt goes off when error_count reaches threshold_limit.
295 * the handler will simply log mcelog w/ software defined bank number.
296 */
297
298 static void amd_threshold_interrupt(void)
299 {
300 u32 low = 0, high = 0, address = 0;
301 int cpu = smp_processor_id();
302 unsigned int bank, block;
303
304 /* assume first bank caused it */
305 for (bank = 0; bank < mca_cfg.banks; ++bank) {
306 if (!(per_cpu(bank_map, cpu) & (1 << bank)))
307 continue;
308 for (block = 0; block < NR_BLOCKS; ++block) {
309 if (block == 0) {
310 address = MSR_IA32_MCx_MISC(bank);
311 } else if (block == 1) {
312 address = (low & MASK_BLKPTR_LO) >> 21;
313 if (!address)
314 break;
315 address += MCG_XBLK_ADDR;
316 } else {
317 ++address;
318 }
319
320 if (rdmsr_safe(address, &low, &high))
321 break;
322
323 if (!(high & MASK_VALID_HI)) {
324 if (block)
325 continue;
326 else
327 break;
328 }
329
330 if (!(high & MASK_CNTP_HI) ||
331 (high & MASK_LOCKED_HI))
332 continue;
333
334 /*
335 * Log the machine check that caused the threshold
336 * event.
337 */
338 if (high & MASK_OVERFLOW_HI)
339 goto log;
340 }
341 }
342 return;
343
344 log:
345 __log_error(bank, true, ((u64)high << 32) | low);
346 }
347
348 /*
349 * Sysfs Interface
350 */
351
352 struct threshold_attr {
353 struct attribute attr;
354 ssize_t (*show) (struct threshold_block *, char *);
355 ssize_t (*store) (struct threshold_block *, const char *, size_t count);
356 };
357
358 #define SHOW_FIELDS(name) \
359 static ssize_t show_ ## name(struct threshold_block *b, char *buf) \
360 { \
361 return sprintf(buf, "%lu\n", (unsigned long) b->name); \
362 }
363 SHOW_FIELDS(interrupt_enable)
364 SHOW_FIELDS(threshold_limit)
365
366 static ssize_t
367 store_interrupt_enable(struct threshold_block *b, const char *buf, size_t size)
368 {
369 struct thresh_restart tr;
370 unsigned long new;
371
372 if (!b->interrupt_capable)
373 return -EINVAL;
374
375 if (kstrtoul(buf, 0, &new) < 0)
376 return -EINVAL;
377
378 b->interrupt_enable = !!new;
379
380 memset(&tr, 0, sizeof(tr));
381 tr.b = b;
382
383 smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1);
384
385 return size;
386 }
387
388 static ssize_t
389 store_threshold_limit(struct threshold_block *b, const char *buf, size_t size)
390 {
391 struct thresh_restart tr;
392 unsigned long new;
393
394 if (kstrtoul(buf, 0, &new) < 0)
395 return -EINVAL;
396
397 if (new > THRESHOLD_MAX)
398 new = THRESHOLD_MAX;
399 if (new < 1)
400 new = 1;
401
402 memset(&tr, 0, sizeof(tr));
403 tr.old_limit = b->threshold_limit;
404 b->threshold_limit = new;
405 tr.b = b;
406
407 smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1);
408
409 return size;
410 }
411
412 static ssize_t show_error_count(struct threshold_block *b, char *buf)
413 {
414 u32 lo, hi;
415
416 rdmsr_on_cpu(b->cpu, b->address, &lo, &hi);
417
418 return sprintf(buf, "%u\n", ((hi & THRESHOLD_MAX) -
419 (THRESHOLD_MAX - b->threshold_limit)));
420 }
421
422 static struct threshold_attr error_count = {
423 .attr = {.name = __stringify(error_count), .mode = 0444 },
424 .show = show_error_count,
425 };
426
427 #define RW_ATTR(val) \
428 static struct threshold_attr val = { \
429 .attr = {.name = __stringify(val), .mode = 0644 }, \
430 .show = show_## val, \
431 .store = store_## val, \
432 };
433
434 RW_ATTR(interrupt_enable);
435 RW_ATTR(threshold_limit);
436
437 static struct attribute *default_attrs[] = {
438 &threshold_limit.attr,
439 &error_count.attr,
440 NULL, /* possibly interrupt_enable if supported, see below */
441 NULL,
442 };
443
444 #define to_block(k) container_of(k, struct threshold_block, kobj)
445 #define to_attr(a) container_of(a, struct threshold_attr, attr)
446
447 static ssize_t show(struct kobject *kobj, struct attribute *attr, char *buf)
448 {
449 struct threshold_block *b = to_block(kobj);
450 struct threshold_attr *a = to_attr(attr);
451 ssize_t ret;
452
453 ret = a->show ? a->show(b, buf) : -EIO;
454
455 return ret;
456 }
457
458 static ssize_t store(struct kobject *kobj, struct attribute *attr,
459 const char *buf, size_t count)
460 {
461 struct threshold_block *b = to_block(kobj);
462 struct threshold_attr *a = to_attr(attr);
463 ssize_t ret;
464
465 ret = a->store ? a->store(b, buf, count) : -EIO;
466
467 return ret;
468 }
469
470 static const struct sysfs_ops threshold_ops = {
471 .show = show,
472 .store = store,
473 };
474
475 static struct kobj_type threshold_ktype = {
476 .sysfs_ops = &threshold_ops,
477 .default_attrs = default_attrs,
478 };
479
480 static int allocate_threshold_blocks(unsigned int cpu, unsigned int bank,
481 unsigned int block, u32 address)
482 {
483 struct threshold_block *b = NULL;
484 u32 low, high;
485 int err;
486
487 if ((bank >= mca_cfg.banks) || (block >= NR_BLOCKS))
488 return 0;
489
490 if (rdmsr_safe_on_cpu(cpu, address, &low, &high))
491 return 0;
492
493 if (!(high & MASK_VALID_HI)) {
494 if (block)
495 goto recurse;
496 else
497 return 0;
498 }
499
500 if (!(high & MASK_CNTP_HI) ||
501 (high & MASK_LOCKED_HI))
502 goto recurse;
503
504 b = kzalloc(sizeof(struct threshold_block), GFP_KERNEL);
505 if (!b)
506 return -ENOMEM;
507
508 b->block = block;
509 b->bank = bank;
510 b->cpu = cpu;
511 b->address = address;
512 b->interrupt_enable = 0;
513 b->interrupt_capable = lvt_interrupt_supported(bank, high);
514 b->threshold_limit = THRESHOLD_MAX;
515
516 if (b->interrupt_capable) {
517 threshold_ktype.default_attrs[2] = &interrupt_enable.attr;
518 b->interrupt_enable = 1;
519 } else {
520 threshold_ktype.default_attrs[2] = NULL;
521 }
522
523 INIT_LIST_HEAD(&b->miscj);
524
525 if (per_cpu(threshold_banks, cpu)[bank]->blocks) {
526 list_add(&b->miscj,
527 &per_cpu(threshold_banks, cpu)[bank]->blocks->miscj);
528 } else {
529 per_cpu(threshold_banks, cpu)[bank]->blocks = b;
530 }
531
532 err = kobject_init_and_add(&b->kobj, &threshold_ktype,
533 per_cpu(threshold_banks, cpu)[bank]->kobj,
534 (bank == 4 ? bank4_names(b) : th_names[bank]));
535 if (err)
536 goto out_free;
537 recurse:
538 if (!block) {
539 address = (low & MASK_BLKPTR_LO) >> 21;
540 if (!address)
541 return 0;
542 address += MCG_XBLK_ADDR;
543 } else {
544 ++address;
545 }
546
547 err = allocate_threshold_blocks(cpu, bank, ++block, address);
548 if (err)
549 goto out_free;
550
551 if (b)
552 kobject_uevent(&b->kobj, KOBJ_ADD);
553
554 return err;
555
556 out_free:
557 if (b) {
558 kobject_put(&b->kobj);
559 list_del(&b->miscj);
560 kfree(b);
561 }
562 return err;
563 }
564
565 static int __threshold_add_blocks(struct threshold_bank *b)
566 {
567 struct list_head *head = &b->blocks->miscj;
568 struct threshold_block *pos = NULL;
569 struct threshold_block *tmp = NULL;
570 int err = 0;
571
572 err = kobject_add(&b->blocks->kobj, b->kobj, b->blocks->kobj.name);
573 if (err)
574 return err;
575
576 list_for_each_entry_safe(pos, tmp, head, miscj) {
577
578 err = kobject_add(&pos->kobj, b->kobj, pos->kobj.name);
579 if (err) {
580 list_for_each_entry_safe_reverse(pos, tmp, head, miscj)
581 kobject_del(&pos->kobj);
582
583 return err;
584 }
585 }
586 return err;
587 }
588
589 static int threshold_create_bank(unsigned int cpu, unsigned int bank)
590 {
591 struct device *dev = per_cpu(mce_device, cpu);
592 struct amd_northbridge *nb = NULL;
593 struct threshold_bank *b = NULL;
594 const char *name = th_names[bank];
595 int err = 0;
596
597 if (is_shared_bank(bank)) {
598 nb = node_to_amd_nb(amd_get_nb_id(cpu));
599
600 /* threshold descriptor already initialized on this node? */
601 if (nb && nb->bank4) {
602 /* yes, use it */
603 b = nb->bank4;
604 err = kobject_add(b->kobj, &dev->kobj, name);
605 if (err)
606 goto out;
607
608 per_cpu(threshold_banks, cpu)[bank] = b;
609 atomic_inc(&b->cpus);
610
611 err = __threshold_add_blocks(b);
612
613 goto out;
614 }
615 }
616
617 b = kzalloc(sizeof(struct threshold_bank), GFP_KERNEL);
618 if (!b) {
619 err = -ENOMEM;
620 goto out;
621 }
622
623 b->kobj = kobject_create_and_add(name, &dev->kobj);
624 if (!b->kobj) {
625 err = -EINVAL;
626 goto out_free;
627 }
628
629 per_cpu(threshold_banks, cpu)[bank] = b;
630
631 if (is_shared_bank(bank)) {
632 atomic_set(&b->cpus, 1);
633
634 /* nb is already initialized, see above */
635 if (nb) {
636 WARN_ON(nb->bank4);
637 nb->bank4 = b;
638 }
639 }
640
641 err = allocate_threshold_blocks(cpu, bank, 0, MSR_IA32_MCx_MISC(bank));
642 if (!err)
643 goto out;
644
645 out_free:
646 kfree(b);
647
648 out:
649 return err;
650 }
651
652 /* create dir/files for all valid threshold banks */
653 static int threshold_create_device(unsigned int cpu)
654 {
655 unsigned int bank;
656 struct threshold_bank **bp;
657 int err = 0;
658
659 bp = kzalloc(sizeof(struct threshold_bank *) * mca_cfg.banks,
660 GFP_KERNEL);
661 if (!bp)
662 return -ENOMEM;
663
664 per_cpu(threshold_banks, cpu) = bp;
665
666 for (bank = 0; bank < mca_cfg.banks; ++bank) {
667 if (!(per_cpu(bank_map, cpu) & (1 << bank)))
668 continue;
669 err = threshold_create_bank(cpu, bank);
670 if (err)
671 return err;
672 }
673
674 return err;
675 }
676
677 static void deallocate_threshold_block(unsigned int cpu,
678 unsigned int bank)
679 {
680 struct threshold_block *pos = NULL;
681 struct threshold_block *tmp = NULL;
682 struct threshold_bank *head = per_cpu(threshold_banks, cpu)[bank];
683
684 if (!head)
685 return;
686
687 list_for_each_entry_safe(pos, tmp, &head->blocks->miscj, miscj) {
688 kobject_put(&pos->kobj);
689 list_del(&pos->miscj);
690 kfree(pos);
691 }
692
693 kfree(per_cpu(threshold_banks, cpu)[bank]->blocks);
694 per_cpu(threshold_banks, cpu)[bank]->blocks = NULL;
695 }
696
697 static void __threshold_remove_blocks(struct threshold_bank *b)
698 {
699 struct threshold_block *pos = NULL;
700 struct threshold_block *tmp = NULL;
701
702 kobject_del(b->kobj);
703
704 list_for_each_entry_safe(pos, tmp, &b->blocks->miscj, miscj)
705 kobject_del(&pos->kobj);
706 }
707
708 static void threshold_remove_bank(unsigned int cpu, int bank)
709 {
710 struct amd_northbridge *nb;
711 struct threshold_bank *b;
712
713 b = per_cpu(threshold_banks, cpu)[bank];
714 if (!b)
715 return;
716
717 if (!b->blocks)
718 goto free_out;
719
720 if (is_shared_bank(bank)) {
721 if (!atomic_dec_and_test(&b->cpus)) {
722 __threshold_remove_blocks(b);
723 per_cpu(threshold_banks, cpu)[bank] = NULL;
724 return;
725 } else {
726 /*
727 * the last CPU on this node using the shared bank is
728 * going away, remove that bank now.
729 */
730 nb = node_to_amd_nb(amd_get_nb_id(cpu));
731 nb->bank4 = NULL;
732 }
733 }
734
735 deallocate_threshold_block(cpu, bank);
736
737 free_out:
738 kobject_del(b->kobj);
739 kobject_put(b->kobj);
740 kfree(b);
741 per_cpu(threshold_banks, cpu)[bank] = NULL;
742 }
743
744 static void threshold_remove_device(unsigned int cpu)
745 {
746 unsigned int bank;
747
748 for (bank = 0; bank < mca_cfg.banks; ++bank) {
749 if (!(per_cpu(bank_map, cpu) & (1 << bank)))
750 continue;
751 threshold_remove_bank(cpu, bank);
752 }
753 kfree(per_cpu(threshold_banks, cpu));
754 }
755
756 /* get notified when a cpu comes on/off */
757 static void
758 amd_64_threshold_cpu_callback(unsigned long action, unsigned int cpu)
759 {
760 switch (action) {
761 case CPU_ONLINE:
762 case CPU_ONLINE_FROZEN:
763 threshold_create_device(cpu);
764 break;
765 case CPU_DEAD:
766 case CPU_DEAD_FROZEN:
767 threshold_remove_device(cpu);
768 break;
769 default:
770 break;
771 }
772 }
773
774 static __init int threshold_init_device(void)
775 {
776 unsigned lcpu = 0;
777
778 /* to hit CPUs online before the notifier is up */
779 for_each_online_cpu(lcpu) {
780 int err = threshold_create_device(lcpu);
781
782 if (err)
783 return err;
784 }
785 threshold_cpu_callback = amd_64_threshold_cpu_callback;
786
787 return 0;
788 }
789 /*
790 * there are 3 funcs which need to be _initcalled in a logic sequence:
791 * 1. xen_late_init_mcelog
792 * 2. mcheck_init_device
793 * 3. threshold_init_device
794 *
795 * xen_late_init_mcelog must register xen_mce_chrdev_device before
796 * native mce_chrdev_device registration if running under xen platform;
797 *
798 * mcheck_init_device should be inited before threshold_init_device to
799 * initialize mce_device, otherwise a NULL ptr dereference will cause panic.
800 *
801 * so we use following _initcalls
802 * 1. device_initcall(xen_late_init_mcelog);
803 * 2. device_initcall_sync(mcheck_init_device);
804 * 3. late_initcall(threshold_init_device);
805 *
806 * when running under xen, the initcall order is 1,2,3;
807 * on baremetal, we skip 1 and we do only 2 and 3.
808 */
809 late_initcall(threshold_init_device);
Linux kernel - Deliverables
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