2 * (c) 2005-2012 Advanced Micro Devices, Inc.
3 * Your use of this code is subject to the terms and conditions of the
4 * GNU general public license version 2. See "COPYING" or
5 * http://www.gnu.org/licenses/gpl.html
7 * Written by Jacob Shin - AMD, Inc.
9 * Maintained by: Borislav Petkov <bp@alien8.de>
12 * - added support for AMD Family 0x10 processors
16 * All MC4_MISCi registers are shared between multi-cores
18 #include <linux/interrupt.h>
19 #include <linux/notifier.h>
20 #include <linux/kobject.h>
21 #include <linux/percpu.h>
22 #include <linux/errno.h>
23 #include <linux/sched.h>
24 #include <linux/sysfs.h>
25 #include <linux/slab.h>
26 #include <linux/init.h>
27 #include <linux/cpu.h>
28 #include <linux/smp.h>
30 #include <asm/amd_nb.h>
37 #define THRESHOLD_MAX 0xFFF
38 #define INT_TYPE_APIC 0x00020000
39 #define MASK_VALID_HI 0x80000000
40 #define MASK_CNTP_HI 0x40000000
41 #define MASK_LOCKED_HI 0x20000000
42 #define MASK_LVTOFF_HI 0x00F00000
43 #define MASK_COUNT_EN_HI 0x00080000
44 #define MASK_INT_TYPE_HI 0x00060000
45 #define MASK_OVERFLOW_HI 0x00010000
46 #define MASK_ERR_COUNT_HI 0x00000FFF
47 #define MASK_BLKPTR_LO 0xFF000000
48 #define MCG_XBLK_ADDR 0xC0000400
50 static const char * const th_names
[] = {
59 static DEFINE_PER_CPU(struct threshold_bank
**, threshold_banks
);
60 static DEFINE_PER_CPU(unsigned char, bank_map
); /* see which banks are on */
62 static void amd_threshold_interrupt(void);
68 struct thresh_restart
{
69 struct threshold_block
*b
;
76 static inline bool is_shared_bank(int bank
)
78 /* Bank 4 is for northbridge reporting and is thus shared */
82 static const char *bank4_names(const struct threshold_block
*b
)
96 WARN(1, "Funny MSR: 0x%08x\n", b
->address
);
102 static bool lvt_interrupt_supported(unsigned int bank
, u32 msr_high_bits
)
105 * bank 4 supports APIC LVT interrupts implicitly since forever.
111 * IntP: interrupt present; if this bit is set, the thresholding
112 * bank can generate APIC LVT interrupts
114 return msr_high_bits
& BIT(28);
117 static int lvt_off_valid(struct threshold_block
*b
, int apic
, u32 lo
, u32 hi
)
119 int msr
= (hi
& MASK_LVTOFF_HI
) >> 20;
122 pr_err(FW_BUG
"cpu %d, failed to setup threshold interrupt "
123 "for bank %d, block %d (MSR%08X=0x%x%08x)\n", b
->cpu
,
124 b
->bank
, b
->block
, b
->address
, hi
, lo
);
129 pr_err(FW_BUG
"cpu %d, invalid threshold interrupt offset %d "
130 "for bank %d, block %d (MSR%08X=0x%x%08x)\n",
131 b
->cpu
, apic
, b
->bank
, b
->block
, b
->address
, hi
, lo
);
139 * Called via smp_call_function_single(), must be called with correct
142 static void threshold_restart_bank(void *_tr
)
144 struct thresh_restart
*tr
= _tr
;
147 rdmsr(tr
->b
->address
, lo
, hi
);
149 if (tr
->b
->threshold_limit
< (hi
& THRESHOLD_MAX
))
150 tr
->reset
= 1; /* limit cannot be lower than err count */
152 if (tr
->reset
) { /* reset err count and overflow bit */
154 (hi
& ~(MASK_ERR_COUNT_HI
| MASK_OVERFLOW_HI
)) |
155 (THRESHOLD_MAX
- tr
->b
->threshold_limit
);
156 } else if (tr
->old_limit
) { /* change limit w/o reset */
157 int new_count
= (hi
& THRESHOLD_MAX
) +
158 (tr
->old_limit
- tr
->b
->threshold_limit
);
160 hi
= (hi
& ~MASK_ERR_COUNT_HI
) |
161 (new_count
& THRESHOLD_MAX
);
165 hi
&= ~MASK_INT_TYPE_HI
;
167 if (!tr
->b
->interrupt_capable
)
170 if (tr
->set_lvt_off
) {
171 if (lvt_off_valid(tr
->b
, tr
->lvt_off
, lo
, hi
)) {
172 /* set new lvt offset */
173 hi
&= ~MASK_LVTOFF_HI
;
174 hi
|= tr
->lvt_off
<< 20;
178 if (tr
->b
->interrupt_enable
)
183 hi
|= MASK_COUNT_EN_HI
;
184 wrmsr(tr
->b
->address
, lo
, hi
);
187 static void mce_threshold_block_init(struct threshold_block
*b
, int offset
)
189 struct thresh_restart tr
= {
195 b
->threshold_limit
= THRESHOLD_MAX
;
196 threshold_restart_bank(&tr
);
199 static int setup_APIC_mce(int reserved
, int new)
201 if (reserved
< 0 && !setup_APIC_eilvt(new, THRESHOLD_APIC_VECTOR
,
202 APIC_EILVT_MSG_FIX
, 0))
208 /* cpu init entry point, called from mce.c with preempt off */
209 void mce_amd_feature_init(struct cpuinfo_x86
*c
)
211 struct threshold_block b
;
212 unsigned int cpu
= smp_processor_id();
213 u32 low
= 0, high
= 0, address
= 0;
214 unsigned int bank
, block
;
215 int offset
= -1, new;
217 for (bank
= 0; bank
< mca_cfg
.banks
; ++bank
) {
218 for (block
= 0; block
< NR_BLOCKS
; ++block
) {
220 address
= MSR_IA32_MCx_MISC(bank
);
221 else if (block
== 1) {
222 address
= (low
& MASK_BLKPTR_LO
) >> 21;
226 address
+= MCG_XBLK_ADDR
;
230 if (rdmsr_safe(address
, &low
, &high
))
233 if (!(high
& MASK_VALID_HI
))
236 if (!(high
& MASK_CNTP_HI
) ||
237 (high
& MASK_LOCKED_HI
))
241 per_cpu(bank_map
, cpu
) |= (1 << bank
);
243 memset(&b
, 0, sizeof(b
));
248 b
.interrupt_capable
= lvt_interrupt_supported(bank
, high
);
250 if (!b
.interrupt_capable
)
253 b
.interrupt_enable
= 1;
254 new = (high
& MASK_LVTOFF_HI
) >> 20;
255 offset
= setup_APIC_mce(offset
, new);
257 if ((offset
== new) &&
258 (mce_threshold_vector
!= amd_threshold_interrupt
))
259 mce_threshold_vector
= amd_threshold_interrupt
;
262 mce_threshold_block_init(&b
, offset
);
267 static void __log_error(unsigned int bank
, bool threshold_err
, u64 misc
)
272 rdmsrl(MSR_IA32_MCx_STATUS(bank
), status
);
273 if (!(status
& MCI_STATUS_VAL
))
284 if (m
.status
& MCI_STATUS_ADDRV
)
285 rdmsrl(MSR_IA32_MCx_ADDR(bank
), m
.addr
);
288 wrmsrl(MSR_IA32_MCx_STATUS(bank
), 0);
292 * APIC Interrupt Handler
296 * threshold interrupt handler will service THRESHOLD_APIC_VECTOR.
297 * the interrupt goes off when error_count reaches threshold_limit.
298 * the handler will simply log mcelog w/ software defined bank number.
301 static void amd_threshold_interrupt(void)
303 u32 low
= 0, high
= 0, address
= 0;
304 int cpu
= smp_processor_id();
305 unsigned int bank
, block
;
307 /* assume first bank caused it */
308 for (bank
= 0; bank
< mca_cfg
.banks
; ++bank
) {
309 if (!(per_cpu(bank_map
, cpu
) & (1 << bank
)))
311 for (block
= 0; block
< NR_BLOCKS
; ++block
) {
313 address
= MSR_IA32_MCx_MISC(bank
);
314 } else if (block
== 1) {
315 address
= (low
& MASK_BLKPTR_LO
) >> 21;
318 address
+= MCG_XBLK_ADDR
;
323 if (rdmsr_safe(address
, &low
, &high
))
326 if (!(high
& MASK_VALID_HI
)) {
333 if (!(high
& MASK_CNTP_HI
) ||
334 (high
& MASK_LOCKED_HI
))
338 * Log the machine check that caused the threshold
341 if (high
& MASK_OVERFLOW_HI
)
348 __log_error(bank
, true, ((u64
)high
<< 32) | low
);
355 struct threshold_attr
{
356 struct attribute attr
;
357 ssize_t (*show
) (struct threshold_block
*, char *);
358 ssize_t (*store
) (struct threshold_block
*, const char *, size_t count
);
361 #define SHOW_FIELDS(name) \
362 static ssize_t show_ ## name(struct threshold_block *b, char *buf) \
364 return sprintf(buf, "%lu\n", (unsigned long) b->name); \
366 SHOW_FIELDS(interrupt_enable
)
367 SHOW_FIELDS(threshold_limit
)
370 store_interrupt_enable(struct threshold_block
*b
, const char *buf
, size_t size
)
372 struct thresh_restart tr
;
375 if (!b
->interrupt_capable
)
378 if (kstrtoul(buf
, 0, &new) < 0)
381 b
->interrupt_enable
= !!new;
383 memset(&tr
, 0, sizeof(tr
));
386 smp_call_function_single(b
->cpu
, threshold_restart_bank
, &tr
, 1);
392 store_threshold_limit(struct threshold_block
*b
, const char *buf
, size_t size
)
394 struct thresh_restart tr
;
397 if (kstrtoul(buf
, 0, &new) < 0)
400 if (new > THRESHOLD_MAX
)
405 memset(&tr
, 0, sizeof(tr
));
406 tr
.old_limit
= b
->threshold_limit
;
407 b
->threshold_limit
= new;
410 smp_call_function_single(b
->cpu
, threshold_restart_bank
, &tr
, 1);
415 static ssize_t
show_error_count(struct threshold_block
*b
, char *buf
)
419 rdmsr_on_cpu(b
->cpu
, b
->address
, &lo
, &hi
);
421 return sprintf(buf
, "%u\n", ((hi
& THRESHOLD_MAX
) -
422 (THRESHOLD_MAX
- b
->threshold_limit
)));
425 static struct threshold_attr error_count
= {
426 .attr
= {.name
= __stringify(error_count
), .mode
= 0444 },
427 .show
= show_error_count
,
430 #define RW_ATTR(val) \
431 static struct threshold_attr val = { \
432 .attr = {.name = __stringify(val), .mode = 0644 }, \
433 .show = show_## val, \
434 .store = store_## val, \
437 RW_ATTR(interrupt_enable
);
438 RW_ATTR(threshold_limit
);
440 static struct attribute
*default_attrs
[] = {
441 &threshold_limit
.attr
,
443 NULL
, /* possibly interrupt_enable if supported, see below */
447 #define to_block(k) container_of(k, struct threshold_block, kobj)
448 #define to_attr(a) container_of(a, struct threshold_attr, attr)
450 static ssize_t
show(struct kobject
*kobj
, struct attribute
*attr
, char *buf
)
452 struct threshold_block
*b
= to_block(kobj
);
453 struct threshold_attr
*a
= to_attr(attr
);
456 ret
= a
->show
? a
->show(b
, buf
) : -EIO
;
461 static ssize_t
store(struct kobject
*kobj
, struct attribute
*attr
,
462 const char *buf
, size_t count
)
464 struct threshold_block
*b
= to_block(kobj
);
465 struct threshold_attr
*a
= to_attr(attr
);
468 ret
= a
->store
? a
->store(b
, buf
, count
) : -EIO
;
473 static const struct sysfs_ops threshold_ops
= {
478 static struct kobj_type threshold_ktype
= {
479 .sysfs_ops
= &threshold_ops
,
480 .default_attrs
= default_attrs
,
483 static int allocate_threshold_blocks(unsigned int cpu
, unsigned int bank
,
484 unsigned int block
, u32 address
)
486 struct threshold_block
*b
= NULL
;
490 if ((bank
>= mca_cfg
.banks
) || (block
>= NR_BLOCKS
))
493 if (rdmsr_safe_on_cpu(cpu
, address
, &low
, &high
))
496 if (!(high
& MASK_VALID_HI
)) {
503 if (!(high
& MASK_CNTP_HI
) ||
504 (high
& MASK_LOCKED_HI
))
507 b
= kzalloc(sizeof(struct threshold_block
), GFP_KERNEL
);
514 b
->address
= address
;
515 b
->interrupt_enable
= 0;
516 b
->interrupt_capable
= lvt_interrupt_supported(bank
, high
);
517 b
->threshold_limit
= THRESHOLD_MAX
;
519 if (b
->interrupt_capable
) {
520 threshold_ktype
.default_attrs
[2] = &interrupt_enable
.attr
;
521 b
->interrupt_enable
= 1;
523 threshold_ktype
.default_attrs
[2] = NULL
;
526 INIT_LIST_HEAD(&b
->miscj
);
528 if (per_cpu(threshold_banks
, cpu
)[bank
]->blocks
) {
530 &per_cpu(threshold_banks
, cpu
)[bank
]->blocks
->miscj
);
532 per_cpu(threshold_banks
, cpu
)[bank
]->blocks
= b
;
535 err
= kobject_init_and_add(&b
->kobj
, &threshold_ktype
,
536 per_cpu(threshold_banks
, cpu
)[bank
]->kobj
,
537 (bank
== 4 ? bank4_names(b
) : th_names
[bank
]));
542 address
= (low
& MASK_BLKPTR_LO
) >> 21;
545 address
+= MCG_XBLK_ADDR
;
550 err
= allocate_threshold_blocks(cpu
, bank
, ++block
, address
);
555 kobject_uevent(&b
->kobj
, KOBJ_ADD
);
561 kobject_put(&b
->kobj
);
568 static int __threshold_add_blocks(struct threshold_bank
*b
)
570 struct list_head
*head
= &b
->blocks
->miscj
;
571 struct threshold_block
*pos
= NULL
;
572 struct threshold_block
*tmp
= NULL
;
575 err
= kobject_add(&b
->blocks
->kobj
, b
->kobj
, b
->blocks
->kobj
.name
);
579 list_for_each_entry_safe(pos
, tmp
, head
, miscj
) {
581 err
= kobject_add(&pos
->kobj
, b
->kobj
, pos
->kobj
.name
);
583 list_for_each_entry_safe_reverse(pos
, tmp
, head
, miscj
)
584 kobject_del(&pos
->kobj
);
592 static int threshold_create_bank(unsigned int cpu
, unsigned int bank
)
594 struct device
*dev
= per_cpu(mce_device
, cpu
);
595 struct amd_northbridge
*nb
= NULL
;
596 struct threshold_bank
*b
= NULL
;
597 const char *name
= th_names
[bank
];
600 if (is_shared_bank(bank
)) {
601 nb
= node_to_amd_nb(amd_get_nb_id(cpu
));
603 /* threshold descriptor already initialized on this node? */
604 if (nb
&& nb
->bank4
) {
607 err
= kobject_add(b
->kobj
, &dev
->kobj
, name
);
611 per_cpu(threshold_banks
, cpu
)[bank
] = b
;
612 atomic_inc(&b
->cpus
);
614 err
= __threshold_add_blocks(b
);
620 b
= kzalloc(sizeof(struct threshold_bank
), GFP_KERNEL
);
626 b
->kobj
= kobject_create_and_add(name
, &dev
->kobj
);
632 per_cpu(threshold_banks
, cpu
)[bank
] = b
;
634 if (is_shared_bank(bank
)) {
635 atomic_set(&b
->cpus
, 1);
637 /* nb is already initialized, see above */
644 err
= allocate_threshold_blocks(cpu
, bank
, 0, MSR_IA32_MCx_MISC(bank
));
655 /* create dir/files for all valid threshold banks */
656 static int threshold_create_device(unsigned int cpu
)
659 struct threshold_bank
**bp
;
662 bp
= kzalloc(sizeof(struct threshold_bank
*) * mca_cfg
.banks
,
667 per_cpu(threshold_banks
, cpu
) = bp
;
669 for (bank
= 0; bank
< mca_cfg
.banks
; ++bank
) {
670 if (!(per_cpu(bank_map
, cpu
) & (1 << bank
)))
672 err
= threshold_create_bank(cpu
, bank
);
680 static void deallocate_threshold_block(unsigned int cpu
,
683 struct threshold_block
*pos
= NULL
;
684 struct threshold_block
*tmp
= NULL
;
685 struct threshold_bank
*head
= per_cpu(threshold_banks
, cpu
)[bank
];
690 list_for_each_entry_safe(pos
, tmp
, &head
->blocks
->miscj
, miscj
) {
691 kobject_put(&pos
->kobj
);
692 list_del(&pos
->miscj
);
696 kfree(per_cpu(threshold_banks
, cpu
)[bank
]->blocks
);
697 per_cpu(threshold_banks
, cpu
)[bank
]->blocks
= NULL
;
700 static void __threshold_remove_blocks(struct threshold_bank
*b
)
702 struct threshold_block
*pos
= NULL
;
703 struct threshold_block
*tmp
= NULL
;
705 kobject_del(b
->kobj
);
707 list_for_each_entry_safe(pos
, tmp
, &b
->blocks
->miscj
, miscj
)
708 kobject_del(&pos
->kobj
);
711 static void threshold_remove_bank(unsigned int cpu
, int bank
)
713 struct amd_northbridge
*nb
;
714 struct threshold_bank
*b
;
716 b
= per_cpu(threshold_banks
, cpu
)[bank
];
723 if (is_shared_bank(bank
)) {
724 if (!atomic_dec_and_test(&b
->cpus
)) {
725 __threshold_remove_blocks(b
);
726 per_cpu(threshold_banks
, cpu
)[bank
] = NULL
;
730 * the last CPU on this node using the shared bank is
731 * going away, remove that bank now.
733 nb
= node_to_amd_nb(amd_get_nb_id(cpu
));
738 deallocate_threshold_block(cpu
, bank
);
741 kobject_del(b
->kobj
);
742 kobject_put(b
->kobj
);
744 per_cpu(threshold_banks
, cpu
)[bank
] = NULL
;
747 static void threshold_remove_device(unsigned int cpu
)
751 for (bank
= 0; bank
< mca_cfg
.banks
; ++bank
) {
752 if (!(per_cpu(bank_map
, cpu
) & (1 << bank
)))
754 threshold_remove_bank(cpu
, bank
);
756 kfree(per_cpu(threshold_banks
, cpu
));
759 /* get notified when a cpu comes on/off */
761 amd_64_threshold_cpu_callback(unsigned long action
, unsigned int cpu
)
765 case CPU_ONLINE_FROZEN
:
766 threshold_create_device(cpu
);
769 case CPU_DEAD_FROZEN
:
770 threshold_remove_device(cpu
);
777 static __init
int threshold_init_device(void)
781 /* to hit CPUs online before the notifier is up */
782 for_each_online_cpu(lcpu
) {
783 int err
= threshold_create_device(lcpu
);
788 threshold_cpu_callback
= amd_64_threshold_cpu_callback
;
793 * there are 3 funcs which need to be _initcalled in a logic sequence:
794 * 1. xen_late_init_mcelog
795 * 2. mcheck_init_device
796 * 3. threshold_init_device
798 * xen_late_init_mcelog must register xen_mce_chrdev_device before
799 * native mce_chrdev_device registration if running under xen platform;
801 * mcheck_init_device should be inited before threshold_init_device to
802 * initialize mce_device, otherwise a NULL ptr dereference will cause panic.
804 * so we use following _initcalls
805 * 1. device_initcall(xen_late_init_mcelog);
806 * 2. device_initcall_sync(mcheck_init_device);
807 * 3. late_initcall(threshold_init_device);
809 * when running under xen, the initcall order is 1,2,3;
810 * on baremetal, we skip 1 and we do only 2 and 3.
812 late_initcall(threshold_init_device
);