2 * (c) 2005-2012 Advanced Micro Devices, Inc.
3 * Your use of this code is subject to the terms and conditions of the
4 * GNU general public license version 2. See "COPYING" or
5 * http://www.gnu.org/licenses/gpl.html
7 * Written by Jacob Shin - AMD, Inc.
9 * Maintained by: Borislav Petkov <bp@alien8.de>
12 * - added support for AMD Family 0x10 processors
16 * All MC4_MISCi registers are shared between multi-cores
18 #include <linux/interrupt.h>
19 #include <linux/notifier.h>
20 #include <linux/kobject.h>
21 #include <linux/percpu.h>
22 #include <linux/errno.h>
23 #include <linux/sched.h>
24 #include <linux/sysfs.h>
25 #include <linux/slab.h>
26 #include <linux/init.h>
27 #include <linux/cpu.h>
28 #include <linux/smp.h>
30 #include <asm/amd_nb.h>
38 #define THRESHOLD_MAX 0xFFF
39 #define INT_TYPE_APIC 0x00020000
40 #define MASK_VALID_HI 0x80000000
41 #define MASK_CNTP_HI 0x40000000
42 #define MASK_LOCKED_HI 0x20000000
43 #define MASK_LVTOFF_HI 0x00F00000
44 #define MASK_COUNT_EN_HI 0x00080000
45 #define MASK_INT_TYPE_HI 0x00060000
46 #define MASK_OVERFLOW_HI 0x00010000
47 #define MASK_ERR_COUNT_HI 0x00000FFF
48 #define MASK_BLKPTR_LO 0xFF000000
49 #define MCG_XBLK_ADDR 0xC0000400
51 static const char * const th_names
[] = {
60 static DEFINE_PER_CPU(struct threshold_bank
* [NR_BANKS
], threshold_banks
);
61 static DEFINE_PER_CPU(unsigned char, bank_map
); /* see which banks are on */
63 static void amd_threshold_interrupt(void);
69 struct thresh_restart
{
70 struct threshold_block
*b
;
77 static inline bool is_shared_bank(int bank
)
79 /* Bank 4 is for northbridge reporting and is thus shared */
83 static const char * const bank4_names(struct threshold_block
*b
)
97 WARN(1, "Funny MSR: 0x%08x\n", b
->address
);
103 static bool lvt_interrupt_supported(unsigned int bank
, u32 msr_high_bits
)
106 * bank 4 supports APIC LVT interrupts implicitly since forever.
112 * IntP: interrupt present; if this bit is set, the thresholding
113 * bank can generate APIC LVT interrupts
115 return msr_high_bits
& BIT(28);
118 static int lvt_off_valid(struct threshold_block
*b
, int apic
, u32 lo
, u32 hi
)
120 int msr
= (hi
& MASK_LVTOFF_HI
) >> 20;
123 pr_err(FW_BUG
"cpu %d, failed to setup threshold interrupt "
124 "for bank %d, block %d (MSR%08X=0x%x%08x)\n", b
->cpu
,
125 b
->bank
, b
->block
, b
->address
, hi
, lo
);
130 pr_err(FW_BUG
"cpu %d, invalid threshold interrupt offset %d "
131 "for bank %d, block %d (MSR%08X=0x%x%08x)\n",
132 b
->cpu
, apic
, b
->bank
, b
->block
, b
->address
, hi
, lo
);
140 * Called via smp_call_function_single(), must be called with correct
143 static void threshold_restart_bank(void *_tr
)
145 struct thresh_restart
*tr
= _tr
;
148 rdmsr(tr
->b
->address
, lo
, hi
);
150 if (tr
->b
->threshold_limit
< (hi
& THRESHOLD_MAX
))
151 tr
->reset
= 1; /* limit cannot be lower than err count */
153 if (tr
->reset
) { /* reset err count and overflow bit */
155 (hi
& ~(MASK_ERR_COUNT_HI
| MASK_OVERFLOW_HI
)) |
156 (THRESHOLD_MAX
- tr
->b
->threshold_limit
);
157 } else if (tr
->old_limit
) { /* change limit w/o reset */
158 int new_count
= (hi
& THRESHOLD_MAX
) +
159 (tr
->old_limit
- tr
->b
->threshold_limit
);
161 hi
= (hi
& ~MASK_ERR_COUNT_HI
) |
162 (new_count
& THRESHOLD_MAX
);
166 hi
&= ~MASK_INT_TYPE_HI
;
168 if (!tr
->b
->interrupt_capable
)
171 if (tr
->set_lvt_off
) {
172 if (lvt_off_valid(tr
->b
, tr
->lvt_off
, lo
, hi
)) {
173 /* set new lvt offset */
174 hi
&= ~MASK_LVTOFF_HI
;
175 hi
|= tr
->lvt_off
<< 20;
179 if (tr
->b
->interrupt_enable
)
184 hi
|= MASK_COUNT_EN_HI
;
185 wrmsr(tr
->b
->address
, lo
, hi
);
188 static void mce_threshold_block_init(struct threshold_block
*b
, int offset
)
190 struct thresh_restart tr
= {
196 b
->threshold_limit
= THRESHOLD_MAX
;
197 threshold_restart_bank(&tr
);
200 static int setup_APIC_mce(int reserved
, int new)
202 if (reserved
< 0 && !setup_APIC_eilvt(new, THRESHOLD_APIC_VECTOR
,
203 APIC_EILVT_MSG_FIX
, 0))
209 /* cpu init entry point, called from mce.c with preempt off */
210 void mce_amd_feature_init(struct cpuinfo_x86
*c
)
212 struct threshold_block b
;
213 unsigned int cpu
= smp_processor_id();
214 u32 low
= 0, high
= 0, address
= 0;
215 unsigned int bank
, block
;
218 for (bank
= 0; bank
< NR_BANKS
; ++bank
) {
219 for (block
= 0; block
< NR_BLOCKS
; ++block
) {
221 address
= MSR_IA32_MC0_MISC
+ bank
* 4;
222 else if (block
== 1) {
223 address
= (low
& MASK_BLKPTR_LO
) >> 21;
227 address
+= MCG_XBLK_ADDR
;
231 if (rdmsr_safe(address
, &low
, &high
))
234 if (!(high
& MASK_VALID_HI
))
237 if (!(high
& MASK_CNTP_HI
) ||
238 (high
& MASK_LOCKED_HI
))
242 per_cpu(bank_map
, cpu
) |= (1 << bank
);
244 memset(&b
, 0, sizeof(b
));
249 b
.interrupt_capable
= lvt_interrupt_supported(bank
, high
);
251 if (b
.interrupt_capable
) {
252 int new = (high
& MASK_LVTOFF_HI
) >> 20;
253 offset
= setup_APIC_mce(offset
, new);
256 mce_threshold_block_init(&b
, offset
);
257 mce_threshold_vector
= amd_threshold_interrupt
;
263 * APIC Interrupt Handler
267 * threshold interrupt handler will service THRESHOLD_APIC_VECTOR.
268 * the interrupt goes off when error_count reaches threshold_limit.
269 * the handler will simply log mcelog w/ software defined bank number.
271 static void amd_threshold_interrupt(void)
273 u32 low
= 0, high
= 0, address
= 0;
274 unsigned int bank
, block
;
279 /* assume first bank caused it */
280 for (bank
= 0; bank
< NR_BANKS
; ++bank
) {
281 if (!(per_cpu(bank_map
, m
.cpu
) & (1 << bank
)))
283 for (block
= 0; block
< NR_BLOCKS
; ++block
) {
285 address
= MSR_IA32_MC0_MISC
+ bank
* 4;
286 } else if (block
== 1) {
287 address
= (low
& MASK_BLKPTR_LO
) >> 21;
290 address
+= MCG_XBLK_ADDR
;
295 if (rdmsr_safe(address
, &low
, &high
))
298 if (!(high
& MASK_VALID_HI
)) {
305 if (!(high
& MASK_CNTP_HI
) ||
306 (high
& MASK_LOCKED_HI
))
310 * Log the machine check that caused the threshold
313 machine_check_poll(MCP_TIMESTAMP
,
314 &__get_cpu_var(mce_poll_banks
));
316 if (high
& MASK_OVERFLOW_HI
) {
317 rdmsrl(address
, m
.misc
);
318 rdmsrl(MSR_IA32_MC0_STATUS
+ bank
* 4,
320 m
.bank
= K8_MCE_THRESHOLD_BASE
334 struct threshold_attr
{
335 struct attribute attr
;
336 ssize_t (*show
) (struct threshold_block
*, char *);
337 ssize_t (*store
) (struct threshold_block
*, const char *, size_t count
);
340 #define SHOW_FIELDS(name) \
341 static ssize_t show_ ## name(struct threshold_block *b, char *buf) \
343 return sprintf(buf, "%lu\n", (unsigned long) b->name); \
345 SHOW_FIELDS(interrupt_enable
)
346 SHOW_FIELDS(threshold_limit
)
349 store_interrupt_enable(struct threshold_block
*b
, const char *buf
, size_t size
)
351 struct thresh_restart tr
;
354 if (!b
->interrupt_capable
)
357 if (strict_strtoul(buf
, 0, &new) < 0)
360 b
->interrupt_enable
= !!new;
362 memset(&tr
, 0, sizeof(tr
));
365 smp_call_function_single(b
->cpu
, threshold_restart_bank
, &tr
, 1);
371 store_threshold_limit(struct threshold_block
*b
, const char *buf
, size_t size
)
373 struct thresh_restart tr
;
376 if (strict_strtoul(buf
, 0, &new) < 0)
379 if (new > THRESHOLD_MAX
)
384 memset(&tr
, 0, sizeof(tr
));
385 tr
.old_limit
= b
->threshold_limit
;
386 b
->threshold_limit
= new;
389 smp_call_function_single(b
->cpu
, threshold_restart_bank
, &tr
, 1);
394 static ssize_t
show_error_count(struct threshold_block
*b
, char *buf
)
398 rdmsr_on_cpu(b
->cpu
, b
->address
, &lo
, &hi
);
400 return sprintf(buf
, "%u\n", ((hi
& THRESHOLD_MAX
) -
401 (THRESHOLD_MAX
- b
->threshold_limit
)));
404 static struct threshold_attr error_count
= {
405 .attr
= {.name
= __stringify(error_count
), .mode
= 0444 },
406 .show
= show_error_count
,
409 #define RW_ATTR(val) \
410 static struct threshold_attr val = { \
411 .attr = {.name = __stringify(val), .mode = 0644 }, \
412 .show = show_## val, \
413 .store = store_## val, \
416 RW_ATTR(interrupt_enable
);
417 RW_ATTR(threshold_limit
);
419 static struct attribute
*default_attrs
[] = {
420 &threshold_limit
.attr
,
422 NULL
, /* possibly interrupt_enable if supported, see below */
426 #define to_block(k) container_of(k, struct threshold_block, kobj)
427 #define to_attr(a) container_of(a, struct threshold_attr, attr)
429 static ssize_t
show(struct kobject
*kobj
, struct attribute
*attr
, char *buf
)
431 struct threshold_block
*b
= to_block(kobj
);
432 struct threshold_attr
*a
= to_attr(attr
);
435 ret
= a
->show
? a
->show(b
, buf
) : -EIO
;
440 static ssize_t
store(struct kobject
*kobj
, struct attribute
*attr
,
441 const char *buf
, size_t count
)
443 struct threshold_block
*b
= to_block(kobj
);
444 struct threshold_attr
*a
= to_attr(attr
);
447 ret
= a
->store
? a
->store(b
, buf
, count
) : -EIO
;
452 static const struct sysfs_ops threshold_ops
= {
457 static struct kobj_type threshold_ktype
= {
458 .sysfs_ops
= &threshold_ops
,
459 .default_attrs
= default_attrs
,
462 static __cpuinit
int allocate_threshold_blocks(unsigned int cpu
,
467 struct threshold_block
*b
= NULL
;
471 if ((bank
>= NR_BANKS
) || (block
>= NR_BLOCKS
))
474 if (rdmsr_safe_on_cpu(cpu
, address
, &low
, &high
))
477 if (!(high
& MASK_VALID_HI
)) {
484 if (!(high
& MASK_CNTP_HI
) ||
485 (high
& MASK_LOCKED_HI
))
488 b
= kzalloc(sizeof(struct threshold_block
), GFP_KERNEL
);
495 b
->address
= address
;
496 b
->interrupt_enable
= 0;
497 b
->interrupt_capable
= lvt_interrupt_supported(bank
, high
);
498 b
->threshold_limit
= THRESHOLD_MAX
;
500 if (b
->interrupt_capable
)
501 threshold_ktype
.default_attrs
[2] = &interrupt_enable
.attr
;
503 threshold_ktype
.default_attrs
[2] = NULL
;
505 INIT_LIST_HEAD(&b
->miscj
);
507 if (per_cpu(threshold_banks
, cpu
)[bank
]->blocks
) {
509 &per_cpu(threshold_banks
, cpu
)[bank
]->blocks
->miscj
);
511 per_cpu(threshold_banks
, cpu
)[bank
]->blocks
= b
;
514 err
= kobject_init_and_add(&b
->kobj
, &threshold_ktype
,
515 per_cpu(threshold_banks
, cpu
)[bank
]->kobj
,
516 (bank
== 4 ? bank4_names(b
) : th_names
[bank
]));
521 address
= (low
& MASK_BLKPTR_LO
) >> 21;
524 address
+= MCG_XBLK_ADDR
;
529 err
= allocate_threshold_blocks(cpu
, bank
, ++block
, address
);
534 kobject_uevent(&b
->kobj
, KOBJ_ADD
);
540 kobject_put(&b
->kobj
);
547 static __cpuinit
int __threshold_add_blocks(struct threshold_bank
*b
)
549 struct list_head
*head
= &b
->blocks
->miscj
;
550 struct threshold_block
*pos
= NULL
;
551 struct threshold_block
*tmp
= NULL
;
554 err
= kobject_add(&b
->blocks
->kobj
, b
->kobj
, b
->blocks
->kobj
.name
);
558 list_for_each_entry_safe(pos
, tmp
, head
, miscj
) {
560 err
= kobject_add(&pos
->kobj
, b
->kobj
, pos
->kobj
.name
);
562 list_for_each_entry_safe_reverse(pos
, tmp
, head
, miscj
)
563 kobject_del(&pos
->kobj
);
571 static __cpuinit
int threshold_create_bank(unsigned int cpu
, unsigned int bank
)
573 struct device
*dev
= per_cpu(mce_device
, cpu
);
574 struct amd_northbridge
*nb
= NULL
;
575 struct threshold_bank
*b
= NULL
;
576 const char *name
= th_names
[bank
];
579 if (is_shared_bank(bank
)) {
580 nb
= node_to_amd_nb(amd_get_nb_id(cpu
));
582 /* threshold descriptor already initialized on this node? */
583 if (nb
&& nb
->bank4
) {
586 err
= kobject_add(b
->kobj
, &dev
->kobj
, name
);
590 per_cpu(threshold_banks
, cpu
)[bank
] = b
;
591 atomic_inc(&b
->cpus
);
593 err
= __threshold_add_blocks(b
);
599 b
= kzalloc(sizeof(struct threshold_bank
), GFP_KERNEL
);
605 b
->kobj
= kobject_create_and_add(name
, &dev
->kobj
);
611 per_cpu(threshold_banks
, cpu
)[bank
] = b
;
613 if (is_shared_bank(bank
)) {
614 atomic_set(&b
->cpus
, 1);
616 /* nb is already initialized, see above */
623 err
= allocate_threshold_blocks(cpu
, bank
, 0,
624 MSR_IA32_MC0_MISC
+ bank
* 4);
635 /* create dir/files for all valid threshold banks */
636 static __cpuinit
int threshold_create_device(unsigned int cpu
)
641 for (bank
= 0; bank
< NR_BANKS
; ++bank
) {
642 if (!(per_cpu(bank_map
, cpu
) & (1 << bank
)))
644 err
= threshold_create_bank(cpu
, bank
);
652 static void deallocate_threshold_block(unsigned int cpu
,
655 struct threshold_block
*pos
= NULL
;
656 struct threshold_block
*tmp
= NULL
;
657 struct threshold_bank
*head
= per_cpu(threshold_banks
, cpu
)[bank
];
662 list_for_each_entry_safe(pos
, tmp
, &head
->blocks
->miscj
, miscj
) {
663 kobject_put(&pos
->kobj
);
664 list_del(&pos
->miscj
);
668 kfree(per_cpu(threshold_banks
, cpu
)[bank
]->blocks
);
669 per_cpu(threshold_banks
, cpu
)[bank
]->blocks
= NULL
;
672 static void __threshold_remove_blocks(struct threshold_bank
*b
)
674 struct threshold_block
*pos
= NULL
;
675 struct threshold_block
*tmp
= NULL
;
677 kobject_del(b
->kobj
);
679 list_for_each_entry_safe(pos
, tmp
, &b
->blocks
->miscj
, miscj
)
680 kobject_del(&pos
->kobj
);
683 static void threshold_remove_bank(unsigned int cpu
, int bank
)
685 struct amd_northbridge
*nb
;
686 struct threshold_bank
*b
;
688 b
= per_cpu(threshold_banks
, cpu
)[bank
];
695 if (is_shared_bank(bank
)) {
696 if (!atomic_dec_and_test(&b
->cpus
)) {
697 __threshold_remove_blocks(b
);
698 per_cpu(threshold_banks
, cpu
)[bank
] = NULL
;
702 * the last CPU on this node using the shared bank is
703 * going away, remove that bank now.
705 nb
= node_to_amd_nb(amd_get_nb_id(cpu
));
710 deallocate_threshold_block(cpu
, bank
);
713 kobject_del(b
->kobj
);
714 kobject_put(b
->kobj
);
716 per_cpu(threshold_banks
, cpu
)[bank
] = NULL
;
719 static void threshold_remove_device(unsigned int cpu
)
723 for (bank
= 0; bank
< NR_BANKS
; ++bank
) {
724 if (!(per_cpu(bank_map
, cpu
) & (1 << bank
)))
726 threshold_remove_bank(cpu
, bank
);
730 /* get notified when a cpu comes on/off */
731 static void __cpuinit
732 amd_64_threshold_cpu_callback(unsigned long action
, unsigned int cpu
)
736 case CPU_ONLINE_FROZEN
:
737 threshold_create_device(cpu
);
740 case CPU_DEAD_FROZEN
:
741 threshold_remove_device(cpu
);
748 static __init
int threshold_init_device(void)
752 /* to hit CPUs online before the notifier is up */
753 for_each_online_cpu(lcpu
) {
754 int err
= threshold_create_device(lcpu
);
759 threshold_cpu_callback
= amd_64_threshold_cpu_callback
;
764 * there are 3 funcs which need to be _initcalled in a logic sequence:
765 * 1. xen_late_init_mcelog
766 * 2. mcheck_init_device
767 * 3. threshold_init_device
769 * xen_late_init_mcelog must register xen_mce_chrdev_device before
770 * native mce_chrdev_device registration if running under xen platform;
772 * mcheck_init_device should be inited before threshold_init_device to
773 * initialize mce_device, otherwise a NULL ptr dereference will cause panic.
775 * so we use following _initcalls
776 * 1. device_initcall(xen_late_init_mcelog);
777 * 2. device_initcall_sync(mcheck_init_device);
778 * 3. late_initcall(threshold_init_device);
780 * when running under xen, the initcall order is 1,2,3;
781 * on baremetal, we skip 1 and we do only 2 and 3.
783 late_initcall(threshold_init_device
);