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x86/mce/amd: Collect valid address before logging an error
[deliverable/linux.git] / arch / x86 / kernel / cpu / mcheck / mce_amd.c
1 /*
2 * (c) 2005-2012 Advanced Micro Devices, Inc.
3 * Your use of this code is subject to the terms and conditions of the
4 * GNU general public license version 2. See "COPYING" or
5 * http://www.gnu.org/licenses/gpl.html
6 *
7 * Written by Jacob Shin - AMD, Inc.
8 *
9 * Maintained by: Borislav Petkov <bp@alien8.de>
10 *
11 * April 2006
12 * - added support for AMD Family 0x10 processors
13 * May 2012
14 * - major scrubbing
15 *
16 * All MC4_MISCi registers are shared between multi-cores
17 */
18 #include <linux/interrupt.h>
19 #include <linux/notifier.h>
20 #include <linux/kobject.h>
21 #include <linux/percpu.h>
22 #include <linux/errno.h>
23 #include <linux/sched.h>
24 #include <linux/sysfs.h>
25 #include <linux/slab.h>
26 #include <linux/init.h>
27 #include <linux/cpu.h>
28 #include <linux/smp.h>
29
30 #include <asm/amd_nb.h>
31 #include <asm/apic.h>
32 #include <asm/idle.h>
33 #include <asm/mce.h>
34 #include <asm/msr.h>
35
36 #define NR_BLOCKS 9
37 #define THRESHOLD_MAX 0xFFF
38 #define INT_TYPE_APIC 0x00020000
39 #define MASK_VALID_HI 0x80000000
40 #define MASK_CNTP_HI 0x40000000
41 #define MASK_LOCKED_HI 0x20000000
42 #define MASK_LVTOFF_HI 0x00F00000
43 #define MASK_COUNT_EN_HI 0x00080000
44 #define MASK_INT_TYPE_HI 0x00060000
45 #define MASK_OVERFLOW_HI 0x00010000
46 #define MASK_ERR_COUNT_HI 0x00000FFF
47 #define MASK_BLKPTR_LO 0xFF000000
48 #define MCG_XBLK_ADDR 0xC0000400
49
50 static const char * const th_names[] = {
51 "load_store",
52 "insn_fetch",
53 "combined_unit",
54 "",
55 "northbridge",
56 "execution_unit",
57 };
58
59 static DEFINE_PER_CPU(struct threshold_bank **, threshold_banks);
60 static DEFINE_PER_CPU(unsigned char, bank_map); /* see which banks are on */
61
62 static void amd_threshold_interrupt(void);
63
64 /*
65 * CPU Initialization
66 */
67
68 struct thresh_restart {
69 struct threshold_block *b;
70 int reset;
71 int set_lvt_off;
72 int lvt_off;
73 u16 old_limit;
74 };
75
76 static inline bool is_shared_bank(int bank)
77 {
78 /* Bank 4 is for northbridge reporting and is thus shared */
79 return (bank == 4);
80 }
81
82 static const char *bank4_names(const struct threshold_block *b)
83 {
84 switch (b->address) {
85 /* MSR4_MISC0 */
86 case 0x00000413:
87 return "dram";
88
89 case 0xc0000408:
90 return "ht_links";
91
92 case 0xc0000409:
93 return "l3_cache";
94
95 default:
96 WARN(1, "Funny MSR: 0x%08x\n", b->address);
97 return "";
98 }
99 };
100
101
102 static bool lvt_interrupt_supported(unsigned int bank, u32 msr_high_bits)
103 {
104 /*
105 * bank 4 supports APIC LVT interrupts implicitly since forever.
106 */
107 if (bank == 4)
108 return true;
109
110 /*
111 * IntP: interrupt present; if this bit is set, the thresholding
112 * bank can generate APIC LVT interrupts
113 */
114 return msr_high_bits & BIT(28);
115 }
116
117 static int lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi)
118 {
119 int msr = (hi & MASK_LVTOFF_HI) >> 20;
120
121 if (apic < 0) {
122 pr_err(FW_BUG "cpu %d, failed to setup threshold interrupt "
123 "for bank %d, block %d (MSR%08X=0x%x%08x)\n", b->cpu,
124 b->bank, b->block, b->address, hi, lo);
125 return 0;
126 }
127
128 if (apic != msr) {
129 pr_err(FW_BUG "cpu %d, invalid threshold interrupt offset %d "
130 "for bank %d, block %d (MSR%08X=0x%x%08x)\n",
131 b->cpu, apic, b->bank, b->block, b->address, hi, lo);
132 return 0;
133 }
134
135 return 1;
136 };
137
138 /*
139 * Called via smp_call_function_single(), must be called with correct
140 * cpu affinity.
141 */
142 static void threshold_restart_bank(void *_tr)
143 {
144 struct thresh_restart *tr = _tr;
145 u32 hi, lo;
146
147 rdmsr(tr->b->address, lo, hi);
148
149 if (tr->b->threshold_limit < (hi & THRESHOLD_MAX))
150 tr->reset = 1; /* limit cannot be lower than err count */
151
152 if (tr->reset) { /* reset err count and overflow bit */
153 hi =
154 (hi & ~(MASK_ERR_COUNT_HI | MASK_OVERFLOW_HI)) |
155 (THRESHOLD_MAX - tr->b->threshold_limit);
156 } else if (tr->old_limit) { /* change limit w/o reset */
157 int new_count = (hi & THRESHOLD_MAX) +
158 (tr->old_limit - tr->b->threshold_limit);
159
160 hi = (hi & ~MASK_ERR_COUNT_HI) |
161 (new_count & THRESHOLD_MAX);
162 }
163
164 /* clear IntType */
165 hi &= ~MASK_INT_TYPE_HI;
166
167 if (!tr->b->interrupt_capable)
168 goto done;
169
170 if (tr->set_lvt_off) {
171 if (lvt_off_valid(tr->b, tr->lvt_off, lo, hi)) {
172 /* set new lvt offset */
173 hi &= ~MASK_LVTOFF_HI;
174 hi |= tr->lvt_off << 20;
175 }
176 }
177
178 if (tr->b->interrupt_enable)
179 hi |= INT_TYPE_APIC;
180
181 done:
182
183 hi |= MASK_COUNT_EN_HI;
184 wrmsr(tr->b->address, lo, hi);
185 }
186
187 static void mce_threshold_block_init(struct threshold_block *b, int offset)
188 {
189 struct thresh_restart tr = {
190 .b = b,
191 .set_lvt_off = 1,
192 .lvt_off = offset,
193 };
194
195 b->threshold_limit = THRESHOLD_MAX;
196 threshold_restart_bank(&tr);
197 };
198
199 static int setup_APIC_mce(int reserved, int new)
200 {
201 if (reserved < 0 && !setup_APIC_eilvt(new, THRESHOLD_APIC_VECTOR,
202 APIC_EILVT_MSG_FIX, 0))
203 return new;
204
205 return reserved;
206 }
207
208 /* cpu init entry point, called from mce.c with preempt off */
209 void mce_amd_feature_init(struct cpuinfo_x86 *c)
210 {
211 struct threshold_block b;
212 unsigned int cpu = smp_processor_id();
213 u32 low = 0, high = 0, address = 0;
214 unsigned int bank, block;
215 int offset = -1, new;
216
217 for (bank = 0; bank < mca_cfg.banks; ++bank) {
218 for (block = 0; block < NR_BLOCKS; ++block) {
219 if (block == 0)
220 address = MSR_IA32_MCx_MISC(bank);
221 else if (block == 1) {
222 address = (low & MASK_BLKPTR_LO) >> 21;
223 if (!address)
224 break;
225
226 address += MCG_XBLK_ADDR;
227 } else
228 ++address;
229
230 if (rdmsr_safe(address, &low, &high))
231 break;
232
233 if (!(high & MASK_VALID_HI))
234 continue;
235
236 if (!(high & MASK_CNTP_HI) ||
237 (high & MASK_LOCKED_HI))
238 continue;
239
240 if (!block)
241 per_cpu(bank_map, cpu) |= (1 << bank);
242
243 memset(&b, 0, sizeof(b));
244 b.cpu = cpu;
245 b.bank = bank;
246 b.block = block;
247 b.address = address;
248 b.interrupt_capable = lvt_interrupt_supported(bank, high);
249
250 if (!b.interrupt_capable)
251 goto init;
252
253 b.interrupt_enable = 1;
254 new = (high & MASK_LVTOFF_HI) >> 20;
255 offset = setup_APIC_mce(offset, new);
256
257 if ((offset == new) &&
258 (mce_threshold_vector != amd_threshold_interrupt))
259 mce_threshold_vector = amd_threshold_interrupt;
260
261 init:
262 mce_threshold_block_init(&b, offset);
263 }
264 }
265 }
266
267 static void __log_error(unsigned int bank, bool threshold_err, u64 misc)
268 {
269 struct mce m;
270 u64 status;
271
272 rdmsrl(MSR_IA32_MCx_STATUS(bank), status);
273 if (!(status & MCI_STATUS_VAL))
274 return;
275
276 mce_setup(&m);
277
278 m.status = status;
279 m.bank = bank;
280
281 if (threshold_err)
282 m.misc = misc;
283
284 if (m.status & MCI_STATUS_ADDRV)
285 rdmsrl(MSR_IA32_MCx_ADDR(bank), m.addr);
286
287 mce_log(&m);
288 wrmsrl(MSR_IA32_MCx_STATUS(bank), 0);
289 }
290
291 /*
292 * APIC Interrupt Handler
293 */
294
295 /*
296 * threshold interrupt handler will service THRESHOLD_APIC_VECTOR.
297 * the interrupt goes off when error_count reaches threshold_limit.
298 * the handler will simply log mcelog w/ software defined bank number.
299 */
300
301 static void amd_threshold_interrupt(void)
302 {
303 u32 low = 0, high = 0, address = 0;
304 int cpu = smp_processor_id();
305 unsigned int bank, block;
306
307 /* assume first bank caused it */
308 for (bank = 0; bank < mca_cfg.banks; ++bank) {
309 if (!(per_cpu(bank_map, cpu) & (1 << bank)))
310 continue;
311 for (block = 0; block < NR_BLOCKS; ++block) {
312 if (block == 0) {
313 address = MSR_IA32_MCx_MISC(bank);
314 } else if (block == 1) {
315 address = (low & MASK_BLKPTR_LO) >> 21;
316 if (!address)
317 break;
318 address += MCG_XBLK_ADDR;
319 } else {
320 ++address;
321 }
322
323 if (rdmsr_safe(address, &low, &high))
324 break;
325
326 if (!(high & MASK_VALID_HI)) {
327 if (block)
328 continue;
329 else
330 break;
331 }
332
333 if (!(high & MASK_CNTP_HI) ||
334 (high & MASK_LOCKED_HI))
335 continue;
336
337 /*
338 * Log the machine check that caused the threshold
339 * event.
340 */
341 if (high & MASK_OVERFLOW_HI)
342 goto log;
343 }
344 }
345 return;
346
347 log:
348 __log_error(bank, true, ((u64)high << 32) | low);
349 }
350
351 /*
352 * Sysfs Interface
353 */
354
355 struct threshold_attr {
356 struct attribute attr;
357 ssize_t (*show) (struct threshold_block *, char *);
358 ssize_t (*store) (struct threshold_block *, const char *, size_t count);
359 };
360
361 #define SHOW_FIELDS(name) \
362 static ssize_t show_ ## name(struct threshold_block *b, char *buf) \
363 { \
364 return sprintf(buf, "%lu\n", (unsigned long) b->name); \
365 }
366 SHOW_FIELDS(interrupt_enable)
367 SHOW_FIELDS(threshold_limit)
368
369 static ssize_t
370 store_interrupt_enable(struct threshold_block *b, const char *buf, size_t size)
371 {
372 struct thresh_restart tr;
373 unsigned long new;
374
375 if (!b->interrupt_capable)
376 return -EINVAL;
377
378 if (kstrtoul(buf, 0, &new) < 0)
379 return -EINVAL;
380
381 b->interrupt_enable = !!new;
382
383 memset(&tr, 0, sizeof(tr));
384 tr.b = b;
385
386 smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1);
387
388 return size;
389 }
390
391 static ssize_t
392 store_threshold_limit(struct threshold_block *b, const char *buf, size_t size)
393 {
394 struct thresh_restart tr;
395 unsigned long new;
396
397 if (kstrtoul(buf, 0, &new) < 0)
398 return -EINVAL;
399
400 if (new > THRESHOLD_MAX)
401 new = THRESHOLD_MAX;
402 if (new < 1)
403 new = 1;
404
405 memset(&tr, 0, sizeof(tr));
406 tr.old_limit = b->threshold_limit;
407 b->threshold_limit = new;
408 tr.b = b;
409
410 smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1);
411
412 return size;
413 }
414
415 static ssize_t show_error_count(struct threshold_block *b, char *buf)
416 {
417 u32 lo, hi;
418
419 rdmsr_on_cpu(b->cpu, b->address, &lo, &hi);
420
421 return sprintf(buf, "%u\n", ((hi & THRESHOLD_MAX) -
422 (THRESHOLD_MAX - b->threshold_limit)));
423 }
424
425 static struct threshold_attr error_count = {
426 .attr = {.name = __stringify(error_count), .mode = 0444 },
427 .show = show_error_count,
428 };
429
430 #define RW_ATTR(val) \
431 static struct threshold_attr val = { \
432 .attr = {.name = __stringify(val), .mode = 0644 }, \
433 .show = show_## val, \
434 .store = store_## val, \
435 };
436
437 RW_ATTR(interrupt_enable);
438 RW_ATTR(threshold_limit);
439
440 static struct attribute *default_attrs[] = {
441 &threshold_limit.attr,
442 &error_count.attr,
443 NULL, /* possibly interrupt_enable if supported, see below */
444 NULL,
445 };
446
447 #define to_block(k) container_of(k, struct threshold_block, kobj)
448 #define to_attr(a) container_of(a, struct threshold_attr, attr)
449
450 static ssize_t show(struct kobject *kobj, struct attribute *attr, char *buf)
451 {
452 struct threshold_block *b = to_block(kobj);
453 struct threshold_attr *a = to_attr(attr);
454 ssize_t ret;
455
456 ret = a->show ? a->show(b, buf) : -EIO;
457
458 return ret;
459 }
460
461 static ssize_t store(struct kobject *kobj, struct attribute *attr,
462 const char *buf, size_t count)
463 {
464 struct threshold_block *b = to_block(kobj);
465 struct threshold_attr *a = to_attr(attr);
466 ssize_t ret;
467
468 ret = a->store ? a->store(b, buf, count) : -EIO;
469
470 return ret;
471 }
472
473 static const struct sysfs_ops threshold_ops = {
474 .show = show,
475 .store = store,
476 };
477
478 static struct kobj_type threshold_ktype = {
479 .sysfs_ops = &threshold_ops,
480 .default_attrs = default_attrs,
481 };
482
483 static int allocate_threshold_blocks(unsigned int cpu, unsigned int bank,
484 unsigned int block, u32 address)
485 {
486 struct threshold_block *b = NULL;
487 u32 low, high;
488 int err;
489
490 if ((bank >= mca_cfg.banks) || (block >= NR_BLOCKS))
491 return 0;
492
493 if (rdmsr_safe_on_cpu(cpu, address, &low, &high))
494 return 0;
495
496 if (!(high & MASK_VALID_HI)) {
497 if (block)
498 goto recurse;
499 else
500 return 0;
501 }
502
503 if (!(high & MASK_CNTP_HI) ||
504 (high & MASK_LOCKED_HI))
505 goto recurse;
506
507 b = kzalloc(sizeof(struct threshold_block), GFP_KERNEL);
508 if (!b)
509 return -ENOMEM;
510
511 b->block = block;
512 b->bank = bank;
513 b->cpu = cpu;
514 b->address = address;
515 b->interrupt_enable = 0;
516 b->interrupt_capable = lvt_interrupt_supported(bank, high);
517 b->threshold_limit = THRESHOLD_MAX;
518
519 if (b->interrupt_capable) {
520 threshold_ktype.default_attrs[2] = &interrupt_enable.attr;
521 b->interrupt_enable = 1;
522 } else {
523 threshold_ktype.default_attrs[2] = NULL;
524 }
525
526 INIT_LIST_HEAD(&b->miscj);
527
528 if (per_cpu(threshold_banks, cpu)[bank]->blocks) {
529 list_add(&b->miscj,
530 &per_cpu(threshold_banks, cpu)[bank]->blocks->miscj);
531 } else {
532 per_cpu(threshold_banks, cpu)[bank]->blocks = b;
533 }
534
535 err = kobject_init_and_add(&b->kobj, &threshold_ktype,
536 per_cpu(threshold_banks, cpu)[bank]->kobj,
537 (bank == 4 ? bank4_names(b) : th_names[bank]));
538 if (err)
539 goto out_free;
540 recurse:
541 if (!block) {
542 address = (low & MASK_BLKPTR_LO) >> 21;
543 if (!address)
544 return 0;
545 address += MCG_XBLK_ADDR;
546 } else {
547 ++address;
548 }
549
550 err = allocate_threshold_blocks(cpu, bank, ++block, address);
551 if (err)
552 goto out_free;
553
554 if (b)
555 kobject_uevent(&b->kobj, KOBJ_ADD);
556
557 return err;
558
559 out_free:
560 if (b) {
561 kobject_put(&b->kobj);
562 list_del(&b->miscj);
563 kfree(b);
564 }
565 return err;
566 }
567
568 static int __threshold_add_blocks(struct threshold_bank *b)
569 {
570 struct list_head *head = &b->blocks->miscj;
571 struct threshold_block *pos = NULL;
572 struct threshold_block *tmp = NULL;
573 int err = 0;
574
575 err = kobject_add(&b->blocks->kobj, b->kobj, b->blocks->kobj.name);
576 if (err)
577 return err;
578
579 list_for_each_entry_safe(pos, tmp, head, miscj) {
580
581 err = kobject_add(&pos->kobj, b->kobj, pos->kobj.name);
582 if (err) {
583 list_for_each_entry_safe_reverse(pos, tmp, head, miscj)
584 kobject_del(&pos->kobj);
585
586 return err;
587 }
588 }
589 return err;
590 }
591
592 static int threshold_create_bank(unsigned int cpu, unsigned int bank)
593 {
594 struct device *dev = per_cpu(mce_device, cpu);
595 struct amd_northbridge *nb = NULL;
596 struct threshold_bank *b = NULL;
597 const char *name = th_names[bank];
598 int err = 0;
599
600 if (is_shared_bank(bank)) {
601 nb = node_to_amd_nb(amd_get_nb_id(cpu));
602
603 /* threshold descriptor already initialized on this node? */
604 if (nb && nb->bank4) {
605 /* yes, use it */
606 b = nb->bank4;
607 err = kobject_add(b->kobj, &dev->kobj, name);
608 if (err)
609 goto out;
610
611 per_cpu(threshold_banks, cpu)[bank] = b;
612 atomic_inc(&b->cpus);
613
614 err = __threshold_add_blocks(b);
615
616 goto out;
617 }
618 }
619
620 b = kzalloc(sizeof(struct threshold_bank), GFP_KERNEL);
621 if (!b) {
622 err = -ENOMEM;
623 goto out;
624 }
625
626 b->kobj = kobject_create_and_add(name, &dev->kobj);
627 if (!b->kobj) {
628 err = -EINVAL;
629 goto out_free;
630 }
631
632 per_cpu(threshold_banks, cpu)[bank] = b;
633
634 if (is_shared_bank(bank)) {
635 atomic_set(&b->cpus, 1);
636
637 /* nb is already initialized, see above */
638 if (nb) {
639 WARN_ON(nb->bank4);
640 nb->bank4 = b;
641 }
642 }
643
644 err = allocate_threshold_blocks(cpu, bank, 0, MSR_IA32_MCx_MISC(bank));
645 if (!err)
646 goto out;
647
648 out_free:
649 kfree(b);
650
651 out:
652 return err;
653 }
654
655 /* create dir/files for all valid threshold banks */
656 static int threshold_create_device(unsigned int cpu)
657 {
658 unsigned int bank;
659 struct threshold_bank **bp;
660 int err = 0;
661
662 bp = kzalloc(sizeof(struct threshold_bank *) * mca_cfg.banks,
663 GFP_KERNEL);
664 if (!bp)
665 return -ENOMEM;
666
667 per_cpu(threshold_banks, cpu) = bp;
668
669 for (bank = 0; bank < mca_cfg.banks; ++bank) {
670 if (!(per_cpu(bank_map, cpu) & (1 << bank)))
671 continue;
672 err = threshold_create_bank(cpu, bank);
673 if (err)
674 return err;
675 }
676
677 return err;
678 }
679
680 static void deallocate_threshold_block(unsigned int cpu,
681 unsigned int bank)
682 {
683 struct threshold_block *pos = NULL;
684 struct threshold_block *tmp = NULL;
685 struct threshold_bank *head = per_cpu(threshold_banks, cpu)[bank];
686
687 if (!head)
688 return;
689
690 list_for_each_entry_safe(pos, tmp, &head->blocks->miscj, miscj) {
691 kobject_put(&pos->kobj);
692 list_del(&pos->miscj);
693 kfree(pos);
694 }
695
696 kfree(per_cpu(threshold_banks, cpu)[bank]->blocks);
697 per_cpu(threshold_banks, cpu)[bank]->blocks = NULL;
698 }
699
700 static void __threshold_remove_blocks(struct threshold_bank *b)
701 {
702 struct threshold_block *pos = NULL;
703 struct threshold_block *tmp = NULL;
704
705 kobject_del(b->kobj);
706
707 list_for_each_entry_safe(pos, tmp, &b->blocks->miscj, miscj)
708 kobject_del(&pos->kobj);
709 }
710
711 static void threshold_remove_bank(unsigned int cpu, int bank)
712 {
713 struct amd_northbridge *nb;
714 struct threshold_bank *b;
715
716 b = per_cpu(threshold_banks, cpu)[bank];
717 if (!b)
718 return;
719
720 if (!b->blocks)
721 goto free_out;
722
723 if (is_shared_bank(bank)) {
724 if (!atomic_dec_and_test(&b->cpus)) {
725 __threshold_remove_blocks(b);
726 per_cpu(threshold_banks, cpu)[bank] = NULL;
727 return;
728 } else {
729 /*
730 * the last CPU on this node using the shared bank is
731 * going away, remove that bank now.
732 */
733 nb = node_to_amd_nb(amd_get_nb_id(cpu));
734 nb->bank4 = NULL;
735 }
736 }
737
738 deallocate_threshold_block(cpu, bank);
739
740 free_out:
741 kobject_del(b->kobj);
742 kobject_put(b->kobj);
743 kfree(b);
744 per_cpu(threshold_banks, cpu)[bank] = NULL;
745 }
746
747 static void threshold_remove_device(unsigned int cpu)
748 {
749 unsigned int bank;
750
751 for (bank = 0; bank < mca_cfg.banks; ++bank) {
752 if (!(per_cpu(bank_map, cpu) & (1 << bank)))
753 continue;
754 threshold_remove_bank(cpu, bank);
755 }
756 kfree(per_cpu(threshold_banks, cpu));
757 }
758
759 /* get notified when a cpu comes on/off */
760 static void
761 amd_64_threshold_cpu_callback(unsigned long action, unsigned int cpu)
762 {
763 switch (action) {
764 case CPU_ONLINE:
765 case CPU_ONLINE_FROZEN:
766 threshold_create_device(cpu);
767 break;
768 case CPU_DEAD:
769 case CPU_DEAD_FROZEN:
770 threshold_remove_device(cpu);
771 break;
772 default:
773 break;
774 }
775 }
776
777 static __init int threshold_init_device(void)
778 {
779 unsigned lcpu = 0;
780
781 /* to hit CPUs online before the notifier is up */
782 for_each_online_cpu(lcpu) {
783 int err = threshold_create_device(lcpu);
784
785 if (err)
786 return err;
787 }
788 threshold_cpu_callback = amd_64_threshold_cpu_callback;
789
790 return 0;
791 }
792 /*
793 * there are 3 funcs which need to be _initcalled in a logic sequence:
794 * 1. xen_late_init_mcelog
795 * 2. mcheck_init_device
796 * 3. threshold_init_device
797 *
798 * xen_late_init_mcelog must register xen_mce_chrdev_device before
799 * native mce_chrdev_device registration if running under xen platform;
800 *
801 * mcheck_init_device should be inited before threshold_init_device to
802 * initialize mce_device, otherwise a NULL ptr dereference will cause panic.
803 *
804 * so we use following _initcalls
805 * 1. device_initcall(xen_late_init_mcelog);
806 * 2. device_initcall_sync(mcheck_init_device);
807 * 3. late_initcall(threshold_init_device);
808 *
809 * when running under xen, the initcall order is 1,2,3;
810 * on baremetal, we skip 1 and we do only 2 and 3.
811 */
812 late_initcall(threshold_init_device);
Linux kernel - Deliverables
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