arch/x86/kernel/cpu/mcheck/p4.c

   1 /*
   2  * P4 specific Machine Check Exception Reporting
   3  */
   4
   5 #include <linux/interrupt.h>
   6 #include <linux/kernel.h>
   7 #include <linux/types.h>
   8 #include <linux/init.h>
   9 #include <linux/smp.h>
  10
  11 #include <asm/therm_throt.h>
  12 #include <asm/processor.h>
  13 #include <asm/system.h>
  14 #include <asm/apic.h>
  15 #include <asm/mce.h>
  16 #include <asm/msr.h>
  17
  18 /* as supported by the P4/Xeon family */
  19 struct intel_mce_extended_msrs {
  20         u32 eax;
  21         u32 ebx;
  22         u32 ecx;
  23         u32 edx;
  24         u32 esi;
  25         u32 edi;
  26         u32 ebp;
  27         u32 esp;
  28         u32 eflags;
  29         u32 eip;
  30         /* u32 *reserved[]; */
  31 };
  32
  33 static int mce_num_extended_msrs;
  34
  35
  36 #ifdef CONFIG_X86_MCE_P4THERMAL
  37
  38 static void unexpected_thermal_interrupt(struct pt_regs *regs)
  39 {
  40         printk(KERN_ERR "CPU%d: Unexpected LVT TMR interrupt!\n",
  41                         smp_processor_id());
  42         add_taint(TAINT_MACHINE_CHECK);
  43 }
  44
  45 /* P4/Xeon Thermal transition interrupt handler: */
  46 static void intel_thermal_interrupt(struct pt_regs *regs)
  47 {
  48         __u64 msr_val;
  49
  50         ack_APIC_irq();
  51
  52         rdmsrl(MSR_IA32_THERM_STATUS, msr_val);
  53         therm_throt_process(msr_val & THERM_STATUS_PROCHOT);
  54 }
  55
  56 /* Thermal interrupt handler for this CPU setup: */
  57 static void (*vendor_thermal_interrupt)(struct pt_regs *regs) =
  58                                                 unexpected_thermal_interrupt;
  59
  60 void smp_thermal_interrupt(struct pt_regs *regs)
  61 {
  62         irq_enter();
  63         vendor_thermal_interrupt(regs);
  64         __get_cpu_var(irq_stat).irq_thermal_count++;
  65         irq_exit();
  66 }
  67
  68 void intel_set_thermal_handler(void)
  69 {
  70         vendor_thermal_interrupt = intel_thermal_interrupt;
  71 }
  72
  73 #endif /* CONFIG_X86_MCE_P4THERMAL */
  74
  75 /* P4/Xeon Extended MCE MSR retrieval, return 0 if unsupported */
  76 static void intel_get_extended_msrs(struct intel_mce_extended_msrs *r)
  77 {
  78         u32 h;
  79
  80         rdmsr(MSR_IA32_MCG_EAX, r->eax, h);
  81         rdmsr(MSR_IA32_MCG_EBX, r->ebx, h);
  82         rdmsr(MSR_IA32_MCG_ECX, r->ecx, h);
  83         rdmsr(MSR_IA32_MCG_EDX, r->edx, h);
  84         rdmsr(MSR_IA32_MCG_ESI, r->esi, h);
  85         rdmsr(MSR_IA32_MCG_EDI, r->edi, h);
  86         rdmsr(MSR_IA32_MCG_EBP, r->ebp, h);
  87         rdmsr(MSR_IA32_MCG_ESP, r->esp, h);
  88         rdmsr(MSR_IA32_MCG_EFLAGS, r->eflags, h);
  89         rdmsr(MSR_IA32_MCG_EIP, r->eip, h);
  90 }
  91
  92 static void intel_machine_check(struct pt_regs *regs, long error_code)
  93 {
  94         u32 alow, ahigh, high, low;
  95         u32 mcgstl, mcgsth;
  96         int recover = 1;
  97         int i;
  98
  99         rdmsr(MSR_IA32_MCG_STATUS, mcgstl, mcgsth);
 100         if (mcgstl & (1<<0))    /* Recoverable ? */
 101                 recover = 0;
 102
 103         printk(KERN_EMERG "CPU %d: Machine Check Exception: %08x%08x\n",
 104                 smp_processor_id(), mcgsth, mcgstl);
 105
 106         if (mce_num_extended_msrs > 0) {
 107                 struct intel_mce_extended_msrs dbg;
 108
 109                 intel_get_extended_msrs(&dbg);
 110
 111                 printk(KERN_DEBUG "CPU %d: EIP: %08x EFLAGS: %08x\n"
 112                         "\teax: %08x ebx: %08x ecx: %08x edx: %08x\n"
 113                         "\tesi: %08x edi: %08x ebp: %08x esp: %08x\n",
 114                         smp_processor_id(), dbg.eip, dbg.eflags,
 115                         dbg.eax, dbg.ebx, dbg.ecx, dbg.edx,
 116                         dbg.esi, dbg.edi, dbg.ebp, dbg.esp);
 117         }
 118
 119         for (i = 0; i < nr_mce_banks; i++) {
 120                 rdmsr(MSR_IA32_MC0_STATUS+i*4, low, high);
 121                 if (high & (1<<31)) {
 122                         char misc[20];
 123                         char addr[24];
 124
 125                         misc[0] = addr[0] = '\0';
 126                         if (high & (1<<29))
 127                                 recover |= 1;
 128                         if (high & (1<<25))
 129                                 recover |= 2;
 130                         high &= ~(1<<31);
 131                         if (high & (1<<27)) {
 132                                 rdmsr(MSR_IA32_MC0_MISC+i*4, alow, ahigh);
 133                                 snprintf(misc, 20, "[%08x%08x]", ahigh, alow);
 134                         }
 135                         if (high & (1<<26)) {
 136                                 rdmsr(MSR_IA32_MC0_ADDR+i*4, alow, ahigh);
 137                                 snprintf(addr, 24, " at %08x%08x", ahigh, alow);
 138                         }
 139                         printk(KERN_EMERG "CPU %d: Bank %d: %08x%08x%s%s\n",
 140                                 smp_processor_id(), i, high, low, misc, addr);
 141                 }
 142         }
 143
 144         if (recover & 2)
 145                 panic("CPU context corrupt");
 146         if (recover & 1)
 147                 panic("Unable to continue");
 148
 149         printk(KERN_EMERG "Attempting to continue.\n");
 150
 151         /*
 152          * Do not clear the MSR_IA32_MCi_STATUS if the error is not
 153          * recoverable/continuable.This will allow BIOS to look at the MSRs
 154          * for errors if the OS could not log the error.
 155          */
 156         for (i = 0; i < nr_mce_banks; i++) {
 157                 u32 msr;
 158                 msr = MSR_IA32_MC0_STATUS+i*4;
 159                 rdmsr(msr, low, high);
 160                 if (high&(1<<31)) {
 161                         /* Clear it */
 162                         wrmsr(msr, 0UL, 0UL);
 163                         /* Serialize */
 164                         wmb();
 165                         add_taint(TAINT_MACHINE_CHECK);
 166                 }
 167         }
 168         mcgstl &= ~(1<<2);
 169         wrmsr(MSR_IA32_MCG_STATUS, mcgstl, mcgsth);
 170 }
 171
 172 void intel_p4_mcheck_init(struct cpuinfo_x86 *c)
 173 {
 174         u32 l, h;
 175         int i;
 176
 177         machine_check_vector = intel_machine_check;
 178         wmb();
 179
 180         printk(KERN_INFO "Intel machine check architecture supported.\n");
 181         rdmsr(MSR_IA32_MCG_CAP, l, h);
 182         if (l & (1<<8)) /* Control register present ? */
 183                 wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
 184         nr_mce_banks = l & 0xff;
 185
 186         for (i = 0; i < nr_mce_banks; i++) {
 187                 wrmsr(MSR_IA32_MC0_CTL+4*i, 0xffffffff, 0xffffffff);
 188                 wrmsr(MSR_IA32_MC0_STATUS+4*i, 0x0, 0x0);
 189         }
 190
 191         set_in_cr4(X86_CR4_MCE);
 192         printk(KERN_INFO "Intel machine check reporting enabled on CPU#%d.\n",
 193                 smp_processor_id());
 194
 195         /* Check for P4/Xeon extended MCE MSRs */
 196         rdmsr(MSR_IA32_MCG_CAP, l, h);
 197         if (l & (1<<9)) {/* MCG_EXT_P */
 198                 mce_num_extended_msrs = (l >> 16) & 0xff;
 199                 printk(KERN_INFO "CPU%d: Intel P4/Xeon Extended MCE MSRs (%d)"
 200                                 " available\n",
 201                         smp_processor_id(), mce_num_extended_msrs);
 202
 203 #ifdef CONFIG_X86_MCE_P4THERMAL
 204                 /* Check for P4/Xeon Thermal monitor */
 205                 intel_init_thermal(c);
 206 #endif
 207         }
 208 }