x86/cpu: Convert printk(KERN_<LEVEL> ...) to pr_<level>(...)
[deliverable/linux.git] / arch / x86 / kernel / cpu / mcheck / p5.c
1 /*
2 * P5 specific Machine Check Exception Reporting
3 * (C) Copyright 2002 Alan Cox <alan@lxorguk.ukuu.org.uk>
4 */
5 #include <linux/interrupt.h>
6 #include <linux/kernel.h>
7 #include <linux/types.h>
8 #include <linux/smp.h>
9
10 #include <asm/processor.h>
11 #include <asm/traps.h>
12 #include <asm/tlbflush.h>
13 #include <asm/mce.h>
14 #include <asm/msr.h>
15
16 /* By default disabled */
17 int mce_p5_enabled __read_mostly;
18
19 /* Machine check handler for Pentium class Intel CPUs: */
20 static void pentium_machine_check(struct pt_regs *regs, long error_code)
21 {
22 u32 loaddr, hi, lotype;
23
24 ist_enter(regs);
25
26 rdmsr(MSR_IA32_P5_MC_ADDR, loaddr, hi);
27 rdmsr(MSR_IA32_P5_MC_TYPE, lotype, hi);
28
29 pr_emerg("CPU#%d: Machine Check Exception: 0x%8X (type 0x%8X).\n",
30 smp_processor_id(), loaddr, lotype);
31
32 if (lotype & (1<<5)) {
33 pr_emerg("CPU#%d: Possible thermal failure (CPU on fire ?).\n",
34 smp_processor_id());
35 }
36
37 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE);
38
39 ist_exit(regs);
40 }
41
42 /* Set up machine check reporting for processors with Intel style MCE: */
43 void intel_p5_mcheck_init(struct cpuinfo_x86 *c)
44 {
45 u32 l, h;
46
47 /* Default P5 to off as its often misconnected: */
48 if (!mce_p5_enabled)
49 return;
50
51 /* Check for MCE support: */
52 if (!cpu_has(c, X86_FEATURE_MCE))
53 return;
54
55 machine_check_vector = pentium_machine_check;
56 /* Make sure the vector pointer is visible before we enable MCEs: */
57 wmb();
58
59 /* Read registers before enabling: */
60 rdmsr(MSR_IA32_P5_MC_ADDR, l, h);
61 rdmsr(MSR_IA32_P5_MC_TYPE, l, h);
62 pr_info("Intel old style machine check architecture supported.\n");
63
64 /* Enable MCE: */
65 cr4_set_bits(X86_CR4_MCE);
66 pr_info("Intel old style machine check reporting enabled on CPU#%d.\n",
67 smp_processor_id());
68 }
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