2 * P6 specific Machine Check Exception Reporting
3 * (C) Copyright 2002 Alan Cox <alan@lxorguk.ukuu.org.uk>
5 #include <linux/interrupt.h>
6 #include <linux/kernel.h>
7 #include <linux/types.h>
8 #include <linux/init.h>
11 #include <asm/processor.h>
12 #include <asm/system.h>
17 /* Machine Check Handler For PII/PIII */
18 static void intel_machine_check(struct pt_regs
*regs
, long error_code
)
20 u32 alow
, ahigh
, high
, low
;
25 rdmsr(MSR_IA32_MCG_STATUS
, mcgstl
, mcgsth
);
26 if (mcgstl
& (1<<0)) /* Recoverable ? */
29 printk(KERN_EMERG
"CPU %d: Machine Check Exception: %08x%08x\n",
30 smp_processor_id(), mcgsth
, mcgstl
);
32 for (i
= 0; i
< nr_mce_banks
; i
++) {
33 rdmsr(MSR_IA32_MC0_STATUS
+i
*4, low
, high
);
48 rdmsr(MSR_IA32_MC0_MISC
+i
*4, alow
, ahigh
);
49 snprintf(misc
, 20, "[%08x%08x]", ahigh
, alow
);
52 rdmsr(MSR_IA32_MC0_ADDR
+i
*4, alow
, ahigh
);
53 snprintf(addr
, 24, " at %08x%08x", ahigh
, alow
);
56 printk(KERN_EMERG
"CPU %d: Bank %d: %08x%08x%s%s\n",
57 smp_processor_id(), i
, high
, low
, misc
, addr
);
62 panic("CPU context corrupt");
64 panic("Unable to continue");
66 printk(KERN_EMERG
"Attempting to continue.\n");
68 * Do not clear the MSR_IA32_MCi_STATUS if the error is not
69 * recoverable/continuable.This will allow BIOS to look at the MSRs
70 * for errors if the OS could not log the error:
72 for (i
= 0; i
< nr_mce_banks
; i
++) {
75 msr
= MSR_IA32_MC0_STATUS
+i
*4;
76 rdmsr(msr
, low
, high
);
82 add_taint(TAINT_MACHINE_CHECK
);
86 wrmsr(MSR_IA32_MCG_STATUS
, mcgstl
, mcgsth
);
89 /* Set up machine check reporting for processors with Intel style MCE: */
90 void intel_p6_mcheck_init(struct cpuinfo_x86
*c
)
95 /* Check for MCE support */
96 if (!cpu_has(c
, X86_FEATURE_MCE
))
99 /* Check for PPro style MCA */
100 if (!cpu_has(c
, X86_FEATURE_MCA
))
103 /* Ok machine check is available */
104 machine_check_vector
= intel_machine_check
;
105 /* Make sure the vector pointer is visible before we enable MCEs: */
108 printk(KERN_INFO
"Intel machine check architecture supported.\n");
109 rdmsr(MSR_IA32_MCG_CAP
, l
, h
);
110 if (l
& (1<<8)) /* Control register present ? */
111 wrmsr(MSR_IA32_MCG_CTL
, 0xffffffff, 0xffffffff);
112 nr_mce_banks
= l
& 0xff;
115 * Following the example in IA-32 SDM Vol 3:
116 * - MC0_CTL should not be written
117 * - Status registers on all banks should be cleared on reset
119 for (i
= 1; i
< nr_mce_banks
; i
++)
120 wrmsr(MSR_IA32_MC0_CTL
+4*i
, 0xffffffff, 0xffffffff);
122 for (i
= 0; i
< nr_mce_banks
; i
++)
123 wrmsr(MSR_IA32_MC0_STATUS
+4*i
, 0x0, 0x0);
125 set_in_cr4(X86_CR4_MCE
);
126 printk(KERN_INFO
"Intel machine check reporting enabled on CPU#%d.\n",
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